ACPL-C87AT/ACPL-C87BT Automotive High Precision DC Voltage Isolation Sensor Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACPL-C87AT/C87BT isolation sensors utilize superior optical coupling technology, with sigma-delta (S-D) analog-to-digital converter, chopper stabilized amplifiers, and a fully differential circuit topology to provide unequaled isolation-mode noise rejection, low offset, high gain accuracy and stability. • Unity Gain ACPL-C87AT (±1% gain tolerance) and ACPL-C87BT (±0.5% gain tolerance) are designed for high precision DC voltage sensing in electronic motor drives, DC/DC and AC/DC converter and battery monitoring system. The ACPL-C87AT/C87BT features high input impedance and operate with full span of analog input voltage up to 2.46 V. The shutdown feature provides power saving and can be controlled from external source, such as microprocessor. • 25 ppm/°C Gain Drift vs. Temperature The high common-mode transient immunity (15 kV/µs) of the ACPL-C87AT/C87BT maintains the precision and stability needed to accurately monitor DC rail voltage in high noise motor control environments. This galvanic safe isolation solution is delivered in a compact, surface mount stretched SO-8 (SSO-8) package that meets worldwide regulatory safety standards. Avago R2Coupler isolation products provide the reinforced insulation and reliability needed for critical automotive and high temperature industrial applications. • 0.05% Non Linearity • 100 kHz Bandwidth • 0 to 2 V Nominal Input Range • Qualified to AEC-Q100 Grade 1 Test Guidelines • Operating Temperature: -40° C to +125° C • Shutdown Feature (Active High) • 15 kV/ms Common-Mode Rejection at VCM = 1 kV • Working Voltage, VIORM = 1414 Vpeak • Compact, Surface Mount Stretched SO8 Package • Worldwide Safety Approval: – UL 1577 (5000 VRMS / 1 min.) – CSA – IEC/EN/DIN EN 60747-5-5 Applications • Automotive DC/DC Converter Voltage Sensing 8 1 VDD2 • Automotive Motor Inverter DC Bus Voltage Sensing • Automotive AC/DC (Charger) DC Output Voltage Sensing 7 VOUT+ VIN 2 0.1 µF 0.1 µF 6 VOUT- SHDN 3 GND1 4 • -0.3 mV Input Offset Voltage • Automotive BMS Battery Pack Voltage Sensing Functional Diagram VDD1 • +/-0.5% (ACPL-C87BT) and +/-1% (ACPL-C87AT) Gain Tolerance @ 25° C SHIELD 5 • Isolation Interface for Temperature Sensing • General Purpose Voltage Sensing and Monitoring GND2 Figure 1. Functional Diagram 0.1 mF bypass capacitor must be connected between pin 1 and pin 4, and pin 5 and pin 8 as shown. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Functional Diagram (Cont.) VDD1 VDD2 VIN VOUT = VOUT+ − VOUTVOUT+ VIN 0−2V Isolation 0−2V VOUT- SHDN GND1 GND2 Figure 2. Functional Diagram 2 5V 15 V V+ MEV1S1505DC IN OUT Gate Driver 5V 1 nF R1 M 0.1 µF 20 kΩ 39 Ω Gate Driver R2 V- 0.1 µF R4 20 kΩ VOUT R5 20 kΩ 10 nF 1 nF 20 kΩ ACPL-C87AT/BT Figure 3. Typical Voltage Sensing Circuit 1 VDD1 VDD2 8 2 VIN VOUT+ 7 3 SHDN VOUT- 6 4 GND1 GND2 5 Figure 4. Package Pinout Pin Description Pin No. Pin Name Description Pin No. Pin Name Description 1 VDD1 Input power supply When VDD1 = 0, then VOUT+ = 0 V, VOUT- = 2.6 V 8 VDD2 Output power supply 2 VIN Voltage input, Full scale Range = 2.46 V 7 VOUT+ Positive output voltage 3 SHDN Shutdown (Active High) When active, then VOUT+ = 0 V, VOUT- = 2.6 V 6 VOUT- Negative output voltage 4 GND1 Input Side Ground 5 GND2 Output Side Ground 2 Ordering Information Option Surface Mount Part number (RoHS Compliant) Package ACPL-C87AT ACPL-C87BT -000E Stetched SO-8 -500E Tape & Reel X X X UL 5000 Vrms / 1 Minute rating IEC/EN/DIN EN 60747-5-5 X X 80 per tube X X 1000 per reel Quantity To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example: ACPL-C87AT-500E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with RoHS compliant. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawing (Stretched SO8) RECOMMENDED LAND PATTERN 5.850 ± 0.254 (0.230 ± 0.010) PART NUMBER DATE CODE 8 RoHS-COMPLIANCE INDICATOR 7 6 5 C87BT YWW EE 1 2 3 12.650 (0.498) 6.807 ± 0.127 (0.268 ± 0.005) 4 1.905 (0.075) EXTENDED DATECODE FOR LOT TRACKING 0.64 (0.025) 7° 3.180 ± 0.127 (0.125 ± 0.005) 0.381 ± 0.127 (0.015 ± 0.005) 0.200 ± 0.100 (0.008 ± 0.004) 1.270 (0.050) BSG 0.450 (0.018) 1.590 ± 0.127 (0.063 ± 0.005) 45° 0.750 ± 0.250 (0.0295 ± 0.010) 11.50 ± 0.250 (0.453 ± 0.010) 0.254 ± 0.100 (0.010 ± 0.004) Dimensions in millimeters and (inches). Figure 5. Package Outline Drawing 3 Note: Lead coplanarity = 0.1 mm (0.004 inches). Floating lead protrusion = 0.25mm (10mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Note: Non-halide flux should be used Regulatory Information The ACPL-C87AT and ACPL-C87BT are approved by the following organizations: UL CSA IEC/EN/DIN EN 60747-5-5 UL 1577, component recognition program up to VISO = 5kVRMS Approved under CSA Component Acceptance Notice #5. IEC 60747-5-5 EN 60747-5-5 DIN EN 60747-5-5 IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Description Symbol Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 450 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – IV I - IV I - IV I - III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 VIORM 1414 Vpeak Input to Output Test Voltage, Method b VIORM X 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 2651 Vpeak Input to Output Test Voltage, Method a VIORM X 1.6 = VPR, Type and Sample Test with tm = 10 sec, Partial discharge < 5 pC VPR 2262 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure, also see Figure 6. Case Temperature Input Current Output Power Ts IS, INPUT PS,OUTPUT 175 230 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS > 109 W OUTPUT POWER – PS, INPUT CURRENT - IS Maximum Working Insulation Voltage 700 PS (mW) IS (mW) 600 500 400 300 200 100 0 0 25 50 125 150 75 100 TS – CASE TEMPERATURE – °C Figure 6. Dependence of safety limiting values on temperature 4 175 200 Insulation and Safety Related Specifications Parameter Symbol Value Unit Conditions Minimum External Air Gap (External Clearance) L(101) 8.0 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.0 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. > 175 Volts DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group (DIN BDE0109) IIIa Material Group (DIN VDE 0110) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 150 °C Ambient Operating Temperature TA -40 125 °C Supply Voltages VDD1, VDD2 -0.5 6.0 Volts Input Voltage VIN -2.0 VDD1 + 0.5 Volts Shutdown Voltage VSD -0.5 VDD1 + 0.5 Volts Output Voltages VOUT+, VOUT- -0.5 VDD2 + 0.5 Volts Note Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature TA -40 125 °C Input Supply Voltage VDD1 4.5 5.5 Volts Output Supply Voltage VDD2 3.0 5.5 Volts Input Voltage VIN 0 2.0 Volts Shutdown Voltage VSD VDD1 – 0.5 VDD1 Volts 5 Notes Electrical Specifications Unless otherwise noted, all typical values at TA = 25 °C, VDD1 = VDD2 = 5 V, VIN = 0 to 2 V, VSD = 0 V; all Minimum/Maximum specifications are at recommended voltage supply conditions: 4.5V < VDD1 < 5.5V, 4.5V < VDD2 < 5.5V Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. 15 mA VSD = 0 V 18, 19 mA VSD = 5 V Note POWER SUPPLIES Input Supply Current IDD1 10.5 Input Supply Current (Shutdown Mode) IDD1(SD) 20 Output Supply Current IDD2 6.5 12 mA 18, 20 DC CHARACTERISTICS Gain (ACPL-C87BT, +/- 0.5%) G0 0.995 1 1.005 V/V TA = 25 °C, VIN = 0 – 2 V, VDD1 = VDD2 = 5.0 V 8 1 Gain (ACPL-C87AT, +/- 1%) G1 0.99 1 1.01 V/V TA = 25 °C, VIN = 0 – 2 V, VDD1 = VDD2 = 5.0 V 8, 11 1 Magnitude of Gain Change vs Temperature |dG/dTA| 25 ppm/°C TA = -40 °C to +125 °C 11 Magnitude of Gain Change vs VDD1 |dG/dVDD1| 0.05 %/V TA = 25 °C 12 Magnitude of Gain Change vs VDD2 |dG/dVDD2| 0.02 %/V TA = 25 °C 12, 13 Nonlinearity NL 0.05 0.12 % VIN = 0 to 2 V, TA = -40 °C to +125 °C 15, 16 Input Offset Voltage VOS -0.3 10 mV VIN is shorted to GND1, TA = 25 °C 7, 9, 10 Magnitude of Input Offset Change vs. Temperature |dVOS/dTA| 21 mV/°C VIN is shorted to GND1, TA = -40 °C to +125 °C 7, 9 Full-Scale Differential Voltage Input Range FSR 2.46 V Referenced to GND1 Input Bias Current IIN mA VIN = 0 V Equivalent Input Impedance RIN 1000 MW Output Common-Mode Voltage VOCM 1.23 V VIN =0 V, VSD = 0 V VOUT+ Range VOUT+ VOCM+1.23 V VIN = 2.5 V VOUT - Range VOUT- VOCM-1.23 V VIN = 2.5 V Output Short-Circuit Current |IOSC| 30 mA VOUT+ or VOUT-, shorted to GND2 or VDD2 Output Resistance ROUT 36 W VIN = 0 V -10 INPUTS AND OUTPUTS 6 -0.1 -0.001 0.1 22 22 Electrical Specifications (continued) Unless otherwise noted, all typical values at TA = 25 °C, VDD1 = VDD2 = 5 V, VIN = 0 to 2 V, VSD = 0 V; all Minimum/Maximum specifications are at recommended voltage supply conditions: 4.5V < VDD1 < 5.5V, 4.5V < VDD2 < 5.5V Parameter Symbol Min. Typ. Max. Unit Test Conditions Fig. Note 5 AC CHARACTERISTICS Small-Signal Bandwidth (-3 dB) f–3 dB 100 VOUT Noise NOUT 1.3 mVRMS VIN = 2 V; BW = 1 kHz 23 Input to Output Propagation Delay (10%-10%) tPD10 2.2 3.5 ms VIN = 0 to 2 V Step 21, 26 Input to Output Propagation Delay (50%-50%) tPD50 3.7 6.0 ms VIN = 0 to 2 V Step 21, 26 Input to Output Propagation Delay (90%-90%) tPD90 5.3 7.0 ms VIN = 0 to 2 V Step 21, 26 Output Rise / Fall Time (10%-90%) tR/F 2.7 4.0 ms Step Input Shutdown Time tSD 25 ms Shutdown Recovery Time tON 150 ms Power Supply Rejection PSR -78 dB 1 Vp-p, 1 kHz sine wave ripple on VDD1, differential output Common Mode Transient Immunity CMTI 15 kV/μs VCM = 1 kV, TA = 25 °C 10 kHz 25 25 24 2 Package Characteristics Unless otherwise noted, all typical values are at TA = 25 °C; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Input-Output Momentary Withstand Voltage * VISO 5000 Input-Output Resistance RI-O Input-Output Capacitance CI-O * Typ. Max. Units Test Conditions VRMS RH < 50%, t = 1 min., TA = 25 °C Fig. Note 3, 4 1014 W VI-O = 500 VDC 3 0.5 pF f =1 MHz 3 The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. Notes: 1. Gain is defined as the slope of the best-fit line of differential output voltage (VOUT+ - VOUT-) versus input voltage over the nominal range, with offset error adjusted. 0.5% Gain tolerance for ACPL-C87BT and 1% tolerance for ACPL-C87AT. 2. Common mode transient immunity (CMTI) is tested by applying a fast rising/falling voltage pulse across GND1 (pin 4) and GND2 (pin 5). The output glitch observed is less than 0.2 V from the average output voltage for less than 1 ms. 3. Device considered a two terminal device: pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted together. 4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000 VRMS for 1 second. 5. Noise is measured at the output of the differential to single ended post amplifier. 7 Typical Characteristic Plots and Test Conditions All ±3s plots are based on characterization test result at the point of product release. For guaranteed specification, refer to the respective Electrical Specifications section. VDD1 VDD1 VDD2 0.1 µF 1 8 2 7 3 ACPL-C87AT/BT 0.1 µF 6 GND1 ACPL-C87AT/BT 0.1 µF 6 V VOLTMETER 5 GND2 0 +3 SIGMA MEAN -3 SIGMA -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 Vos - INPUT OFFSET VOLTAGE - mV Vos - INPUT OFFSET VOLTAGE - mV 7 Figure 8. Gain and Nonlinearity Test Circuit 120 vs Vdd1 vs Vdd2 -1 -2 -3 -4 -5 -6 -7 4.5 140 4.75 5 5.25 VDD - SUPPLY VOLTAGE - V 5.5 Figure 10. Input Offset vs Supply Voltage 1.003 1.006 1.004 vs Vdd1 vs Vdd2 1.002 1.002 1.000 G - GAIN - V/V G - GAIN - V/V 2 GND1 GND2 Figure 9. Input Offset Voltage vs Temperature 0.998 0.996 0.994 MEAN +3 SIGMA - 3 SIGMA 0.992 0.990 -20 0 Figure 11. Gain vs Temperature 8 8 4 Figure 7. Input Offset Voltage Test Circuit 0.988 -40 1 3 V VOLTMETER 5 4 10 8 6 4 2 0 -2 -4 -6 -8 -10 -40 0.1 µF VIN VDD2 20 40 60 80 TA - TEMPERATURE - °C 1.001 1.000 0.999 0.998 100 120 140 0.997 4.5 4.75 5 5.25 VDD - SUPPLY VOLTAGE - V Figure 12. Gain vs Supply Voltage 5.5 1.006 1.002 vs Vdd1 vs Vdd2 NL - NON LINEARITY - % 1.004 G - GAIN - V/V 0.08 VDD2 = 3.3 V VDD2 = 5 V VDD2 = 5.5 V 1.000 0.998 0.996 0.994 0.992 0.07 0.06 0.05 0.990 0.988 -40 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 Figure 13. Gain vs Temperature at Different VDD2 0.12 0.12 0.10 0.10 0.08 0.06 0.04 MEAN +3 SIGMA -3 SIGMA 0.02 0.00 -40 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 5.5 VDD2 = 3.3 V VDD2 = 5.0 V VDD2 = 5.5 V 0.06 0.04 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 140 Figure 16. Nonlinearity vs Temperature at Different VDD2 12 VOUT+ VOUT- 2 IDD - SUPPLY CURRENT - mA Vo - OUTPUT VOLTAGE - V 5 5.25 VDD - SUPPLY VOLTAGE - V 0.08 0.00 -40 140 2.5 1.5 1 0.5 0 1 2 3 4 VIN - INPUT VOLTAGE - V Figure 17. Output Voltage vs Input Voltage 9 4.75 0.02 Figure 15. Nonlinearity vs Temperature 0 4.5 Figure 14. Nonlinearity vs Supply Voltage NL - NON LINEARITY - % NL - NON LINEARITY - % 0.04 140 5 6 IDD1 IDD2 10 8 6 4 0 0.5 1 1.5 VIN - INPUT VOLTAGE - V Figure 18. Typical Supply Current vs Input Voltage. 2 2.5 9 IDD2 - OUTPUT SUPPLY CURRENT - mA IDD1 - INPUT SUPPLY CURRENT - mA 14 13 12 11 10 9 8 VDD1 = 4.5 V VDD1 = 5.0 V VDD1 = 5.5 V 7 6 -40 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 -40 5 0 4 3 2 TPD 50-10 TPD 50-50 TPD 50-90 1 -20 0 20 40 60 80 TA - TEMPERATURE - °C 100 120 VIN = 2.0 V Phase (deg) 10 8 6 4 2 0 20 40 60 FILTER BANDWIDTH - kHz Figure 23. AC Noise vs Filter Bandwidth 20 40 60 80 TA - TEMPERATURE - °C 100 120 140 -1 -1.5 0 0.5 1 1.5 VIN - INPUT VOLTAGE - V 2 2.5 Figure 22. Input Current vs Input Voltage 12 0 0 -0.5 -2 140 16 14 -20 Figure 20. Typical Output Supply Current vs Temperature at Different VDD2 IIN - INPUT CURRENT - nA Tp - PROPAGATION DELAY - µs VDD2 = 3.3 V VDD2 = 5.0 V VDD2 = 5.5 V 5 0.5 Figure 21. Typical Propagation Delay vs Temperature AC NOISE - mVRMS 6 6 0 -40 10 7 4 140 Figure 19. Typical Input Supply Current vs Temperature at Different VDD1 8 80 100 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 1000 10000 Figure 24. Phase vs Frequency 100000 Frequency (Hz) 1000000 5V 5V 1 nF 20 kΩ 39 Ω 0.1 µF 0.1 µF 20 kΩ 1 nF ACPL-C87AT/BT + – VCM Figure 25. Common Mode Transient Immunity Test Circuit VSHDN VIN 5V 0V 2V 0V 2.4 V VOUT+ – VOUT- tSD tON 0V -2.4 V Figure 26. Shutdown Timing Diagram 2V VIN 0V 2V 90% 1V VO+ – VO- 50% 10% 0V TPD10 TPD50 TPD90 Figure 27. Propagation Delay Diagram 11 VOUT 20 kΩ 10 nF 20 kΩ Application Information The circuit shown in the Figure 28 is a high voltage sensing application using ACPL-C87AT/BT (isolation amplifier) and ACPL-M49T (optocoupler). The high voltage input is sensed by the precision voltage divider resistors R1 and sensing resistor R2. The ratio of the voltage divider is determined by the allowable input range of the isolation amplifier (0 to 2 V). This small analog input goes through a 39 W and 10 nF anti aliasing filter (ACPL-C87AT/BT utilize SD modulation). Inside the isolation amplifier: the analog input signal is digitized and optically transmitted to the output side of the amplifier. The detector will then decode the signal and converted back to analog signal. The output differential signals of ACPL-C87AT/BT go through an op-amp to convert the differential signals to a single ended output. SWITCH MODE POWER SUPPLY V+ R12 10 kΩ Battery Cells C7 1 nF R13 20 Ω ACPL-M49T R1 C4 0.1 µF C2 0.1 µF R2 V- R7 20 kΩ R4 20 kΩ VOUT R3 39 Ω C1 10 nF ACPL-C87AT/BT M C U R5 20 kΩ C6 R6 20 kΩ 1 nF Vref 0.1 µF Figure 28. Typical Application Circuit for Battery Voltage Sensing Bypass Capacitor 0.1 mF bypass capacitor must be connected as near as possible between VDD1 to GND1 and VDD2 to GND2 (Figure 29). C2 0.1 µF C4 0.1 µF Anti-aliasing Filter 39 W resistor and 10 nF capacitor are recommended to be connected to the input (VIN) as anti-aliasing filter because ACPL-C87AT/BT uses sigma data modulation (Figure 30). The value of the capacitor must be greater than 1 nF and bandwidth must be less than 410 kHz. ACPL-C87AT/BT Fig 29. Bypass Capacitors C2, C4 R3 39 Ω R4 20 kΩ C1 10 nF R5 20 kΩ ACPL-C87AT/BT Fig 30. Anti aliasing Filter C1 , R3 12 ACPL-C87AT/BT Fig 31. Loading Resistors R4, R5 Designing the input resistor divider 1. Choose the sensing current (Isense) for bus voltage. E.g., 1 mA 2. Determine R2, Voltage Voltage input input range range = 22 VV = 2 kΩ RR22 = = 1 mA = 2 kΩ 2= IISENSE SENSE 1 mA SENSE 3. Determine R1 using voltage divider formula: RR22 2 (V+ (V+ –– V-) V-) •• R11 + R22 = = Voltage Voltage input input range, range, or or R1 + R2 (V+ (V+ –– V-) V-) •• RR222 – R2 RR11 = 1 = Voltage input range – R2 2 Voltage input range where (V+ – V-) is the high voltage input , E.g.: 0 to 600 V, (600 (600 VV –– 00 V) V) •• 22 kΩ kΩ – 2 kΩ = 598 kΩ RR11 = – 2 kΩ = 598 kΩ 1= 22 VV To reduce the voltage stress of a sole resistor, R1 can be a series of several resistors. Post Amplifier Circuit Shutdown Function The output of ACPL-C87AT/BT is a differential output (VOUT+ and VOUT- pins). A post amplifier circuit is needed to convert the differential output to single ended output with a reference ground. The post amplifier circuit can also be configured to establish a desired gain if needed. It also functions as filter to high frequency chopper noise. The bandwidth can be adjusted by changing the feedback resistor and capacitor (R7 and C7). Adjusting this bandwidth to a minimum level helps minimize the output noise. ACPL-C87AT/BT has a shutdown function to disable the device and make the output (VOUT+ - VOUT-) low. A voltage of 5V on SHDN pin will shutdown the device producing an output (VOUT+ - VOUT-) of -2.6 V. To be able to control the SHDN function (example, from microprocessor), an optocoupler (ACPL-M49T) is used. Post op-amp resistive loading (R4, R5) should be equal or greater than 20 kW (Figure 31). Resistor values lower than this can affect the overall system error due to output impedance of isolation amplifier. The application circuit in Figure 28 features two op-amps to improve the linearity at voltage near 0 V caused by the limited headroom of the amplifier. The second op-amp can set the reference voltage to above 0 V. Total System Error Total system error is the sum of the resistor divider error, isolation amplifier error and post amplifier error. The resistor divider error is due to the accuracy of the resistors used. It is recommended to use high accuracy resistor of 0.1%. Post Amplifier Error is due to the resistor matching and the voltage offset characteristic which can be found on the supplier datasheet. Isolation Amplifier Error is shown in the table below: Isolation Amplifier Error Calculation 3s distribution or specification * Typical ACPL-C87AT ACPL-C87BT Fig A Error due to offset voltage (25 °C) 0.015% 0.5% 0.5% Offset Voltage /Recommended specs input voltage range (2.0 V) B Error due to offset voltage drift (across temperature) 0.1% 0.4% 0.4% Offset Voltage /Recommended input voltage range (2.0 V) C Error due to gain tolerance (25 °C) 0% 1% 0.5% D Error due to gain drift (across temperature) 0.25% 0.8% 0.8% 0.12% 0.12% F Total uncalibrated error (A+B+C+D+E) 0.415% 2.82% 2.32% G Total offset calibrated error (F – A) 0.4% 2.32% 1.82% H Total gain and offset calibrated error (G – C) 0.4% 1.32% 1.32% E Error due to Nonlinearity (across temperature) 0.05% * 3s distribution is based on corner wafers. 13 specs specs PCB Layout Recommendations Bypass capacitor C2 and C4 must be located close to ACPL-C87xT Pins 1 and Pin 8 respectively. Grounded pins of C4 and C5 can be connected by vias through the respective ground layers. If the design has multiple layers, a dedicated layer for ground is recommended for flexibility in component placement. GND1 and GND2 must be totally isolated in the PCB layout (Figure 33). Distance of separation depends on the high voltage level of the equipment. The higher the voltage level the larger the distance of separation needed. Designers can refer to specific IEC standard of their equipment for the creepage/clearance requirements. Anti aliasing filters R3 and C1 also need to be connected as close as possible to Pin 2 of ACPL-C87AT/BT. See Figure 32 for actual component placement of the anti-aliasing filter and bypass capacitors. R1 which is directly connected to the high voltage input must have sufficient clearance with the low voltage components. Clearance depends on the high voltage level of the input. Designers can refer to specific IEC standards of their equipment for the clearance requirements. R1 (Series Resistors) BYPASS CAPACITORS Isolation Clearance GND1 ANTI ALIASING FILTER GND2 ACPL-C87AT/BT Figure 32. Component Placement Recommendation For product information and a complete list of distributors, please go to our web site: Figure 33. Bottom Layer Layout Recommendation www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. AV02-3563EN - August 2, 2013