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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN604 Offline Quasi-Resonant PWM Controller The FAN604 is an advanced PWM controller aimed at achieving power density of ≥10W/in3 in universal input range AC/DC flyback isolated power supplies. It incorporates Quasi-Resonant (QR) control with proprietary Valley Switching with a limited frequency variation. QR switching provides high efficiency by reducing switching losses while Valley Switching with a limited frequency variation bounds the frequency band to overcome the inherent limitation of QR switching. FAN604 features mWSaver® burst mode operation with extremely low operating current (300 μA) and significantly reduces standby power consumption to meet the most stringent efficiency regulations such as Energy Star’s 5-Star Level and CoC Tier II specifications. FAN604 includes several user configurable features aimed at optimizing efficiency, EMI and protections. FAN604 has a wide blanking frequency range that improves light load efficiency and eliminating audio noise for adaptive application. It incorporates user-configurable constant current reference, which allows controlling the maximum output current from primary-side, thereby optimizing transformer design to improve the overall efficiency. It also includes several rich programmable protection features such as over-voltage protection (OVP), precise constant output current regulation (CC). MARKING DIAGRAM 10 ZXYTT 604 TM 1 Z: Assembly Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package Type (M=SOIC) M: Manufacture Flow Code PIN CONNECTIONS Features www.onsemi.com Higher Average Efficiency by Quasi-Resonant Switching Operation with Wide Blanking Time Range Wide Input and Output Conditions Achieve High Power Density Power Supply Optimization Transformer Design for Adaptive Charger Application User Configurable Constant Current Reference (CCR) to Limit the Maximum Output Current Precise Constant Output Current Regulation with Programmable Line Compensation mWSaver® Technology for Ultra Low Standby Power Consumption (<20 mW) Forced and Inherent Frequency Modulation of Valley Switching for Low EMI Emissions and Common Mode Noise Built-In and User Configurable Over-Voltage Protection (OVP), Under-Voltage Protection (UVP) and Over-Temperature Protection (OTP) Programmable Over-Temperature-Protection through External NTC Resistor Fully Programmable Brown-In and Brownout Protection Built-In High-Voltage Startup to Reduce External Components HV 1 10 GND NC 2 9 FB CS 3 8 SD 7 CCR 6 VS FAN604MX GATE 4 VDD 5 (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. Typical Applications Battery Charges for Smart Phones, Feature Phones, and Tablet PCs AC-DC Adapters for Portable Devices or Battery Chargers that Require CV/CC Control © Semiconductor Components Industries, LLC, 2013 March 2017- Rev. P0 1 FAN604 Publication Order Number: FAN604 RSNS CSNP TX LF DR CSNP Fuse Choke AC IN RSNP Ns CO RBias1 RBias2 Bridge XC DSNP RHV2 Photo coupler HV GATE RGF FAN604 SD Shunt Regulator DG CS Na RCS_COMP CCR CFB RSD NTC VDD GND CCCR CComp2 RF1 RGR FB Photo coupler VO RHV1 CBLK2 CBLK1 Np RCS CCSF VS DAUX RCCR RVS1 CVDD CVS Figure 1 FAN604 Typical Application www.onsemi.com 2 RVS2 RComp CComp1 RF2 FAN604 HV 1 HV Start-up HV Burst/Green Mode Brown IN VDD UVLO VDD UVLO 17.2V/5.5V VDD UVLO VNVS VFB Brown OUT VDD OVP Fault VS UVP Fault VS OVP Fault OTP Fault VCS Fault SD Fault Auto-Restart Protection VDD 5 VDD OVP Fault Debounce VVDD-OVP GND 10 VS_SH S/H VS OVP Fault VS Protection S/H = Sampling and Hold D VD 6 VS Valley Detection Forced Frequency Modulation VDD Maximum On Time VS UVP Fault OSC Driver Control Q CLK VFB C 4 GATE 3 CS 7 CCR Q VNVS tDIS 5V ISD SD 8 VCS Fault SD Fault VSD-TH CS Protection VCS-LIM ICOMP VCS 5.25V VCS VCS Peak Current LEB 5V ZFB AV-CC AV 9 FB 5V IO Estimator tDIS VCCR ICCR Figure 2 FAN604 Block Diagram PIN FUNCTION DESCRIPTION Description Pin No. Pin Name 1 HV High Voltage. This pin connects to DC bus for high-voltage startup. 2 NC No Connect. 3 CS Current Sense. This pin connects to a current-sense resistor to sense the MOSFET current for Peak-Current-Mode control for output regulation. The current sense information is also used to estimate the output current for CC regulation. 4 GATE PWM Signal Output. This pin has an internal totem-pole output driver to drive the power MOSFET. The gate driving voltage is internally clamped at 7.5V. 5 VDD Power Supply. IC operating current and MOSFET driving current are supplied through this pin. This pin is typically connected to an external VDD capacitor. 6 VS 7 CCR 8 SD Shut Down. This pin is implemented for external over-temperature-protect by connecting NTC thermistor. 9 FB Feedback. Typically Opto-Coupler is connected to this pin to provide feedback information to the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation. 10 GND Voltage Sense. The VS voltage is used to detect resonant valleys for quasi-resonant switching. This pin detects the output voltage information and diode current discharge time based on the auxiliary winding voltage. It also senses input voltage for Brown-out protection. Constant Current Reference. This pin connects to external resistor to program the reference voltage of constant output current. Ground. www.onsemi.com 3 FAN604 MAXIMUM RATINGS Rating Symbol Value Unit Maximum Voltage on HV Pin VHV 500 V DC Supply Voltage VVDD 30 V Maximum Voltage on GATE Pin VGETE -0.3 to 30 V Maximum Voltage on Low Power Pins (Except Pin 1, Pin 4, Pin 5) Vmax -0.3 to 6 V Power Dissipation (TA=25C) PD 850 mW Thermal Resistance (Junction-to-Ambient) θJA 140 C/W Thermal Resistance (Junction-to-Top) ΨJT 13 C/W TJ -40 to +150 C TSTG -40 to +150 C Operating Junction Temperature Storage Temperature Range Human Body Model, JEDEC:JESD22_A114 2.0 (Except HV Pin) ESD Charged Device Model, JEDEC:JESD22_C101 0.75 (Except HV Pin) 1. All voltage values, except differential voltages, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD ratings including HV pin: HBM=2.0 kV, CDM=0.75kV. kV RECOMMENDED OPERATING RANGES Rating Symbol Min Max Unit HV Pin Supply Voltage VHV 50 400 V VDD Pin Supply Voltage VVDD 6 25 V VS Pin Supply Voltage VVS 0.65 2.3 V CS Pin Supply Voltage VCS 0 0.9 V FB Pin Supply Voltage VFB 0 5.25 V CCR Pin Supply Voltage VCCR 0.2 1.7 V SD Pin Supply Voltage VSD 0 5 V Operating Temperature TA -40 +85 C 4. The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance. ON does not recommend exceeding them or designing to Absolute Maximum Ratings. www.onsemi.com 4 FAN604 ELECTRICAL CHARACTERISTICS For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit IHV 1.2 2.0 10 mA IHV-LC 0 0.8 10 μA HV Section Supply Current Drawn from HV Pin VHV=120 V, VDD=0 V Leakage Current Drawn from HV Pin VHV=500 V, VDD=VDD-OFF+1 V Brown-In Threshold Voltage RHV=150kΩ, VIN =80VAC VBrown-IN 100 110 120 V Turn-On Threshold Voltage VDD Rising VDD-ON 15.3 17.2 18.7 V Turn-Off Threshold Voltage VDD Falling VDD-OFF 5.0 5.5 5.7 V Threshold Voltage for HV Startup TJ = 25C VDD-HV-ON 4.1 4.7 5.4 V Startup Current VDD=VDD-ON-0.16 V IDD-ST - 300 450 μA Operating Supply Current VCS=5.0 V, VVS=3 V, VFB=3 V CGATE=1nF IDD-OP - 2 3 mA Burst-Mode Operating Supply Current VCS=0.3 V, VVS=0 V, VFB=0 V; VDD=VDD-ONVDD-OVP10 V, CGATE=1nF IDD-Burst - 300 600 μA VDD Over-Voltage-Protection Level TJ = 25C VVDD-OVP 27.5 29.0 29.5 V tD-VDDOVP - 70 105 μs VDD Section VDD Over-Voltage-Protection Debounce Time Oscillator Section Maximum Blanking Frequency VFB > VFB-BNK-H fBNK-MAX 125 130 135 kHz Minimum Blanking Frequency VFB < VFB-BNK-L fBNK-MIN 16.5 18.5 20.5 kHz Minimum Frequency VVS = 1V fOSC-MIN 15 17 19 kHz ΔtFM-Range 210 265 310 ns ΔtFM-Period 2.1 2.5 2.9 ms FB Pin Input Impedance ZFB 39 42 45 kΩ Internal Voltage Attenuator of FB Pin (Note 5) AV 1/3 1/3.5 1/4 V/V FB Pin Open VFB-Open 4.55 5.25 5.90 V TJ = 25C VFB-BNK-H 2.10 2.25 2.40 V TJ = 25C VFB-BNK-L 1.10 1.25 1.40 V VFB Rising VFB-Burst-H 0.65 0.75 0.85 V VFB Falling VFB-Burst-L 0.60 0.70 0.80 V Forced Frequency Modulation Range VFB> VFB-Burst--H Forced Frequency Modulation Period Feedback Input Section FB Pin Pull-Up Voltage Frequency Foldback Starting/Stopping VFB FB Threshold to Enable/Disable Gate Drive in Burst Mode www.onsemi.com 5 FAN604 ELECTRICAL CHARACTERISTICS (CONTINUED) For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit IVS-MAX - - 3 mA Voltage-Sense Section Maximum VS Source Current Capability VS Sampling Blanking Time 1 after GATE Pin Pull-Low VFB Falling and VFB < 2.0V tVS-BNK1 0.84 1.0 1.23 μs VS Sampling Blanking Time 2 after GATE Pin Pull-Low VFB Rising and VFB > 2.2V tVS-BNK2 1.45 1.8 2.15 μs Delay from VS Voltage Zero Crossing to PWM ON (Note 5) VVS=0V, CGATE=1nF tZCD-to PWM 175 ns VS Source Current Threshold to Enable Brown-out IVS-Brown-Out 360 450 530 μA Brown-Out Debounce Time tD-Brown-Out 12.5 16.5 21 ms Output Over-Voltage-Protection with Vs Sampling Voltage VVS-OVP 2.2 2.3 2.4 V Output Over-Voltage-Protection Debounce Pulse Counts NVS-OVP - 2 - Pulse VVS-UVP 0.625 0.650 0.675 V Output Over-Voltage-Protection Debounce Pulse Counts NVS-UVP - 2 - Pulse Output Under-Voltage Protection Blanking Time at start-up tVS-UVP-BLANK 25 40 55 ms NVDD-Hiccup - 2 - Cycle TOTP - 140 - C Output Under-Voltage-Protection with Vs Sampling Voltage Auto-Restart Cycle Counts when Extend AutoRestart Mode is triggered TJ = 25C VVS < VVS-UVP Over-Temperature Protection Section Threshold Temperature for Over-Temperature-Protection (Note 5) Current-Sense Section Current Limit Threshold Voltage FB Pin Open VCS-LIM 0.865 0.890 0.915 V High Threshold Voltage of Current Sense VFB > VFB-BNK-L VCS-IMIN-H 0.39 0.44 0.51 V Middle Threshold Voltage of Current Sense VFB = 1V, TJ = 25C VCS-IMIN-M 0.30 0.35 0.40 V Low Threshold Voltage of Current Sense VFB < VFB-Burst-H, TJ = 25C VCS-IMIN-L 0.21 0.25 0.29 V GATE Output Turn-Off Delay (Note 5) tPD - 50 100 ns Leading-Edge Blanking Time (Note 5) tLEB - 150 200 ns www.onsemi.com 6 FAN604 ELECTRICAL CHARACTERISTICS (CONTINUED) For typical values TJ = 25°C, for min/max values TJ = -40°C to 125°C, VDD = 15 V; unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit ISD 90 103 110 μA VSD-TH 0.95 1.00 1.05 V tD-SD 200 400 600 μs ZSD-TH 8.5 10 11 kΩ VSD-TH-ST 1.30 1.35 1.40 V tSD-ST 0.4 1.0 1.6 ms Shut-Down Function Section SD Pin Source Current Threshold Voltage for Shut-Down Function Enable Debounce Time for Shut-Down Function Ratio between threshold voltage and source current Hysteresis of Threshold Voltage for ShutDown Function Enable Duration of VSD-TH-ST at startup Constant Current Correction Section High Line Compensation Current VIN = 264 Vrms ICOMP-H 90 100 110 μA Low Line Compensation Current VIN = 90 Vrms ICOMP-L 32 36 40 μA ICCR 18.2 20 21.8 μA Constant Current Estimator Section CCR Pin Source Current Constant Current Control Reference Offset Voltage (Note 5) VREF_CC_Offset 0.8 V Peak Value Amplifying Gain (Note 5) APK 3.6 V/V FB CC Pull-Up Voltage CC (Note 5) VFB-CC-Open 4.0 V AV-CC 0.444 V/V Internal Voltage Attenuator of FB CC (Note 5) GATE Section Gate Output Voltage Low VGATE-L 0 - 1.5 V Internal Gate PMOS Driver ON VDD Falling VDD-PMOS-ON 7.0 7.5 8.0 V Internal Gate PMOS Driver OFF VDD Rising VDD-PMOS-OFF 9.0 9.5 10.0 V Rising Time VCS=0 V, VS=0 V, CGATE=1nF tr 100 135 180 ns Falling Time VCS=0 V, VS=0 V, CGATE=1nF TJ = 25C tf 30 50 70 ns Gate Output Clamping Voltage VDD=25 V VGATE-CLAMP 6.8 7.5 8.2 V Maximum On Time VFB=3V, VCS=0.3V tON-MAX 20 22 25 μs 5. Design guaranteed. www.onsemi.com 7 FAN604 TYPICAL CHARACTERISTICS 1.05 1.05 Normalized 1.1 Normalized 1.1 1 0.95 0.95 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 3 Turn-On Threshold Voltage Figure 4 Turn-Off Threshold Voltage (VDD-ON) vs. Temperature (VDD-OFF) vs. Temperature 1.1 1.1 1.05 1.05 Normalized Normalized 0.9 -40℃ -30℃ -15℃ 1 0.95 1 0.95 0.9 -40℃ -30℃ -15℃ 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 5 VDD Over Voltage-Protection Level Figure 6 Brown-In Threshold Voltage (VVDD-OVP) vs. Temperature (VBrown-IN) vs. Temperature 1.1 1.1 1.05 Normalized 1.05 Normalized 1 1 1 0.95 0.95 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 8 Minimum Blanking Frequency Figure 7 Maximum Blanking Frequency (fBNK-MIN) vs. Temperature (fBNK-MAX) vs. Temperature www.onsemi.com 8 1.1 1.1 1.05 1.05 Normalized Normalized FAN604 1 0.95 0.95 0.9 -40℃ -30℃ -15℃ 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 10 Frequency Foldback Stopping VFB (VFB-BNK-H) vs. Temperature (VFB-BNK-L) vs. Temperature 1.1 1.1 1.05 1.05 1 0.95 1 0.95 0.9 -40℃ -30℃ -15℃ 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 11 VS Sampling Blanking Time 1 Figure 12 VS Sampling Blanking Time 2 (tVS-BNK1) vs. Temperature (tVS-BNK2) vs. Temperature 1.1 1.1 1.05 Normalized 1.05 Normalized 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 9 Frequency Foldback Starting VFB Normalized Normalized 1 1 1 0.95 0.95 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 14 Output Under-Voltage Protection Figure 13 Output Over-Voltage-Protection (VVS-UVP) vs. Temperature (VVS-OVP) vs. Temperature www.onsemi.com 9 1.1 1.1 1.05 1.05 Normalized Normalized FAN604 1 0.95 0.95 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 15 Current Limit Threshold Voltage Figure 16 High Threshold Voltage of Current Sense (VCS-LIM) vs. Temperature (VCS-IMIN-H) vs. Temperature 1.1 1.1 1.05 1.05 Normalized Normalized 0.9 -40℃ -30℃ -15℃ 1 0.95 1 0.95 0.9 -40℃ -30℃ -15℃ 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 17 Ratio between Threshold Voltage Figure 18 During of VSD-TH-ST at startup and Source Current (ZSD-TH) vs. Temperature (tSD-ST) vs. Temperature 1.1 1.1 1.05 1.05 Normalized Normalized 1 1 0.95 1 0.95 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) 0.9 -40℃ -30℃ -15℃ 0℃ 25℃ 50℃ 75℃ 85℃ 100℃ 125℃ Temperature ( C) Figure 19 CCR Pin Source Current Figure 20 Maximum On Time (ICCR) vs. Temperature (tON-MAX) vs. Temperature www.onsemi.com 10 FAN604 APPLICATIONS INFORMATION FAN604 is an offline PWM controller which operates in a quasi-resonant (QR) mode and significantly enhances system efficiency and power density. Its control method is based on the load condition (valley switching with fixed blanking time at heavy load and valley switching with variable blanking time at medium load) to maximize the efficiency. It offers constant output voltage (CV) regulation through opto-coupler feedback circuitry. Line voltage compensation gain can be programmed by using an external resistor to minimize the effect of line voltage variation on output current regulation due to turnoff delay of the gate drive circuit. FAN604 incorporates HV startup and accurate brown-in through HV pin. The brown-in voltage is programmed by using an external HV pin resistor. The constant current regulation (CCR), which sets the maximum output current level, is programmable via an external resistor connected to the CCR pin. Protections such as VDD Over-Voltage Protection (VDD OVP), VS Over-Voltage Protection (VS OVP), VS UnderVoltage Protection (VS UVP), internal Over-Temperature Protection (OTP), Brownout protection and externally triggered shut-down (SD) function improve reliability. upper limit of the blanking frequency varies from fBNKMAX as load decreases where the blanking frequency reduction stop point is fBNK-MIN. For the light load condition (5%~25%)), the blanking time for the valley detection is fixed such that the switching time is between fBNK-MIN and fBNK-MIN + tresonance and primary side peak current will be modulated by the function of VCS-IMN modulation, as shown in Figure 22 Burst Mode Operation Figure 21 shows when VFB drops below VFB-Burst-L, the PWM output shuts off and the output voltage drops at a rate which is depended on the load current level. This causes the feedback voltage to rise. Once VFB exceeds VFB-Burst-H, FAN604 resumes switching. When the FB voltage drops below the corresponding VCS-IMIN-L, the peak currents in switching cycles are limited by VCS-IMINL regardless of FB voltage. Thus, more power is delivered to the load than required and once FB voltage is pulled low below VFB-Burst-L, switching stops again. In this manner, the burst mode operation alternately enables and disables switching of the MOSFET to reduce the switching losses. Basic Operation Principle Output Voltage Quasi-resonant switching is a method to reduce primary MOSFET switching losses low line is more effective. In order to perform QR turn-on of the primary MOSFET, the valley of the resonance occurring between transformer magnetizing inductance (Lm) and MOSFET effective output capacitance (Coss-eff) must be detected. COSS-eff COSSMOSFET Ctrans C parasitic (eq. 1) VCS-IMIN-L VFB-Burst-H VFB-Burst-L VFB Figure 21 Burst-Mode Operation t resonance 2 Lm COSS eff (eq. 2) For heavy load condition (50%~100% of full load), the blanking time for the valley detection is fixed such that the switching time is between 1/fBNK-MAX and 1/fBNK-MAX + tresonance and primary side peak current will be modulated by voltage level of feedback. For the medium load condition (25%~50% of full load), the blanking time is modulated as a function of load current such that the Deep Burst Mode FAN604 enters deep burst mode if FB voltage stays lower than VFB-Burst-L for more than tDeep-Burst-Entry (640 µs). Once FAN604 enters deep burst mode, the operating current is reduced to IDD-Burst (300 μA) to minimize power consumption. Once feedback voltage is more than VFBBurst-H, power-on-reset occurs within a time period of t DeepBurst-Exit (25 μs) and IC resumes switching with normal operating current, IDD-OP. VFB IPK fBNK-MAX =1/ tBNK-MIN tBNK tEXT tBNK tEXT tBNK tEXT fBNK-MIN = 1/tBNK-MAX VDS Fixed Blanking Time Modulated Blanking Time Figure 22 Frequency Fold-back Function www.onsemi.com 11 Fixed Blanking Time FAN604 Valley Detection Inherent and Forced Frequency Modulation There will be a logic propagation delay from VS ZeroCrossing Detection (VS-ZCD) to IC GATE turn on and a MOSFET gate drives propagation delay from GATE pin to MOSFET turn on. We can assume the sum of these propagation delays to be tZCD-to-PWM (175ns), as shown in Figure 23. However, if 1/2 tF is longer than tZCD-to-PWM, the switching occurs away from the valley causing higher losses. The time period of resonant ringing is dependent on Lm and Coss-eff. Typically, the time period of resonance ringing is around 1~1.5 μs depending on the system parameters. Hence, the switching may occur at a point different from the valley depending on the system. When PCB layout is poor, it may cause noise on the VS pin. The VS pin needs to be in parallel with the capacitor (CVS) less than 10 pF to filter the noise. Typically, the bulk capacitor of flyback converter has a longer charging time in low line than in high line. Thus, the voltage ripple (∆ VDC) in low line is higher as shown in Figure 24. This large ripple results in 4~6% variation of the switching frequency in low line for a valley switched converter, the switching frequency could vary accordingly. This frequency variation scatters EMI noise nearby frequency band, this is helpful to meet EMI requirement easily. Hence, the EMI performance in low line is satisfied. However, in high line, the ripple is very small and consequently the EMI performance for high line may suffer. In order to maintain good EMI performance for high line, forced frequency modulation is provided. FAN604 varies the valley switching point from 0 to ΔtFM-Range (265 ns) in every ΔtFM-Period (2.5 ms) as shown in Figure 25. Since the drain voltage at which the switching occurs does not change much with this variation, there is minimum impact on the efficiency. VAux VS VAUX VS Zero-Crossing Detect 0V NA RVS1 Zero-Crossing Detection VS RVS2 VD tON CVS tZCD-to-PWM tD tF/2 tF GATE CVS < 10pF Figure 23 The Valley Detection Circuit and Behaior VDC LF VDC Bridge Diode AC IN CBLK1 CBLK2 Figure 24 Inherent Frequency Modulation VDS ½ tresonance nVO IPK VDS 265ns VDC Figure 25 Forced Frequency Modulation www.onsemi.com 12 FAN604 Output Voltage Detection I VS Figure 26 shows the VS voltage is sampled (VS-SH) after tVS-BNK of GATE turn-off so that the ringing does not introduce any error in the sampling. FAN604 dynamically varies tVS-BNK with load. At heavy load, tVSBNK=tVS-BNK1 (1.8 µs) when VFB > VFB-BNK-H. At light-load, tVS-BNK=tVS-BNK2 (1.0 µs) when VFB < VFB-BNK-L. This dynamic variation ensures that VS sampling occurs after ringing due to leakage inductance has stopped and before secondary current goes to zero. VS-SH VO RVS 2 NA N S RVS 1 RVS 2 (eq. 4) The IVS current, reflecting the line voltage information, is used for brownout protection and CC control correction weighting. CV / CC PWM Operation Principle Figure 27 shows a simplified CV / CC PWM control circuit of the FAN604. The Constant Voltage (CV) regulation is implemented in the same manner as the conventional isolated power supply, where the output voltage is sensed using a voltage divider and compared with the internal reference of the shunt regulator to generate a compensation signal. The compensation signal is transferred to the primary side through an opto-coupler and scaled down by attenuator AV to generate a COMV signal. This COMV signal is applied to the PWM comparator to determine the duty cycle. The Constant Current (CC) regulation is implemented internally with primary-side control. The output current estimator calculates the output current using the transformer primary-side current and diode current discharge time. By comparing the estimated output current with internal reference signal, a COMI signal is generated to determine the duty cycle. These two control signals, COMV and COMI, are compared with an internal sawtooth waveform (V SAW) by two PWM comparators to determine the duty cycle. Figure 27 illustrates the outputs of two comparators, combined with an OR gate, to determine the MOSFET turn-off instant. Either of COMV or COMI, the lower signal determines the duty cycle. During CV regulation, COMV determines the duty cycle while COMI is saturated to HIGH level. During CC regulation, COMI determines the duty cycle while COMV is saturated to HIGH level. (eq. 3) GATE tVS-BNK VBLK N A RVS 1 N P VS-SH VS Figure 26 Output Voltage Detection Line Voltage Detection The FAN604 indirectly senses the line voltage through the VS pin while the MOSFET is turned on, as illustrated in Figure 27 MOSFET turn-on period, the auxiliary winding voltage, VAUX, is proportional to the input bulk capacitor voltage, VBLK, due to the transformer coupling between the primary and auxiliary windings. During the MOSFET conduction time, the line voltage detector clamps the VS pin voltage to VS-Clamp (0 V), and then the current IVS flowing out of VS pin is expressed as: VBLK NP OSC ON TRIG OFF TRIG CC COMI GATE 4 PWM Control Logic Block CV Vo NS COMV CS ZCOMP VSAW 5V COMV GATE VSAW AV FB VAUX 0.8V CCR Z IO Estimator VAUX IVS COMI Line signal 0V Line Voltage Detector Zero Current Detector RVS1 NA -VAUX = VBLK (NA/NP) VS RVS2 VS VS-Clamp Figure 27 Simplified PWM Control Circuit and PWM Operation for CV/CC Regulation www.onsemi.com 13 FAN604 Primary-Side Constant Current Operation Line Voltage Compensation Figure 28 shows the key waveforms of a flyback converter operation in DCM. The output current is estimated by calculating the average of output diode current in one switching cycle: The output current estimation is also affected by the turnoff delay of the MOSFET as illustrated in Figure 29. The actual MOSFET’s turn-off time is delayed due to the MOSFET gate charge and gate driver’s capability, resulting in peak current detection error as IO 1 1 VCS PK Tdis N P 1 1 VREF _ CC N P E ff E ff 2 RCS TS NS 2 RCS APK N S (eq. 5) PK I DS When the diode current reaches zero, the transformer winding voltage begins to drop sharply and VS pin voltage drops as well. When VS pin voltage drops below the VS-SH by more than 500 mV, zero current detection of diode current is obtained. The output current can be programmed by setting the resistor as of CCR: RCCR N 1 1 (2 I O RCS APK S VREF _ CC _ Offset ) I CCR N P E ff VBLK tOFF .DLY Lm Where Lm is the transformer’s primary side magnetizing inductance. Since the output current error is proportional to the line voltage, the FAN604 incorporates line voltage compensation to improve output current estimation accuracy. Line information is obtained through the line voltage detector as shown in Figure 27. ICOMP is an internal current source, which is proportional to line voltage. The line compensation gain is programmed by using CS pin series resistor, RCS_COMP, depending on the MOSFET turn-off delay, tOFF.DLY. ICOMP creates a voltage drop, VOFFSET, across RCS_COMP. This line compensation offset is proportional to the DC link capacitor voltage, VBLK, and turn-off delay, tOFF.DLY. Figure 29 demonstrates the effect of the line compensation. (eq. 6) When PCB layout is poor, it may cause noise on the CCR pin. The CCR pin needs to be in parallel with the capacitor (CCCR) less than 4.7nF stabilizing the voltage against noise. TS Tdis TON VBLK NP OSC ON TRIG ICCR OFF TRIG RCCR VCS-PK GATE Idiode RCS_COMP CS ZCOMP RCS COMI CCR TQR Gate Vo NS 4 VREF_CC VCCR CCCR PWM Control Logic Block (eq. 7) 1.8µs VS-SH 500mV VS-SH 1.8µs Z VCS-PK CCCR : 1nF ~ 4.7nF IO Estimator APK RVS1 Tdis VS VAUX S/H Zero Current Detector VS Zero Current Detect NA APKVCS-PK RVS2 VREF_CC IO_ESTM Figure 28 Waveforms for Estimate Output Current ICOMP tOFF.DLY IDSRCS IDSRCS IDS-SHRCS VGS CS + VCS RCS_COMP CCSF CCSF < 20pF IDSPKRCS VOFFSET - IDSRCS IDSRCS Actual diode current Estimated diode current PK IDS NP/NS IDSRCS IDSRCS IDSRCS IDS-SHNP/NS tOFF.DLY GATE tOFF.DLY Tdis VCS VOFFSET-L VCS VOFFSET-H VGS VGS VGS Low Line High Line Figure 29 Effect of MOSFET Turn-off Delay and Line Voltage Compensation www.onsemi.com 14 IDS RCS 500mV FAN604 CCM Prevention The constant current calculation logic is based on flyback converter operation in DCM. The output current is estimated by calculating the average of output diode current in one switching cycle. If flyback converter goes into CCM operation, the discharge time of magnetizing current will be fixed. Once this discharge time is fixed, it will increase the average of output diode current. During the CC region, when output voltage becomes lower, the time that the magnetizing current decreases down to zero is longer, as shown in Figure 30. FAN604 provides the lower operation frequency that can be down to 17 kHz (fOSC-MIN) to prevent the system goes into CCM operation. Once switching starts, the internal HV startup circuit is disabled. During normal switching, the line voltage information is obtained from the IVS signal. Once the HV startup circuit is disabled, the energy stored in CVDD supplies the IC operating current until the transformer auxiliary winding voltage reaches the nominal value. Therefore, CVDD should be properly designed to prevent VDD from dropping below VDD-OFF threshold (typically 5.5 V) before the auxiliary winding builds up enough voltage to supply VDD. During startup, the IC current is limited to IDD-ST (300 μA). RHV 8 ILm HV RJFET =6.4kΩ S1 tON tD VDD.ON/ VDD.OFF tD CX1 tD UVP RLS=1.2kΩ nVO nVO nVO CC Region IO VDD - CV Region 5 + CX2 CV-CC Curve VO S2 VDD Good AC Line CDD VDD=VDD-ON(17.2V) + Brown IN Vref = 0.845V VIN VDS - Figure 31 HV Startup Circuit IHV fOSC-MIN Figure 30 The Minimum Operation Frequency 10mA HV Startup and Brown-In Figure 31 shows the high-voltage (HV) startup circuit. An Internal JFET provides a high voltage current source, whose characteristics are shown in Figure 32. To improve reliability and surge immunity, it is typical to use a RHV resistor between the HV pin and the bulk capacitor voltage. The actual current flowing into the HV pin at a given bulk capacitor voltage and startup resistor value is determined by the intersection point of characteristics I-V line and the load line as shown in Figure 32. During startup, the internal startup circuit is enabled and the bulk capacitor voltage supplies the current, I HV, to charge the hold-up capacitor, CVDD, through RHV. When the VDD voltage reaches VDD-ON, the sampling circuit shown in Figure 31 is turned on for tHV-det (100 µs) to sample the bulk capacitor voltage. Voltage across R LS is compared with reference which generates a signal to start switching. If brown-in condition is not detected within this time, switching does not start. Equation 8 can be used to program the brown-in of the system. If line voltage is lower than the programmed brown-in voltage, FAN604 goes in auto-restart mode. VIN RLS R JEFT RHV VREF RLS VBLK RHV (eq. 8) www.onsemi.com 15 2mA 1.2mA 100V 200V 300V 400V VBLK Figure 32 Characteristics of HV pin 500V VHV FAN604 Protections The FAN604 protection functions include VDD OverVoltage Protection (VDD-OVP), brownout protection, VS Over-Voltage Protection (VS-OVP), VS UnderVoltage Protection (VS-UVP), and IC internal OverTemperature Protection (OTP). The VDD-OVP, brownout protection, VS-OVP and OTP are implemented with Auto-Restart mode. The VS-UVP is implemented with Extend Auto-Restart mode. When the Auto-Restart Mode protection is triggered, switching is terminated and the MOSFET remains off, causing VDD to drop because of IC operating current IDD-OP (2 mA). When VDD drops to the VDD turn-off voltage of VDD-OFF (5.5 V), operation current reduces to IDD-Burst (300 µA). When the VDD voltage drops further to VDD-HV-ON, the protection is reset and the supply current drawn from HV pin begins to charge the VDD hold-up capacitor. When VDD reaches the turn-on voltage of VDD-ON (17.2 V), the FAN604 resumes normal operation. In this manner, the Auto-Restart mode alternately enables and disables the switching of the MOSFET until the abnormal condition is eliminated as shown in Figure 33. When the Extend Auto-Restart Mode protection is triggered via VS under-voltage protection (VS-UVP), switching is terminated and the MOSFET remains off, causing VDD to drop. While V DD drops to VDD-HV-ON for HV startup circuit enable, then IC enters Extend Auto-Restart period with two cycles as shown Figure 34. During Extend Auto-Restart period, VDD voltage swings between VDD-ON and VDD-HVON without gate switching, and IC operation current is reduced to IDD-Burst of 300 μA for slowing down the VDD capacitor discharging slope. As Extend Auto-Restart period ends, normal operation resumes. VDS Power On VDS VDD Power On Vs UVP Occurs Extend Auto-Restart VDD-ON VDD-OFF VDD-HV-ON Operating Current IDD-OP IDD-Brust Figure 34 Extend Auto-Restart Mode Operation VDD Over-Voltage-Protection (VDD-OVP) VDD over-voltage protection prevents IC damage from over-voltage stress. It is operated in Auto-Restart mode. When the VDD voltage exceeds VDD-OVP (29.0 V) for the de-bounce time, tD-VDDOVP (70 μs), due to abnormal condition, the protection is triggered. This protection is typically caused by an open circuit of secondary side feedback network. Brownout Protection Line voltage information is used for brownout protection. When the IVS current out of the VS pin during the MOSFET conduction time is less than 450 μA for longer than 16.5 ms, the brownout protection is triggered. The input bulk capacitor voltage to trigger brownout protection is given as V BLK.BO 1.2 450A VDD-OVP Fault Removed VDD-ON (eq. 9) IC Internal Over-Temperature-Protection (OTP) Fault Occurs VDD RVS 1 NA NP The internal temperature-sensing circuit disables the PWM output if the junction temperature exceeds 140°C (TOTP) and the FAN604 enters Auto-Restart Mode protection. VDD-OFF VDD-HV-ON Operating Current IDD-OP IDD-Brust Figure 33 Auto-Restart Mode Operation www.onsemi.com 16 FAN604 VS Over-Voltage-Protection (VS-OVP) VAUX VS over-voltage protection prevents damage caused by output over-voltage condition. It is operated in AutoRestart mode. Figure 35 shows the internal circuit of VSOVP protection. When abnormal system conditions occur, which cause VS sampling voltage to exceed V VSOVP (2.3V) for more than 2 consecutive switching cycles (NVS-OVP), PWM pulses are disabled and FAN604 enters Auto-Restart protection. VS over-voltage conditions are usually caused by open circuit of the secondary side feedback network or a fault condition in the VS pin voltage divider resistors. For VS pin voltage divider design, RVS1 is obtained from Equation 9, and RVS2 is determined by the desired VS-OVP protection function as RVS 2 RVS 1 1 VO OVP N A 1 VVS OVP N S VAUX (eq. 10) 2.3V RVS1 NA VS D S/H Q RVS2 PWM Auto Restart VS-OVP Debounce time Counter Figure 35 VS-OVP Protection Circuit VS Under-Voltage-Protection (VS-UVP) In the event of an output short, output voltage will drop and the primary peak current will increase. To prevent operation for a long time in this condition, FAN604 incorporates under-voltage protection through VS pin. Figure 36 shows the internal circuit for VS-UVP. By sampling the auxiliary winding voltage on the VS pin at the end of diode conduction time, the output voltage is indirectly sensed. When VS sampling voltage is less than VVS-UVP (0.65 V) and longer than de-bounce cycles NVSUVP, VS-UVP is triggered and the FAN604 enters Extend Auto-Restart Mode. To avoid VS-UVP triggering during the startup sequence, a startup blanking time, tVS-UVP-BLANK (40 ms), is included for system power on. For VS pin voltage divider design, RVS1 is obtained from Equation 9 and RVS2 is determined by Equation 10. VO-UVP can be determined by Equation 11. VO UVP NS R (1 VS 1 ) VVS UVP NA RVS 2 RVS1 NA 0.65V VS D S/H Q RVS2 PWM Extend Auto Restart VS-UVP Debounce time Counter Figure 36 VS-UVP Protection Circuit Externally Triggered Shutdown (SD) When VDD is VDD-ON, Shut-Down comparing level is VSDTH-ST (1.35V), after the startup time tSD-ST (1ms), the comparing level is changed to VSD-TH (1.0 V). By pulling down SD pin voltage below the VSD-TH (1.0 V) shutdown can be externally triggered and the FAN604 will enter Auto-Restart mode protection. It can be also used for external Over-Temperature-Protection by connecting a NTC thermistor between the shutdown (SD) programming pin and ground. An internal constant current source ISD (103 µA) creates a voltage drop across the thermistor. The resistance of the NTC thermistor becomes smaller as the ambient temperature increases, which reduces the voltage drop across the thermistor. SD pin voltage is sampled every gate cycle when VFB > VFB-Burst-H and sampled continuously when VFB < VFB-BurstL. When the voltage at SD pin is sampled to be below the threshold voltage, VSD-TH (1.0 V), for a de-bounce time of tD-SD (400 µs), Auto-Restart protection is triggered. A capacitor may also be placed in parallel with the NTC thermistor to further improve the noise immunity. The capacitor should be designed such that SD pin voltage is more than VSD-TH-ST within the time of tSD-ST. 5V Debounce 103μA CSD : 1nF ~ 20nF Auto-Restart SD CSD (eq. 11) www.onsemi.com 17 VDD-ON VDD NTC Thermistor tSD-ST VS Blanking VFB < VFB-BURST-L VSD-TH-ST VSD-TH VSD Figure 37 External OTP using SD Pin FAN604 Pulse-by-Pulse Current Limit Current Sense Short Protection During startup or overload condition, the feedback loop is saturated to high and is unable to control the primary peak current. To limit the current during such conditions, FAN604 has pulse-by-pulse current limit protection which forces the GATE to turn off when the CS pin voltage reaches the current limit threshold, VCS-LIM (0.89 V). Current sense short protection prevents damage caused by CS pin open or short to ground. After two switching cycle, it will operate in Auto-Restart mode. Figure 38 shows the internal circuit of current sense short protection. When abnormal system conditions occur, which cause CS pin voltage lower than 0.2 V after debounce time (tCS-short) for more than 2 consecutive switching cycles, PWM pulses are disabled and FAN604 enters Auto-Restart protection. The ICS-Short is an internal current source, which is proportional to line voltage. The de-bounce time (tCS-short) is created by ICS-short, capacitor (2 pF) and threshold voltage (3.0 V). This de-bounce time (tCS-short) is inversely proportional to the DC link capacitor voltage, VBLK. Secondary-Side Diode Shot Protection When the secondary-side diode is damaged, the slope of the primary-side peak current will be sharp within leading-edge blanking time. To limit the current during such conditions, FAN604 has secondary-side diode short protection which forces the GATE to turn off when the CS pin voltage reaches 1.6 V. After one switching cycle, it will operate in Auto-Restart mode as shown in Figure 38. VBLK GATE ICS-Short tCS-Short Np 2pF 3.0V GATE IDS D Q 0.2V CS RCS PWM RCS_COMP CCSF Auto Restart Counter 1.6V D Q PWM Auto Restart Counter 0.89V LEB Pulse-by-Pulse Figure 38 Current Sense Protection Circuit www.onsemi.com 18 FAN604 PCB Layout Guideline Print circuit board (PCB) layout and design are very import for switching power supplies where the voltage and current change with high dv/dt and di/dt. Good PCB layout minimizes excessive EMI and prevent the power supply from being disrupted during surge/ESD tests. The following guidelines are recommended for layout designs. To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors CBLK1 and CBLK2 first, then to the transformer and MOSFET. The primary-side high-voltage current loop is CBLK2 - Transformer - MOSFET - RCS - CBLK2. The area enclosed by this current loop should be as small as possible. The trace for the control signal (FB, CS, VS and GATE) should not go across this primary high-voltage current loop to avoid interference. Place RHV for protection against the inrush spike on the HV pin (150kΩ is recommended). RCS should be connected to the ground of CBLK2 directly. Keep the trace short and wide (Trace 4 to 1) and place it close to the CS pin to reduce switching noise. High-voltage traces related to the drain of MOSFET and RCD snubber should be away from control circuits to prevent unnecessary interference. If a heat sink is used for the MOSFET, connect this heat sink to ground. As indicated by 2, the area enclosed by the transformer auxiliary winding, DAUX and CVDD, should also be small. Place CVDD, CVS, RVS2, CFB, RCCR, CCCR, RCS_COMP and CCSF close to the controller for good decoupling and low switching noise. As indicated by 3, the ground of the control circuits should be connected as a single point first, then to other circuitry. Connect ground by 3 to 2 to 4 to 1 sequence. This helps to avoid common impedance interference for the sense signal. Regarding the ESD discharge path, use the shortcut pad between AC line and DC output (most recommended). Another method is to discharge the ESD energy to the AC line through the primary-side main ground 1. Because ESD energy is delivered from the secondary side to the primary side through the transformer stray capacitor or the Y capacitor, the controller circuit should not be placed on the discharge path. 5 shows where the pointdischarge route can be placed to effectively bypass the static electricity energy. For the surge path, select fusible resistor of wire wound type to reduce inrush current and surge energy and use π input filter (two bulk capacitors and one inductance) to share the surge energy. RSNS CSNP 5 TX LF DR CSNP Fuse Choke CBLK1 AC IN Np RSNP CO RBias1 RBias2 VO RHV1 CBLK2 Bridge XC DSNP RHV2 1 Photo coupler GATE Shunt Regulator FB RGF FAN604 SD DG CS CCR RSD NTC VDD GND CCCR RF1 VS RCS 5 4 CY DAUX RCCR RVS1 2 3 CCSF CVDD CVS RVS2 Figure 39 Recommended Layout for FAN604 www.onsemi.com 19 RComp CComp1 RF2 Na RCS_COMP CFB CComp2 RGR HV Photo coupler Ns FAN604 ORDERING INFORMATION Device Operating Temperature Range Package Shipping † FAN604MX -40C to +125C 10-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch Narrow Body Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D www.onsemi.com 20 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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