IRF ART2812TEMA Hybrid - high reliability radiation hardened dc-dc converter Datasheet

PD-94529G
ART28XXT SERIES
28V Input, Triple Output
HYBRID - HIGH RELIABILITY
RADIATION HARDENED
DC-DC CONVERTER
Description
The ART Series of three output DC-DC converters are
designed specifically for use in the hostile radiation
environments characteristic of space and weapon
systems. The extremely high level of radiation tolerance
inherent in the ART design is the culmination of
extensive research, thorough analysis and testing and
of careful component selection. Many of the proven
circuit design features characterizing the International
Rectifier standard product line were adapted for
incorporation into the ART topology. Capable of
uniformly high performance over long term exposures
in radiation intense environments, this series sets the
standard for distributed power systems demanding high
performance and reliability.
The ART converters are hermetically sealed in a
rugged, low profile package utilizing copper core pins
to minimize resistive DC losses. Long-term hermeticity
is assured through use of parallel seam welded lid
attachment along with International Rectifier’s rugged
ceramic pin-to-package seal. Axial orientation of the
leads facilitates preferred bulkhead mounting to the
principal heat-dissipating surface.
Manufactured in a facility fully qualified to MIL-PRF-38534,
these converters are fabricated utilizing DLA qualified
processes. For available screening options, refer to
device screening table in the data sheet.
ART
Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
Total Dose > 100 krad (Si), 2:1margin
SEE Hardened to LET up to 83 Mev.cm2/mg
Output Power Range 3 to 30 Watts
19 to 50 Volt Input Range
Input Undervoltage Lockout
High Electrical Efficiency > 83%
Full Performance from -55°C to +125°C
Continuous Short Circuit and Overload
Protection
12.8 W/in3 Output Power Density
True Hermetic Package
External Inhibit Port
Externally Synchronizable
Fault Tolerant Design
5V, ±12V or ±15 V Outputs Available
Standard Microcircuit Drawings Available
Variations in electrical, mechanical and screening
specifications can be accommodated. Contact IR San
Jose for special requirements.
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1
08/15/12
ART28XXT SERIES
SPECIFICATIONS
Absolute Maximum/Minimum Ratings Note 1
Recommended Operating Conditions Note 2
Input voltage range
-0.5V to +80V
Input Voltage range
Minimum Output Current
5% maximum rated
+19V to +60V
+19V to +50V for full
current, any output
derating to MIL-STD-975
Soldering temperature
300°C for 10 seconds
Output Power range
3.0W to 30W
Storage temperature
-65°C to +135°C
Operating temperature
-55°C to +125°C
-55°C to +85°C for full
derating to MIL-STD-975
Electrical Performance -55°C < TCASE < +125°C, VIN=28V, CL=0 unless otherwise specified.
Parameter
Output voltage accuracy
Symbol
VOUT
Conditions
IOUT = 1.5Adc, TC = +25°C
Min
(main)
IOUT = ±250mAdc, TC = +25°C ART2812(dual)
IOUT = ±250mAdc, TC = +25°C ART2815(dual)
Output power Note 5
POUT
Output current Note 5
IOUT
Line regulation Note 3
VRLINE
19 Vdc< VIN < 50Vdc
VRLOAD
Total regulation
Input current
VRCROSS
VR
IIN
5.05
±11.50
±14.50
±12.50
±15.15
3.0
30
3000
(dual)
75
750
(main)
-15
+15
±75 mAdc < IOUT < ±750 mAdc
(dual)
-60
+60
150 mAdc < IOUT < 3000 mAdc
(main)
-180
+180
(dual)
-300
+300
(main)
-10
+10
(dual)
-500
+500
All conditions of Line, Load,
(main)
Cross Regulation, Aging,
Temperature and Radiation ART2812(dual)
ART2815(dual)
4.8
5.2
±11.1
±13.9
±12.9
±16.0
19 Vdc< VIN < 50Vdc
Units
Vdc
150
W
mAdc
mV
19 Vdc< VIN < 50Vdc
mV
19 Vdc< VIN < 50Vdc
±75 mAdc < IOUT < ±750 mAdc
Cross regulation Note 8
4.95
(main)
150 mAdc < IOUT < 3000 mAdc
Load regulation Note 4
Max
mV
19 Vdc< VIN < 50Vdc
V
IOUT = minimum rated, Pin 3 open
250
Pin 3 shorted to pin 2 (disabled)
8.0
mA
Output ripple voltage Note 6
VRIP
19 Vdc< VIN < 50Vdc
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
70
mVp.p
Input ripple current Note 6
IRIP
19 Vdc< VIN < 50Vdc
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
100
mAp.p
Switching frequency
FS
Sychronization input open. (pin 6)
225
275
KHz
kHz
Efficiency
Eff
IOUT = 3000 mAdc (main), ±500 mAdc (dual)
83
%
For Notes to SPECIFICATIONS, refer to page 3
2
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ART28XXT SERIES
Electrical Performance (Continued)
Parameter
Symbol
Conditions
Enable Input
open circuit voltage
drive current (sink)
voltage range
Synchronization Input
frequency range
pulse high level
pulse low level
pulse rise time
pulse duty cycle
External clock signal on Sync. input (pin 4)
Synchronization Output
pulse high level
pulse low level
Signal compatible with synchronization input
MIN
MAX
Units
3.0
0.1
-0.5
5.0
V
mA
V
50.0
KHz
Khz
225
4.5
-0.5
40
20
310
10.0
0.25
3.7
0.0
4.3
0.25
V
16
W
200
200
mVPK
200
200
µs
Short circuit, any output
V
V
s
V/µS
%
80
Power dissipation, load fault
PD
Output response to step load
changes Notes 7, 11
VTLD
10% Load to/from 50% load
50% Load to/from 100% load
Recovery time from step load
changes Notes 11, 12
TTLD
10% Load to/from 50% load
50% Load to/from 100% load
Output response to step line
changes Notes 10, 11
VTLN
IOUT = 3000 mAdc
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
(main)
-350
350
(dual)
-1050
1050
Recovery time from step line
changes Notes 10, 11,13
IOUT = 3000 mAdc
VIN = 19 V to/from 50 V
IOUT = ±500 mAdc
(main)
500
TTLN
(dual)
500
VOS
IOUT = minimum and full rated
(main)
(dual)
100
500
mV
Turn on delay Note 14
TDLY
IOUT = minimum and full rated
20
ms
mS
Capacitive load Notes 9, 10
CL
No effect on DC performance
500
100
µF
Isolation
ISO
500VDC Input to Output or any pin to case
(except pin 12)
Turn on overshoot
-200
-200
5.0
(main)
(dual)
µS
mVPK
100
µs
µS
MΩ
Notes to SPECIFICATIONS
1.
2.
3.
4.
5.
Operation outside absolute maximum/minimum limits may cause permanent damage to the device. Extended operation at the limits may permanently
degrade performance and affect reliability.
Device performance specified in Electrical Performance table is guaranteed when operated within recommended limits. Operation outside
recommended limits is not specified.
Parameter measured from 28V to 19 V or to 50V while loads remain fixed.
Parameter measured from nominal to minimum or maximum load conditions while line remains fixed.
Up to 750 mA is available from the dual outputs provided the total output power does not exceed 30W.
6.
7.
8.
9.
Guaranteed for a bandwidth of DC to 20MHz. Tested using a 20KHz to 2MHz bandwidth.
Load current is stepped for output under test while other outputs are fixed at half rated load.
Load current is fixed for output under test while other output loads are varied for any combination of minimum to maximum.
A capacitive load of any value from 0 to the specified maximum is permitted without comprise to DC performance. A capacitive load in excess of the
maximum limit may interfere with the proper operation of the converter’s short circuit protection, causing erratic behavior during turn on.
10.
Parameter is tested as part of design characterization or after design or process changes. Thereafter, parameters shall be guaranteed to the limits
specified in the table.
11.
12.
Load transient rate of change, di/dt ≤ 2 A/µSec.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
13.
14.
Line transient rate of change, dv/dt ≤ 50 V/µSec.
Turn on delay time is for either a step application of input power or a logical low to high transition on the enable pin (pin 3) while power is present at the
input.
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3
ART28XXT SERIES
Group A Tests VIN= 28Volts, CL =0 unless otherwise specified.
Test
Symbol
Output voltage accuracy
VOUT
Output power Note 1
POUT
VIN = 19 V, 28V, 50 V
Output current
Note 1
IOUT
VIN 19 V, 28V, 50 V
Output regulation Note 4
VR
Input current
IIN
Group A
Subgroups
MIN
MAX
(main)
1, 2, 3
4.95
5.05
ART2812(dual)
ART2815(dual)
1, 2, 3
1, 2, 3
±11.70
±14.50
±12.30
±15.15
1, 2, 3
3.0
30
(main)
1, 2, 3
150
3000
(dual)
1, 2, 3
75
500
(main)
1, 2, 3
4.8
5.2
2812(dual)
2815(dual)
1, 2, 3
1, 2, 3
±11.1
±14.0
±12.9
±15.8
Conditions unless otherwise specified
IOUT = 1.5 Adc
IOUT = ±250mAdc
IOUT = ±250mAdc
IOUT = 150, 1500, 3000mAdc
VIN = 19 V, 28V, 50 V
IOUT = ±75, ±310, ±625mAdc
IOUT = ±75, ±250, ±500mAdc
IOUT = minimum rated, Pin 3 open
1, 2, 3
250
Pin 3 shorted to pin 2 (disabled)
1, 2, 3
8.0
Units
V
W
mA
V
mA
Output ripple Note 2
VRIP
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
70
mVP-P
Input ripple Note 2
IRIP
VIN = 19 V, 28V, 50 V
IOUT = 3000mA main, ±500mA dual
1, 2, 3
100
mAP-P
Switching frequency
FS
Synchronization pin (pin 6) open
4, 5, 6
225
275
KHz
Efficiency
Eff
IOUT = 3000mA main, ±500mA dual
1
2, 3
83
81
Power dissipation,
load fault
PD
Short circuit, any output
1, 2, 3
10% Load to/from 50% load
4, 5, 6
-200
200
50% Load to/from 100% load
4, 5, 6
-200
200
10% Load to/from 50% load
4, 5, 6
200
50% Load to/from 100% load
4, 5, 6
200
(main)
4, 5, 6
100
(dual)
4, 5, 6
500
Output response to step
load changes Notes 3, 5
VTL
Recovery time from step
load changes Notes 5, 6
TTL
Turn on overshoot
VOS
IOUT = minimum and full rated
Turn on delay Note 7
TDLY
IOUT = minimum and full rated
Isolation
ISO
500VDC Input to output or any pin to case
(except pin 12)
%
16
4, 5, 6
5.0
1
100
20
W
mVPK
µs
µS
mV
mS
ms
MΩ
Notes to Group A Test Table
1.
Parameter verified during dynamic load regulation tests.
2.
Guaranteed for DC to 20 MHz bandwidth. Test conducted using a 20KHz to 2MHz bandwidth.
3.
Load current is stepped for output under test while other outputs are fixed at half rated load.
4.
Each output is measured for all combinations of line and load. Only the minimum and maximum readings for each output are recorded.
5.
Load step transition time ≥ 10µS.
6.
Recovery time is measured from the initiation of the transient to where VOUT has returned to within ±1% of its steady state value.
7.
Turn on delay time is tested by application of a logical low to high transition on the enable pin (pin 3) with power present at the input.
8.
Subgroups 1 and 4 are performed at +25ºC, subgroups 2 and 5 at -55ºC and subgroups 3 and 6 at +125ºC.
4
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ART28XXT SERIES
Radiation Performance
performance variations. In the few instances where such
margins were not assured, element lots were selected
from which die were fabricated (and characterized) as
radiation hard devices so that realization of the design
goals could be assured.
The radiation tolerance characteristics inherent in the
ART28XXT converter are the direct result of a carefully
planned ground-up design program with specific radiation
design goals. After identification of the general circuit
topology, a primary task of the design effort was selection
of appropriate elements from the list of devices for which
extensive radiation effects data was available. By imposing
sufficiently large margins on those electrical parameters
subject to the degrading effects of radiation, designers
were able to select appropriate elements for incorporation
into the circuit. Known radiation data was utilized for input
to PSPICE and RadSPICE in the generation of circuit
performance verification analyses. Thus, electrical
performance capability under all environmental conditions
including radiation was well understood before first
application of power to the inputs.
Completion of first article fabrication, screening and
standard environmental testing was followed by radiation
testing to confirm design goals. All design goals were met
handily and in most cases exceeded by large margin.
These test samples were built with elements that, with the
foregoing exceptions, were not screened for radiation
characteristics. Additional radiation tests on subsequent
ART28XXT manufacturing lots provide continued
confirmation of the soundness of the design goals as well
as justification for the element selection criteria.
A principal design goal was a converter topology that,
because of large design margins, had radiation performance
essentially independent of normal elemental lot radiation
The following table specifies guaranteed minimum radiation
exposure levels tolerated while maintaining specification
limits.
Radiation Performance Characteristics
Test Inspection
Method
Min
Typ
Unit
200
300
Krads(Si)
Operating bias applied during exposure,
Full Rated Load, VIN = 28V
1E8
4E10
1E11
MIL-STD-883, Method 1017
Heavy Ions (LET)
8E12
1E13
MIL-PRF-883, Method 1019
Total Ionizing Dose (Gamma)
Operating bias applied during exposure,
Full Rated Load, VIN = 28V
Dose Rate (Gamma Dot)
MIL-STD-883, Method 1023
Temporary Saturation
Survival
Neutron Fluence
Single Event Effects
SEU, SEL, SEGR, SEB
Operating bias applied during exposure,
Full Rated Load, VIN = 28V
83
Rads(Si)/sec
Neutrons/cm
2
2
MeVxcm /mg
Test lab: Brookhaven National Laboratory,
Tandem Van de Graaff Generator
International Rectifier currently does not have a DLA Land and Maritime certified Radiation Hardness
Assurance Program.
Standard Periodic Inspections on ART28XXT Series
As prescribed by MIL-PRF-38534 for Option 2
Inspection
Application
Quantity
Group A
Part of Screening on Each Unit
100%
Group B
Each Inspection Lot
5 units
Group C
First Inspection Lot or
Following Class 1 Change
Group D
In Line (Part of Element Evaluation)
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10 Units
5
ART28XXT SERIES
Figure I. Block Diagram
EMI
Filter
1
+Input
11 +12/+15 Vdc
Output
10 +12/+15 Vdc
Output Return
Under-Voltage
Detector
3
Enable
9
Primary Bias
& Reference
13
Short
Circuit
14
4
Sync In
Pulse Width
Modulator
-12/-15 Vdc
Output
+5 Vdc
Output
+5 Vdc
Output Return
Sample
Hold
5
Sync Out
Input
Return
2
Circuit Description and Application Information
Operating Guidelines
The ART28XXT series of converters have been designed
using a single ended forward switched mode converter
topology. (refer to Figure I.) Single ended topologies enjoy
some advantage in radiation hardened designs in that they
eliminate the possibility of simultaneous turn on of both
switching elements during a radiation induced upset; in
addition, single ended topologies are not subject to
transformer saturation problems often associated with
double ended implementations.
The circuit topology used for regulating output voltages in
the ART28XXT series of converters was selected for a
number of reasons. Significant among these is the ability
to simultaneously provide adequate regulation to three
output voltages while maintaining modest circuit complexity.
These attributes were fundamental in retaining the high
reliability and insensitivity to radiation that characterizes
device performance. Use of this topology dictates
maintaining the minimum load specified in the electrical
tables on each output. Operating the converter without a
load on any output will result in peak charging to an output
voltage well above the specified voltage regulation limits,
potentially in excess of ratings, and should be avoided.
Output load currents less than specification minimums will
result in regulation performance that exceeds the limits
presented in the tables. In most practical applications, this
lower bound on the load range does not present a serious
constraint; however the user should be mindfull of device
performance when operated outside specified limits.
The design incorporates a two-stage LC input filter to
attenuate input ripple current. A low overhead linear bias
regulator is used to provide bias voltage for the converter
primary control logic and a stable, well regulated reference
for the error amplifier. Output control is realized using a
wide band discrete pulse width modulator control circuit
incorporating a unique non-linear ramp generator circuit.
This circuit helps stabilize loop gain over variations in line
voltage for superior output transient response. Nominal
conversion frequency has been selected as 250 KHz to
maximize efficiency and minimize magnetic element size.
Output voltages are sensed using a coupled inductor and
a patented magnetic feedback circuit. This circuit is
relatively insensitive to variations in temperature, aging,
radiation and manufacturing tolerances making it
particularly well suited to radiation hardened designs. The
control logic has been designed to use only radiation
tolerant components, and all current paths are limited with
series resistance to limit photo currents.
Other key circuit design features include short circuit
protection, undervoltage lockout and an external
synchronization port permitting operation at an externally
set clock rate.
6
Thermal Considerations
The ART series of converters is capable of providing
relatively high output power from a package of modest
volume. The power density exhibited by these devices is
obtained by combining high circuit efficiency with effective
methods of heat removal from the die junctions. Good
design practices have effectively addressed this
requirement inside the device. However when operating
at maximum loads, significant heat generated at the die
junctions must be carried away by conduction from the
base. To maintain case temperature at or below the
specified maximum of 125°C, this heat can be transferred
by attachment to an appropriate heat dissipater held in
intimate contact with the converter base-plate.
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ART28XXT SERIES
Effectiveness of this heat transfer is dependent on the
intimacy of the baseplate-heatsink interface. It is therefore
suggested that a heat transferring medium possessing
good thermal conductivity is inserted between the
baseplate and heatsink. A material utilized at the factory
during testing and burn-in processes is sold under the
®
trade name of Sil-Pad 400 1. This particular product is an
insulator but electrically conductive versions are also
available. Use of these materials assures optimum surface
contact with the heat dissipater by compensating for minor
surface variations. While other available types of heat
conducting materials and thermal compounds provide
similar effectiveness, these alternatives are often less
convenient and are frequently messy to use.
A conservative aid to estimating the total heat sink surface
area (A HEAT SINK) required to set the maximum case
temperature rise (∆T) above ambient temperature is given
by the following expression:
⎧ ∆T ⎫
A HEAT SINK ≈ ⎨
0.85 ⎬
⎩ 80 P ⎭
−1. 43
− 5.94
Thus, a total heat sink surface area (including fins, if any)
of approximately 32 in2 in this example, would limit case
rise to 35°C above ambient. A flat aluminum plate, 0.25"
thick and of approximate dimension 4" by 4" (16 in 2 per
side) would suffice for this application in a still air
environment. Note that to meet the criteria, both sides of
the plate require unrestricted exposure to the ambient air.
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing an input referenced, TTL compatible,
logic signal to the enable pin 3. This port is internally pulled
“high” so that when not used, an open connection on the
pin permits normal converter operation. When inhibited
outputs are desired, a logical “low” on this port will shut the
converter down. An open collector device capable of
sinking at least 100 µA connected to enable pin 3 will work
well in this application.
A benefit of utilization of the enable input is that following
initial charge of the input capacitor, subsequent turn-on
commands will induce no uncontrolled current inrush.
where
∆T = Case temperature rise above ambient
⎧ 1
⎫
P = Device dissipation in Watts = P ⎨
− 1⎬
⎩ Eff
⎭
Figure II. Enable Input Equivalent Circuit
Vin
OUT
As an example, assume that it is desired to maintain the
case temperature of an ART2815T at +65°C or less while
operating in an open area whose ambient temperature
does not exceed +35°C; then
118K
2N2907A
64K
Enable
Input
5.6 V
150K
CR2
2N2222A
186K
150K
∆T = 65 - 35 = 35°C
2N2222A
From the Specification Table, the worst case full load
efficiency for this device is 80%; therefore the maximum
power dissipation at full load is given by
Input
Return
65K
150K
Converter inhibit is initiated when
this transistor is turned off
⎫
⎧1
.W
P = 30 • ⎨ − 1⎬ = 30 • (0.25) = 75
⎩ .80 ⎭
and the required heat sink area is
35
⎧
⎫
A HEAT SINK = ⎨
0.85 ⎬
•
80
7.5
⎩
⎭
−1. 43
− 5.94 = 318
. in 2
1Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
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7
ART28XXT SERIES
Synchronization
Output Load Fault Protection
Systems using multiple convertors may dictate operating
the group at a common switching frequency. To
accomodate this requirement, the ART28XXT converters
include a synchronization input (pin 4). Topology is
illustrated in Figure III.
An additional feature is a synchronization output (pin 5)
permitting multiple Protection against overload or short
circuit on any output is provided in the ART28XXT converter
series. This protection is implemented by sensing primary
switching current and, when a load fault condition is
detected, pulse width is limited by the protection circuitry.
The converter is able to operate continuously with a load
fault witout damage or exceeding derating limits.
An additional feature is a synchronization output (pin 5)
permitting multiple ART28XX converters in a system to be
synchronized to one of the converters in the set. See
Figure IV.
Figure III. Synchronization Input Equivalent Circuit
+10V
5K
Sync
Input
2N2907A
47pf
10K
Input
Return
Figure IV. Synchronization Output Equivalent Circuit
+10V
To Internal
Clock
6K
Parallel Operation
Although no special provision for forced current sharing
has been incorporated in the ART28XXT series, multiple
units may be operated in parallel for increased output power
applications. The 5.0 volt outputs will typically share to
within approximately 10% of their full load capability and
the dual (±15 volt) outputs will typically share to within
50% of their full load. Load sharing is a function of the
individual impedance of each output and the converter
with the highest nominal set voltage will furnish the
predominant load current.
Input Undervoltage Protection
A minimum voltage is required at the input of the converter
to initiate operation. This voltage is set to a nominal value
of 16.8 volts. To preclude the possibility of noise or other
variations at the input falsely initiating and halting converter
operation, a hysteresis of approximately 1.0 volts is
incorporated in this circuit. The converter is guaranteed to
operate at 19 Volts input under all specified conditions.
10pf
Sync
Output
Input Filter
5
4K
10K
2N2222
Input
Return 2
The sync input port permits synchronization of an ART
converter to any compatible external frequency source
operating in the band of 225 to 310 KHz. The synchronization
input is edge triggered with synchronization initiated on
the negative transition. This input signal should be a
negative going pulse referenced to the input return and
have a 20% to 80% duty cycle. Compatibility requires the
negative transition time to be less than 100 ns with minimum
pulse amplitude of +4.25 volts referred to the input return.
In the absence of an external source, the converter will
revert to its own internally set frequency. If external
synchronization is not desired, the sync in pin may be left
open (unconnected) permitting the converter to operate at
its’ own internally set frequency.
8
To attenuate input ripple current, the ART28XXT series
converters incorporate a two-stage LC input filter. The
elements of this filter comprise the dominant input load
impedance characteristic, and therefore determine the
nature of the current inrush at turn-on. The input filter
circuit elements are as shown in Figure V.
Figure V. Input Filter Circuit
4.7 µH
Pin 1
1.35Ω
34 µH
5.4 µfd
Pin 2
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ART28XXT SERIES
Additional Filtering
Although internal filtering is provided at both the input and
output terminals of the ART28XX series, additional filtering
may be desirable in some applications to accommodate
more stringent system requirements.
While the internal input filter of Figure V keeps input ripple
current below 100 mAp-p, an external filter may be applied
to further attenuate this ripple to a level below the CE03
limits imposed by MIL-STD-461B. Figure VI is a general
diagram of the International Rectifier filter module designed
to operate in conjunction with the ART28XX series
converters to provide that attenuation.
It is important to be aware that when filtering high frequency
noise, parasitic circuit elements can easily dominate filter
performance. Therefore, it is incumbent on the designer to
exercise care when preparing a circuit layout for such
devices. Wire runs and lengths should be minimized, high
frequency loops should be avoided and careful attention
paid to the construction details of magnetic circuit elements.
Tight magnetic coupling will improve overall magnetic
performance and reduce stray magnetic fields.
Figure VII. External Output Filter
L1
+5 V
Figure VI. External Input EMI Filter
+5V Out
L3
C1
C6
C2
5V
Return
+5V
Return
L2
+15V
+15V
Out
L4
C3
C7
This circuit as shown in Figure VI is constructed using the
same quality materials and processes as those employed
in the ART28XX series converters and is intended for use
in the same environments. This filter is fabricated in a
complementary package style whose output pin configuration
allows pin to pin connection between the filter and the
converter. More complete information on this filter can be
obtained from the ARF461 data sheet.
An external filter may also be added to the output where
circuit requirements dictate extremely low output ripple
noise. The output filter described by Figure VII has been
characterized with the ART2815T using the values shown
in the associated material list.
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15V
Return
15V
Return
C4
C8
C5
-15V
Out
-15V
/
WXUQV$:*ELILODURQ0DJ,QFFRUH31<-7&RUHTXLYDOHQW
/
WXUQV$:*WULILODURQ0DJ,QFFRUH31<-7&RUHTXLYDOHQW
/
WXUQV$:*RQ0DJ,QFFRUH31033RUHTXLYDOHQW
/
WXUQV$:*ELILODURQ0DJ,QFFRUH31033RUHTXLYDOHQW
&&
S)W\SH&.5FHUDPLFFDSDFLWRU
&
—)907DQWDOXP
&& —)907DQWDOXP
Measurement techniques can impose a significant influence on results. All noise measurements should be measured with test leads as close to the device output pins as
physically possible. Probe ground leads should be kept to
a minimum length.
9
ART28XXT SERIES
Performance Characteristics (Typical @ 25°C)
Figure VIII.
Efficiency vs Output Power
for Three Line Voltages.
Figure IX.
5.0 V Output Regulation Limits
0.3 A load on ±15 V outputs
5.20
Vout
5.10
5.00
4.90
4.80
0.0
0.5
1.0
1.5
2.0
2.5
3.0
5V Load Current, Amps
10
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ART28XXT SERIES
Mechanical Outline
Ø 0.136 - 6 Holes
8
0.040
Pin Dia.
9
5
3
4
1.950
2
6 x 0.200
= 1.200
1
2.200
10 11 12 13 14
1.675
0.375
0.263
0.138
0.300
1.400
0.150
2.400
0.275
0.240
2.700
3.25 Ref.
Max
Mounting
Plane
0.050
Flange
0.500
Max
Note:
1. Dimensions are in inches.
2. Base Plate Mounting Plane Flatness 0.003 maximum.
3. Unless otherwise specified, tolerances are
∠
= ± 2°
.XX
= ± .01
.XXX
= ± .005
4. Device Weight - 120 grams maximum.
Pin Designation
Pin #
Designation
Pin #
Designation
1
+ Input
9
-12/-15 Vdc Output
2
Input Return
10
+12/+15 Vdc Output Return
3
Enable
11
+12/+15 Vdc Output
4
Sync. In
12
Case Ground
5
Sync. Out
13
+5 Vdc Output
8
NC
14
+5 Vdc Output Return
Standard Microcircuit Drawing Equivalence Table
Standard Microcircuit
Drawing Number
5962-04234
5962-04237
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IR Standard
Part Number
ART2815T
ART2812T
11
ART28XXT SERIES
Device Screening
Requirement
MIL-STD-883 Method
Temperature Range
No Suffix
d
CK
d
EM
-55°C to +85°C
-55°C to +85°C
-55°C to +85°C
Element Evaluation
MIL-PRF-38534
Class K
Class K
N/A
Non-Destructive Bond Pull
2023
Yes
Yes
N/A
Internal Visual
2017
Yes
Yes
c
Temperature Cycle
1010
Cond C
Cond C
Cond C
Constant Acceleration
2001, Y1 Axis
3000 Gs
3000 Gs
3000 Gs
PIND
2020
Cond A
Cond A
N/A
Burn-In
1015
320 hrs @ 125°C
320 hrs @ 125°C
48 hrs @ 125°C
( 2 x 160 hrs )
( 2 x 160 hrs )
Final Electrical
MIL-PRF-38534
-55°C, +25°C,
-55°C, +25°C,
-55°C, +25°C,
( Group A )
& Specification
+85°C
+85°C
+85°C
PDA
MIL-PRF-38534
2%
2%
N/A
Seal, Fine and Gross
1014
Cond A, C
Cond A, C
Cond A
Radiographic
2012
Yes
Yes
N/A
External Visual
2009
Yes
Yes
c
Notes:
c
d
Best commercial practice.
CK is a DLA class K compliant without radiation performance. No Suffix is a radiation rated device but
not available as a DLA quallified SMD per MIL-PRF-38534.
International Rectifier currently does not have a DLA certified Radiation Hardness Assurance Program.
Part Numbering
ART 28 15 T / XX X
Model
Input Voltage
28 = 28V
Output Voltage
12 = 5V, ± 12V
15 = 5V, ± 15V
Output
T = Triple
Lead Finish for CK only
C = Gold Plated
A = Solder Dipped
Blank for No Suffix and EM
Lead Finish for No Suffix = Solder Dipped
Lead Finish for EM is Gold Plated or
Solder Dipped depending on availability
Screening Level
(Please refer to Screening Table)
No Suffix, CK, EM
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 252-7105
IR SAN JOSE: 2520 Junction Avenue, San Jose, California 95134, Tel: (408) 434-5000
Visit us at www.irf.com for sales contact information.
Data and specifications subject to change without notice. 08/2012
12
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