CY62168G/CY62168GE MoBL® 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC) 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC) Features Devices with a single chip enable input are accessed by asserting the chip enable input (CE) LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as LOW and CE2 as HIGH. ■ Ultra-low standby power ❐ Typical standby current: 5.5 A ❐ Maximum standby current: 16 A ■ High speed: 45 ns/55 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V ■ 1.0 V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ ERR pin to indicate 1-bit error detection and correction ■ Available in Pb-free 48-ball VFBGA package Write to the device by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and the Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A20). Read from the device by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable 2 (CE2) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table – CY62168G/CY62168GE on page 14 for a complete description of read and write modes. Functional Description CY62168G and CY62168GE are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62168GE device includes an error indication pin that signals a single-bit error-detection and correction event during a read cycle. On CY62168GE devices, the detection and correction of a single bit error in the accessed location is indicated by the assertion of the ERR output (ERR = HIGH) [1]. The CY62168G and CY62168GE devices are available in a Pb-free 48-pin VFBGA package. The logic block diagrams are on page 2. For a complete list of related resources, click here. Product Portfolio Power Dissipation Product Features and Options (see Pin Configurations section) CY62168G(E)18 Single or dual Chip Enables CY62168G(E)30 CY62168G(E) Range Industrial Optional ERR pin VCC Range (V) Speed Operating ICC, (mA) (ns) f = fmax Standby, ISB2 (µA) Typ[2] Max Typ[2] Max 1.65 V–2.2 V 55 29 32 7 26 2.2 V–3.6 V 45 29 36 5.5 16 4.5 V–5.5 V Notes 1. This device does not support automatic write-back on error detection. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-84771 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 22, 2017 CY62168G/CY62168GE MoBL® Logic Block Diagram – CY62168G 2M x 8 RAM ARRAY SENSE AMPLIFIERS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ECC DECODER DATAIN DRIVERS ECC ENCODER I/O0‐I/O7 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 WE OE CE2 CE1 Logic Block Diagram – CY62168GE 2M x 8 RAM ARRAY SENSE AMPLIFIERS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O0‐I/O7 ERR WE OE CE2 CE1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 COLUMN DECODER ECC DECODER DATAIN DRIVERS ECC ENCODER Document Number: 001-84771 Rev. *I Page 2 of 19 CY62168G/CY62168GE MoBL® Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Characteristics ....................................... 8 Data Retention Waveform ................................................ 8 Switching Characteristics ................................................ 9 Switching Waveforms .................................................... 10 Truth Table – CY62168G/CY62168GE ........................... 14 ERR Output – CY62168GE ............................................. 14 Document Number: 001-84771 Rev. *I Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 17 Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Document History Page ................................................. 18 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 3 of 19 CY62168G/CY62168GE MoBL® Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3] CY62168G 1 2 3 4 5 6 NC OE A0 A1 A2 CE2 A NC NC A3 A4 CE1 NC B I/O0 NC A5 A6 NC I/O4 C VSS I/O1 A17 A7 I/O5 VCC D VCC I/O2 A18 A16 I/O6 VSS E I/O3 NC A14 A15 NC I/O7 F NC NC A12 A13 WE NC G A19 A8 A9 A10 A11 A20 H Figure 2. 48-ball VFBGA (6 × 8 × 1 mm) pinout[3, 4] CY62168GE Note 3. NC pins are not connected internally to the die and are typically used for address expansion to a higher-density device. Refer to the respective datasheets for pin configuration. 4. ERR is an Output pin.If not used, this pin should be left floating. Document Number: 001-84771 Rev. *I Page 4 of 19 CY62168G/CY62168GE MoBL® Maximum Ratings Output current into outputs (LOW) ............................. 20 mA Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied .................................. –55 °C to + 125 °C Static discharge voltage (MIL-STD-883, Method 3015) ................................. >2001 V Latch up current ...................................................... >140 mA Operating Range Supply voltage to ground potential ...................–0.5 V to 6 V DC voltage applied to outputs in High Z state[5] .................................. –0.5 V to VCC + 0.5 V Grade Ambient Temperature VCC[6] Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC input voltage[5] .............................. –0.5 V to VCC + 0.5 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter VOH Description Output HIGH voltage VIH VIL Output LOW voltage Input HIGH voltage Input LOW voltage[9] 45 ns/55 ns Unit Min Typ [7] Max 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V 2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2.0 – – V 2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA 2.4 – – V 4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – – V – – V 4.5 V to 5.5 V VOL Test Conditions VCC = Min, IOH = –0.1 mA VCC – 0.4 [8] 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V 2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA – – 0.4 V 2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA – – 0.4 V 4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4 V 1.65 V to 2.2 V – 1.4 – VCC + 0.2 V 2.2 V to 2.7 V – 1.8 – VCC + 0.3 V 2.7 V to 3.6 V – 2.0 – VCC + 0.3 V 4.5 V to 5.5 V – 2.2 – VCC + 0.5 V 1.65 V to 2.2 V – –0.2 – 0.4 V 2.2 V to 2.7 V – –0.3 – 0.6 V 2.7 V to 3.6 V – –0.3 – 0.8 V 4.5 V to 5.5 V – –0.5 – 0.8 V IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 A Notes 5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C. 8. This parameter is guaranteed by design and is not tested. 9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document Number: 001-84771 Rev. *I Page 5 of 19 CY62168G/CY62168GE MoBL® DC Electrical Characteristics (continued) Over the operating range of –40 C to 85 C Parameter ICC ISB1 Description ISB2[10] 45 ns/55 ns Unit Min Typ [7] Max f = 22.22 MHz (45 ns) – 29.0 36.0 f = 18.18 MHz (55 ns) – 29.0 32.0 mA f = 1 MHz – 7.0 9.0 mA Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V, CMOS inputs; VIN > VCC – 0.2 V, VIN < 0.2 V, VCC = 2.2 to 3.6 V and 4.5 to 5.5 V f = fmax (address and data only), – 5.5 16.0 A Automatic power down current – f = 0 (OE, and WE), V = V CC CC(max) CMOS inputs; VCC = 1.65 to 2.2 V – 7 26.0 A Automatic power down current – CE1 > VCC – 0.2 V or 25 °C [11] CMOS inputs; CE2 < 0.2 V, 40 °C [11] VCC = 2.2 to 3.6 V and 4.5 to 5.5 V VIN > VCC – 0.2 V or 70 °C [11] VIN < 0.2 V, 85 °C f = 0, VCC = VCC(max) – 5.5 6.5 A – 6.3 8.0 A VCC operating supply current [10] Test Conditions VCC = Max, IOUT = 0 mA, CMOS levels Automatic power down current – CE1 > VCC – 0.2 V or CE2 < 0.2 V, CMOS inputs; VIN > VCC – 0.2 V or VIN < 0.2 V, VCC = 1.65 to 2.2 V mA mA – 8.4 12.0 A – 12.0 [11] 16.0 A – 7.0 26.0 A f = 0, VCC = VCC(max) Notes 10. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 11. The ISB2 limits at 25 °C, 40 °C, 70 °C and typical limit at 85 °C are guaranteed by design and not 100% tested. Document Number: 001-84771 Rev. *I Page 6 of 19 CY62168G/CY62168GE MoBL® Capacitance Parameter [12] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [12] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 31.50 °C/W 15.75 °C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms R1 VHIGH VCC OUTPUT GND R2 30 pF INCLUDING JIG AND SCOPE 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 1.8 V 2.5 V 3.0 V 5.0 V Unit R1 13500 16667 1103 1800 R2 10800 15385 1554 990 RTH 6000 8000 645 639 VTH 0.8 1.2 1.75 1.77 V VHIGH 1.8 2.5 3.0 5.0 V Note 12. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-84771 Rev. *I Page 7 of 19 CY62168G/CY62168GE MoBL® Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for data retention ICCDR[14, 15] Data retention current Conditions Min Typ[13] Max Unit 1.0 – – V – 7.0 26.0 A – 5.5 16.0 A 0 – – – 45/55 – – ns 1.2 V < VCC < 2.2 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V 2.2 V < VCC < 3.6 V or 4.5 V < VCC < 5.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V tCDR [16] Chip deselect to data retention time tR[16, 17] Operation recovery time Data Retention Waveform Figure 4. Data Retention Waveform V CC V C C (m in ) tCD R D A T A R E T E N T IO N M O D E V D R = 1 .0 V V C C (m in ) tR CE1 (o r) CE2 Notes 13. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C. 14. Chip enables (CE1 and CE2) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 15. ICCDR is guaranteed only after device is first powered up to VCC(min) and brought down to VDR. 16. These parameters are guaranteed by design. 17. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 001-84771 Rev. *I Page 8 of 19 CY62168G/CY62168GE MoBL® Switching Characteristics Parameter [18, 19] 45 ns Description 55 ns Unit Min Max Min Max 45.0 – 55.0 – ns Read Cycle tRC Read cycle time tAA Address to data valid / Address to ERR valid tOHA Data hold from address change / ERR hold from address change tACE tDOE – 45.0 – 55.0 ns 10.0 – 10.0 – ns CE1 LOW and CE2 HIGH to data valid / CE LOW to ERR valid – 45.0 – 55.0 ns OE LOW to data valid / OE LOW to ERR valid – 22.0 – 25.0 ns 5.0 – 5.0 – ns – 18.0 – 18.0 ns 10.0 – 10.0 – ns – 18.0 – 18.0 ns [19, 20] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z [19, 20, 21] CE1 LOW and CE2 HIGH to Low Z [19, 20] tHZCE CE1 HIGH and CE2 LOW to High Z [19, 20, 21] tPU[22] tPD[22] CE1 LOW and CE2 HIGH to power-up 0 – 0 – ns CE1 HIGH and CE2 LOW to power-down – 45.0 – 55.0 ns tLZCE Write Cycle[23, 24] tWC Write cycle time 45.0 – 55.0 – ns tSCE CE1 LOW and CE2 HIGH to write end 35.0 – 40.0 – ns tAW Address setup to write end 35.0 – 40.0 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 35.0 – 40.0 – ns tSD Data setup to write end 25.0 – 25.0 – ns tHD Data hold from write end 0 – 0 – ns – 18.0 – 20.0 ns 10.0 – 10.0 – ns tHZWE tLZWE WE LOW to High Z [19, 21, 20] WE HIGH to Low Z [19, 20] Notes 18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use output loading shown in AC Test Loads and Waveforms section, unless specified otherwise. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. Tested initially and after any design or process changes that may affect these parameters. 21. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 22. These parameters are guaranteed by design and are not tested. 23. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 24. The minimum write cycle pulse width for write cycle No. 2 (WE Controlled, OE Low) should be equal to he sum of tHZWE and tSD. Document Number: 001-84771 Rev. *I Page 9 of 19 CY62168G/CY62168GE MoBL® Switching Waveforms Figure 5. Read Cycle No. 1 of CY62168G (Address Transition Controlled)[25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 1 of CY62168GE (Address Transition Controlled)[25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 25. The device is continuously selected. OE = VIL, CE = VIL. 26. WE is HIGH for read cycle. Document Number: 001-84771 Rev. *I Page 10 of 19 CY62168G/CY62168GE MoBL® Switching Waveforms (continued) Figure 7. Read Cycle No. 2 (OE Controlled)[27, 28, 29] ADDRESS tRC CE tPD t HZCE tACE OE t HZOE t DOE t LZOE DATA I /O HIGH IMPEDANCE DATAOUT VALID HIGH IMPEDANCE t LZCE VCC SUPPLY CURRENT tPU ISB Notes 27. WE is HIGH for read cycle. 28. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 29. Address valid prior to or coincident with CE LOW transition. Document Number: 001-84771 Rev. *I Page 11 of 19 CY62168G/CY62168GE MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled)[30, 31, 32] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE OE tH Z O E D A T A I/O Note 33 tH D tS D D A T A I N V A L ID Notes 30. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 31. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 32. Data I/O is in the high-impedance state if CE = VIH, or OE = VIH. 33. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-84771 Rev. *I Page 12 of 19 CY62168G/CY62168GE MoBL® Switching Waveforms (continued) Figure 9. Write Cycle No. 2 (WE Controlled, OE Low)[34, 35, 36, 37] tWC ADDRESS tSCE CE tAW tHA tSA t PWE WE tSD t HZWE DATA I/O Note 38 t LZWE tHD DATAIN VALID Figure 10. Write Cycle No. 3 (CE Controlled)[34, 35, 36] tWC ADDRESS tSA tSCE CE tAW tHA t PWE WE OE t HZOE DATA I/O Note 38 tHD tSD DATAIN VALID Notes 34. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 35. The internal write time of the memory is defined by the overlap of WE = VIL, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write. 36. Data I/O is in high impedance state if CE = VIH, or OE = VIH. 37. The minimum write cycle pulse width should be equal to the sum of the tHZWE and tSD. 38. During this period I/O are in the output state. Do not apply input signals. Document Number: 001-84771 Rev. *I Page 13 of 19 CY62168G/CY62168GE MoBL® Truth Table – CY62168G/CY62168GE CE1 H CE2 WE [39] [39] X X I/Os Mode Power [39] High Z Deselect / Power down Standby (ISB2) [39] High Z Deselect / Power down Standby (ISB2) X [39] L L H H L Data Out (I/O0–I/O7) Read Active (ICC) L H H H High Z Output disabled Active (ICC) L H L X Data In (I/O0–I/O7) Write Active (ICC) X [39] OE X X ERR Output – CY62168GE Output[40] Mode 0 Read Operation, no single-bit error in the stored data. 1 Read Operation, single-bit error detected and corrected. High Z Device deselected / Outputs disabled / Write Operation. Note 39. The ‘X’ (Don’t care) state for the chip enables refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. 40. ERR is an Output pin.If not used, this pin should be left floating. Document Number: 001-84771 Rev. *I Page 14 of 19 CY62168G/CY62168GE MoBL® Ordering Information Speed (ns) 45 Ordering Code CY62168GE30-45BVXI Package Diagram Package Type (all Pb-free) 51-85150 48-ball VFBGA 51-85150 48-ball VFBGA CY62168G18-55BVXI Industrial 48-ball VFBGA, Tape and Reel CY62168G30-45BVXIT 55 Industrial 48-ball VFBGA, Tape and Reel CY62168GE30-45BVXIT CY62168G30-45BVXI Operating Range 51-85150 48-ball VFBGA Industrial 48-ball VFBGA, Tape and Reel CY62168G18-55BVXIT Ordering Code Definitions CY 621 6 8 G X XX - XX BV X I X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: BV = 48-ball VFBGA Speed Grade: XX = 45 or 55 45 = 45 ns; 55 = 55 ns Voltage Range: XX = 30 or 18 30 = 3 V typ; 18 = 1.8 V typ X = blank or E blank = without ERR output; E = with ERR output, Single bit error correction indicator Process Technology: G = 65 nm Bus Width: 8 = × 8 Density: 6 = 16-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document Number: 001-84771 Rev. *I Page 15 of 19 CY62168G/CY62168GE MoBL® Package Diagrams Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-84771 Rev. *I Page 16 of 19 CY62168G/CY62168GE MoBL® Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output MHz megahertz OE Output Enable A microampere SRAM Static Random Access Memory s microsecond VFBGA Very Fine-Pitch Ball Grid Array mA milliampere mm millimeter ns nanosecond ohm % percent pF picofarad V volt W watt WE Write Enable Document Number: 001-84771 Rev. *I Symbol Unit of Measure Page 17 of 19 CY62168G/CY62168GE MoBL® Document History Page Document Title: CY62168G/CY62168GE MoBL®, 16-Mbit (2M words × 8 bits) Static RAM with Error-Correcting Code (ECC) Document Number: 001-84771 Rev. ECN No. Orig. of Change Submission Date *G 4800984 VINI 07/31/2015 Changed status from Preliminary to Final. *H 5449003 VINI 11/03/2016 Updated Maximum Ratings: Updated Note 5 (Replaced “2 ns” with “20 ns”). Updated DC Electrical Characteristics: Changed minimum value of VOH parameter from 2.2 V to 2.4 V corresponding to Operating Range “2.7 V to 3.6 V”. Changed minimum value of VIH parameter from 2.0 V to 1.8 V corresponding to Operating Range “2.2 V to 2.7 V”. Updated Thermal Resistance: Replaced “two-layer” with “four-layer” in “Test Conditions” column. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Updated to new template. Completing Sunset Review. *I 6003639 AESATP12 12/22/2017 Updated logo and copyright. Document Number: 001-84771 Rev. *I Description of Change Page 18 of 19 CY62168G/CY62168GE MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/iot cypress.com/memory cypress.com/mcu PSoC cypress.com/psoc Touch Sensing USB Controllers Wireless Connectivity Cypress Developer Community Community | Projects | Video | Blogs | Training | Components cypress.com/interface Microcontrollers Power Management ICs PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2012-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). 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Document Number: 001-84771 Rev. *I Revised December 22, 2017 Page 19 of 19