TI1 CDC208NSR Dual 1-line to 4-line clock driver with 3-state output Datasheet

SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
D Low-Skew Propagation Delay
D
D
D
D
D
D
DW PACKAGE
(TOP VIEW)
Specifications for Clock-Driver
Applications
TTL-Compatible Inputs and
CMOS-Compatible Outputs
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC  (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic
Small-Outline (DW)
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
2Y2
2Y3
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1Y1
1A
1OE1
1OE2
VCC
VCC
2A
2OE1
2OE2
2Y4
description
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew
for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each
circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level
independent of the signal on the respective A input.
Skew parameters are specified for a reduced temperature and voltage range common to many applications.
The CDC208 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLES
INPUTS
OUTPUTS
1OE1
1OE2
1A
1Y1
1Y2
1Y3
1Y4
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
X
L
L
L
L
H
L
X
H
H
H
H
H
H
X
Z
Z
Z
Z
2A
2Y1
2Y2
INPUTS
OUTPUTS
2OE1
2OE2
2Y3
2Y4
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
X
L
L
L
L
H
L
X
H
H
H
H
H
H
X
Z
Z
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1998, Texas Instruments Incorporated
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#"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*&
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1
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
logic symbol†
X/Y
1OE1
18
17
1OE2
1
2
1
1
V4
2
G5
3
EN
4, 5
1A
19
4, 5
4, 5
4, 5
2OE1
1
2
3
13
8
12
9
2OE2
2A
20
10
11
14
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE1
18
20
1OE2
17
1
2
3
1A
2OE1
19
9
11
2
1Y3
1Y4
2Y1
12
10
2A
1Y2
13
8
2OE2
1Y1
14
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2Y2
2Y3
2Y4
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t / ∆v
Input transition rise or fall rate
fclock
TA
Input clock frequency
High-level input voltage
MIN
NOM
MAX
4.5
5
5.5
2
0
Low-level output current
0
Operating free-air temperature
−40
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V
V
0.8
Input voltage
UNIT
VCC
−24
V
V
mA
24
mA
10
ns / V
60
MHz
85
°C
3
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4.5 V
4.4
4.4
5.5 V
5.4
5.4
4.5 V
3.94
3.8
IOH = − 24 mA
5.5 V
4.94
4.8
IOH = − 75 mA†
5.5 V
IOH = − 50 µA
A
VOH
II
IOZ
ICC
IOL = 24 mA
IOL = 75 mA†
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
MIN
0.1
∆ICC‡
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
VO = VCC or GND
0.1
0.1
0.36
0.44
5.5 V
0.36
0.44
V
1.65
5.5 V
± 0.1
±1
µA
5.5 V
± 0.5
±5
µA
5.5 V
8
80
µA
5.5 V
0.9
1
mA
5V
POST OFFICE BOX 655303
0.1
4.5 V
4
Co
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
4
UNIT
V
5.5 V
5.5 V
IO = 0
MAX
3.85
4.5 V
IOL = 50 µA
A
VOL
TA = 25°C
TYP
MAX
VCC
• DALLAS, TEXAS 75265
pF
pF
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
1A and 2A
Any Y
tPLH
tPHL
1OE1, 1OE2, and
2OE1, 2OE2
Any Y
tPZH
tPZL
1OE2 or 2OE2
tPHZ
tPLZ
1OE2 or 2OE2
MIN
Any Y
1OE1 or 2OE1
MIN
MAX
5.3
8.5
10.9
5.3
11.7
3.6
7.7
11
3.6
11.5
4.7
8.5
11.7
4.7
12.8
4.4
8.4
11.3
4.4
12.4
4.4
8.1
11.3
4.4
12.4
5
9.6
13.3
5
14.9
4.2
7.4
9.3
4.2
10.2
5.4
7.5
9.2
5.4
9.9
Any Y
1OE1 or 2OE1
TA = 25°C
TYP
MAX
UNIT
ns
ns
ns
ns
switching characteristics, VCC = 5 V ± 0.25 V, TA = 25°C to 70°C (see Note 3 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
1A and 2A
Any Y
MIN
MAX
6.6
10.2
6.6
9.8
tsk(o)
1A and 2A
Any Y
NOTE 3: All specifications are valid only for all outputs switching simultaneously and in phase.
1
UNIT
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance per bank
TEST CONDITIONS
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CL = 50 pF,
f = 1 MHz
TYP
96
12
UNIT
pF
5
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
2 × VCC
From Output
Under Test
500 Ω
3V
Output
Control
(low-level
enabling)
LOAD CIRCUIT FOR OUTPUTS
1.5 V
3V
1.5 V
1.5 V
0V
tPLH
Output
tPHL
VOH
50% VCC
VOL
50% VCC
tPLZ
≈ VCC
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at 2 × VCC
(see Note C)
1.5 V
0V
tPZL
Input
(see Note B)
S1
Open
2 × VCC
GND
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
GND
CL = 50 pF
(see Note A)
(see Note A)
S1
500 Ω
50% VCC
tPZH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
20% VCC
VOL
tPHZ
50% VCC
80% VCC
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
1A, 2A
1Y1
tPLH1
tPHL1
tPLH2
tPHL2
tPLH3
tPHL3
tPLH4
tPHL4
tPLH5
tPHL5
tPLH6
tPHL6
tPLH7
tPHL7
tPLH8
tPHL8
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
NOTE A: Output skew, tsk(o), is calculated as the greater of:
− The difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8)
− The difference between the fastest and slowest of tPHLn (n = 1, 2, . . . , 8)
Figure 2. Waveforms for Calculation of tsk(o)
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7
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDC208DBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
CDC208DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC208
CDC208DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC208
CDC208DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC208
CDC208DWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CDC208
CDC208N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
CDC208NS
ACTIVE
SO
NS
20
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDC208
CDC208NSG4
ACTIVE
SO
NS
20
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDC208
CDC208NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDC208
CDC208NSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CDC208
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
11-Apr-2013
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDC208DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
CDC208NSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.5
4.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDC208DWR
SOIC
DW
20
2000
367.0
367.0
45.0
CDC208NSR
SO
NS
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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