TI CY29FCT52TQSOP 8-bit registered transceiver Datasheet

CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
D
Q OR SO PACKAGE
(TOP VIEW)
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM2952
Reduced VOH (Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Ioff Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
64-mA Output Sink Current
32-mA Output Source Current
D
D
D
D
D
D
D
B7
B6
B5
B4
B3
B2
B1
B0
OEB
CPA
CEA
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
A7
A6
A5
A4
A3
A2
A1
A0
OEA
CPB
CEB
description
The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two
bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each
register. Both A outputs and B outputs are specified to sink 64 mA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
DESCRIPTION
A
A register inputs or B register outputs
B
B register inputs or A register outputs
CPA
Clock for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal.
CEA
Clock enable for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal. When CEA
is high, the A register holds its contents, regardless of CPA signal transitions.
OEA
Output enable for the A register. When OEA is low, the A register outputs are enabled onto the B lines. When OEA is high, the A outputs
are in the high-impedance state.
CPB
Clock for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal.
CEB
Clock enable for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. When
CEB is high, the B register holds its contents, regardless of CPA signal transitions.
OEB
Output enable for the B register. When OEB is low, the B register outputs are enabled onto the A lines. When OEB is high, the B outputs
are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
ORDERING INFORMATION
QSOP – Q
–40°C to 85°C
SPEED
(ns)
PACKAGE†
TA
SOIC – SO
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tape and reel
6.3
CY29FCT52CTQCT
Tube
6.3
CY29FCT52CTSOC
Tape and reel
6.3
CY29FCT52CTSOCT
29FCT52C
29FCT52C
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Function Tables
FUNCTION TABLE
INPUTS
D
CP
CE
INTERNAL
Q
FUNCTION
X
X
H
NC
Hold data
L
L
L
H
L
H
Load data
H = High logic level, L = Low logic level, X = Don’t care,
NC = No change
OUTPUT CONTROL
OE
INTERNAL
Q
Y
OUTPUTS
FUNCTION
H
X
Z
Disable outputs
L
L
L
L
H
H
Enable outputs
H = High logic level, L = Low logic level, X = Don’t care,
Z = High impedance (off) state.
logic diagram
CPA
CEA
OEB
A0
D0 CE CP Q0
B0
A1
D1
Q1
B1
A2
D2
Q2
B2
A3
D3
Q3
B3
A4
D4
Q4
B4
D5
Q5
D6
Q6
D7
Q7
Q0
D0
Q1
D1
Q2
D2
Q3
D3
Q4
D4
Q5
D5
Q6
D6
A5
A6
A7
B5
B6
B7
Q7 CE CP D7
OEA
2
CPB
CEB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
absolute maximum rating over operating free-air temperature range (unless otherwise noted)†
Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA
Package thermal impedance, qJA (see Note 1): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W
SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 135_C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65_C to 150_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 2)
VCC
VIH
Supply voltage
VIL
IOH
Low-level input voltage
IOL
TA
Low-level output current
High-level input voltage
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
High-level output current
Operating free-air temperature
–40
V
0.8
V
– 32
mA
64
mA
85
°C
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
VCC = 4.75 V,
IIN = –18 mA
IOH = –32 mA
VOH
VCC = 4
4.75
75 V
VOL
VH
VCC = 4.75 V,
All inputs
II
IIH
VCC = 5.25 V,
VCC = 5.25 V,
VIN = VCC
VIN = 2.7 V
IIL
IOS‡
VCC = 5.25 V,
VCC = 5.25 V,
VIN = 0.5 V
VOUT = 0 V
Ioff
VCC = 0 V,
VOUT = 4.5 V
ICC
∆ICC
VCC = 5.25 V, VIN < 0.2 V, VIN ≥ VCC – 0.2 V
VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open
ICCD¶
VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open,
OEA or OEB = GND, VIN < 0.2 V or VIN > VCC – 0.2 V
TYP†
MAX
UNIT
–0.7
–1.2
V
2
IOH = –15 mA
IOL = 64 mA
2.4
V
3.3
0.3
0.55
V
5
µA
±1
µA
0.2
V
±1
µA
–120
–225
mA
±1
µA
0.1
0.2
mA
0.5
2
mA
0.06
0.12
mA/
MHz
0.7
1.4
VIN = 3.4 V or GND
VIN < 0.2 V or
VIN > VCC – 0.2 V
1.2
3.4
1.6
3.2||
VIN = 3.4 V or GND
3.9
12.2||
Ci
5
10
Co
9
12
IC#
VCC = 5
5.25
25 V
V,
f0 = 10 MHz,,
Outputs open,
OEA or OEB = GND
–60
One bit switching
at f1 = 5 MHz
at 50% duty cycle
Eight bits switching
at f1 = 2.5 MHz
at 50% duty cycle
VIN < 0.2 V or
VIN > VCC – 0.2 V
mA
pF
pF
† Typical values are at VCC = 5 V, TA = 25°C.
‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or
sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged
shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence
of parameter tests, IOS tests should be performed last.
§ Per TTL driven input (VIN = 3.4 V); all other inputs at VCC or GND
¶ This parameter is derived for use in total power-supply calculations.
# IC
= ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1)
Where:
IC
= Total supply current
ICC = Power-supply current with CMOS input levels
∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V)
DH
= Duty cycle for TTL inputs high
NT
= Number of TTL inputs at DH
ICCD = Dynamic current caused by an input transition pair (HLH or LHL)
f0
= Clock frequency for registered devices, otherwise zero
f1
= Input signal frequency
N1
= Number of inputs changing at f1
All currents are in milliamperes and all frequencies are in megahertz.
|| Values for these conditions are examples of the ICC formula.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
PARAMETER
tw
Pulse duration, clock
tsu
Setup time,
time before CPA↑ or CPB↑
th
time after CPA↑ or CPB↑
Hold time,
MIN
MAX
3
Data
Data
ns
2.5
CEA or CEB
ns
3
1.5
CEA or CEB
UNIT
ns
2
switching characteristics over operating free-air temperature range (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
CPA CPB
CPA,
A B
A,
tPZH
tPZL
OEA or OEB
A or B
tPHZ
tPLZ
OEA or OEB
A or B
PARAMETER
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
MAX
2
6.3
2
6.3
1.5
7
1.5
7
1.5
6.5
1.5
6.5
UNIT
ns
ns
ns
5
CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A – MAY 1994 – REVISED OCTOBER 2001
PARAMETER MEASUREMENT INFORMATION
7V
From Output
Under Test
From Output
Under Test
Test
Point
CL = 50 pF
(see Note A)
Open
TEST
GND
CL = 50 pF
(see Note A)
500 Ω
S1
500 Ω
S1
Open
7V
Open
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
LOAD CIRCUIT FOR
3-STATE OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
tsu
3V
1.5 V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
Out-of-Phase
Output
tPLZ
≈3.5 V
1.5 V
tPZH
VOH
1.5 V
VOL
1.5 V
0V
Output
Waveform 1
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
VOH
In-Phase
Output
3V
Output
Control
Output
Waveform 2
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CY29FCT52CTQC
PREVIEW
SSOP/
QSOP
DBQ
24
CY29FCT52CTQCT
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
CY29FCT52CTQCTE4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
CY29FCT52CTSOC
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT52CTSOCE4
ACTIVE
SOIC
DW
24
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT52CTSOCT
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CY29FCT52CTSOCTE4
ACTIVE
SOIC
DW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
55
TBD
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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