ON FDMC86183 N-channel shielded gate powertrench Datasheet

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FDMC86183
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 47 A, 12.8 mΩ
Features
General Description
„ Shielded Gate MOSFET Technology
This N-Channel MV MOSFET is produced using ON
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized to minimise on-state resistance and yet maintain
superior switching performance with best in class soft body
diode.
„ Max rDS(on) = 12.8 mΩ at VGS = 10 V, ID = 16 A
„ Max rDS(on) = 34.6 mΩ at VGS = 6 V, ID = 8 A
„ 50% Lower Qrr than Other MOSFET Suppliers
„ Lowers Switching Noise/EMI
Applications
„ MSL1 Robust Package Design
„ 100% UIL Tested
„ Primary DC-DC MOSFET
„ RoHS Compliant
„ Synchronous Rectifier in DC-DC and AC-DC
„ Motor Drive
„ Solar
Pin 1
Pin 1
S
D
Top
D
D
S
S
S
D
S
D
S
D
G
D
G
D
Bottom
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
ID
TC = 25 °C
-Continuous
TC = 100 °C
-Continuous
TA = 25 °C
-Pulsed
Single Pulse Avalanche Energy
EAS
PD
TJ, TSTG
(Note 5)
TC = 25 °C
Power Dissipation
TA = 25 °C
Units
V
±20
V
47
(Note 5)
29
(Note 1a)
9.7
(Note 4)
189
(Note 3)
Power Dissipation
Ratings
100
96
52
(Note 1a)
Operating and Storage Junction Temperature Range
2.3
-55 to +150
A
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
2.4
RθJA
Thermal Resistance, Junction to Ambient
(Note 1a)
53
°C/W
Package Marking and Ordering Information
Device Marking
FDMC86183
Device
FDMC86183
Package
Power 33
Semiconductor Components Industries, LLC, 2016
December, 2016, Rev. 1.0
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
Publication Order Number:
FDMC86183/D
1
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
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Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 80 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
100
nA
4.0
V
100
V
63
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 90 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 90 μA, referenced to 25 °C
VGS = 10 V, ID = 16 A
11
12.8
rDS(on)
Static Drain to Source On Resistance
VGS = 6 V, ID = 8 A
18
34.6
VGS = 10 V, ID = 16 A, TJ = 125 °C
18
21
VDS = 5 V, ID = 16 A
20
gFS
Forward Transconductance
2.0
3.2
-8
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 50 V, VGS = 0 V,
f = 1 MHz
0.1
1080
1515
646
905
pF
pF
10
15
pF
0.5
1.5
Ω
Switching Characteristics
td(on)
Turn-On Delay Time
11
20
ns
tr
Rise Time
3
10
ns
td(off)
Turn-Off Delay Time
15
27
ns
tf
Fall Time
3
10
ns
nC
VDD = 50 V, ID = 16 A,
VGS = 10 V, RGEN = 6 Ω
Qg
Total Gate Charge
VGS = 0 V to 10 V
15
21
Qg
Total Gate Charge
VGS = 0 V to 6 V
10
14
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
Qoss
Output Charge
VDD = 50 V,
ID = 16 A
VDD = 50 V, VGS = 0 V
nC
5
nC
3.4
nC
43
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 2.1 A
(Note 2)
0.7
1.2
VGS = 0 V, IS = 16 A
(Note 2)
0.9
1.3
IF = 8 A, di/dt = 300 A/μs
IF = 8 A, di/dt = 1000 A/μs
V
22
36
ns
36
58
nC
18
33
ns
79
127
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.
a. 53 °C/W when mounted
on a 1 in2 pad of 2 oz
copper
b. 125 °C/W when mounted
on a minimum pad of 2 oz
copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 96 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 8 A, VDD = 100 V, VGS =10 V. 100% test at L = 0.3 mH, IAS = 18 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
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2
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
100
5
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
VGS = 10 V
VGS = 7 V
ID, DRAIN CURRENT (A)
80
VGS = 6.5 V
60
VGS = 6 V
40
VGS = 5.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
VGS = 5.5 V
4
VGS = 6 V
3
VGS = 6.5 V
2
VGS = 7 V
1
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
5
0
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
80
100
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.0
60
ID = 16 A
VGS = 10 V
1.8
rDS(on), DRAIN TO
1.6
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
40
ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
1.4
1.2
1.0
0.8
0.6
-75
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
50
ID = 16 A
40
30
TJ = 125 oC
20
10
TJ = 25 oC
0
-50
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
4
5
6
7
8
9
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On- Resistance
vs. Junction Temperature
Figure 4. On-Resistance vs. Gate to
Source Voltage
100
IS, REVERSE DRAIN CURRENT (A)
100
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
80
ID, DRAIN CURRENT (A)
VGS = 10 V
VDS = 5 V
60
40
TJ = 150 oC
TJ = 25 oC
20
TJ = -55 oC
0
2
3
4
5
6
7
8
9
VGS = 0 V
10
1
0.1
TJ = 150 oC
0.01
TJ = -55 oC
0.001
0.0
10
TJ = 25 oC
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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3
1.2
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
5000
ID = 16 A
Ciss
VDD = 50 V
1000
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 25 V
6
VDD = 75 V
4
Coss
100
10
2
f = 1 MHz
VGS = 0 V
0
0
4
8
12
16
Crss
1
0.1
20
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
50
50
o
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
RθJC = 2.4 C/W
TJ = 25 oC
10
TJ = 100 oC
TJ = 125
1
0.01
0.1
oC
1
10
40
VGS = 10 V
30
20
VGS = 6 V
10
0
25
100
50
150
P(PK), PEAK TRANSIENT POWER (W)
10000
100
ID, DRAIN CURRENT (A)
125
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
300
10 μs
THIS AREA IS
LIMITED BY rDS(on)
100 μs
SINGLE PULSE
TJ = MAX RATED
RθJC = 2.4 oC/W
o
TC = 25 C
1
1 ms
CURVE BENT TO
MEASURED DATA
10
10 ms
100 ms
100
SINGLE PULSE
RθJC = 2.4 oC/W
TC = 25 oC
1000
10
0.1
0.1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
1
75
o
tAV, TIME IN AVALANCHE (ms)
100
500
10
-5
10
-4
10
-3
10
-2
10
-1
10
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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4
1
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
0.005
-5
10
ZθJC(t) = r(t) x RθJC
RθJC = 2.4 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
-4
10
-3
-2
10
10
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
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5
-1
10
1
FDMC86183 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted.
3.40
3.20
PKG
CL
8
2.37 MIN
A
(0.45) 8
B
5
PKG
CL
3.40
3.20
PKG CL
SYM
CL
5
2.15 MIN
(0.40)
(0.65)
0.70 MIN
PIN 1
INDICATOR
1
4
1
4
0.65
1.95
SEE
DETAIL A
0.65
1
LAND PATTERN
RECOMMENDATION
0.10 C
1.95
0.10 C A B
0.37 (8X)
0.27
0.42 MIN
(8X)
4
0.60
0.40
0.80
0.70
0.08 C
0.25
0.15
0.05
0.00
C
SEATING
PLANE
PKG CL
1.99
1.79
SCALE: 2X
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
(0.52 TYP)
8
5
(2.27)
(0.33) TYP
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: MKT-PQFN08SREV1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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