Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DS90UH929-Q1 SNLS458 – NOVEMBER 2014 DS90UH929-Q1 720p HDMI to FPD-Link III Bridge Serializer with HDCP 1 Features 3 Description • The DS90UH929-Q1 is a HDMI to FPD-Link III bridge device which, in conjunction with the FPD-Link III DS90UH926Q-Q1/DS90UH928Q-Q1 deserializers, provides 1-lane high-speed serial stream over costeffective 50Ω single-ended coaxial or 100Ω differential shielded twisted-pair (STP) cable. It serializes a HDMI v1.4b input supporting video resolutions up to WXGA and 720p with 24-bit color depth. The DS90UH929-Q1 is also compatible with the DS90UH940-Q1/DS90UH948-Q1 deserializers. 1 • • • • • • • • • • Supports TMDS Clock up to 96 MHz for WXGA and 720p60 or 1080i60 Resolutions with 24-Bit Color Depth FPD-Link III Outputs High-Definition Multimedia (HDMI) v1.4b Inputs HDMI-Mode DisplayPort (DP++) Inputs Integrated HDCP v1.4 Cipher Engine with OnChip Key Storage HDMI Audio Extraction for up to 8 Channels Supports up to 15 Meters of Cable with Automatic Temperature and Aging Compensation Tracks Spread Spectrum Input Clock to Reduce EMI I2C (Master/Slave) with 1Mbps Fast-Mode Plus compatible with DS90UH926Q-Q1 and DS90UH928Q-Q1 FPD-Link III Deserializers Automotive Grade Product: AEC-Q100 Grade 2 Qualified 2 Applications • • • Automotive Infotainment: – IVI Head Units and HMI Modules – Rear Seat Entertainment Systems – Digital Instrument Clusters Security and Surveillance Camera Consumer Input HDMI Port The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C communication, over the same differential link. Consolidation of video data and control over one differential pair reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. The DS90UH929-Q1 supports HDCP Repeater applications where all authentication and encryption functions are handled without the need for an external controller. HDMI audio and video data are decrypted at the input and re-encrypted prior to sending onto the FPD-Link III interface. The DS90UH929-Q1 supports multi-channel audio received through HDMI or an external I2S interface. The device also supports an optional auxiliary audio interface. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DS90UH929-Q1 VQFN RGC (64) 9.00 mm X 9.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Applications Diagram VDDIO 1.8V Mobile Device /Graphics Processor TMDS Interface HDMI 3.3V 1.1V VDDIO 1.8V or 3.3V RIN- R[7:0] G[7:0] B[7:0] HS VS DE PCLK DS90UH926Q-Q1 Deserializer LOCK PASS FPD-Link III 1 Pair / AC Coupled IN_CLK+ IN_D0+ DOUT+ IN_D1+ IN_D2+ CEC DDC HPD GPIO RIN+ DOUTDS90UH929-Q1 Serializer 4 / PDB OSS_SEL OEN MODE_SEL 3 / INTB_IN I2C_SCL I2C_SDA IDx DAP SCL SDA IDx RGB Display 720p 24-bit color depth I2S AUDIO (STEREO) MCLK DAP HDCP ± High-Bandwidth Digital Content Protection TMDS ± Transition-Minimized Differential Signaling HDMI ± High Definition Multimedia Interface 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Applications Diagram ............................................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 1 1 1 1 2 3 7 Absolute Maximum Ratings ..................................... 7 Handling Ratings....................................................... 7 Recommended Operating Conditions....................... 7 Thermal Information .................................................. 8 DC Electrical Characteristics .................................... 9 AC Electrical Characteristics................................... 11 DC And AC Serial Control Bus Characteristics ...... 12 Recommended Timing for the Serial Control Bus .. 13 Typical Characteristics ............................................ 16 Detailed Description ............................................ 17 8.1 Overview ................................................................. 17 8.2 Functional Block Diagram ....................................... 17 8.3 8.4 8.5 8.6 9 Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 18 27 29 32 Application and Implementation ........................ 61 9.1 Applications Information.......................................... 61 9.2 Typical Applications ................................................ 61 10 Power Supply Recommendations ..................... 66 10.1 Power Up Requirements And PDB Pin................. 66 11 Layout................................................................... 67 11.1 Layout Guidelines ................................................. 67 11.2 Layout Example .................................................... 68 12 Device and Documentation Support ................. 69 12.1 12.2 12.3 12.4 Documentation Support ....................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 69 69 69 69 13 Mechanical, Packaging and Orderable Information ........................................................... 69 5 Revision History 2 DATE REVISION November 2014 * NOTES Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 6 Pin Configuration and Functions I2S_DA / GPIO6_REG I2S_CLK / GPIO8_REG I2S_WC / GPIO7_REG 35 34 33 I2S_DD / GPIO3 38 I2S_DC / GPIO2 X1 39 I2S_DB / GPIO5_REG REM_INTB 40 36 VDDL11 41 37 RX_5V HPD 42 45 DDC_SDA VDDIO DDC_SCL 46 43 NC6 47 44 NC7 48 64 PINS Top View IN_CLK- 49 32 MODE_SEL1 IN_CLK+ 50 31 PDB VDD18 51 30 RES2 VDDHA11 52 29 RES1 NC8 53 28 VDDHS11 VDDHA11 54 27 DOUT+ IN_D0- 55 26 DOUT- IN_D0+ 56 VTERM 57 VDDHA11 58 IN_D1- 59 22 NC4 IN_D1+ 60 21 VDDHS11 VDDHA11 61 20 IN_D2- 62 19 LFT IDx IN_D2+ 63 18 MODE_SEL0 VDD18 64 17 VDDP11 DS90UH929-Q1 64 VQFN Top View 7 8 9 10 11 12 13 VDDL11 NC0 VDDA11 NC1 NC2 NC3 INTB 16 6 MCLK 5 SWC / GPIO1 SCLK / I2CSEL 15 4 SDIN / GPIO0 14 3 VDDIO SCL 2 SDA 1 CEC RES0 DAP = GND 25 VDDS11 24 VDD18 23 NC5 Pin Functions PIN NAME NO. I/O, TYPE DESCRIPTION HDMI TMDS INPUT IN_CLKIN_CLK+ 49 50 I, TMDS TMDS Clock Differential Input IN_D0IN_D0+ 55 56 I, TMDS TMDS Data Channel 0 Differential Input IN_D1IN_D1+ 59 60 I, TMDS TMDS Data Channel 1 Differential Input IN_D2IN_D2+ 62 63 I, TMDS TMDS Data Channel 2 Differential Input HPD 42 O, OpenDrain Hot Plug Detect Output. Pull up to RX_5V with a 1kΩ resistor RX_5V 43 I DDC_SDA 44 IO, OpenDrain DDC_SCL 45 OTHER HDMI HDMI 5V Detect Input DDC Slave Serial Data Pull up to RX_5V with a 47kΩ resistor I, Open-Drain DDC Slave Serial Clock Pull up to RX_5V with a 47kΩ resistor Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 3 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Pin Functions (continued) PIN NAME NO. I/O, TYPE DESCRIPTION CEC 1 IO, OpenDrain Consumer Electronic Control Channel Input/Output Interface. Pull-up with a 27kΩ resistor to 3.3V X1 39 I, LVCMOS DOUT- 26 O FPD-Link III Inverting Output The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers DOUT+ 27 O FPD-Link III True Output The output must be AC-coupled with a 0.1µF capacitor for interfacing with 92x deserializers and 33nF capacitor for 94x deserializers LFT 20 Analog SDA 14 IO, OpenDrain I2C Data Input / Output Interface Open drain. Must have an external pull-up to resistor to 1.8V or 3.3V. See I2CSEL pin. DO NOT FLOAT. Recommended pull-up: 4.7kΩ. SCL 15 IO, OpenDrain I2C Clock Input / Output Interface Open drain. Must have an external pull-up resistor to 1.8V or 3.3V. See I2CSEL pin. DO NOT FLOAT. Recommended pull-up: 4.7kΩ. I2CSEL 6 I, LVCMOS IDx 19 Analog I2C Serial Control Bus Device ID Address Select MODE_SEL0 18 Analog Mode Select 0. See Table 4. MODE_SEL1 32 Analog Mode Select 1. See Table 4. PDB 31 I, LVCMOS Power-Down Mode Input Pin INTB 13 O, OpenDrain Open Drain. Remote interrupt. Active LOW. Pull up to VDDIO with a 4.7kΩ resistor. REM_INTB 40 O, OpenDrain Remote interrupt. Mirrors status of INTB_IN from the deserializer. Note: External pull-up to 1.8V required. Recommended pull-up: 4.7kΩ. INTB = H, Normal Operation INTB = L, Interrupt Request Optional Oscillator Input: This pin is the optional reference clock for CEC. It must be connected to a 25 MHz 0.1% (1000ppm), 45-55% duty cycle clock source at CMOS-level 1.8V. Leave it open if unused. FPD-LINK III SERIAL FPD-Link III Loop Filter Connect to a 10nF capacitor to GND CONTROL 4 I2C Voltage Level Strap Option Tie to VDDIO with a 10kΩ resistor for 1.8V I2C operation. Leave floating for 3.3V I2C operation. This pin is read as an input at power up. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Pin Functions (continued) PIN NAME I/O, TYPE NO. DESCRIPTION BIDIRECTIONAL CONTROL CHANNEL (BCC) GPIO PINS GPIO0 4 IO, LVCMOS BCC GPIO0. Shared with SDIN GPIO1 5 IO, LVCMOS BCC GPIO1. Shared with SWC GPIO2 37 IO, LVCMOS BCC GPIO2. Shared with I2S_DC GPIO3 38 IO, LVCMOS BCC GPIO3. Shared with I2S_DD REGISTER-ONLY GPIO GPIO5_REG 36 IO, LVCMOS General Purpose Input/Output 5 Local register control only. Shared with I2S_DB GPIO6_REG 35 IO, LVCMOS General Purpose Input/Output 6 Local register control only. Shared with I2S_DA GPIO7_REG 33 IO, LVCMOS General Purpose Input/Output 7 Local register control only. Shared with I2S_WC GPIO8_REG 34 IO, LVCMOS General Purpose Input/Output 8 Local register control only. Shared with I2S_CLK SLAVE MODE LOCAL I2S CHANNEL PINS I2S_WC 33 I, LVCMOS Slave Mode I2S Word Clock Input. Shared with GPIO7_REG I2S_CLK 34 I, LVCMOS Slave Mode I2S Clock Input. Shared with GPIO8_REG I2S_DA 35 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO6_REG I2S_DB 36 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO5_REG I2S_DC 37 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO2 I2S_DD 38 I, LVCMOS Slave Mode I2S Data Input. Shared with GPIO3 AUXILIARY I2S CHANNEL PINS SWC 5 O, LVCMOS Master Mode I2S Word Clock Ouput. Shared with GPIO1 SCLK 6 O, LVCMOS Master Mode I2S Clock Ouput. Shared with I2CSEL. This pin is sampled following power-up as I2CSEL, then it will switch to SCLK operation as an output. I, LVCMOS Master Mode I2S Data Input. Shared with GPIO0 SDIN 4 MCLK 16 IO, LVCMOS Master Mode I2S System Clock Input/Output POWER and GROUND VTERM 57 Power 3.3V (±5%) Supply for DC-coupled internal termination OR 1.8V (±5%) Supply for AC-coupled internal termination Refer to Figure 22 or Figure 21. VDD18 24 51 64 Power 1.8 (±5%) Analog supply. Refer to Figure 22 or Figure 21. VDDA11 9 Power 1.1V(±5%) Analog supply. Refer to Figure 22 or Figure 21. VDDHA11 52 54 58 61 Power 1.1V(±5%) TMDS supply. Refer to Figure 22 or Figure 21. VDDHS11 21 28 Power 1.1V(±5%) supply. Refer to Figure 22 or Figure 21. VDDL11 7 41 Power 1.1V(±5%) Digital supply. Refer to Figure 22 or Figure 21. VDDP11 17 Power 1.1V(±5%) PLL supply. Refer to Figure 22 or Figure 21. VDDS11 25 Power 1.1V(±5%) Serializer supply. Refer to Figure 22 or Figure 21. VDDIO 3 46 Power 1.8V (±5%) IO supply. Refer to Figure 22 or Figure 21. Thermal Pad GND Ground. Connect to Ground plane with at least 9 vias. GND OTHER RES0 RES1 2 29 Reserved. Tie to GND. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 5 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Pin Functions (continued) PIN I/O, TYPE DESCRIPTION NAME NO. RES2 30 Reserved. Connect with 50Ω to GND. NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 8 10 11 12 22 23 47 48 53 No connect. Leave floating. Do not connect to VDD or GND. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 7 Specifications 7.1 Absolute Maximum Ratings MIN MAX UNIT Supply Voltage – VDD11 −0.3 1.7 V Supply Voltage – VDD18 -0.3 2.5 V Supply Voltage – VDDIO −0.3 2.5 V OpenLDI Inputs -0.3 2.75 V LVCMOS I/O Voltage −0.3 (VDDIO + 0.3) V 1.8V Tolerant I/O -0.3 2.5 V 3.3V Tolerant I/O -0.3 4.0 V 5V Tolerant I/O -0.3 5.3 V FPD-Link III Output Voltage −0.3 1.7 V 150 °C Junction Temperature For soldering specifications: see product folder at www.ti.com and www.ti.com/lit/an/snoa549c/snoa549c.pdf 7.2 Handling Ratings Tstg Storage temperature range 64 Lead VQFN Package MAX UNIT -65 +150 °C -2 +2 kV Charged device model (CDM), per AEC Q100-011 -750 +750 V ESD Rating (IEC 61000-4-2) RD = 330Ω, CS = 150pF Air Discharge (DOUT+, DOUT-) -15 +15 Contact Discharge (DOUT+, DOUT-) -8 +8 ESD Rating (ISO10605) RD = 330Ω, CS = 150pF RD = 2KΩ, CS = 150pF or 330pF Air Discharge (DOUT+, DOUT-) -15 +15 Contact Discharge (DOUT+, DOUT-) -8 +8 V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) MIN kV kV AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 7.3 Recommended Operating Conditions MIN NOM MAX UNIT Supply Voltage (VDD11) 1.045 1.1 1.155 V Supply Voltage (VDD18) 1.71 1.8 1.89 V LVCMOS Supply Voltage (VDDIO) 1.71 1.8 1.89 V VDDI2C, 1.8V Operation 1.71 1.8 1.89 V VDDI2C, 3.3V Operation 3.135 3.3 3.465 V HDMI Termination (VTERM), DC-coupled 3.135 3.3 3.465 V HDMI Termination (VTERM), AC-coupled 1.71 1.8 1.89 V Operating Free Air −40 +25 +105 °C 96 MHz Temperature (TA) TMDS Frequency 25 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 7 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 7.4 Thermal Information THERMAL METRIC (1) VQFN 64 PINS RθJA Junction-to-ambient thermal resistance 25.8 RθJC(top) Junction-to-case (top) thermal resistance 11.4 RθJB Junction-to-board thermal resistance 5.1 ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.1 RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 (1) 8 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 7.5 DC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT 1.8V LVCMOS I/O VIH High Level Input Voltage VIL Low Level Input Voltage IIN Input Current VIN = 0V or 1.89V VOH High Level Output Voltage IOH = −4mA VOL Low Level Output Voltage IOL = +4mA IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE™ Output VOUT = 0V or VDDIO, PDB = L Current SCLK/I2CSEL, PDB, SDIN/GPIO0, SWC/GPIO1, MCLK I2S_DC/GPIO2, I2S_DD/GPIO3, I2S_DB/GPIO5_RE G, I2S_DA/GPIO6_RE G, I2S_CLK/GPIO8_R EG, I2S_WC/GPIO7_R EG 0.65 * VDDIO V 0 0.35 * VDDIO V −10 10 μA 0.7 * VDDIO VDDIO V GND 0.26 * VDDIO V Same as above -50 mA −10 10 μA VTERM - 300 VTERM - 37.5 mV VTERM - 10 VTERM + 10 mV 150 1200 mVP-P 110 Ω TMDS INPUTS -- FROM HDMI v1.4b SECTION 4.2.5 VICM1 Input Common-Mode Voltage VICM2 Input Common-Mode IN_CLK ≤ 96MHz Voltage VIDIFF Input Differential Voltage Level RTMDS Termination Resistance IN_D[2:0]+, IN_D[2:0]IN_CLK+, IN_CLKVTERM = 1.8V (+,5%) or VTERM = 3.3V (+,- 5%) IN_D[2:0]+, IN_D[2:0]IN_CLK+, IN_CLK- Differential 90 100 HDMI IO -- FROM HDMI v1.4b SECTION 4.2.7 to 4.2.9 VRX_5V 4.8 +5V Power Signal 5.3 V 50 mA 2.4 5.3 V GND 0.4 V -10 10 uA 0.3*VDD,DDC V RX_5V I5V_Sink +5V Input Current VOH,HPD High Level Output Voltage, HPD IOH = -4mA VOL,HPD Low Level Output Voltage, HPD IOL = +4mA IIZ,HPD Power-Down Input Current, HPD PDB = L VIL,DDC Low Level Input Voltage, DDC VIH,DDC High Level Input Voltage, DDC IIZ,DDC Power-Down Input Current, DDC HPD, RPU = 1 kΩ DDC_SCL, DDC_SDA PDB = L 0.7*VDD,DDC -10 V 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 µA 9 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com DC Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER VIH,CEC High Level Input Voltage, CEC VIL,CEC Low Level Input Voltage, CEC VHY,CEC Input Hysteresis, CEC VOL,CEC Low Level Output Voltage, CEC VOH,CEC High Level Output Voltage, CEC IOFF_CE Power-Down Input Current, CEC C TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT 2 V 0.8 0.4 V V CEC GND 0.6 V 2.5 3.63 V -1.8 1.8 µA PDB = L FPD-LINK III DIFFERENTIAL DRIVER VODp-p Output Differential Voltage ΔVOD Output Voltage Unbalance VOS Output Differential Offset Voltage 900 1 IOS Output Short Circuit Current FPD-Link III Outputs = 0V RT Termination Resistance Single-ended IDD,VTER VTERM Current, Normal Operation M Colorbar Pattern IDDZ18 IDDZ,VTE RM (1) 10 50 mV -50 40 mA 50 Ω 60 (1) Colorbar Pattern IDDZ11 mV mV 1 Supply Current, Normal Operation IDD18 50 550 Offset Voltage Unbalance IDD11 mVp-p DOUT+, DOUT- ΔVOS SUPPLY CURRENT 1200 Supply Current, Power Down Mode PDB = L VTERM Current, Power Down Mode Colorbar Pattern 330 mA 50 mA 60 mA 15 mA 5 mA 5 mA Specification is ensured by bench characterization. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 7.6 AC Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. PARAMETER GPIO FREQUENCY TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT (1) Rb,FC Forward Channel GPIO Frequency IN_CLK = 25MHz - 96MHz GPIO[3:0] tGPIO,FC GPIO Pulse Width, Forward Channel IN_CLK = 25MHz - 96MHz GPIO[3:0] 0.25 * IN_CLK MHz >2 / IN_CLK s TMDS INPUT Skew-Intra Maximum Intra-Pair Skew 0.4 UITMDS (2) IN_CLK±, IN_D[2:0]± 0.2*Tchar (3) + 1.78ns Skew-Inter Maximum Inter-Pair Skew ITJIT Input Total Jitter Tolerance IN_CLK± ns UITMDS (2) 0.3 FPD-LINK III OUTPUT tLHT tHLT Low Voltage Differential Low-to-High Transition Time 80 ps Low Voltage Differential High-to-Low Transition Time 80 ps 100 ns 5 ms (2) s tXZD Output Active to OFF Delay tPLD Lock Time (HDMI Rx) tSD Delay — Latency tDJIT Output Total Jitter(Figure 5 ) λSTXBW δSTX (1) (2) (3) (4) PDB = L IN_CLK± Random Pattern Low pass filter IN_CLK/20 145*T 0.3 UIFPD3 (4) Jitter Transfer Function (-3dB Bandwidth) 960 kHz Jitter Transfer Function Peaking 0.1 dB Back channel rates are available on the companion deserializer datasheet. One bit period of the TMDS input. Ten bit periods of the TMDS input. One bit period of the serializer output. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 11 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 7.7 DC And AC Serial Control Bus Characteristics Over VDDI2C supply and temperature ranges unless otherwise specified. VDDI2C can be 1.8V (+,- 5%) or 3.3V (+,- 5%) (refer to I2CSEL pin description for 1.8V or 3.3V operation). PARAMETER VIH,I2C TEST CONDITIONS MIN SDA and SCL, VDDI2C = 1.8V MAX 0.7* VDDI2C SDA and SCL, VDDI2C = 3.3V UNIT V VDDI2C Input High Level, I2C VIL,I2C TYP 0.7* V SDA and SCL, VDDI2C = 1.8V 0.3* VDDI2C V SDA and SCL, VDDI2C = 3.3V 0.3* VDDI2C V Input Low Level Voltage, I2C VHY Input Hysteresis, I2C SDA and SCL, VDDI2C = 1.8V or 3.3V VOL,I2C Output Low Level, I2C SDA and SCL, VDDI2C = 1.8V, Fast-Mode, 3mA Sink Current GND 0.2 * VDDI2C V SDA and SCL, VDDI2C = 3.3V, 3mA Sink Current GND 0.4 V SDA and SCL, VDDI2C = 0V -800 -600 µA -10 +10 µA IIN,I2C Input Current, I2C SDA and SCL, VDDI2C = VDD18 or VDD33 CIN,I2C 12 Input Capacitance, I2C SDA and SCL Submit Documentation Feedback >50 5 mV pF Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 7.8 Recommended Timing for the Serial Control Bus Over I2C supply and temperature ranges unless otherwise specified. PARAMETER fSCL tLOW tHIGH SCL Clock Frequency SCL Low Period SCL High Period TEST CONDITIONS tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF tr tf tSP Hold time for a start or a repeated start condition Set Up time for a start or a repeated start condition Data Hold Time Data Set Up Time Set Up Time for STOP Condition Bus Free Time Between STOP and START SCL & SDA Rise Time, SCL & SDA Fall Time, Input Filter TYP MAX UNIT Standard-Mode >0 100 Fast-Mode >0 400 kHz Fast-Mode Plus >0 1 MHz Standard-Mode 4.7 µs Fast-Mode 1.3 µs Fast-Mode Plus 0.5 µs Standard-Mode 4.0 µs Fast-Mode tHD;STA MIN kHz 0.6 µs Fast-Mode Plus 0.26 µs Standard-Mode 4.0 µs Fast-Mode 0.6 µs Fast-Mode Plus 0.26 µs Standard-Mode 4.7 µs Fast-Mode 0.6 µs Fast-Mode Plus 0.26 µs Standard-Mode 0 µs Fast-Mode 0 µs Fast-Mode Plus 0 µs Standard-Mode 250 ns Fast-Mode 100 ns Fast-Mode Plus 50 ns Standard-Mode 4.0 µs Fast-Mode 0.6 µs Fast-Mode Plus 0.26 µs Standard-Mode 4.7 µs Fast-Mode 1.3 µs Fast-Mode Plus 0.5 µs Standard-Mode 1000 ns Fast-Mode 300 ns Fast-Mode Plus 120 ns Standard-Mode 300 ns Fast-Mode 300 ns Fast-Mode Plus 120 ns Fast-Mode 50 ns Fast-Mode Plus 50 ns Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 13 DS90UH929-Q1 www.ti.com PARALLEL-TO-SERIAL SNLS458 – NOVEMBER 2014 IN_CLK± IN_D[2:0]± 100 nF DOUT+ Differential probe D 100: DOUT- SCOPE BW û 4GHz Input Impedance û 100 k: CL ú 0.5 pf BW û 3.5 GHz 100 nF DOUT- VOD/2 Single Ended VOD/2 DOUT+ | VOS 0V Differential VOD (DOUT+) - (DOUT-) 0V Figure 1. Serializer VOD Output 80% (DOUT+) - (DOUT-) VOD tLHT 0V 20% tHLT Figure 2. Output Transition Times VDD VDDIO PDB RX_5V IN_CLK (Diff.) tPLD DOUT (Diff.) Driver OFF, VOD = 0V Driver On Figure 3. Serializer Lock Time 14 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 IN_D[2:0] N-1 N N+1 | | www.ti.com N+2 | tSD IN_CLK 0 1 2 0 1 2 0 1 2 0 1 2 | | 2 START STOP BIT SYMBOL N BIT | | 1 START STOP BIT SYMBOL N-1 BIT | | 0 START STOP BIT SYMBOL N-2 BIT | | DOUT START STOP BIT SYMBOL N-3 BIT | | STOP SYMBOL N-4 BIT Figure 4. Latency Delay tDJIT tDJIT DOUT (Diff.) EYE OPENING 0V tBIT (1 UI) Figure 5. Serializer Output Jitter SDA tf tHD;STA tLOW tr tf tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tSU;STO tSU;DAT tHD;DAT START STOP REPEATED START START Figure 6. Serial Control Bus Timing Diagram T tLC tHC VIH I2S_CLK VIL tsr thr I2S_WC I2S_D[A,B,C,D] Figure 7. I2S Timing Diagram Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 15 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 7.9 Typical Characteristics Figure 8. Serializer Output at 2.975Gbps (85MHz TMDS Clock) 16 Figure 9. Serializer Output at 3.36Gbps (96MHz TMDS Clock) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 8 Detailed Description 8.1 Overview The DS90UH929-Q1 converts an HDMI interface (3 TMDS data channels + 1 TMDS Clock) to an FPD-Link III interface. This device transmits a 35-bit symbol over a single serial pair operating up to 3.36Gbps line rate. The serial stream contains an embedded clock, video control signals, RGB video data, and audio data. The payload is DC-balanced to enhance signal quality and support AC coupling. The DS90UH929-Q1 serializer is intended for use with a DS90UH926Q-Q1, DS90UH928Q-Q1, DS90UH940-Q1, DS90UH948-Q1 deserializer. The DS90UH929-Q1 serializer and companion deserializer incorporate an I2C compatible interface. The I2C compatible interface allows programming of serializer or deserializer devices from a local host controller. In addition, the devices incorporate a bidirectional control channel (BCC) that allows communication between serializer/deserializer as well as remote I2C slave devices. The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either side of the serial link. 8.2 Functional Block Diagram KSV FIFO Packet FIFO Audio PLL TMDS HDMI RX PHY Digital TMDS Interface Audio FIFO HDCP Key NVM Video HDMI Controller Digital I2S Audio PAT GEN H D C P RX_5V FPD3 TX Analog FPD-Link III Digital H D C P HPA FPD-Link III TX Digital FPD-Link III FPD-Link III TX Digital DDC EDID/ Config NVM EDID Bridge Control Digital I/F I2C Optional Secondary I2S Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 17 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 8.3 Feature Description 8.3.1 High-Definition Multimedia Interface (HDMI) HDMI is a leading interface standard used to transmit digital video and audio from sources (such as a DVD player) to sinks (such as an LCD display). The interface is capable of transmitting high-definition video, audio, and also supports HDCP. Other HDMI signals consist of various control and status data that travel bidirectionally. 8.3.1.1 HDMI Receive Controller The HDMI Receiver is an HDMI version 1.4b compliant receiver. The HDMI receiver is capable of operation at greater than 1080p resolutions. The DS90UH929-Q1 implementation is restricted to 720p operation (or 1080i or 1080p/30).The configuration used in the DS90UH929-Q1does not include version 1.4b features such as the ethernet channel (HEC) or Audio Return Channel (ARC). 8.3.2 Transition Minimized Differential Signaling HDMI uses Transition Minimized Differential Signaling (TMDS) over four differential pairs (3 TMDS channels and 1 TMDS clock) to transmit video and audio data. TMDS is widely used to transmit high-speed serial data. The technology incorporates a form of 8b/10b encoding and its differential signaling allows it to reduce electromagnetic interference (EMI) and achieve high skew tolerance. 8.3.3 Enhanced Display Data Channel The Display Data Channel or DDC is a collection of digital communication protocols between a computer display and a graphics adapter that enables the display to communicate its supported display modes to the adapter and allow the computer host to adjust monitor parameters, such as brightness and contrast. 8.3.4 Extended Display Identification Data (EDID) EDID is a data structure provided by a digital display to describe its capabilities to a video source. By providing this information, the video source can then send video data with proper timing and resolution that the display supports. The DS90UH929-Q1 supports several options for delivering display identification (EDID) information to the HDMI graphics source. The EDID information is accessible via the DDC interface and comply with the DDC and EDID requirements given in the HDMI v1.4b specification. The EDID configurations supported are as follows: • External local EDID (EEPROM) • Internal EDID loaded into device memory • Remote EDID connected to I2C bus at deserializer side • Internal pre-programmed EDID The EDID mode selected should be configurable from the MODE_SEL pins, or from internal control registers. For all modes, the EDID information should be accessible at the default address of 0xA0. 8.3.4.1 External Local EDID (EEPROM) The DS90UH929-Q1 can be configured to allow a local EEPROM EDID device. The local EDID device may implement any EDID configuration allowable by the HDMI v1.4b and DVI 1.0 standards, including multiple extension blocks up to 32KB. 8.3.4.2 Internal EDID (SRAM) The DS90UH929-Q1 also allows internal loading of an EDID profile up to 256 bytes. This SRAM storage is volatile and requires loading from an external I2C master (local or remote). The internal EDID is reloadable and readable (local/remote) from control registers during normal operation. 8.3.4.3 External Remote EDID The serializer copies the remote EDID connected to the I2C bus of the remote deserializer into its internal SRAM. The remote EDID device can be a standalone I2C EEPROM, or integrated into the digital display panel. In this mode, the serializer automatically accesses the Bidirectional Control Channel to search for the EDID information at the default address 0xA0. Once found, the serializer copies the remote EDID into local SRAM. 18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Feature Description (continued) 8.3.4.4 Internal Pre-Programmed EDID The serializer also has an internal eFuse that is loaded into the internal SRAM with pre-programmed 256-byte EDID data at startup. This EDID profile supports several generic video (480p, 720p) and audio (2-channel audio) timing profiles within the single-link operating range of the device (25MHz-96MHz pixel clock). In this mode, the internal EDID SRAM data is readable from the DDC interface. The EDID contents are below: 0x00 0xFF 0xFF 0xFF 0x1C 0x18 0x01 0x03 0x0F 0x48 0x4C 0x00 0x01 0x01 0x01 0x01 0x55 0x00 0x00 0x20 0x64 0x08 0x00 0x0A 0x49 0x2D 0x44 0x53 0x00 0x00 0x00 0x00 0x02 0x03 0x15 0x40 0x0C 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0x80 0x34 0x20 0x00 0x00 0x01 0x01 0x01 0x01 0x21 0x00 0x00 0x20 0x20 0x20 0x39 0x30 0x55 0x00 0x00 0x00 0x41 0x84 0x23 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x53 0x0E 0x49 0x09 0x01 0x78 0x0A 0xEC 0x18 0xA3 0x54 0x01 0x01 0x01 0x01 0x01 0x01 0x1D 0x00 0x72 0x51 0xD0 0x1E 0x18 0x00 0x00 0x00 0xFD 0x00 0x20 0x20 0x20 0x00 0x00 0x00 0x78 0x39 0x34 0x39 0x0A 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x09 0x7F 0x05 0x83 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x28 0x00 0x46 0x01 0x20 0x3B 0xFC 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x98 0x01 0x6E 0x3D 0x00 0x00 0x01 0x66 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x25 0x01 0x50 0x62 0x54 0x10 0x57 0x03 0x00 0x00 0x00 0x00 0x00 0x00 8.3.5 Consumer Electronics Control (CEC) Consumer Electronics Control (CEC) is designed to allow the system user to command and control up-to ten CEC-enabled devices connected through HDMI, using only one of their remote controls (for example by controlling a television set, set-top box, and DVD player using only the remote control of the TV). CEC also allows for individual CEC-enabled devices to command and control each other without user intervention. CEC is a one-wire open drain bus with an external 27kohm (+/-10%) resistor pull-up to 3.3V. CEC protocol can be implemented using an external clock reference or the 25MHz internal oscillator inside the DS90UH929-Q1. 8.3.6 +5V Power Signal +5V is asserted by the HDMI source through the HDMI interface. The +5V signal propagates through the connector and cable until it reaches the sink. The +5V supply is used for various HDMI functions, such as HPD and DDC signals. 8.3.7 Hot Plug Detect (HPD) The HPD pin is asserted by the sink to let the source know that it is ready to receive the HDMI signal. The source initiates the connection by first providing the +5V power signal through the HDMI interface. The sink holds HPD low until it is ready to receive signals from the source, at which point it will release HPD to be pulled up to +5V. 8.3.8 High Speed Forward Channel Data Transfer The High Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, HDCP, I2C, GPIOs, and I2S audio transmitted from serializer to deserializer. Figure 10 illustrates the serial stream per clock cycle. This data payload is optimized for signal transmission over an AC coupled link. Data is randomized, balanced and scrambled. C0 C1 Figure 10. FPD-Link III Serial Stream Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 19 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Feature Description (continued) The device supports TMDS clocks in the range of 25 MHz to 96 MHz over one lane. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum) . 8.3.9 Back Channel Data Transfer The Backward Channel provides bidirectional communication between the display and host processor. The information is carried from the deserializer to the serializer as serial frames. The back channel control data is transferred over both serial links along with the high-speed forward data, DC balance coding and embedded clock information. This architecture provides a backward path across the serial link together with a high speed forward channel. The back channel contains the I2C, HDCP, CRC and 4 bits of standard GPIO information with 5, 10, or 20 Mbps line rate (configured by the compatible deserializer). 8.3.10 Power Down (PDB) The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an external device, or through VDDIO, where VDDIO = 1.71V to 1.89V. To save power, disable the link when the display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have reached final levels. When PDB is driven low, ensure that the pin is driven to 0V for at least 3ms before releasing or driving high. In the case where PDB is pulled up to VDDIO directly, a 10kΩ pull-up resistor and a >10µF capacitor to ground are required (See Power Up Requirements And PDB Pin). Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time, PDB must be held low for a minimum of 3ms before going high again. 8.3.11 Serial Link Fault Detect The DS90UH929-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 8). The DS90UH929-Q1 will detect any of the following conditions: 1. Cable open 2. “+” to “-” short 3. ”+” to GND short 4. ”-” to GND short 5. ”+” to battery short 6. ”-” to battery short 7. Cable is linked incorrectly (DOUT+/DOUT- connections reversed) Note: The device will detect any of the above conditions, but does not report specifically which one has occurred. 8.3.12 Interrupt Pin (INTB) The INTB pin is an active low interrupt output pin that acts as an interrupt for various local and remote interrupt conditions (see registers 0xC6 and 0xC7 of Register Maps). For the remote interrupt condition, the INTB pin works in conjunction with the INTB_IN pin on the deserializer. This interrupt signal, when configured, will propagate from the deserializer to the serializer. 1. On the Serializer, set register 0xC6[5] = 1 and 0xC6[0] = 1 2. Deserializer INTB_IN pin is set LOW by some downstream device. 3. Serializer pulls INTB pin LOW. The signal is active LOW, so a LOW indicates an interrupt condition. 4. External controller detects INTB = LOW; to determine interrupt source, read ISR register. 5. A read to ISR will clear the interrupt at the Serializer, releasing INTB. 6. The external controller typically must then access the remote device to determine downstream interrupt source and clear the interrupt driving the Deserializer INTB_IN. This would be when the downstream device releases the INTB_IN pin on the Deserializer. The system is now ready to return to step (2) at next falling edge of INTB_IN. 20 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Feature Description (continued) 8.3.13 Remote Interrupt Pin (REM_INTB) REM_INTB will mirror the status of INTB_IN pin on the deserializer and does not need to be cleared. If the serializer is not linked to the deserializer, REM_INTB will be high. 8.3.14 General-purpose I/O 8.3.14.1 GPIO[3:0] Configuration In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back channel (inputs) mode. GPIO modes may be configured from the registers. See Table 1 for GPIO enable and configuration. Table 1. GPIO Enable and Configuration Description Device Forward Channel Back Channel GPIO3 Serializer 0x0F[3:0] = 0x3 0x0F[3:0] = 0x5 Deserializer 0x1F[3:0] = 0x5 0x1F[3:0] = 0x3 GPIO2 GPIO1 GPIO0 Serializer 0x0E[7:4] = 0x3 0x0E[7:4] = 0x5 Deserializer 0x1E[7:4] = 0x5 0x1E[7:4] = 0x3 Serializer 0x0E[3:0] = 0x3 0x0E[3:0] = 0x5 Deserializer 0x1E[3:0] = 0x5 0x1E[3:0] = 0x3 Serializer 0x0D[3:0] = 0x3 0x0D[3:0] = 0x5 Deserializer 0x1D[3:0] = 0x5 0x1D[3:0] = 0x3 8.3.14.2 GPIO_REG[8:5] Configuration GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local register bits only. Where applicable, these bits are shared with I2S pins and will override I2S input if enabled into GPIO_REG mode. See Table 2 for GPIO enable and configuration. Note: Local GPIO value may be configured and read either through local register access, or remote register access through the Bidirectional Control Channel. Configuration and state of these pins are not transported from serializer to deserializer as is the case for GPIO[3:0]. Table 2. GPIO_REG and GPIO Local Enable and Configuration Description Register Configuration GPIO_REG8 0x11[7:4] = 0x01 Output, L 0x11[7:4] = 0x09 Output, H 0x11[7:4] = 0x03 Input, Read: 0x1D[0] GPIO_REG7 GPIO_REG6 GPIO_REG5 GPIO3 Function 0x11[3:0] = 0x1 Output, L 0x11[3:0] = 0x9 Output, H 0x11[3:0] = 0x3 Input, Read: 0x1C[7] 0x10[7:4] = 0x1 Output, L 0x10[7:4] = 0x9 Output, H 0x10[7:4] = 0x3 Input, Read: 0x1C[6] 0x10[3:0] = 0x1 Output, L 0x10[3:0] = 0x9 Output, H 0x10[3:0] = 0x3 Input, Read: 0x1C[5] 0x0F[3:0] = 0x1 Output, L 0x0F[3:0] = 0x9 Output, H 0x0F[3:0] = 0x3 Input, Read: 0x1C[3] Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 21 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Table 2. GPIO_REG and GPIO Local Enable and Configuration (continued) Description Register Configuration Function GPIO2 0x0E[7:4] = 0x1 Output, L GPIO1 GPIO0 0x0E[7:4] = 0x9 Output, H 0x0E[7:4] = 0x3 Input, Read: 0x1C[2] 0x0E[3:0] = 0x1 Output, L 0x0E[3:0] = 0x9 Output, H 0x0E[3:0] = 0x3 Input, Read: 0x1C[1] 0x0D[3:0] = 0x1 Output, L 0x0D[3:0] = 0x9 Output, H 0x0D[3:0] = 0x3 Input, Read: 0x1C[0] 8.3.15 Backward Compatibility This FPD-Link III serializer is backward compatible to the DS90UH926Q-Q1 and DS90UH928Q-Q1 for TMDS clock frequencies ranging from 25MHz to 85MHz. Backward compatibility does not need to be enabled. 8.3.16 Audio Modes The DS90UH929-Q1 supports several audio modes and functions: • HDMI Mode • DVI Mode • AUX Audio Channel 8.3.16.1 HDMI Audio The DS90UH929-Q1 allows embedded audio in the HDMI interface to be transported over the FPD-Link III serial link and output on the compatible deserializer. Depending on the number of channels, HDMI audio can be output on several I2S pins on the deserializer, or it can be converted to TDM to output on one audio output pin on the deserializer. 8.3.16.2 DVI I2S Audio Interface The DS90UH929-Q1 serializer features six I2S input pins that, when paired with a compatible deserializer, supports 7.1 High-Definition (HD) Surround Sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1MHz and the lesser of IN_CLK/2 or 13MHz. Four I2S data inputs transport two channels of I2S-formatted digital audio each, with each channel delineated by the word select (I2S_WC) input. Refer to Figure 11 and Figure 12 for I2S connection diagram and timing information. Serializer I2S Transmitter Bit Clock Word Select 4 Data I2S_CLK I2S_WC I2S_Dx Figure 11. I2S Connection Diagram I2S_WC I2S_CLK I2S_Dx MSB LSB MSB LSB Figure 12. I2S Frame Timing Diagram 22 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Table 3 covers several common I2S sample rates: Table 3. Audio Interface Frequencies Sample Rate (kHz) I2S Data Word Size (bits) I2S CLK (MHz) 32 16 1.024 44.1 16 1.411 48 16 1.536 96 16 3.072 192 16 6.144 32 24 1.536 44.1 24 2.117 48 24 2.304 96 24 4.608 192 24 9.216 32 32 2.048 44.1 32 2.822 48 32 3.072 96 32 6.144 192 32 12.288 8.3.16.2.1 I2S Transport Modes By default, audio is packetized and transmitted during video blanking periods in dedicated Data Island Transport frames. Data Island frames may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired. In this mode, only I2S_DA is transmitted to a DS90UH928Q-Q1,DS90UH940-Q1, or DS90UH948-Q1 deserializer. If connected to a DS90UH926Q-Q1 deserializer, I2S_DA and I2S_DB are transmitted. Surround Sound Mode, which transmits all four I2S data inputs (I2S_D[A..D]), may only be operated in Data Island Transport mode. This mode is only available when connected to a DS90UH928Q-Q1,DS90UH940Q1, or DS90UH948-Q1 deserializer. 8.3.16.2.2 I2S Repeater I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via Data Island Transport during the video blanking periods. If frame transport is desired, then the I2S pins should be connected from the deserializer to all serializers. Activating surround sound at the top-level deserializer automatically configures downstream serializers and deserializers for surround sound transport utilizing Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 8). 8.3.16.3 AUX Audio Channel The AUX Audio Channel is a single separate I2S audio data channel that may be transported independently of the main audio stream received in either HDMI Mode or DVI Mode. This channel is shared with the GPIO[1:0] interface and is supported by DS90UH940-Q1and DS90UH948-Q1 deserializers. 8.3.16.4 TDM Audio Interface In addition to the I2S audio interface, the DS90UH929-Q1 serializer also supports TDM format. Since a number of specifications for TDM format are in common use, the DS90UH929-Q1 offers flexible support for word length, bit clock, number of channels to be multiplexed, etc. For example, let’s assume that word clock signal (I2S_WC) period = 256 * bit clock (I2S_CLK) time period. In this case, the DS90UH929-Q1 can multiplex 4 channels with maximum word length of 64 bits each, or 8 channels with maximum word length of 32 bits each. Figure 13 illustrates the multiplexing of 8 channels with 24 bit word length, in a format similar to I2S. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 23 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com t1/fS (256 BCKs at Single Rate, 128 BCKs at Dual Rate)t I2S_WC I2S_CLK I2S Mode DIN1 (Single) Ch 1 t32 BCKst Ch 2 t32 BCKst Ch 3 t32 BCKst Ch 4 t32 BCKst Ch 5 t32 BCKst Ch 6 t32 BCKst Ch 7 t32 BCKst Ch 8 t32 BCKst 23 22 23 22 23 22 23 22 23 22 23 22 23 22 23 22 0 0 0 0 0 0 0 0 23 22 Figure 13. TDM Format 8.3.17 HDCP The HDCP Cipher function is implemented in the serializer per HDCP v1.4 specification. The serializer provides HDCP encryption of audiovisual content when connected to an HDCP capable source. HDCP authentication and shared key generation is performed using the HDCP Control Channel, which is embedded in the forward and backward channels of the serial link. On-chip Non-Volatile Memory (NVM) is used to store the HDCP keys. The confidential HDCP keys are loaded by TI during the manufacturing process and are not accessible external to the device. 8.3.17.1 HDCP I2S Audio Encryption Depending on the quality and specifications of the audiovisual source, HDCP encryption of digital audio may be required. When HDCP is active, packetized Data Island Transport audio is also encrypted along with the video data per HDCP v.1.4. I2S audio transmitted in Forward Channel Frame Transport mode is not encrypted. System designers should consult the specific HDCP specifications to determine if encryption of digital audio is required by the specific application audiovisual source. 8.3.18 Built In Self Test (BIST) An optional At-Speed Built-In Self Test (BIST) feature supports testing of the high speed serial link and back channel without external data connections. This is useful in the prototype stage, equipment production, in-system test, and system diagnostics. 8.3.18.1 BIST Configuration And Status The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may select either an external TMDS clock or the internal Oscillator clock (OSC) frequency. In the absence of TMDS clock, the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration register. When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the Back Channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel frame. The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width applied to the deserializer BISTEN pin. LOCK is valid throughout the entire duration of BIST. See Figure 14 for the BIST mode flow diagram. 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Step 1: The Serializer is paired with another FPD-Link III Deserializer, BIST Mode is enabled via the BISTEN pin or through register on the Deserializer. Right after BIST is enabled, part of the BIST sequence requires bit 0x04[5] be toggled locally on the Serializer (set 0x04[5]=1, then set 0x04[5]=0). The desired clock source is selected through the deserializer BISTC pin, or through register on the Deserializer. Step 2: An all-zeros pattern is balanced, scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer and the deserializer are in BIST mode and the deserializer acquires Lock, the PASS pin of the deserializer goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be monitored and counted to determine the payload error rate. Step 3: To Stop the BIST mode, the deserializer BISTEN pin is set Low. The deserializer stops checking the data. The final test result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a new BIST is run, the device is RESET, or the device is powered down. The BIST duration is user controlled by the duration of the BISTEN signal. Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. Figure 15 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing signal condition enhancements (Rx Equalization). Normal Step 1: DES in BIST BIST Wait Step 2: Wait, SER in BIST BIST start Step 3: DES in Normal Mode - check PASS BIST stop Step 4: DES/SER in Normal Figure 14. BIST Mode Flow Diagram 8.3.18.2 Forward Channel And Back Channel Error Checking While in BIST mode, the serializer stops sampling the FPD-Link input pins and switches over to an internal all zeroes pattern. The internal all-zeroes pattern goes through scrambler, DC-balancing, etc. and is transmitted over the serial link to the deserializer. The deserializer, on locking to the serial stream, compares the recovered serial stream with all-zeroes and records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer. The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream, as indicated by link detect status (register bit 0x0C[0] - Table 8). CRC errors are recorded in an 8-bit register in the deserializer. The register is cleared when the serializer enters BIST mode. As soon as the serializer enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST mode CRC error register is active in BIST mode only and keeps a record of the last BIST run until cleared or the serializer enters BIST mode again. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 25 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com DES Outputs BISTEN (DES) TxCLKOUT± TxOUT[3:0]± Case 1 - Pass DATA (internal) PASS Prior Result PASS DATA (internal) PASS X X X FAIL Prior Result Normal PRBS Case 2 - Fail X = bit error(s) BIST Test BIST Duration BIST Result Held Normal Figure 15. BIST Waveforms, in Conjunction with Deserializer Signals 8.3.19 Internal Pattern Generation The DS90UH929-Q1 serializer provides an internal pattern generation feature. It allows basic testing and debugging of an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel operation. As long as the device is not in power down mode, the test pattern will be displayed even if no input is applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For detailed information, refer to Application Note AN-2198. 8.3.19.1 Pattern Options The DS90UH929-Q1 serializer pattern generator is capable of generating 17 default patterns for use in basic testing and debugging of panels. Each can be inverted using register bits (Table 8), shown below: 1. White/Black (default/inverted) 2. Black/White 3. Red/Cyan 4. Green/Magenta 5. Blue/Yellow 6. Horizontally Scaled Black to White/White to Black 7. Horizontally Scaled Black to Red/Cyan to White 8. Horizontally Scaled Black to Green/Magenta to White 9. Horizontally Scaled Black to Blue/Yellow to White 10. Vertically Scaled Black to White/White to Black 11. Vertically Scaled Black to Red/Cyan to White 12. Vertically Scaled Black to Green/Magenta to White 13. Vertically Scaled Black to Blue/Yellow to White 14. Custom Color (or its inversion) configured in PGRS 15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL) 16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL 17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the autoscrolling feature Additionally, the Pattern Generator incorporates one user-configurable full-screen 24-bit color, which is controlled by the PGRS, PGGS, and PGBS registers. This is pattern #14. One of the pattern options is statically selected in the PGCTL register when Auto-Scrolling is disabled. The PGTSC and PGTSO1-8 registers control the pattern selection and order when Auto-Scrolling is enabled. 26 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 8.3.19.2 Color Modes By default, the Pattern Generator operates in 24-bit color mode, where all bits of the Red, Green, and Blue outputs are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit mode, the 6 most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least significant bits will be 0. 8.3.19.3 Video Timing Modes The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator uses custom video timing as configured in the control registers. The internal timing generation may also be driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with External Clock are enabled by the control registers (Table 8). 8.3.19.4 External Timing In external timing mode, the Pattern Generator passes the incoming DE, HS, and VS signals unmodified to the video control outputs after a two pixel clock delay. It extracts the active frame dimensions from the incoming signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without DE asserted. 8.3.19.5 Pattern Inversion The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes the output pattern to be bitwise-inverted. For example, the full screen Red pattern becomes full-screen cyan, and the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta. 8.3.19.6 Auto Scrolling The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may appear in any order in the sequence and may also appear more than once. 8.3.19.7 Additional Features Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It consists of the Pattern Generator Indirect Address (PGIA reg_0x66 — Table 8) and the Pattern Generator Indirect Data (PGID reg_0x67 — Table 8). See Application Note AN-2198. 8.3.20 Spread Spectrum Clock Tolerance The DS90UH929-Q1 (for DVI mode) tolerates a spread spectrum input clock to help reduce EMI. The following triangular SSC profile is supported: • Frequency deviation ≤2.5% • Modulation rate ≤ 100kHz Note: Maximum frequency deviation and maximum modulation rate are not supported simultaneously. Some typical examples: • Frequency deviation: 2.5%, modulation rate: 50kHz • Frequency deviation: 1.25%, modulation rate: 100kHz 8.4 Device Functional Modes 8.4.1 Mode Select Configuration Settings (MODE_SEL[1:0]) Configuration of the device may be done via the MODE_SEL[1:0] input pins, or via the configuration register bits. A pull-up resistor and a pull-down resistor of suggested values may be used to set the voltage ratio of the MODE_SEL[1:0] inputs. See Table 5 and Table 6. These values will be latched into register location during power-up: Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 27 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Device Functional Modes (continued) Table 4. MODE_SEL[1:0] Settings Mode Setting Function 0 Look for remote EDID, if none found, use internal SRAM EDID. Can be overridden from register. Remote EDID address may be overridden from default 0xA0. 1 Use external local EDID. 0 Disable. 1 Enable. 0 HDMI audio. 1 HDMI + AUX audio channel. 0 Internal HDCP/HDMI control. 1 External HDCP/HDMI control from I2C interface pins. 0 Enable FPD-Link III for twisted pair cabling. 1 Enable FPD-Link III for coaxial cabling. 0 Use internal SRAM EDID. 1 If available, remote EDID is copied into internal SRAM EDID. EDID_SEL: Display ID Select AUTO-SS: Auto Sleep-State AUX_I2S: AUX Audio Channel EXT_CTL: External Controller Override COAX: Cable Type REM_EDID_LOAD: Remote EDID Load 1.8V R3 VR4 MODE_SEL0 MODE_SEL1 1.8V R4 Serializer R5 VR6 R6 Figure 16. MODE_SEL[1:0] Connection Diagram Table 5. Configuration Select (MODE_SEL0) # Ratio VR4/VDD18 Target VR4 (V) Suggested Suggested Resistor Pull-Up Resistor PullR3 kΩ (1% tol) Down R4 kΩ (1% tol) EDID_SEL AUTO_SS AUX_I2S 1 0 0 OPEN 40.2 0 0 0 2 0.208 0.374 3 0.323 0.582 118 30.9 0 0 1 107 51.1 0 1 4 0.440 0 0.792 113 88.7 0 1 5 1 0.553 0.995 82.5 102 1 0 0 6 0.668 1.202 68.1 137 1 0 1 7 0.789 1.420 56.2 210 1 1 0 8 1 1.8 13.3 OPEN 1 1 1 EXT_CTL COAX REM_EDID_LOA D Table 6. Configuration Select (MODE_SEL1) # Ratio VR6/VDD18 Target VR6 (V) Suggested Suggested Resistor Pull-Up Resistor PullR5 kΩ (1% tol) Down R6 kΩ (1% tol) 1 0 0 OPEN 40.2 0 0 0 2 0.208 0.374 118 30.9 0 0 1 3 0.323 0.582 107 51.1 0 1 0 4 0.440 0.792 113 88.7 0 1 1 28 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Table 6. Configuration Select (MODE_SEL1) (continued) # Ratio VR6/VDD18 Target VR6 (V) Suggested Suggested Resistor Pull-Up Resistor PullR5 kΩ (1% tol) Down R6 kΩ (1% tol) EXT_CTL COAX REM_EDID_LOA D 5 0.553 0.995 82.5 102 1 0 0 6 0.668 1.202 7 0.789 1.420 68.1 137 1 0 1 56.2 210 1 1 8 1 1.8 0 13.3 OPEN 1 1 1 The strapped values can be viewed and/or modified in the following locations: • EDID_SEL : Latched into BRIDGE_CTL[0], EDID_DISABLE (0x4F[0]). • AUTO_SS : Latched into SOFT_SLEEP (0x01[7]). • AUX_I2S : Latched into BRIDGE_CFG[1], AUDIO_MODE[1] (0x54[1]). • EXT_CTL: Latched into BRIDGE_CFG[7], EXT_CONTROL (0x54[7]). • COAX : Latched into DUAL_CTL1[7], COAX_MODE (0x5B[7]). • REM_EDID_LOAD : Latched into BRIDGE_CFG[5] (0x54[5]). 8.4.2 FPD-Link III Single Link Operation The DS90UH929-Q1's single link mode transmits the video over a single FPD-Link III to a single receiver. Single link mode supports frequencies up to 96MHz for 24-bit video when paired with the DS90UH940-Q1/DS90UH948Q1. This mode is compatible with the DS90UH926Q-Q1/DS90UH928Q-Q1 when operating below 85MHz. 8.5 Programming 8.5.1 Serial Control Bus This serializer may also be configured by the use of a I2C compatible serial control bus. Multiple devices may share the serial control bus (up to 8 device addresses supported). The device address is set via a resistor divider (R1 and R2 — see Figure 17 below) connected to the IDx pin. VDD18 VDDI2C R1 VR2 4.7k 4.7k IDx R2 HOST SER SCL SCL SDA SDA To other Devices Figure 17. Serial Control Bus Connection The serial control bus consists of two signals, SCL and SDA. SCL is a Serial Bus Clock Input. SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull-up resistor to VDD18 or VDD33. For most applications, a 4.7kΩ pull-up resistor is recommended. However, the pull-up resistor value may be adjusted for capacitive loading and data rate requirements. The signals are either pulled High, or driven Low. The IDx pin configures the control interface to one of 8 possible device addresses. A pull-up resistor and a pulldown resistor may be used to set the appropriate voltage on the IDx input pin See Table 8 below. Table 7. Serial Control Bus Addresses For IDx # Ratio VR2 / VDD18 Ideal VR2 (V) 1 0 0 Suggested Resistor Suggested Resistor R1 kΩ (1% tol) R2 kΩ (1% tol) OPEN 40.2 7-Bit Address 8-Bit Address 0x0C 0x18 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 29 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Programming (continued) Table 7. Serial Control Bus Addresses For IDx (continued) # Ratio VR2 / VDD18 Ideal VR2 (V) Suggested Resistor Suggested Resistor R1 kΩ (1% tol) R2 kΩ (1% tol) 2 0.208 0.374 118 3 0.323 0.582 4 0.440 0.792 5 0.553 6 7 8 7-Bit Address 8-Bit Address 30.9 0x0E 0x1C 107 51.1 0x10 0x20 113 88.7 0x12 0x24 0.995 82.5 102 0x14 0x28 0.668 1.202 68.1 137 0x16 0x2C 0.789 1.420 56.2 210 0x18 0x30 1 1.8 13.3 OPEN 0x1A 0x34 The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL transitions Low while SDA is High. A STOP occurs when SDA transitions High while SCL is also HIGH. See Figure 18 SDA SCL S P START condition, or START repeat condition STOP condition Figure 18. Start And Stop Conditions To communicate with an I2C slave, the host controller (master) sends the slave address and listens for a response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled High. ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus begins with either a Start condition or a Repeated Start condition. All communication on the bus ends with a Stop condition. A READ is shown in Figure 25 and a WRITE is shown in Figure 26. Register Address Slave Address S A 2 A 1 A 0 Slave Address a c k a 0 ck A 2 S A 1 A 0 Data a c a c k 1 k P Figure 19. Serial Control Bus — Read Register Address Slave Address S A 2 A 1 A 0 0 a c k Data a c k a c k P Figure 20. Serial Control Bus — Write The I2C Master located at the serializer must support I2C clock stretching. For more information on I2C interface requirements and throughput considerations, please refer to TI Application Note SNLA131. 30 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 8.5.2 Multi-Master Arbitration Support The Bidirectional Control Channel in the FPD-Link III devices implements I2C compatible bus arbitration in the proxy I2C master implementation. When sending a data bit, each I2C master senses the value on the SDA line. If the master is sending a logic 1 but senses a logic 0, the master has lost arbitration. It will stop driving SDA, retrying the transaction when the bus becomes idle. Thus, multiple I2C masters may be implemented in the system. If the system does require master-slave operation in both directions across the BCC, some method of communication must be used to ensure only one direction of operation occurs at any time. The communication method could include using available read/write registers in the deserializer to allow masters to communicate with each other to pass control between the two masters. An example would be to use register 0x18 or 0x19 in the deserializer as a mailbox register to pass control of the channel from one master to another. 8.5.3 I2C Restrictions on Multi-Master Operation The I2C specification does not provide for arbitration between masters under certain conditions. The system should make sure the following conditions cannot occur to prevent undefined conditions on the I2C bus: • One master generates a repeated Start while another master is sending a data bit. • One master generates a Stop while another master is sending a data bit. • One master generates a repeated Start while another master sends a Stop. Note that these restrictions mainly apply to accessing the same register offsets within a specific I2C slave. 8.5.4 Multi-Master Access to Device Registers for Newer FPD-Link III Devices When using the latest generation of FPD-Link III devices, DS90UH929-Q1 or DS90UH940-Q1/DS90UH948-Q1 registers may be accessed simultaneously from both local and remote I2C masters. These devices have internal logic to properly arbitrate between sources to allow proper read and write access without risk of corruption. Access to remote I2C slaves would still be allowed in only one direction at a time . 8.5.5 Multi-Master Access to Device Registers for Older FPD-Link III Devices When using older FPD-Link III devices, simultaneous access to serializer or deserializer registers from both local and remote I2C masters may cause incorrect operation, thus restrictions should be imposed on accessing of serializer and deserializer registers. The likelihood of an error occurrence is relatively small, but it is possible for collision on reads and writes to occur, resulting in an errored read or write. Two basic options are recommended. The first is to allow device register access only from one controller. This would allow only the Host controller to access the serializer registers (local) and the deserializer registers (remote). A controller at the deserializer would not be allowed to access the deserializer or serializer registers. The second basic option is to allow local register access only with no access to remote serializer or deserializer registers. The Host controller would be allowed to access the serializer registers while a controller at the deserializer could access those register only. Access to remote I2C slaves would still be allowed in one direction . In a very limited case, remote and local access could be allowed to the deserializer registers at the same time. Register access is guaranteed to work correctly if both local and remote masters are accessing the same deserializer register. This allows a simple method of passing control of the Bidirectional Control Channel from one master to another. 8.5.6 Restrictions on Control Channel Direction for Multi-Master Operation Only one direction should be active at any time across the Bidirectional Control Channel. If both directions are required, some method of transferring control between I2C masters should be implemented. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 31 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 8.6 Register Maps Table 8. Serial Control Bus Registers ADD (dec) ADD (hex) Register Name 0 0x00 I2C Device ID 1 0x01 Reset Bit(s) Register Type Default (hex) 7:1 RW 0 7 Function Description Strap DEVICE_ID 7-bit address of Serializer. Defaults to address configured by the IDx strap pin. RW 0x00 ID Setting I2C ID setting. 0: Device I2C address is from IDx strap pin (default). 1: Device I2C address is from 0x00[7:1]. RW Strap Soft Sleep 0: Do not power down when no Bidirectional Control Channel link is detected. 1: Power down when no Bidirectional Control Channel link is detected. This bit is strapped from MODE_SEL0 at power-up. 6:5 4 0x00 Reserved. RW HDMI Reset 1 RW Digital RESET1 Reset the entire digital block including registers. This bit is self-clearing. 0: Normal operation (default). 1: Reset. 0 RW Digital RESET0 Reset the entire digital block except registers. This bit is self-clearing. 0: Normal operation (default). 1: Reset. 3:2 32 HDMI Digital Reset. Resets the HDMI digital block. This bit is self-clearing. 0: Normal operation. 1: Reset. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 3 0x03 Register Name General Configuration Bit(s) Register Type Default (hex) 7 RW 0xD2 Function Description Back channel CRC Checker Enable Enable/disable back channel CRC Checker. 0: Disable. 1: Enable (default). 6 Reserved. 5 RW I2C Remote Write Auto Acknowledge Automatically acknowledge I2C remote writes. When enabled, I2C writes to the Deserializer (or any remote I2C Slave, if I2C PASS ALL is enabled) are immediately acknowledged without waiting for the Deserializer to acknowledge the write. This allows higher throughput on the I2C bus. Note: this mode will prevent any NACK from a remote device from reaching the I2C master. 0: Disable (default). 1: Enable. 4 RW Filter Enable HS, VS, DE two-clock filter. When enabled, pulses less than two full TMDS clock cycles on the DE, HS, and VS inputs will be rejected. 0: Filtering disable. 1: Filtering enable (default). 3 RW I2C Passthrough I2C pass-through mode. Read/Write transactions matching any entry in the Slave Alias registers will be passed through to the remote Deserializer. 0: Pass-through disabled (default). 1: Pass-through enabled. RW TMDS Clock Auto 2 1 Reserved. 0 4 0x04 Mode Select 7 Reserved. RW 0x80 Failsafe State 6 5 4:0 Switch over to internal oscillator in the absence of TMDS Clock. 0: Disable auto-switch. 1: Enable auto-switch (default). Input failsafe state. 0: Failsafe to High. 1: Failsafe to Low (default). Reserved. RW CRC Error Reset Clear back channel CRC Error counters. This bit is NOT self-clearing. 0: Normal operation (default). 1: Clear counters. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 33 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 5 0x05 I2C Control 6 7 0x06 0x07 DES ID Slave ID[0] Bit(s) 7:5 Default (hex) Function 0x00 Description Reserved. 4:3 RW SDA Output Delay Configures output delay on the SDA output. Setting this value will increase output delay in units of 40ns. Nominal output delay values for SCL to SDA are: 00: 240ns (default). 01: 280ns. 10: 320ns. 11: 360ns. 2 RW Local Write Disable Disable remote writes to local registers. Setting this bit to 1 will prevent remote writes to local device registers from across the control channel. This prevents writes to the Serializer registers from an I2C master attached to the Deserializer. Setting this bit does not affect remote access to I2C slaves at the Serializer. 0: Enable (default). 1: Disable. 1 RW I2C Bus Timer Speedup Speed up I2C bus Watchdog Timer. 0: Watchdog Timer expires after approximately 1s (default). 1: Watchdog Timer expires after approximately 50µs. 0 RW I2C Bus Timer Disable Disable I2C bus Watchdog Timer. The I2C Watchdog Timer may be used to detect when the I2C bus is free or hung up following an invalid termination of a transaction. If SDA is high and no signaling occurs for approximately 1s, the I2C bus will be assumed to be free. If SDA is low and no signaling occurs, the device will attempt to clear the bus by driving 9 clocks on SCL. 0: Enable (default). 1: Disable. 7:1 RW 0 RW 7:1 RW 0 34 Register Type 0x00 0x00 DES Device ID 7-bit I2C address of the remote Deserializer. A value of 0 in this field disables I2C access to the remote Deserializer. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but should also assert the FREEZE DEVICE ID bit to prevent overwriting by the Bidirectional Control Channel. Freeze Device ID Freeze Deserializer Device ID. 1: Prevents auto-loading of the Deserializer Device ID by the Bidirectional Control Channel. The ID will be frozen at the value written. 0: Allows auto-loading of the Deserializer Device ID from the Bidirectional Control Channel. Slave ID 0 7-bit I2C address of the remote Slave 0 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 0, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 0. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 8 0x08 Slave Alias[0] 7:1 RW 10 0x0A CRC Errors 7:0 11 0x0B 7:0 12 0x0C Function Description 0x00 Slave Alias ID 0 7-bit Slave Alias ID of the remote Slave 0 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 0 register. A value of 0 in this field disables access to the remote Slave 0. R 0x00 CRC Error LSB Number of back channel CRC errors – 8 least significant bits. Cleared by 0x04[5]. R 0x00 CRC Error MSB Number of back channel CRC errors – 8 most significant bits. Cleared by 0x04[5]. 0x00 Link Lost Link lost flag for selected port: This bit indicates that loss of link has been detected. This register bit will stay high until cleared using the CRC Error Reset in register 0x04. 0 General Status Reserved. 7:5 Reserved. 4 13 0x0D GPIO0 Configuration 3 R BIST CRC Error Back channel CRC error(s) during BIST communication with Deserializer. This bit is cleared upon loss of link, restart of BIST, or assertion of CRC Error Reset bit in 0x04[5]. 0: No CRC errors detected during BIST. 1: CRC error(s) detected during BIST. 2 R TMDS Clock Detect Pixel clock status: 0: Valid clock not detected at HDMI input. 1: Valid clock detected at HDMI input. 1 R DES Error CRC error(s) during normal communication with Deserializer. This bit is cleared upon loss of link or assertion of 0x04[5]. 0: No CRC errors detected. 1: CRC error(s) detected. 0 R Link Detect Link detect status: 0: Cable link not detected. 1: Cable link detected. Revision ID Revision ID. GPIO0 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled. 0: Output LOW (default). 1: Output HIGH. GPIO0 Mode Determines operating mode for the GPIO pin: xx0: TRI-STATE™. 001: GPIO mode, output. 011: GPIO mode, input. 101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss. 111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. 7:4 R 3 RW 2:0 RW 0x00 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 35 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 14 0x0E 15 36 0x0F Register Name GPIO1 and GPIO2 Configuration GPIO3 Configuration Bit(s) Register Type Default (hex) 7 RW 0x00 6:4 Function Description GPIO2 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled. 0: Output LOW (default). 1: Output HIGH. RW GPIO2 Mode Determines operating mode for the GPIO pin: x00: Functional input mode. x10: TRI-STATE™. 001: GPIO mode, output. 011: GPIO mode, input. 101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss. 111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. 3 RW GPIO1 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled. 0: Output LOW (default). 1: Output HIGH. 2:0 RW GPIO1 Mode Determines operating mode for the GPIO pin: xx0: TRI-STATE™. 001: GPIO mode, output. 011: GPIO mode, input. 101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss. 111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. 7:4 0x00 Reserved. 3 RW GPIO3 Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled, the local GPIO direction is set to output, and remote GPIO control is disabled. 0: Output LOW (default). 1: Output HIGH. 2:0 RW GPIO3 Mode Determines operating mode for the GPIO pin: x00: Functional input mode. x10: TRI-STATE™. 001: GPIO mode, output. 011: GPIO mode, input. 101: Remote-hold mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-hold mode, data is maintained on link loss. 111: Remote-default mode. The GPIO pin will be an output, and the value is received from the remote Deserializer. In remote-default mode, GPIO's Output Value bit is output on link loss. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 16 0x10 Register Name GPIO5_REG and GPIO6_REG Configuration Bit(s) Register Type Default (hex) 7 RW 0x00 Function Description GPIO6_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output. 0: Output LOW (default). 1: Output HIGH. 6 Reserved. 5:4 RW GPIO6_REG Mode Determines operating mode for the GPIO pin: 00: Functional input mode. 10: TRI-STATE™. 01: GPIO mode, output. 11: GPIO mode; input. 3 RW GPIO5_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output. 0: Output LOW (default). 1: Output HIGH. 2 17 0x11 GPIO7_REG and GPIO8_REG Configuration Reserved. 1:0 RW 7 RW 0x00 GPIO5_REG Mode Determines operating mode for the GPIO pin: 00: Functional input mode. 10: TRI-STATE™. 01: GPIO mode, output. 11: GPIO mode; input. GPIO8_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output. 0: Output LOW (default). 1: Output HIGH. 6 Reserved. 5:4 RW GPIO8_REG Mode Determines operating mode for the GPIO pin: 00: Functional input mode. 10: TRI-STATE. 01: GPIO mode, output. 11: GPIO mode; input. 3 RW GPIO7_REG Output Value Local GPIO Output Value. This value is output on the GPIO pin when the GPIO function is enabled and the local GPIO direction is set to output. 0: Output LOW (default). 1: Output HIGH. RW GPIO7_REG Mode 2 1:0 Reserved. Determines operating mode for the GPIO pin: 00: Functional input mode. 10: TRI-STATE. 01: GPIO mode, output. 11: GPIO mode; input. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 37 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 18 0x12 19 38 0x13 Register Name Data Path Control General Purpose Control Bit(s) Register Type 7 Default (hex) Function 0x00 Description Reserved. 6 RW Pass RGB Setting this bit causes RGB data to be sent independent of DE. However, setting this bit prevents HDCP operation and blocks packetized audio. 0: Normal operation. 1: Pass RGB independent of DE. 5 RW DE Polarity This bit indicates the polarity of the DE (Data Enable) signal. 0: DE is positive (active high, idle low). 1: DE is inverted (active low, idle high). 4 RW I2S Repeater Regen Regenerate I2S data from Repeater I2S pins. 0: Repeater pass through I2S from video pins (default). 1: Repeater regenerate I2S from I2S pins. 3 RW I2S Channel B Enable Override I2S Channel B Enable Override. 0: Disable I2S Channel B override. 1: Set I2S Channel B Enable from 0x12[0]. 2 RW 18-Bit Video Select 0: Select 24-bit video mode. 1: Select 18-bit video mode. 1 RW I2S Transport Select Select I2S transport mode: 0: Enable I2S Data Island transport (default). 1: Enable I2S Data Forward Channel Frame transport. 0 RW I2S Channel B Enable I2S Channel B Enable. 0: I2S Channel B disabled. 1: Enable I2S Channel B on B1 input. Note that in a repeater, this bit may be overridden by the in-band I2S mode detection. 7 R MODE_SEL1 Done Indicates MODE_SEL1 value has stabilized and has been latched. 6:4 R MODE_SEL1 Decode Returns the 3-bit decode of the MODE_SEL1 pin. 3 R MODE_SEL0 Done Indicates MODE_SEL0 value has stabilized and has been latched. 2:0 R MODE_SEL0 Decode Returns the 3-bit decode of the MODE_SEL0 pin. 0x88 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 20 0x14 BIST Control Bit(s) Register Type 7:3 Default (hex) Function 0x00 Description Reserved. 2:1 RW OSC Clock Source Allows choosing different OSC clock frequencies for forward channel frame. OSC clock frequency in functional mode when TMDS clock is not present and 0x03[2]=1: 00: 50 MHz oscillator. 01: 50 MHz oscillator. 10: 100 MHz oscillator. 11: 25 MHz oscillator. Clock source in BIST mode i.e. when 0x14[0]=1: 00: External pixel clock. 01: 33 MHz oscillator. 1x: 100 MHz oscillator. 0 RW BIST Enable BIST control: 0: Disabled (default). 1: Enabled. 21 0x15 I2C Voltage Select 7:0 RW 0x01 I2C Voltage Select Selects 1.8 or 3.3V for the I2C_SDA and I2C_SCL pins. This register is loaded from the I2C_VSEL strap option from the SCLK pin at power-up. At power-up, a logic LOW will select 3.3V operation, while a logic HIGH (pull-up resistor attached) will select 1.8V signaling. Reads of this register return the status of the I2C_VSEL control: 0: Select 1.8V signaling. 1: Select 3.3V signaling. This bit may be overwritten via register access or via eFuse program by writing an 8-bit value to this register: Write 0xb5 to set I2C_VSEL. Write 0xb6 to clear I2C_VSEL. 22 0x16 BCC Watchdog Control 7:1 RW 0xFE Timer Value The watchdog timer allows termination of a control channel transaction if it fails to complete within a programmed amount of time. This field sets the Bidirectional Control Channel Watchdog Timeout value in units of 2 milliseconds. This field should not be set to 0. 0 RW Timer Control Disable Bidirectional Control Channel (BCC) Watchdog Timer: 0: Enable BCC Watchdog Timer operation (default). 1: Disable BCC Watchdog Timer operation. 7 RW I2C Pass All 0: Enable Forward Control Channel pass-through only of I2C accesses to I2C Slave IDs matching either the remote Deserializer Slave ID or the remote Slave ID (default). 1: Enable Forward Control Channel pass-through of all I2C accesses to I2C Slave IDs that do not match the Serializer I2C Slave ID. 6:4 RW SDA Hold Time Internal SDA hold time: Configures the amount of internal hold time provided for the SDA input relative to the SCL input. Units are 40 nanoseconds. 3:0 RW I2C Filter Depth Configures the maximum width of glitch pulses on the SCL and SDA inputs that will be rejected. Units are 5 nanoseconds. 23 0x17 I2C Control 0x1E Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 39 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 24 0x18 SCL High Time 7:0 RW 0x7F TX_SCL_HIGH I2C Master SCL high time: This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional oscillator clock periods. Min_delay = 38.0952ns * (TX_SCL_HIGH + 5). 25 0x19 SCL Low Time 7:0 RW 0x7F TX_SCL_LOW 26 0x1A Data Path Control 2 7:4 R Strap SECONDARY _AUDIO 3 40 0x1B BIST BC Error Count Description I2C Master SCL low time: This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the internal oscillator clock running at 26.25MHz rather than the nominal 25MHz. Delay includes 5 additional clock periods. Min_delay = 38.0952ns * (TX_SCL_LOW + 5). Reserved. 2 27 Function 0x01 Enable Secondary Audio. This register indicates that the AUX audio channel is enabled. The control for this function is via the AUX_AUDIO bit in the BRIDGE_CFG register register offset 0x54). The AUX_AUDIO control is strapped from the MODE_SEL0 pin at power-up. Reserved. 1 RW MODE_28B Enable 28-bit Serializer Mode. 0: 24-bit high-speed data + 3 low-speed control (DE, HS, VS). 1: 28-bit high-speed data mode. 0 RW I2S Surround Enable 5.1- or 7.1-channel I2S audio transport: 0: 2-channel or 4-channel I2S audio is enabled as configured in register 0x12 bits 3 and 0 (default). 1: 5.1- or 7.1-channel audio is enabled. Note that I2S Data Island Transport is the only option for surround audio. Also note that in a repeater, this bit may be overridden by the in-band I2S mode detection. 7:0 R BIST BC Error BIST back channel CRC error counter. This register stores the back channel CRC error count during BIST Mode (saturates at 255 errors). Clears when a new BIST is initiated or by 0x04[5]. 0x00 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 28 0x1C Register Name Bit(s) Register Type Default (hex) GPIO Pin Status 1 7 R 0x00 6 5 Function Description GPIO7_REG Pin Status GPIO7_REG input pin status. Note: status valid only if pin is set to GPI (input) mode. R GPIO6_REG Pin Status GPIO6_REG input pin status. Note: status valid only if pin is set to GPI (input) mode. R GPIO5_REG Pin Status GPIO5_REG input pin status. Note: status valid only if pin is set to GPI (input) mode. 4 29 30 0x1D 0x1E Reserved. 3 R GPIO3 Pin Status GPIO3 input pin status. Note: status valid only if pin is set to GPI (input) mode. 2 R GPIO2 Pin Status GPIO2 input pin status. Note: status valid only if pin is set to GPI (input) mode. 1 R GPIO1 Pin Status GPIO1 input pin status. Note: status valid only if pin is set to GPI (input) mode. 0 R GPIO0 Pin Status GPIO0 input pin status. Note: status valid only if pin is set to GPI (input) mode. GPIO Pin Status 2 7:1 Transmitter Port Select 7:3 0 0x00 R Reserved GPIO8_REG Pin Status GPIO8_REG input pin status. Note: status valid only if pin is set to GPI (input) mode. Reserved. 2 RW 0x01 PORT1_I2C_E Port1 I2C Enable. N Enables secondary I2C address. The second I2C address provides access to Port1 registers as well as registers that are shared between Port0 and Port1. The second I2C address value will be set to DeviceID + 1 (7-bit format). The PORT1_I2C_EN bit must also be set to allow accessing remote devices over the second link when the device is in Replicate mode. 1 RW PORT1_SEL Selects Port1 for register access from primary I2C address. For writes, Port1 registers and shared registers will both be written. For reads, Port1 registers and shared registers will be read. This bit must be cleared to read Port0 registers. This bit is ignored if PORT1_I2C_EN is set. 0 RW PORT0_SEL Selects Port0 for register access from primary I2C address. For writes, Port0 registers and shared registers will both be written. For reads, Port0 registers and shared registers will be read. Note that if PORT1_SEL is also set, then Port1 registers will be read. This bit is ignored if PORT1_I2C_EN is set. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 41 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 31 0x1F Frequency Counter 32 0x20 Deserializer Capabilities 1 Register Name Bit(s) Register Type Default (hex) 7:0 RW 7 RW Function Description 0x00 Frequency Count Frequency counter control. A write to this register will enable a frequency counter to count the number of pixel clock during a specified time interval. The time interval is equal to the value written multiplied by the oscillator clock period (nominally 40ns). A read of the register returns the number of pixel clock edges seen during the enabled interval. The frequency counter will freeze at 0xff if it reaches the maximum value. The frequency counter will provide a rough estimate of the pixel clock period. If the pixel clock frequency is known, the frequency counter may be used to determine the actual oscillator clock frequency. 0x00 FREEZE_DES _CAP Freeze Deserializer Capabilities. Prevent auto-loading of the Deserializer Capabilities by the Bidirectional Control Channel. The Capabilities will be frozen at the values written in registers 0x20 and 0x21. 6 Reserved. 5 42 0x00 SEND_FREQ Send Frequency Training Pattern. Indicates the DS90UH929-Q1 should send the Frequency Training Pattern. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. SEND_EQ Send Equalization Training Pattern. Indicates the DS90UH929-Q1 should send the Equalization Training Pattern. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. 4 RW 3 RW DUAL_LINK_C Dual link Capabilities. AP Indicates if the Deserializer is capable of dual link operation. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. 2 RW DUAL_CHANN Dual Channel 0/1 Indication. EL In a dual-link capable device, indicates if this is the primary or secondary channel. 0: Primary channel (channel 0). 1: Secondary channel (channel 1). This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 32 0x20 33 38 0x21 0x26 Register Name Deserializer Capabilities 1 Bit(s) Register Type Default (hex) 1 RW 0x00 0 RW Function Description VID_24B_HD_ AUD Deserializer supports 24-bit video concurrently with HD audio. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. DES_CAP_FC _GPIO Deserializer supports GPIO in the Forward Channel Frame. This field is automatically configured by the Bidirectional Control Channel once RX Lock has been detected. Software may overwrite this value, but must also set the FREEZE DES CAP bit to prevent overwriting by the Bidirectional Control Channel. Deserializer Capabilities 2 7:2 Reserved. 1:0 Reserved. Link Detect Control 7:3 Reserved. 2:0 RW 0x00 LINK DETECT TIMER Bidirectional Control Channel Link Detect Timer. This field configures the link detection timeout period. If the timer expires without valid communication over the reverse channel, link detect will be deasserted. 000: 162 microseconds. 001: 325 microseconds. 010: 650 microseconds. 011: 1.3 milliseconds. 100: 10.25 microseconds. 101: 20.5 microseconds. 110: 41 microseconds. 111: 82 microseconds. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 43 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 48 0x30 SCLK_CTRL Register Type Default (hex) Function Description 7 RW 0x00 SCLK/WS SCLK to Word Select Ratio. 0 : 64. 1 : 32. 6:5 RW MCLK/SCLK MCLK to SCLK Select Ratio. 00 : 4. 01 : 2. 10 : 1. 11 : 8. 4:3 RW CLEAN CLOCK_DIV Clock Cleaner divider. 00 : FPD_VCO_CLOCK/8. 01 : FPD_VCO_CLOCK/4. 10 : FPD_VCO_CLOCK/2. 11 : AON_OSC. 2:1 RW CLEAN Mode If non-zero, the SCLK Input or HDMI N/CTS generated Audio Clock is cleaned digitally before being used. 00 : Off. 01 : ratio of 1. 10 : ratio of 2. 11 : ratio of 4. 0 RW MASTER If set, the SCLK I/O and the WS_IO are used as an output and the Clock Generation Circuits are enabled, otherwise they are inputs. 49 0x31 AUDIO_CTS0 7:0 RW 0x00 CTS[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. 50 0x32 AUDIO_CTS1 7:0 RW 0x00 CTS[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. 51 0x33 AUDIO_CTS2 7:0 RW 0x00 CTS[23:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. 52 0x34 AUDIO_N0 7:0 RW 0x00 N[7:0] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. 53 0x35 AUDIO_N1 7:0 RW 0x00 N[15:8] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. 54 0x36 AUDIO_N2_CO EFF 7:4 RW 0x00 COEFF[3:0] Selects the LPF_COEFF in the Clock Cleaner (Feedback is divided by 2^COEFF). 3:0 RW 0x00 N[19:16] If non-zero, the CTS value is used to generate a new clock from the PFD PLLs VCO. CLK_CLEAN_ST S 7:6 55 44 Bit(s) 0x37 Reserved. 5:3 R 0x00 IN_FIFO_LVL 2:0 R 0x00 OUT_FIFO_LV Clock Cleaner Output FIFO Level. L Clock Cleaner Input FIFO Level. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 72 0x48 APB_CTL Register Type Default (hex) 4:3 RW 0x00 2 Bit(s) Function 7:5 Description Reserved. APB_SELECT APB Select: Selects target for register access. 00 : HDMI APB interface. 01 : EDID SRAM. 10 : Configuration Data (read only). 11 : Die ID (read only). RW APB_AUTO_I NC APB Auto Increment: Enables auto-increment mode. Upon completion of an APB read or write, the APB address will automatically be incremented by 0x4 for HDMI registers or by 0x1 for others. 1 RW APB_READ Start APB Read: Setting this bit to a 1 will begin an APB read. Read data will be available in the APB_DATAx registers. The APB_ADRx registers should be programmed prior to setting this bit. This bit will be cleared when the read is complete. 0 RW APB_ENABLE APB Interface Enable: Set to a 1 to enable the APB interface. The APB_SELECT bits indicate what device is selected. 73 0x49 APB_ADR0 7:0 RW 0x00 APB_ADR0 APB Address byte 0 (LSB). 74 0x4A APB_ADR1 7:0 RW 0x00 APB_ADR1 APB Address byte 1 (MSB). 75 0x4B APB_DATA0 7:0 RW 0x00 APB_DATA0 Byte 0 (LSB) of the APB Interface Data. 76 0x4C APB_DATA1 7:0 RW 0x00 APB_DATA1 Byte 1 of the APB Interface Data. 77 0x4D APB_DATA2 7:0 RW 0x00 APB_DATA2 Byte 2 of the APB Interface Data. 78 0x4E APB_DATA3 7:0 RW 0x00 APB_DATA3 Byte 3 (MSB) of the APB Interface Data. 79 0x4F BRIDGE_CTL 7:5 Reserved. 4 RW 3 0x00 CEC_CLK_SR C CEC Clock Source Select: Selects clock source for generating the 32.768kHz clock for CEC operations in the HDMI Receive Controller. 0 : Selects internal generated clock. 1 : Selects external 25MHz oscillator clock. RW CEC_CLK_EN CEC Clock Enable: Enable CEC clock generation. Enables generation of the 32.768kHz clock for the HDMI Receive controller. This bit should be set prior to enabling CEC operation via the HDMI controller registers. 2 RW EDID_CLEAR Clear EDID SRAM: Set to 1 to enable clearing the EDID SRAM. The EDID_INIT bit must be set at the same time for the clear to occur. This bit will be cleared when the initialization is complete. 1 RW EDID_INIT Initialize EDID SRAM from EEPROM: Causes a reload of the EDID SRAM from the nonvolatile EDID EEPROM. This bit will be cleared when the initialization is complete. 0 R EDID_DISABL E Disable EDID access via DDC/I2C: Disables access to the EDID SRAM via the HDMI DDC interface. This value is loaded from the MODE_SEL0 pin at power-up. Strap Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 45 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 80 0x50 BRIDGE_STS 81 82 83 0x51 0x52 0x53 EDID_ID EDID_CFG0 EDID_CFG1 Bit(s) Register Type Default (hex) 7 R 0x03 6 Function Description RX5V_DETEC T RX +5V detect: Indicates status of the RX_5V pin. When asserted, indicates the HDMI interface has detected valid voltage on the RX_5V input. R HDMI_INT HDMI Interrupt Status: Indicates an HDMI Interrupt is pending. HDMI interrupts are serviced through the HDMI Registers via the APB Interface. 5 R HDCP_INT HDCP Interrupt Status: Indicates an HDCP Transmitter Interrupt is pending. HDCP Transmit interrupts are serviced through the HDCP Interrupt Control and Status registers. 4 R INIT_DONE Initialization Done: Initialization sequence has completed. This step will complete after configuration complete (CFG_DONE). 3 R REM_EDID_L OAD Remote EDID Loaded: Indicates EDID SRAM has been loaded from a remote EDID EEPROM device over the Bidirectional Control Channel. The EDID_CKSUM value indicates if the EDID load was successful. 2 R CFG_DONE Configuration Complete: Indicates automatic configuration has completed. This step will complete prior to initialization complete (INIT_DONE). 1 R CFG_CKSUM Configuration checksum status: Indicates result of Configuration checksum during initialization. The device verifies the 2’s complement checksum in the last 128 bytes of the EEPROM. A value of 1 indicates the checksum passed. 0 R EDID_CKSUM EDID checksum Status: Indicates result of EDID checksum during EDID initialization. The device verifies the 2’s complement checksum in the first 256 bytes of the EEPROM. A value of 1 indicates the checksum passed. 7:1 RW 0x50 EDID_ID EDID I2C Slave Address: I2C address used for accessing the EDID information. These are the upper 7 bits in 8-bit format addressing, where the lowest bit is the Read/Write control. 0 RW 0 EDID_RDONL Y EDID Read Only: Set to a 1 puts the EDID SRAM memory in read-only mode for access via the HDMI DDC interface. Setting to a 0 allows writes to the EDID SRAM memory. 7 6:4 RW 0x01 EDID_SDA_H OLD 3:0 RW 0x0E EDID_FLTR_D I2C Glitch Filter Depth: This field configures the maximum width of glitch pulses on the PTH DDC_SCL and DDC_SDA inputs that will be rejected. Units are 5 nanoseconds. RW 0x00 EDID_SDA_DL SDA Output Delay: This field configures output delay on the DDC_SDA output when the Y EDID memory is accessed. Setting this value will increase output delay in units of 40ns. Nominal output delay values for DDC_SCL to DDC_SDA are: 00 : 240ns. 01 : 280ns. 10 : 320ns. 11 : 360ns. 7:2 1:0 46 Reserved. Internal SDA Hold Time: This field configures the amount of internal hold time provided for the DDC_SDA input relative to the DDC_SCL input. Units are 40 nanoseconds. The hold time is used to qualify the start detection to avoid false detection of Start or Stop conditions. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) Function Description 84 0x54 BRIDGE_CFG 7 RW Strap EXT_CTL External Control: When this bit Is set, the internal bridge control function is disabled. This disables initialization of the HDMI Receiver as well as initiation of HDCP functions. These operations must be controlled by an external controller attached to the I2C interface. This value is loaded from the MODE_SEL1 pin at power-up. 6 RW 0x00 HDMI_INT_EN HDMI Interrupt Enable: When this bit is set, Interrupts from the HDMI Receive controller will be reported on the INTB pin. Software may check the BRIDGE_STS register to determine if the interrupt is from the HDMI Receiver or the HDCP Transmitter. 5 RW Strap DIS_REM_EDI Disable Remote EDID load: Disables automatic load of EDID SRAM from a remote EDID D EEPROM. By default, the device will check the remote I2C bus for an EEPROM with a valid EDID, and load the EDID data to local EDID SRAM. If this bit is set to a 1, the remote EDID load will be bypassed. This value is loaded from the MODE_SEL1 pin at power-up. 4 RW 0x00 AUTO_INIT_DI Disable Automatic initialization: The Bridge control will automatically initialize the HDMI S Receiver for operation. Setting this bit to a 1 will disable automatic initialization of the HDMI Receiver. In this mode, initialization of the HDMI Receiver must be done through EEPROM configuration or via external control. 3 RW 0x00 AUTO_HDCP_ Disable Automatic HDCP_CTRL setting: By default the internal bridge control function will DIS configure the HDMI Receiver for HDCP operation using default settings for bits in the HDCP_CTRL register. Setting this bit to a 1 will disable automatic control of the HDCP_CTRL register in the HDMI Receiver. 2 RW 0x00 AUDIO_TDM 1 RW 0 RW Enable TDM Audio: Setting this bit to a 1 will enable TDM audio for the HDMI audio. AUDIO_MODE Audio Mode: Selects source for audio to be sent over the FPD-Link III downstream link. 0 : HDMI audio. 1 : Local/DVI audio. Local audio is sourced from the device I2S pins rather than from HDMI, and is useful in modes such as DVI that do not include audio. Strap AUX_AUDIO_ EN AUX Audio Channel Enable: Setting this bit to a 1 will enable the AUX audio channel. This allows sending additional 2-channel audio in addition to the HDMI or DVI audio. This bit is loaded from the MODE_SEL0 pin at power-up. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 47 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 85 0x55 AUDIO_CFG Bit(s) Register Type Default (hex) 7 RW 0x00 6 RW Function Description TDM_2_PARA LLEL Enable I2S TDM to parallel audio conversion: When this bit is set, the i2s tdm to parallel conversion module is enabled. The clock output from the i2s tdm to parallel conversion module is them used to send data to the deserializer. HDMI_I2S_OU HDMI Audio Output Enable: When this bit is set, the HDMI I2S audio data will be output T on the I2S audio interface pins. This control is ignored if the BRIDGE_CFG:AUDIO_MODE is not set to 00 (HDMI audio only). 5:4 90 48 0x5A FPD3_STS Reserved. 3 RW 2 0x0C RST_ON_TYP E Reset Audio FIFO on Type Change: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio type. RW RST_ON_AIF Reset Audio FIFO on Audio Infoframe: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Infoframe checksum. 1 RW RST_ON_AVI Reset Audio FIFO on Audio Video Information Infoframe: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Video Information Infoframe checksum. 0 RW RST_ON_ACR Reset Audio FIFO on Audio Control Frame: When this bit is set, the internal bridge control function will reset the HDMI Audio FIFO on a change in the Audio Control Frame N or CTS fields. 7 R 6 0x00 FPD3_LINK_R DY This bit indicates that the FPD-Link III has detected a valid downstream connection and determined capabilities for the downstream link. R FPD3_TX_ST S FPD-Link III transmit status: This bit indicates that the FPD-Link III transmitter is active and the receiver is LOCKED to the transmit clock. It is only asserted once a valid input has been detected, and the FPDLink III transmit connection has entered the correct mode (Single vs. Dual mode). 5:4 R FPD3_PORT_ STS FPD3 Port Status: If FPD3_TX_STS is set to a 1, this field indicates the port mode status as follows: 01: Single FPD-Link III Transmit on port 0. 3 R TMDS_VALID HDMI TMDS Valid: This bit indicates the TMDS interface is recovering valid TMDS data from HDMI. In revA1 silicon, this bit will always return 1. 2 R HDMI_PLL_LO HDMI PLL lock status: Indicates the HDMI PLL has locked to the incoming HDMI clock. CK 1 R NO_HDMI_CL K No HDMI Clock Detected: This bit indicates the Frequency Detect circuit did not detect an HDMI clock greater than the value specified in the FREQ_LOW register. 0 R FREQ_STABL E HDMI Frequency is Stable: Indicates the Frequency Detection circuit has detected a stable HDMI clock frequency. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 91 0x5B FPD3_CTL1 Bit(s) Register Type Default (hex) 7 RW 5 4 Function Description Strap FPD3_COAX_ MODE FPD3 Coax Mode: Enables configuration for the FPD3 Interface cabling type. 0 : Twisted Pair. 1 : Coax This bit is loaded from the MODE_SEL1 pin at power-up. RW 1 RST_PLL_FR EQ Reset FPD3 PLL on Frequency Change: When set to a 1, frequency changes detected by the Frequency Detect circuit will result in a reset of the FPD3 PLL. RW 0 FREQ_DET_P LL Frequency Detect Select PLL Clock: Determines the clock source for the Frequency detection circuit: 0 : HDMI clock (prior to PLL). 1: HDMI PLL clock. 6 92 93 0x5C 0x5D FPD3_CTL2 FREQ_LOW Reserved. 3 Reserved. 2 Reserved. 1 Reserved. 0 Reserved. 7 Reserved. 6 RW 0x00 FORCE_LINK_ Force Link Ready: Forces link ready indication, bypassing back channel link detection. RDY 5 RW FORCE_CLK_ DET Force Clock Detect: Forces the HDMI/OpenLDI clock detect circuit to indicate presence of a valid input clock. This bypasses the clock detect circuit, allowing operation with an input clock that does not meet frequency or stability requirements. 4:3 RW FREQ_STBL_ THR Frequency Stability Threshold: The Frequency detect circuit can be used to detect a stable clock frequency. The Stability Threshold determines the amount of time required for the clock frequency to stay within the FREQ_HYST range to be considered stable: 00 : 160us. 01 : 640us. 10 : 1.28ms. 11 : 2.55ms. 2:0 RW 0x02 FREQ_HYST Frequency Detect Hysteresis: The Frequency detect hysteresis setting allows ignoring minor fluctuations in frequency. A new frequency measurement will be captured only if the measured frequency differs from the current measured frequency by more than the FREQ_HYST setting. The FREQ_HYST setting is in MHz. 6 RW 0 HDMI_RST_M ODE HDMI Phy Reset Mode: 0 : Reset HDMI Phy on change in mode or frequency. 1 : Don't reset HDMI Phy on change in mode or frequency if +5V is asserted. 5:0 RW 6 FREQ_LO_TH R Frequency Low Threshold: Sets the low threshold for the HDMI Clock frequency detect circuit in MHz. This value is used to determine if the HDMI clock frequency is too low for proper operation. 7 Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 49 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 95 0x5F HDMI Frequency 7:0 R 100 0x64 Pattern Generator Control 7:4 RW Function Description 0x00 HDMI_FREQ HDMI frequency: Returns the value of the HDMI frequency in MHz. A value of 0 indicates the HDMI receiver is not detecting a valid signal. 0x10 Pattern Generator Select Fixed Pattern Select Selects the pattern to output when in Fixed Pattern Mode. Scaled patterns are evenly distributed across the horizontal or vertical active regions. This field is ignored when Auto-Scrolling Mode is enabled. xxxx: normal/inverted. 0000: Checkerboard. 0001: White/Black (default). 0010: Black/White. 0011: Red/Cyan. 0100: Green/Magenta. 0101: Blue/Yellow. 0110: Horizontal Black-White/White-Black. 0111: Horizontal Black-Red/White-Cyan. 1000: Horizontal Black-Green/White-Magenta. 1001: Horizontal Black-Blue/White-Yellow. 1010: Vertical Black-White/White-Black. 1011: Vertical Black-Red/White-Cyan. 1100: Vertical Black-Green/White-Magenta. 1101: Vertical Black-Blue/White-Yellow. 1110: Custom color (or its inversion) configured in PGRS, PGGS, PGBS registers. 1111: VCOM. See TI App Note AN-2198. 3 50 Reserved. 2 RW Color Bars Pattern Enable color bars: 0: Color Bars disabled (default). 1: Color Bars enabled. Overrides the selection from reg_0x64[7:4]. 1 RW VCOM Pattern Reverse Reverse order of color bands in VCOM pattern: 0: Color sequence from top left is (YCBR) (default). 1: Color sequence from top left is (RBCY). 0 RW Pattern Generator Enable Pattern Generator enable: 0: Disable Pattern Generator (default). 1: Enable Pattern Generator. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) 101 0x65 Register Name Pattern Generator Configuration Bit(s) Register Type 7 Default (hex) Function 0x00 Description Reserved. 6 RW Checkerboard Scale Scale Checkered Patterns: 0: Normal operation (each square is 1x1 pixel) (default). 1: Scale checkered patterns (VCOM and checkerboard) by 8 (each square is 8x8 pixels). Setting this bit gives better visibility of the checkered patterns. 5 RW Custom Checkerboard Use Custom Checkerboard Color: 0: Use white and black in the Checkerboard pattern (default). 1: Use the Custom Color and black in the Checkerboard pattern. 4 RW PG 18–bit Mode 18-bit Mode Select: 0: Enable 24-bit pattern generation. Scaled patterns use 256 levels of brightness (default). 1: Enable 18-bit color pattern generation. Scaled patterns will have 64 levels of brightness and the R, G, and B outputs use the six most significant color bits. 3 RW External Clock Select External Clock Source: 0: Selects the internal divided clock when using internal timing (default). 1: Selects the external pixel clock when using internal timing. This bit has no effect in external timing mode (PATGEN_TSEL = 0). 2 RW Timing Select Timing Select Control: 0: The Pattern Generator uses external video timing from the pixel clock, Data Enable, Horizontal Sync, and Vertical Sync signals (default). 1: The Pattern Generator creates its own video timing as configured in the Pattern Generator Total Frame Size, Active Frame Size. Horizontal Sync Width, Vertical Sync Width, Horizontal Back Porch, Vertical Back Porch, and Sync Configuration registers. See TI App Note AN-2198. 1 RW Color Invert Enable Inverted Color Patterns: 0: Do not invert the color output (default). 1: Invert the color output. See TI App Note AN-2198. 0 RW Auto Scroll Auto Scroll Enable: 0: The Pattern Generator retains the current pattern (default). 1: The Pattern Generator will automatically move to the next enabled pattern after the number of frames specified in the Pattern Generator Frame Time (PGFT) register. See TI App Note AN-2198. 102 0x66 PGIA 7:0 RW 0x00 PG Indirect Address This 8-bit field sets the indirect address for accesses to indirectly-mapped registers. It should be written prior to reading or writing the Pattern Generator Indirect Data register. See TI App Note AN-2198 103 0x67 PGID 7:0 RW 0x00 PG Indirect Data When writing to indirect registers, this register contains the data to be written. When reading from indirect registers, this register contains the read back value. See TI App Note AN-2198 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 51 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) Function Description 112 0x70 Slave ID[1] 7:1 RW 0x00 Slave ID 1 7-bit I2C address of the remote Slave 1 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 1, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 1. 113 0x71 Slave ID[2] 7:1 RW 0x00 Slave ID 2 114 0x72 Slave ID[3] 7:1 RW 0x00 Slave ID 3 115 0x73 Slave ID[4] 7:1 RW 0x00 Slave ID 4 116 0x74 Slave ID[5] 7:1 RW 0x00 Slave ID 5 0 Reserved. 0 Reserved. 0 Slave ID[6] 7:1 118 0x76 Slave ID[7] 7:1 119 0x77 Slave Alias[1] 7:1 RW 0x00 Slave ID 6 RW 0x00 Slave ID 7 RW 0x00 Slave Alias ID 1 7-bit I2C address of the remote Slave 6 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 6, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 6. Reserved. 0 52 7-bit I2C address of the remote Slave 5 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 5, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 5. Reserved. 0 0 7-bit I2C address of the remote Slave 4 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 4, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 4. Reserved. 0 0x75 7-bit I2C address of the remote Slave 3 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 3, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 3. Reserved. 0 117 7-bit I2C address of the remote Slave 2 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 2, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 2. 7-bit I2C address of the remote Slave 7 attached to the remote Deserializer. If an I2C transaction is addressed to Slave Alias ID 7, the transaction will be remapped to this address before passing the transaction across the Bidirectional Control Channel to the Deserializer. A value of 0 in this field disables access to the remote Slave 7. Reserved. 7-bit Slave Alias ID of the remote Slave 1 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 1 register. A value of 0 in this field disables access to the remote Slave 1. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name Bit(s) Register Type Default (hex) 120 0x78 Slave Alias[2] 7:1 RW 121 0x79 Slave Alias[3] 7:1 122 0x7A Slave Alias[4] 7:1 123 0x7B Slave Alias[5] 7:1 124 0x7C Slave Alias[6] 7:1 125 0x7D Slave Alias[7] 7:1 128 0x80 RX_BKSV0 129 0x81 130 0x82 131 Function Description 0x00 Slave Alias ID 2 7-bit Slave Alias ID of the remote Slave 2 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 2 register. A value of 0 in this field disables access to the remote Slave 2. RW 0x00 Slave Alias ID 3 RW 0x00 Slave Alias ID 4 RW 0x00 Slave Alias ID 5 RW 0x00 Slave Alias ID 6 RW 0x00 Slave Alias ID 7 7:0 R 0x00 RX_BKSV0 BKSV0: Value of byte0 of the Receiver KSV. RX_BKSV1 7:0 R 0x00 RX_BKSV1 BKSV1: Value of byte1 of the Receiver KSV. RX_BKSV2 7:0 R 0x00 RX_BKSV2 BKSV2: Value of byte2 of the Receiver KSV. 0x83 RX_BKSV3 7:0 R 0x00 RX_BKSV3 BKSV3: Value of byte3 of the Receiver KSV. 132 0x84 RX_BKSV4 7:0 R 0x00 RX_BKSV4 BKSV4: Value of byte4 of the Receiver KSV. 144 0x90 TX_KSV0 7:0 R 0x00 TX_KSV0 TX_KSV0: Value of byte0 of the Transmitter KSV. 145 0x91 TX_KSV1 7:0 R 0x00 TX_KSV1 TX_KSV1: Value of byte1 of the Transmitter KSV. 146 0x92 TX_KSV2 7:0 R 0x00 TX_KSV2 TX_KSV2: Value of byte2 of the Transmitter KSV. 147 0x93 TX_KSV3 7:0 R 0x00 TX_KSV3 TX_KSV3: Value of byte3 of the Transmitter KSV. 148 0x94 TX_KSV4 7:0 R 0x00 TX_KSV4 TX_KSV4: Value of byte4 of the Transmitter KSV. 0 Reserved. 0 7-bit Slave Alias ID of the remote Slave 3 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 3 register. A value of 0 in this field disables access to the remote Slave 3. Reserved. 0 7-bit Slave Alias ID of the remote Slave 4 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 4 register. A value of 0 in this field disables access to the remote Slave 4. Reserved. 0 7-bit Slave Alias ID of the remote Slave 5 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 5 register. A value of 0 in this field disables access to the remote Slave 5. Reserved. 0 7-bit Slave Alias ID of the remote Slave 6 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 6 register. A value of 0 in this field disables access to the remote Slave 6. Reserved. 0 7-bit Slave Alias ID of the remote Slave 7 attached to the remote Deserializer. The transaction will be remapped to the address specified in the Slave ID 7 register. A value of 0 in this field disables access to the remote Slave 7. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 53 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 160 0xA0 RX_BCAPS Register Type Default (hex) Function 6 R 0x01 Repeater 5 R KSV_FIFO_RD KSV FIFO Ready: Indicates the receiver has built the list of attached KSVs and computed Y the verification value V’. 4 R FAST_I2C Bit(s) 7 Reserved. 3:2 161 162 163 54 0xA1 0xA2 0xA3 RX_BSTATUS0 RX_BSTATUS1 KSV_FIFO Description Repeater: Indicates if the attached Receiver supports downstream connections. This bit is valid once the Bksv is ready as indicated by the BKSV_RDY bit in the HDCP. Fast I2C: The HDCP Receiver supports fast I2C. Since the I2C is embedded in the serial data, this bit is not relevant. Reserved. 1 R 0 R 7 R 6:0 R 0x03 0x00 FEATURES_1 _1 1.1_Features: The HDCP Receiver supports the Enhanced Encryption Status Signaling (EESS), Advance Cipher, and Enhanced Link Verification options. FAST_REAUT H Fast Reauthentication: The HDCP Receiver is capable of receiving (unencrypted) video signal during the session re-authentication. MAX_DEVS_E Maximum Devices Exceeded: Indicates a topology error was detected. Indicates the XCEEDED number of downstream devices has exceeded the depth of the Repeater's KSV FIFO. DEVICE_COU NT 7:4 Device Count: Total number of attached downstream device. For a Repeater, this will indicate the number of downstream devices, not including the Repeater. For an HDCP Receiver that is not also a Repeater, this field will be 0. Reserved. 3 R 2:0 R 7:0 R 0x00 0x00 MAX_CASC_E Maximum Cascade Exceeded: Indicates a topology error was detected. Indicates that XCEEDED more than seven levels of repeaters have been cascad-ed together. Cascade Depth Cascade Depth: Indicates the number of attached levels of devices for the Repeater. KSV_FIFO KSV FIFO: Each read of the KSV FIFO returns one byte of the KSV FIFO list composed by the downstream Receiver. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 192 0xC0 HDCP_DBG Register Type Default (hex) RW 0x00 HDCP_I2C_T O_DIS 4 RW 0x00 DIS_RI_SYNC Disable Ri Synchronization check: Ri is normally checked both before and after the start of frame 128. The check at frame 127 ensures synchronization between the two. Setting this bit to a 1 will disable the check at frame 127. 3 RW RGB_CHKSU M_EN Enable RBG video line checksum: Enables sending of ones-complement checksum for each 8-bit RBG data channel following end of each video data line. 2 RW FC_TESTMOD Frame Counter Testmode: Speeds up frame counter used for Pj and Ri verification. E When set to a 1, Pj is computed every 2 frames and Ri is computed every 16 frames. When set to a 0, Pj is computed every 16 frames and Ri is computed every 128 frames. 1 RW TMR_SPEEDU Timer Speedup: Speed up HDCP authentication timers. P 0 RW HDCP_I2C_FA HDCP I2C Fast Mode Enable Setting this bit to a 1 will enable the HDCP I2C Master in ST the HDCP Receiver to operation with Fast mode timing. If set to a 0, the I2C Master will operation with Standard mode timing. This bit is mirrored in the IND_STS register. Bit(s) Function 7 6 Description Reserved. 5 HDCP I2C Timeout Disable: Setting this bit to a 1 will disable the bus timeout function in the HDCP I2C master. When enabled, the bus timeout function allows the I2C master to assume the bus is free if no signaling occurs for more than 1 second. Reserved. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 55 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) 56 ADD (dec) ADD (hex) Register Name 194 0xC2 HDCP_CFG Bit(s) Register Type Default (hex) Function Description 7 RW 0xA8 ENH_LV Enable Enhanced Link Verification: Enables enhanced link verification. Allows checking of the encryption Pj value on every 16th frame. 0 = Enhanced Link Verification disabled. 1 = Enhanced Link Verification enabled. 6 RW HDCP_EESS Enable Enhanced Encryption Status Signaling: Enables Enhanced Encryption Status Signaling (EESS) instead of the Original Encryption Status Signaling (OESS). 0 = OESS mode enabled. 1 = EESS mode enabled. 5 RW TX_RPTR Transmit Repeater Enable: Enables the transmitter to act as a repeater. In this mode, the HDCP Transmitter incorporates the additional authentication steps required of an HDCP Repeater. 0 = Transmit Repeater mode disabled. 1 = Transmit Repeater mode enabled. 4:3 RW ENC_MODE Encryption Control Mode: Determines mode for controlling whether encryption is required for video frames. 00 = Enc_Authenticated. 01 = Enc_Reg_Control. 10 = Enc_Always. 11 = Enc_InBand_Control (per frame). 2 RW WAIT_100MS Enable 100MS Wait: The HDCP 1.3 specification allows for a 100Ms wait to allow the HDCP Receiver to compute the initial encryption values. The FPD-LinkIII implementation guarantees that the Receiver will complete the computations before the HDCP Transmitter. Thus the timer is unnecessary. To enable the 100ms timer, set this bit to a 1. 1 RW RX_DET_SEL RX Detect Select: Controls assertion of the Receiver Detect Interrupt. If set to 0, the Receiver Detect Interrupt will be asserted on detection of an FPD-Link III Receiver. If set to 1, the Receiver Detect Interrupt will also require a receive lock indication from the receiver. 0 RW HDCP_AVMU TE Enable AVMUTE: Setting this bit to a 1 will initiate AVMUTE operation. The transmitter will ignore encryption status controls while in this state. If this bit is set to a 0, normal opera¬tion will resume. This bit may only be set if the HDCP_EESS bit is also set. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 195 0xC3 HDCP_CTL Bit(s) Register Type Default (hex) 7 RW 0x00 Function Description HDCP_RST HDCP Reset : Setting this bit will reset the HDCP transmitter and dis-able HDCP authentication. This bit is self-clearing. 6 Reserved. 5 RW 4 0x00 KSV_LIST_VA LID KSV List Valid : The controller sets this bit after validating the Repeater’s KSV List against the Key revocation list. This allows completion of the Authentication process. This bit is self-clearing. RW KSV_VALID KSV Valid : The controller sets this bit after validating the Receiver’s KSV against the Key revocation list. This allows continuation of the Authentication process. This bit will be cleared upon assertion of the KSV_RDY flag in the HDCP_STS register. Setting this bit to a 0 will have no effect. 3 RW HDCP_ENC_D HDCP Encrypt Disable : Disables HDCP encryption. Setting this bit to a 1 will cause IS video data to be sent without encryption. Authen-tication status will be maintained. This bit is self-clear-ing. 2 RW HDCP_ENC_E HDCP Encrypt Enable : Enables HDCP encryption. When set, if the device is N authenticated, encrypted data will be sent. If device is not authenticated, a blue screen will be sent. Encryption should always be enabled when video data requiring content protection is being supplied to the transmitter. When this bit is not set, video data will be sent without encryption. Note that when CFG_ENC_MODE is set to Enc_Always, this bit will be read only with a value of 1. 1 RW HDCP_DIS HDCP Disable: Disables HDCP authentication. Setting this bit to a 1 will disable the HDCP authentication. This bit is self-clearing. 0 RW HDCP_EN HDCP Enable/Restart: Enables HDCP authentication. If HDCP is already en-abled, setting this bit to a 1 will restart authentication. Setting this bit to a 0 will have no effect. A register read will return the current HDCP enabled status. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 57 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 196 0xC4 HDCP_STS 198 58 0xC6 ICR Bit(s) Register Type Default (hex) 7 R 0x00 6 R RX_INT RX Interrupt : Status of the RX Interrupt signal. The signal is received from the attached HDCP Receiver and is the status on the INTB_IN pin of the HDCP Receiver. The signal is active low, so a 0 indicates an interrupt condition. 5 R RX_LOCK_DE T Receiver Lock Detect : This bit indicates that the downstream Receiver has indicated Receive Lock to incoming serial data. 4 R DOWN_HPD Downstream Hot Plug Detect: This bit indicates a downstream repeater has reported a Hot Plug event, indicating addition of a new receiver. This bit will be cleared on read. 3 R RX_DETECT Receiver Detect : This bit indicates that a downstream Receiver has been detected. 2 R KSV_LIST_RD HDCP Repeater KSV List Ready : This bit indicates that the Receiver KSV list has been Y read and is available in the KSV_FIFO registers. The device will wait for the controller to set the KSV_LIST_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_LIST_VALID bit. 1 R KSV_RDY HDCP Receiver KSV Ready : This bit indicates that the Receiver KSV has been read and is available in the HDCP_BKSV registers. If the de-vice is not a Repeater, it will wait for the controller to set the KSV_VALID bit in the HDCP_CTL register before continuing. This bit will be cleared once the controller sets the KSV_VALID bit. 0 R AUTHED HDCP Authenticated: Indicates the HDCP authentication has completed successfully. The controller may now send video data re-quiring content protection. This bit will be cleared if authentication is lost or if the controller restarts authentication. 7 RW IE_IND_ACC Interrupt on Indirect Access Complete: Enables interrupt on completion of Indirect Register Access. 6 RW IE_RXDET_IN T Interrupt on Receiver Detect: Enables interrupt on detection of a downstream Receiver. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect. 5 RW IE_RX_INT Interrupt on Receiver interrupt: Enables interrupt on indication from the HDCP Receiver. Allows propagation of interrupts from downstream devices. 4 RW IE_LIST_RDY Interrupt on KSV List Ready: Enables interrupt on KSV List Ready. 3 RW IE_KSV_RDY Interrupt on KSV Ready: Enables interrupt on KSV Ready. 2 RW IE_AUTH_FAI L Interrupt on Authentication Failure: Enables interrupt on authentication failure or loss of authentication. 1 RW IE_AUTH_PAS Interrupt on Authentication Pass: Enables interrupt on successful completion of S authentication. 0 RW INT_EN 0x00 Function Description I2C_ERR_DET HDCP I2C Error Detected: This bit indicates an error was detected on the embedded communications channel with the HDCP Receiver. Setting of this bit might indicate that a problem exists on the link between the HDCP Transmitter and HDCP Receiver. This bit will be cleared on read. Global Interrupt Enable: Enables interrupt on the interrupt signal to the controller. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Register Maps (continued) Table 8. Serial Control Bus Registers (continued) ADD (dec) ADD (hex) Register Name 199 0xC7 ISR 200 0xC8 NVM_CTL Bit(s) Register Type Default (hex) 7 R 0x00 6 R 5 Function Description IS_IND_ACC Interrupt on Indirect Access Complete: Indirect Register Access has completed. IS_RXDET_IN T Interrupt on Receiver Detect interrupt: A downstream receiver has been detected. If HDCP_CFG:RX_DET_SEL is set to a 1, the interrupt will wait for Receiver Lock Detect. R IS_RX_INT Interrupt on Receiver interrupt: Receiver has indicated an interrupt request from downstream device. 4 R IS_LIST_RDY Interrupt on KSV List Ready: The KSV list is ready for reading by the controller. 3 R IS_KSV_RDY Interrupt on KSV Ready: The Receiver KSV is ready for reading by the controller. 2 R IS_AUTH_FAI L Interrupt on Authentication Failure: Authentication failure or loss of authentication has occurred. 1 R IS_AUTH_PAS Interrupt on Authentication Pass: Authentication has completed successfully. S 0 R 7 R 6 R 5 RW 0x00 INT Global Interrupt: Set if any enabled interrupt is indicated. NVM_PASS NVM Verify pass: This bit indicates the completion status of the NVM verification process. This bit is valid only when NVM_DONE is asserted. 0: NVM Verify failed. 1: NVM Verify passed. NVM_DONE NVM Verify done: This bit indicates that the NVM Verifcation has completed. NVM_PARALL EL NVM Parallel Load Enable: Setting this bit enables external parallel data to be written to NVM SRAM. Byte data and a memory clock are brought in on the R[7:0] and G[0] pins respectively. In this mode of operation NVM_DATA[0] acts as a memory enable to enable writes to the NVM SRAM. 4:3 Reserved. 2 RW 1 0x00 NVM_VFY NVM Verify: Setting this bit will enable a verification of the NVM contents. This is done by reading all NVM keys, computing a SHA-1 hash value, and verifying against the SHA-1 hash stored in NVM. This bit will be cleared upon completion of the NVM Verification. RW NVM_PROG NVM Program: Setting this bit to a 1 allows programming of the NVM memory from the NVM SRAM. 0 RW NVM_PROG_ EN NVM Program Enable: Set to a 1 to allow erase or programming of NVM. BLUE_SCREE N_VAL Blue Screen Data Value: Provides the 8-bit data value sent on the Blue channel when the HDCP Transmitter is sending a blue screen. 206 0xCE BLUE_SCREEN 7:0 RW 0xFF 224 0xE0 HDCP_DBG_ALI AS 7:0 R HDCP_DBG Read-only alias of HDCP_DBG register. 226 0xE2 HDCP_CFG_ALI AS 7:0 R HDCP_CFG Read-only alias of HDCP_CFG register. 227 0xE3 HDCP_CTL_ALI AS 7:0 R HDCP_CTL Read-only alias of HDCP_CTL register. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 59 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Register Maps (continued) Table 8. Serial Control Bus Registers (continued) 60 ADD (dec) ADD (hex) Register Name Bit(s) Register Type 228 0xE4 HDCP_STS_ALI AS 7:0 230 0xE6 HDCP_ICR_ALI AS 231 0xE7 240 0xF0 241 242 Default (hex) Function Description R HDCP_STS Read-only alias of HDCP_STS register. 7:0 R HDCP_ICR Read-only alias of HDCP_ICR register. HDCP_ISR_ALI AS 7:0 R HDCP_ISR Read-only alias of HDCP_ISR register. TX ID 7:0 R 0x5F ID0 First byte ID code: "_". 0xF1 7:0 R 0x55 ID1 Second byte of ID code: "U". 0xF2 7:0 R 0x48 ID2 Third byte of ID code: "H". 243 0xF3 7:0 R 0x39 ID3 Fourth byte of ID code: "9". 244 0xF4 7:0 R 0x32 ID4 Fifth byte of ID code: "2". 245 0xF5 7:0 R 0x39 ID5 Sixth byte of ID code: “9”. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Applications Information The DS90UH929-Q1, in conjunction with the DS90UH926Q-Q1/DS90UH928Q-Q1deserializer, is intended to interface between a host (graphics processor) and a display, supporting 24-bit color depth (RGB888) and high definition (720p) digital video format. It can receive an 8-bit RGB stream with a pixel clock rate up to 96 MHz together with four I2S audio streams when paired with the DS90UH940-Q1/DS90UH948-Q1 deserializer. 9.2 Typical Applications Bypass capacitors should be placed near the power supply pins. A capacitor and resistor are placed on the PDB pin to delay the enabling of the device until power is stable. See below for typical STP and coax connection diagrams. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 61 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Typical Applications (continued) VDD18 (Filtered 1.8V) 1.8V FB1 10µF 1µF 0.01µF - 0.1µF 0.1µF 0.01µF - 0.1µF VDD18 VDDHA11 VDD18 0.1µF FB2 10µF 1µF 10µF 0.01µF - 0.1µF VDDHS11 0.01µF - 0.1µF VDDL11 VDDHS11 VDDL11 VDDS11 FB4 0.01µF - 0.1µF 0.01µF - 0.1µF 3.3V (DC coupled)/1.8V (AC coupled) 1µF VDDHA11 0.01µF - 0.1µF 0.1µF 0.1µF FB3 0.01µF - 0.1µF VDDIO 1.1V 10µF VDDHA11 VDDIO 1µF 1µF 0.01µF - 0.1µF VDD18 0.1µF 0.1µF VDDHA11 0.01µF - 0.1µF 1µF 1.1V 0.01µF - 0.1µF 0.01µF - 0.1µF VDDA11 0.01µF - 0.1µF VTERM FB5 VDDP11 0.01µF 0.01µF - 0.1µF IN_CLK+ IN_CLKTMDS (DC coupled) C1 C2 DOUT+ DOUT- IN_D0+ IN_D0- FPD-Link III 50 IN_D1+ IN_D1LFT IN_D2+ IN_D2- 10nF VDD18 (Filtered 1.8V) R1 IDx R2 0.1µF R3 MODE_SEL0 Hot Plug Detect R4 RX_5V HPD 1k 0.1µF R5 MODE_SEL1 R6 3.3V 27k 47k 0.1µF 47k DDC_SDA DDC_SCL CEC HDMI Control VDDI2C 1.8V 4.7k 4.7k 4.7k SDA SCL INTB REM_INTB 1.8V 10k PDB Controller (Optional) >10µF REF CLKIN 4.7k I2C Interrupts X1 SCLK SWC SDIN MCLK I2S_WC I2S_CLK I2S_DA I2S_DB I2S_DC I2S_DD I2S Audio float RES0 RES1 RES2 DAP NC[8:0] Aux Audio 50 NOTE: FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz C1 = 0.033µF (50 WV; 0402) C2 = 0.015µF (50 WV; 0402) R1 ± R2 (see IDx Resistor Values Table) R3 ± R6 (see MODE_SEL Resistor Values Table) VDDI2C = Pull up voltage of I2C bus. Refer to I2CSEL pin description for 1.8V or 3.3V operation. DS90UH929-Q1 Figure 21. Typical Application Connection -- Coax 62 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 Typical Applications (continued) VDD18 (Filtered 1.8V) 1.8V FB1 10µF 1µF 0.01µF - 0.1µF 0.1µF 0.01µF - 0.1µF VDD18 VDDHA11 VDD18 0.1µF FB2 10µF 1µF 10µF 0.01µF - 0.1µF VDDHS11 0.01µF - 0.1µF VDDL11 VDDHS11 VDDL11 VDDS11 FB4 0.01µF - 0.1µF 0.01µF - 0.1µF 3.3V (DC coupled)/1.8V (AC coupled) 1µF VDDHA11 0.01µF - 0.1µF 0.1µF 0.1µF FB3 0.01µF - 0.1µF VDDIO 1.1V 10µF VDDHA11 VDDIO 1µF 1µF 0.01µF - 0.1µF VDD18 0.1µF 0.1µF VDDHA11 0.01µF - 0.1µF 1µF 1.1V 0.01µF - 0.1µF 0.01µF - 0.1µF VDDA11 0.01µF - 0.1µF VTERM FB5 VDDP11 0.01µF 0.01µF - 0.1µF IN_CLK+ IN_CLKTMDS (DC coupled) C1 C2 DOUT+ DOUT- IN_D0+ IN_D0- FPD-Link III IN_D1+ IN_D1LFT IN_D2+ IN_D2- 10nF VDD18 (Filtered 1.8V) R1 IDx R2 0.1µF R3 MODE_SEL0 Hot Plug Detect R4 RX_5V HPD 1k 0.1µF R5 MODE_SEL1 R6 3.3V 27k 47k 0.1µF 47k DDC_SDA DDC_SCL CEC HDMI Control VDDI2C 1.8V 4.7k 4.7k 4.7k SDA SCL INTB REM_INTB 1.8V 10k PDB Controller (Optional) >10µF REF CLKIN 4.7k I2C Interrupts X1 SCLK SWC SDIN MCLK I2S_WC I2S_CLK I2S_DA I2S_DB I2S_DC I2S_DD I2S Audio float RES0 RES1 RES2 DAP NC[8:0] Aux Audio NOTE: 50 FB1,FB5: DCR<=0.3Ohm; Z=1Kohm@100MHz FB2-FB4: DCR<=25mOhm; Z=120ohm@100MHz C1-C2 = 0.1µF (50 WV; 0402) with DS90UH926/928 C1-C2 = 0.033µF (50 WV; 0402) with DS90UH940/948 R1 ± R2 (see IDx Resistor Values Table) R3 ± R6 (see MODE_SEL Resistor Values Table) VDDI2C = Pull up voltage of I2C bus. Refer to I2CSEL pin description for 1.8V or 3.3V operation. DS90UH929-Q1 Figure 22. Typical Application Connection -- STP Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 63 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com Typical Applications (continued) VDDIO 1.8V Mobile Device /Graphics Processor TMDS Interface HDMI 3.3V 1.1V VDDIO 1.8V or 3.3V RIN- R[7:0] G[7:0] B[7:0] HS VS DE PCLK DS90UH926Q-Q1 Deserializer LOCK PASS FPD-Link III 1 Pair / AC Coupled IN_CLK+ IN_D0+ DOUT+ IN_D1+ IN_D2+ CEC DDC HPD GPIO RIN+ DOUTPDB OSS_SEL OEN MODE_SEL DS90UH929-Q1 Serializer 4 / 3 / INTB_IN I2C_SCL I2C_SDA IDx SCL SDA IDx DAP RGB Display 720p 24-bit color depth I2S AUDIO (STEREO) MCLK DAP HDCP ± High-Bandwidth Digital Content Protection TMDS ± Transition-Minimized Differential Signaling HDMI ± High Definition Multimedia Interface Figure 23. Typical System Diagram 9.2.1 Design Requirements The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme. External AC coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in Figure 24. Table 9. Design Parameters DESIGN PARAMETER EXAMPLE VALUE VDDIO 1.8V AC Coupling Capacitor for DOUT0± and DOUT1± with 92x deserializers 100nF AC Coupling Capacitor for DOUT0± and DOUT1± with 94x deserializers 33nF For applications utilizing single-ended 50Ω coaxial cable, the unused data pins (DOUT-) should utilize a 15nF capacitor and should be terminated with a 50Ω resistor. DOUT+ RIN+ DOUT- RIN- SER DES Figure 24. AC-Coupled Connection (STP) DOUT+ RIN+ DOUT- RIN- SER DES 50Q 50Q Figure 25. AC-Coupled Connection (Coaxial) For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. 64 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 9.2.2 Detailed Design Procedure 9.2.2.1 High Speed Interconnect Guidelines See AN-1108 and AN-905 for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS signal • Minimize the number of Vias • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair • Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the Texas Instruments web site at: LVDS Owner's Manual. 9.2.3 Application Curves 9.2.3.1 Application Performance Plots Figure 26 corresponds to 1080p60 video application with 2-lane FPD-Link III output. Figure 27 corresponds to 3.36Gbps single-lane output from 96MHz input TMDS clock. Figure 26. 720p60 Video at 2.6 Gbps Serial Line Rate Figure 27. Serializer Output at 3.36Gbps (96MHz TMDS Clock) Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 65 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 10 Power Supply Recommendations This device provides separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. The Pin Functions table provides guidance on which circuit blocks are connected to which power pins. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. 10.1 Power Up Requirements And PDB Pin The power supply ramp should be faster than 1.5ms with a monotonic rise. A large capacitor on the PDB pin is needed to ensure PDB arrives after all the supply pins have settled to the recommended operating voltage. When PDB pin is pulled up to VDDIO, a 10kΩ pull-up and a >10μF capacitor to GND are required to delay the PDB input signal rise. All inputs must not be driven until all power supplies have reached steady state. The recommended power up sequence is as follows: VTERM, VDD18, VDD11, wait until all supplies have settled, activate PDB, then apply HDMI input. 66 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 11 Layout 11.1 Layout Guidelines Circuit board layout and stack-up for the LVDS serializer and deserializer devices should be designed to provide low-noise power to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mil) for power / ground sandwiches. This arrangement utilizes the plane capacitance for the PCB power system and has low-inductance, which has proven effectiveness especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01μF to 10μF. Tantalum capacitors may be in the 2.2μF to 10μF range. The voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. MLCC surface mount capacitors are recommended due to their smaller parasitic properties. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommended at the point of power entry. This is typically in the 50μF to 100μF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. A small body size X7R chip capacitor, such as 0603 or 0805, is recommended for external bypass. A small body sized capacitor has less inductance. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20MHz-30MHz. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. For DS90UH929-Q1, only one common ground plane is required to connect all device related ground pins. Use at least a four layer board with a power and ground plane. Locate LVCMOS signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely coupled differential lines of 100Ω are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. At least 9 thermal vias are necessary from the device center DAP to the ground plane. They connect the device ground to the PCB ground plane, as well as conduct heat from the exposed pad of the package to the PCB ground plane. More information on the LLP style package, including PCB design and manufacturing requirements, is provided in TI Application Note: AN-1187. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 67 DS90UH929-Q1 SNLS458 – NOVEMBER 2014 www.ti.com 11.2 Layout Example Figure 28 is derived from a layout design of the DS90UH929-Q1. This graphic is used to demonstrate proper high-speed routing when designing in the Serializer. Figure 28. DS90UH929-Q1 Serializer Layout Example 68 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 DS90UH929-Q1 www.ti.com SNLS458 – NOVEMBER 2014 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: • Soldering Specifications Application Report, SNOA549 • IC Package Thermal Metrics Application Report, SPRA953 • Channel-Link PCB and Interconnect Design-In Guidelines, SNLA008 • Transmission Line RAPIDESIGNER Operation and Application Guide, SNLA035 • Leadless Leadframe Package (LLP) Application Report, SNOA401 • LVDS Owner's Manual, SNLA187 • I2C Communication Over FPD-Link III with Bidirectional Control Channel, SNLA131A • Using the I2S Audio Interface of DS90Ux92x FPD-Link III Devices, SNLA221 • Exploring the Internal Test Pattern Generation Feature of 720p FPD-Link III Devices, SNLA132 12.2 Trademarks TRI-STATE is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: DS90UH929-Q1 69 PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90UH929TRGCRQ1 ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 UH929Q DS90UH929TRGCTQ1 ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 105 UH929Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Jul-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90UH929TRGCRQ1 VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 DS90UH929TRGCTQ1 VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.1 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90UH929TRGCRQ1 VQFN RGC 64 2000 367.0 367.0 38.0 DS90UH929TRGCTQ1 VQFN RGC 64 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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