1/4 ◇Structure ◇Product name ◇Type ◇Applications ◇Functions Silicon Monolithic integrated circuit Audio interface + Video driver + POL + RTC LSI BU76294GUW DSC, etc ＜Audio part＞ ・Monaural・16 bit ΔΣCODEC ・Monaural microphone amplifier with ALC function ・Monaural line amplifier ・BTL output speaker amplifier (300mW@8Ω, THD+N=10%, VDD=3.0V) ・64-step electronic volume with ALC function ・PLL built-in（Reference clock：12MHz、24MHz、27MHz、16fs、32fs、64fs） (sampling rate：8kHz ～ 48kHz) ・Four-line serial interface （power on reset function） ・Audio IF format MSB First, 2’s compliment ＜ADC＞ 16bit word lengths Left justified, I2S ＜DAC＞ 16bit word lengths Left, Right justified, I2S ＜Video part＞ ・Sync-tip-clamp, LPF, 6dB Amplifier ・Output coupling condenser unnecessary ＜Boot system＞ ・Step up charge pump：1ch , Voltage detect circuit：4ch built-in ＜RTC part＞ ・32bit counter built-in ・128bit back up register built-in ◇Absolute maximum ratings （Ta=25℃） Parameter Symbol Supply voltage VDD DVDD Supply voltage DVDD UNREG Supply voltage UNREG BATT Supply voltage BATT Input voltage VIN Storage temperature range TSTG Operating temperature range TOPE Power dissipation *1 PD Limits -0.3～4.5 -0.3～2.5 -0.3～6.0 -0.3～4.5 -0.3～supply voltage +0.3 -50～125 -20～85 800*1 Unit V V V V V ℃ ℃ mW Comment AVDD, IOVDD, SPVDD, VVDD DVDD UNREG BATT keep each limits upon Unit Ｖ V V V Comment AVDD, IOVDD, SPVDD, VVDD DVDD UNREG BATT ＊1：In the case of use at Ta=25℃ or more, 8mW should be reduced per 1℃. （t=1.6mm, 114.3mm x 76.2mm, , board base on SEMI, 4-layer board） Radiation resistance design is not arranged. ◇Operating conditions （Ta=25℃） Parameter Symbol Supply voltage VDD DVDD Supply voltage DVDD UNREG Supply voltage UNREG BATT Supply voltage BATT Limits 2.7～3.6 1.62～1.98 1.7～5.5 2.0～3.3 （note） Please do not set SPVDD lower than AVDD-0.3V. （note） Please do not surpass package permissible loss, when SPVDD is set. REV. A 2/4 ◇Electrical characteristics ○Audio interface + Video driver （Unless specified, Ta=25℃、AVDD=SPVDD=IOVDD=VVDD= 3.0V、DVDD= 1.8V、BATT=3.0V、FBREG=4.2V B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz、XIN=32.768kHz） Parameter Symbol MIN. Limits TYP. Unit < Current consumption > #MASTER=0 MCLK=24MHz Power-down mode IDDS Rec mode/PLL mode IDDR - 0.04 5.8 0.1 16 mA mA Play mode/PLL mode - 5.3 16 mA IDDP Condition MAX. Video mode IDDV 8.2 18 <MREG> output voltage VOREG 0.75AVDD-0.2 0.75AVDD 0.75AVDD+0.2 <REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=48dB Input impedance ZIN 70 100 130 Input level VIN -53 -51 -49 L/R gain mismatch △GV -1.0 0 +1.0 Distortion THD+N 43 58 SNR SNR 59 65 ALC１ output level DOALC -7.3 <PB path1 （DAIN→LINEOUT）> #LGAIN=+5dB Output level VO -5.0 -5.0 -3.5 Distortion THD+N 0.01 0.1 ＳＮＲ SNR 81 89 <PB path2 （DAIN→EVROUT→SPIN→SPOUT BTL output）> #ALC2=OFF, EVR=-6dB, RL=8Ω Output level VO 0.1 2.1 4.1 Distortion THD+N 0.1 1.0 SNR SNR 75 82 ALC２ output level VOALC 0.1 2.1 4.1 < Video path （VIN→VOUT）> Voltage gain GV +5.0 +6.0 +7.0 Maximum output level VOM 2.2 2.6 Frequency characteristic 1 GF1 -1.0 0 +0.5 Frequency characteristic 2 GF2 -20 -6 mA Ｖ #PWAP=0 #PWAP=MDREC=MDPLL=1, MCLK=24MHz #PWAP=MDPB=MDSP=MDPLL=1, MCLK=24MHz #PWAP=PWVD=1 MDPLL=0 2.2kΩ load kΩ dBV dB dB dB dBFS DOUT=0dBFS DOUT=0dBFS DOUT=-6dBFS@1kHz B.W.=JIS-A ALC1=ON dBV % dB DIN=-6dBFS DIN=-6dBFS@1kHz B.W.=JIS-A dBV % dB dBV DIN=0dBFS DIN=0dBFS@1kHz B.W.=JIS-A ALC2=ON, EVR=8dB dB Vpp dB dB VIN=100KHz, 1.0Vpp f=10KHz, THD=1% f=4.5MHz/100KHz f=18MHz/100KHz ○Back up・RTC （Unless specified, Ta=25℃、AVDD=SPVDD=IOVDD=VVDD= 3.0V、DVDD= 1.8V、BATT=3.0V、FBREG=4.2V B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz、XIN=32.768kHz） Parameter Symbol MIN. < Current consumption > UNREG Current consumption BATT Current consumption <DC-DC> Stop oscillation voltage Operation start voltage <Regulator> Output voltage <Back up SW> Change voltage Hysteresis width <Reset> ＲＥＳＥＴ voltage UVLO voltage Hysteresis width <voltage monitor> Output voltage <Logic> L input voltage 1 H input voltage 1 L input voltage 2 H input voltage 2 L output voltage 1 H output voltage 1 L output voltage 2 H output voltage 2 Limits TYP. MAX. Unit Condition Icc - 50 100 μA UNREG=4.5V, EV3=no load Iｒｔｃ - 1.0 2.0 μA BATT=3.0V, Counter start Vout Vstart 3.6 - 3.9 1.3 4.2 1.7 V V EV3 no load, VDET=FBREG Oscillation start, VDET=FBREG*1 VREG 2.940 3.000 3.060 V No load VSW VShys 3.100 40 3.200 100 3.300 160 V mV VDET=FBREG VDET=FBREG VRST VＵLVO VRhys 2.65 1.9 40 2.75 2.0 100 2.85 2.1 160 V V mV Hi→Lo detect, VDET=RESETIN Hi→Lo detect, VDET=UVLO VPMG 0.45×UVLO 0.50×UVLO 0.55×UVLO V VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 DVSS 0.7IOVDD RTCGND 0.7EV3 DVSS 0.8IOVDD RTCGND 0.9EV3 - 0.3IOVDD IOVDD 0.3EV3 EV3 0.2IOVDD IOVDD 0.1EV3 EV3 V V V V V V V V *1 The operation of DC-DC start voltage. REV. A ACT ACT PWRSW0,1 PWRSW0,1 Iout=1.0mA SOUT,PWRSW_STATE,RESETOUT Iout=-1.0mA SOUT,PWRSW_STATE Iout=0.5mA PWRCTRL0,1 Iout=-0.5mA PWRCTRL0,1 PWRSW_STATE EV3 FBREG ◇Block diagram RESETIN 3/4 UNREG + - + - CPOUT OSC RWRCTL DET REF RESETOUT DL REG ACT ONT TEST EV3 MM Adjust PWRSW0 Adjust PWRSW1 POR BATT XIN DL 128Bit REGISTER OSC Det Noise Cancel Delay Lo:100ms UVLO + - BATT RWRCTL PMG_VBAT_DA PWRCTRL0 PWRCTRL1 DL LNF XOUT DIV RTC RTCGND ADC DVDD LPF MICIN ALC Mic Amp Logic Δ∑ADC 16bit IOVDD MREG CLAMP DAC DVSS VIN Δ∑DAC 16bit BIAS PLL EVR ＋ ＋ Audio I/F - Serial I/F VVSS AVSS EVROUT LINEOUT SPIN SPNEG SPVDD SPVSS SPPOS MCLK DAIN ADOUT FCLK BCLK SOUT CSB SDATA SCLK VOUT Figure1. Block diagram (Note)Please the capacitors for AVDD ,BIAS ,LNF ,EV3 pins close to each. Please the capacitors of X’tal for XIN ,XOUT pins close to each. ◇Pin Functional Descriptions Pin name AVDD AVSS BIAS MREG MICIN LNF LINEOUT EVROUT SPIN SPNEG SPPOS SPVDD SPVSS VVDD VVSS VIN VOUT UNREG CPOUT FBREG EV3 BATT XIN XOUT BIAS AVDD LPF - VVDD MREG function Analog power supply Analog ground Bias Regulator for MIC MIC input MIC NF input LINE output EVR output SP input SP negative output SP positive output SP power supply SP ground Video driver power supply Video driver ground Video driver input Video driver output UNREG voltage input Step up pulse output Step up voltage output Regulator output Back up power supply Crystal oscillation input Crystal oscillation output Pin name RTCGND RESETIN UVLO RESETOUT ACT PWRSW0 PWRSW1 PWRCTRL0 PWRCTRL１ PMG_VBAT_DA PWRSW_STATE DVDD IOVDD FCLK BCLK DAIN ADOUT ＭCLK DVSS SCLK CSB SDATA SOUT TEST REV. A function GND for RTC RESET voltage detective output UVLO voltage detective input Reset output ACT input Power SW0 input Power SW1 input Power control0 output Power control1 output Voltage monitor output Power SW output Digital power supply Digital IO power supply CODEC frame clock input CODEC bit clock input CODEC DA serial data input CODEC DA serial data output Master clock input Digital GND Serial clock input Serial chip select input Serial data input Serial data output Test terminal 4/4 ◇Pin assignment(Bottom view)・External dimension Bottom View G RTCGND XIN XOUT VVDD RESETOUT SOUT DVDD F PWRSW1 BATT VVSS VOUT ACT PWRSW_STATE DAIN E PWRCTRL0 PWRSW0 TEST VIN DVSS ADOUT MCLK D EV3 RESETIN SDATA FCLK BCLK C UVLO UNREG FBREG SPIN LNF SCLK IOVDD SPPOS SPVSS LINEOUT BIAS AVDD CSB CPOUT SPVDD SPNEG EVROUT MREG MICIN AVSS 1 2 3 4 5 6 7 76294 Lot No. B A PWRCTRL1 PMG_VBAT_DA Figure 2. pin assignment(Bottom view) Figure 3. External dimension (Unit：ｍｍ) PKG：VBGA048W040 Drawing No.：EX873-6001 ◇Caution （１） About absolute maximum rating When the absolute maximum rating such as the applied voltage and the ranges of the operating temperature is exceeded, LSI might be destroyed. Please apply neither voltage nor the temperature that exceeds the absolute maximum rating. Please execute physical measures for safety such as fuse when it is thought to exceed the absolute maximum rating, and examine it so that the condition to exceed the absolute maximum rating is not applied to LSI. （２） About GND Voltage In any state of operation must be the lowest voltage about the voltage of the terminal GND. Please actually confirm the voltage of each terminal is not a voltage that is lower than the terminal GND including excessive phenomenon. （３） About design of overheating malfunction preventive circuit Please design overheating malfunction preventive circuit with an enough margin in consideration of a permissible loss in the state of using actually. （４） About the short between terminals and the mounting by mistake Please note the direction and the gap of position of LSI enough about LSI when you mount on the substrate. LSI might be destroyed when mounting by mistake and energizing. Moreover, LSI might be destroyed when short-circuited by entering of the foreign substances between the terminal and GND, between terminals, between the terminal and the power supply of LSI. （５） About operation in strong electromagnetic field Use in strong electromagnetic field has the possibility of malfunctioning and evaluate it enough, please. （６） Please note not to be beyond the package permissible range, When SPVDD is set. REV. A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. 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