CY2941x/CY2942x High-Performance Programmable Oscillators High-Performance Programmable Oscillators Features ■ Functional Description Low-noise PLL for integrated crystal applications 2 ■ Differential Clock Output: re-configurable through I C ■ Output frequency support from 15 MHz to 2.1 GHz ■ Fractional N PLL with fully integrated VCO ■ Works on an integrated fixed frequency crystal ■ LVPECL, LVDS, HCSL, and CML output standards available ■ Compatible with 3.3 V, 2.5 V, and 1.8 V supply ■ 150 fs typical integrated jitter performance (12 kHz to 20 MHz frequency offsets) for outputs greater than 150 MHz ■ VCXO functionality provided with tunable Total Pull Range (TPR) from ±50 ppm to ±275 ppm ■ 8-pin LCC package 7.0 × 5.0 (CY2941x) or 5.0 × 3.2 (CY2942x) mm The CY2941x/CY2942x is a programmable PLL-based crystal oscillator solution with flexible output frequency options. It is field or factory-programmable for any output frequency between 15 MHz and 2.1 GHz. Other frequency options can be configured with the I2C interface. Using advanced design technology, it provides excellent jitter performance across the entire output frequency range, working reliably at supply voltages from 1.8 V to 3.3 V for ambient temperatures from –40 °C to +105 °C. This makes it ideally suited for communications applications (for example, OTN, SONET/SDH, xDSL, GbE, networking, wireless infrastructure), test and instrumentation applications, and high-speed data converters. Additionally, the VCXO function enables use of the CY2941x/CY2942x series in applications requiring a clock source with voltage control, and in discrete clocking solutions for synchronous timing applications. The CY2941x/CY2942x device configuration can be created using ClockWizard 2.1. For programming support, contact Cypress technical support or send an email to [email protected]. For a complete list of related documentation, click here. Logic Block Diagram VDD CLK_P XOUT XO Oscillator Fractional - N Output Dividers LC VCO Based PLL Output Drivers CLK_N XIN Digital Configuration and Control NVM I2C Interface SCL Cypress Semiconductor Corporation Document Number: 001-97768 Rev. *H • ADC + Digital Filtering Pathway (for VCXO Function) SDA 198 Champion Court VC • OE GND San Jose, CA 95134-1709 • 408-943-2600 Revised May 31, 2017 CY2941x/CY2942x Contents Pin Diagrams ..................................................................... 3 Pin Description ................................................................. 3 Functional Overview ........................................................ 4 Programmable Features .............................................. 4 Architecture Overview ................................................. 4 Internal State Diagram ................................................ 4 Small/Large Change .................................................... 5 Programming Support ................................................. 5 Programmable OE Polarity .......................................... 5 Programmable VCXO .................................................. 5 Power Supply Sequencing .......................................... 5 I2C Interface ................................................................ 5 Memory Map ............................................................... 5 Absolute Maximum Ratings ............................................ 6 Recommended Operating Conditions ............................ 6 DC Electrical Specifications ............................................ 6 DC Specifications for LVDS Output ................................ 7 DC Specifications for LVPECL Output ........................... 7 DC Specifications for CML Output .................................. 7 DC Specifications for HCSL Output ................................ 7 VCXO Specific Parameters .............................................. 8 Document Number: 001-97768 Rev. *H AC Electrical Specifications for LVPECL, LVDS, CML Outputs ................................... 9 AC Electrical Specifications for HCSL Output ............. 10 Timing Parameters ......................................................... 10 Phase Jitter Characteristics .......................................... 11 I2C Bus Timing Specifications ...................................... 11 Frequency Stability ........................................................ 12 Voltage and Timing Definitions ..................................... 13 Phase Noise Plots .......................................................... 15 Ordering Information ...................................................... 18 Ordering Code Definitions ......................................... 18 Package Diagrams .......................................................... 19 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC® Solutions ...................................................... 23 Cypress Developer Community ................................. 23 Technical Support ..................................................... 23 Page 2 of 23 CY2941x/CY2942x OE 1 NC 2 GND 3 7 VDD VC 1 5 CLKP OE 2 4 CLKN GND 3 7 8 SCL 8 CY29412, CY29422 6 6 VDD 5 CLKP 4 CLKN SCL CY29411, CY29421 SDA SDA Pin Diagrams Pin Description Name Pin Number Description CY29411/CY29421 (8-pin LCC) OE 1 Output Enable input NC 2 Not connected GND 3 Supply ground CLKN 4 Complement clock output CLKP 5 True clock output VDD 6 Power supply SDA 7 Serial data input/output SCL 8 Serial clock input for I2C VC[1] 1 Input voltage for VCXO OE 2 Output enable input CY29412/CY29422 (8-pin LCC) GND 3 Supply ground CLKN 4 Complement clock output CLKP 5 True clock output VDD 6 Power supply SDA 7 Serial data input/output SCL 8 Serial clock input for I2C Note 1. If VC is unused, do not leave it floating; connect it to VDD or GND. Document Number: 001-97768 Rev. *H Page 3 of 23 CY2941x/CY2942x Programmable Features Figure 2 shows the conceptual internal memory structure that consists of Frequency Profile and Common Device Configuration settings. Table 1. Programmable Features Figure 2. Memory Structure Functional Overview Feature Details Frequency Tuning Frequency for the PLL Function OE Polarity, I2C Address VCXO Function Oscillator tuning (load capacitance values) VDD I2C Power Supply VDD (1.8, 2.5, or 3.3 V) Enable/Disable VCXO VCXO Output Standard Kv Polarity Common Device Configurations LOCK TPR Input Reference Modulation Bandwidth Output Standard Frequency Information FS0 Profile LVPECL, LVDS, HCSL, CML Description of Settings for the Memory Structure Architecture Overview The CY2941x/CY2942x devices are high-performance programmable PLL crystal oscillators supporting multiple functions and multiple output standards. The device has internal one-time programmable (OTP) nonvolatile memory (NVM) that can be partitioned into Common Device Configurations and Output frequency-related information (see Figure 2). The Common Device Configurations do not change with output frequency and consist of chip power supply, OE polarity, I2C device address, input reference, output standard, and VCXO. The CY2941x/CY2942x devices also contain volatile memory (shown as “NVMCopy” in Figure 1) that stores an exact copy of the NVM at the release of reset on Power ON. The Chip settings depend on the contents of the volatile memory and the output frequency depends on the configurations stored in it, as explained in Figure 1. The volatile memory can be accessed through the I2C bus and modified. Figure 1. NVM and Volatile Memory Structure Program eFuse Reset “eFuse” Non‐Volatile “NVMCopy” Volatile I2C Document Number: 001-97768 Rev. *H Chip Settings ■ FS0: Contains frequency information ■ VCXO Function: Contains parameters related to VCXO functionality, enable/disable, TPR, modulation bandwidth and Kv (Slope for VC vs. Frequency) information ■ VDD: 1.8-/2.5-/3.3-V range information ■ I2C address: I2C address (programmable) information ■ Output Standard: LVPECL, LVDS, HCSL or CML ■ LOCK: 2-bit pattern to indicate NVM lock ■ Input Reference: Information is Fixed, cannot be modified by the user Internal State Diagram The CY2941x/CY2942x contains a state machine which controls the device behavior. The state machine loads the “eFuse” contents to “NVMCopy” after reset as indicated in the Figure 3 on page 5. The state machine enters one of the following states: “Command Wait state” or “Active state” according to the value of LOCK. In the “Command Wait state” state, user may access all the registers and read/write the “NVMCopy” contents. The following commands can be used in the “Command Wait state”: The LOCK state is determined by a 2-bit pattern: 00, 01, 10, or 11. When the Power rail reaches a value within the specified range, the device comes out of the Reset state. The blank device has LOCK=”00” (NVM not locked) in Figure 3 on page 5 so that it goes to the “Command Wait state” after coming out of Reset. The State machine will wait for the following commands: ■ Write to volatile memory ■ Program Non-Volatile memory (NVM) ■ Loop Lock Page 4 of 23 CY2941x/CY2942x Programmable VCXO Figure 3. State Diagram Release Reset on Power Copy “eFuse” to “NVMCopy” LOCK = "10" or "01" LOCK=“10” The device incorporates a proprietary technique for modulating frequency by modifying the VCO frequency based on the VC control voltage. The pull profile is linear and accurate compared to pulling the crystal reference. Also, the VCXO characteristics are very stable and do not vary over temperature, supply voltage, or process variations. LOCK=“00” Kv (Slope for frequency vs. VC), TPR VC bandwidth, and VCXO on/off are programmable. Loop Lock Power Supply Sequencing Active state Output Clock Command Wait State Small Change Large Change When the LOCK is programmed to "10" or "01", the device will go to the “Active state” and the device will perform at the programmed frequency. In the “Command Wait state”, you can configure the device with or without writing to the NVM. The use case scenarios are as follows: Test output frequency ❐ Write to volatile memory and selectively write to NVM if needed ❐ Proceed to Loop Lock can optionally be done for testing purpose In the NVM locked state, the NVM cannot be reprogrammed. If needed, the output frequency may be changed using Large or Small change commands. ■ Small/Large Change Small Change indicates that the frequency is changing within ±500 ppm. The frequency information will be loaded through I2C and the output frequency will change without any glitch from its original frequency to the new frequency. For more information, see AC Electrical Specifications for LVPECL, LVDS, CML Outputs. Large Change indicates that the frequency is changing more than ±500 ppm and is done through the I2C interface.The device will recalibrate and reconfigure the PLL. The output will be stable after completion of this process. Programming Support The CY2941x/CY2942x is a software-configurable solution, in which Cypress provides programming software to users to configure the programmable features of the device based on their requirements. Programmable OE Polarity The CY2941x/CY2942x contains a bit for OE polarity setting (default is active low). You can choose active-high or active-low polarity for the OE function. The output will be disabled when OE is deasserted. Document Number: 001-97768 Rev. *H The CY2941x/CY2942x does not require any specific sequencing for startup. Startup requires a monotonic VDD ramp specified in the datasheet. After the ramp up, VDD has to be maintained within the limits specified for it in the Recommended Operating Conditions. Brownout detection and protection has to be implemented elsewhere in the system. Other input signals can power up earlier or later than VDD, there is no timing requirement for the input signals with reference to VDD. The device will operate normally when all the input signals are settled to the configured state. I2C Interface The CY2941x/CY2942x supports two-wire serial interface and I2C in Fast Mode (400 kbps) and 7-bit addressing. The device address is programmable and is 55h by default. It supports single-byte access only. The first I2C access to the device has to be 5 ms (minimum) after VDD reaches its minimum specified voltage. Memory Map Table 2. Common Configurations Memory Address 50h–57h Descriptions Device configurations Table 3. FS0: Frequency Configurations Memory Address Descriptions 10h DIVO 11h DIVO, DIVN_INT 12h ICP,DIVN_INT, PLL_MODE 13h DIVN_FRAC_L 14h DIVN_FRAC_M 15h DIVN_FRAC_H Table 4. Misc information Memory Address 00h (Read only) D4h–D6h Description Device ID (= 51h) User configurable information The user must write all the contents created by the Configuration tool. Partial updates to the device is not allowed. Access to locations other than those described here may cause fatal error in device operation. Page 5 of 23 CY2941x/CY2942x Programming voltage .........................................2.5V ±0.1 V Absolute Maximum Ratings Exceeding maximum ratings[2] may shorten the useful life of the device. User guidelines are not tested. Supply Current for eFuse Programming ..................... 50 mA Data retention at TJ = 100 C ...............................> 10 years Supply voltage to ground potential .............–0.5 V to + 3.8 V Maximum programming cycles ............................................1 Input voltage ...............................................–0.5 V to + 3.8 V ESD HBM (JEDEC JS-001-2012) ............................ 2000 V Storage temperature (non-condensing) ... –55 C to +150 C ESD MM (JEDEC JESD22-A115B) ............................. 200 V Junction temperature ............................... –40 C to +125 C ESD CDM (JEDEC JESD22-C101E) .......................... 400 V Programming temperature ........................... 0 C to +125 C Latch-up current ..................................................... ±140 mA Recommended Operating Conditions Parameter Min Max Core supply voltage, 1.8-V operating range, 1.8 V ± 5% 1.71 1.89 Core supply voltage, 2.5-V operating range, 2.5 V ± 10% 2.25 2.75 Core supply voltage, 3.3-V operating range, 3.3 V ± 10% 2.97 3.63 TA Ambient temperature –40 +105 °C UL-94 Flammability rating. V-0 at 1/8 in. – 10 ppm fRES Frequency resolution – 2 ppb TPLLHOLD PLL Hold Temperature Range – 125 C Min Typ Max Unit VDD Description Unit V DC Electrical Specifications Parameter IDD Description Test Conditions Supply current, LVPECL VDD = 3.3 V/2.5 V, 50 to VTT (VDD – 2.0 V), with common mode current – 93 106 Supply current, LVPECL VDD = 3.3 V/2.5 V, 50 to VTT (VDD – 2.0 V), without common mode current[3] – 81 94 Supply current, LVDS VDD = 3.3 V/2.5 V/1.8 V, 100 between CLKP and CLKN – 69 81 Supply current, HCSL VDD = 3.3 V/2.5 V/1.8 V, 33 and 49.9 to GND – 80 93 Supply current, CML VDD = 3.3 V/2.5 V/1.8 V, 50 to VDD – 73 86 mA Supply current, PLL only VDD = 3.3 V/2.5 V/1.8 V – 59 70 IIH Input high current Logic input, Input = VDD – 30 50 A IIL Input low current Logic input, Input = GND – 30 50 A VIH[4] Input high voltage OE, SCL, SDA logic level = 1 0.7 × VDD – – V VIL[4] Input low voltage OE, SCL, SDA logic level = 0 VIN Input voltage level All input, relative to GND RP Internal pull-up resistance RD Internal pull-down resistance – – 0.3 × VDD V –0.5 – 3.8 V OE, configured active High – 200 – k OE, configured active Low – 200 – k Notes 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or at any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to Absolute-Maximum-Rated conditions for extended periods may affect device reliability or cause permanent device damage. 3. In ClockWizard 2.1, setting the output standard to LVPECL2 configures the output to “LVPECL without common mode current”. Refer to AN210253 for LVPECL terminations for different use case configurations. 4. I2C operation applicable for VDD of 1.8 V and 2.5 V only. Document Number: 001-97768 Rev. *H Page 6 of 23 CY2941x/CY2942x DC Specifications for LVDS Output (VDD = 1.8-V, 2.5-V, or 3.3-V range) Parameter VOCM [5] Description Conditions Min Typ Max Units 1.125 1.200 1.375 V – – – 50 mV Output off, VOUT = 0.75 V to 1.75 V –20 – 20 A Output common-mode voltage VDD = 2.5-V or 3.3-V range VOCM Change in VOCM between complementary output states IOZ Output leakage current DC Specifications for LVPECL Output (VDD = 2.5-V or 3.3-V range, with common mode current) Min Typ Max Units VOH Parameter Output high voltage Description R-term = 50 to VTT (VDD – 2.0 V) Conditions VDD – 1.165 – VDD – 0.800 V VOL Output low voltage R-term = 50 to VTT (VDD – 2.0 V) VDD – 2.0 – VDD – 1.55 V DC Specifications for CML Output (VDD = 1.8-V, 2.5-V or 3.3-V range) Parameter Description Conditions Min Typ Max Units VOH Output high voltage R-term = 50 to VDD VDD – 0.085 VDD – 0.01 VDD V VOL Output low voltage R-term = 50 to VDD VDD – 0.6 VDD – 0.4 VDD – 0.32 V DC Specifications for HCSL Output (VDD = 1.8-V, 2.5-V, or 3.3-V range) Parameter Description Conditions Min Typ Max Units VMAX[6] Max output high voltage Measurement taken from single-ended waveform – – 1150 mV VMIN[6] Min output low voltage Measurement taken from single-ended waveform –300 – – mV VOHDIFF Differential output high voltage Measurement taken from differential waveform 150 – – mV VOLDIFF Differential output low voltage Measurement taken from differential waveform – – –150 mV VCROSS[6] Absolute crossing point voltage Measurement taken from single-ended waveform 250 – 600 mV VCROSSDELTA[6] Variation of VCROSS over all rising Measurement taken from clock edges single-ended waveform – – 140 mV Notes 5. Requires external AC coupling for VDD = 1.8-V range, as indicated in Figure 9. 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 001-97768 Rev. *H Page 7 of 23 CY2941x/CY2942x VCXO Specific Parameters Parameter [7] Description Condition Min Typ Max Units VC range 0.1 × VDD to 0.9 × VDD ±50 – ±275 ppm – 5 % TPR Total Pull Range KBSL Best-fit Straight Line (BSL) linearity Deviation from BSL line –5 KINC Incremental linearity Kv slope deviation –10 – 10 % KBW Bandwidth of Kv modulation Programmable 5 10 20 kHz KRANGE Voltage range Permissible voltage range 0 – VDD V VDD configuration = 1.8 V – 0.9 – V Nominal center VC control voltage VDD configuration = 2.5 V – 1.25 – V VDD configuration = 3.3 V – 1.65 – V Input resistance for VC – 5 – – M Input voltage range Linearity guaranteed range 0.1 × VDD – 0.9 × VDD V VCTYP RVCIN [8] VRANGE Notes 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. RVCIN is 100% tested. Document Number: 001-97768 Rev. *H Page 8 of 23 CY2941x/CY2942x AC Electrical Specifications for LVPECL, LVDS, CML Outputs (VDD = 3.3 V and 2.5 V for LVPECL, with common mode current, and VDD = 3.3 V, 2.5 V, and 1.8 V for LVDS and CML outputs) Parameter[9] Description Details/Conditions Min Typ Max Unit Clock Output Frequency LVPECL, CML, LVDS output standards 15 – 2100 MHz LVPECL Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for PECL outputs. – – 350 ps CML Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for CML outputs. – – 350 ps LVDS Output Rise/Fall Time 20% to 80% of AC levels. Measured at 156.25 MHz for LVDS outputs. – – 350 ps tODC Output Duty Cycle Measured at differential 50% level, 156.25 MHz. 45 50 55 % VP LVDS output differential peak 15 MHz to 700 MHz 247 – 454 mV VP LVDS output differential peak 700 MHz to 2100 MHz 150 – 454 mV VP Change in VP between complementary output states – – 50 mV 450 – – mV fOUT tRF fOUT = 15 MHz to 325 MHz VP VP – LVPECL output differential peak fOUT = 325 MHz to 700 MHz VP 350 – – mV fOUT = 700 MHz to 2100 MHz 250 – – mv VP CML output differential peak fOUT = 15 MHz to 700 MHz 250 – 600 mV VP CML output differential peak fOUT = 700 MHz to 2100 MHz 200 – 600 mV tCCJ Cycle to Cycle Jitter pk, measured at differential signal, 156.25 MHz, over 10k cycles, 100 MHz–130 MHz crystal – – 50 ps tPJ Period Jitter pk-pk, measured at differential signal, 156.25 MHz, over 10k cycles, 100 MHz–130 MHz crystal – – 50 ps JRMS RMS Phase Jitter fOUT = 156.25 MHz, 12 kHz–20 MHz offset, non-VCXO mode – 150 250 fs Non-VCXO Mode PN1k Phase Noise, 1 kHz Offset 100-130 MHz crystal reference, fOUT = 156.25 MHz – – -113 dBc/Hz PN10k Phase Noise, 10 kHz Offset 100-130 MHz crystal reference, fOUT = 156.25 MHz – – -127 dBc/Hz PN100k Phase Noise, 100 kHz Offset 100-130 MHz crystal reference, fOUT = 156.25 MHz – – -135 dBc/Hz PN1M Phase Noise, 1MHz Offset 100-130 MHz crystal reference, fOUT = 156.25 MHz – – -144 dBc/Hz PN10M Phase Noise, 10 MHz Offset 100-130 MHz crystal reference, fOUT = 156.25 MHz – – –152 dBc/Hz PN-SPUR Spur At frequency offsets equal to and greater than the update rate of the PLL – – –65 dBc/Hz Note 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. Document Number: 001-97768 Rev. *H Page 9 of 23 CY2941x/CY2942x AC Electrical Specifications for HCSL Output Parameter [10] Min Typ Max Units fOUT Output frequency Description HCSL Test Conditions 15 – 700 MHz ER Rising edge rate Measured taken from differential waveform, –150 mV to +150 mV 0.6 – 5.7[11] V/ns EF Falling edge rate Measured taken from differential waveform, –150 mV to +150 mV 0.6 – 5.7[11] V/ns tSTABLE Time before voltage ring back (VRB) is allowed Measured taken from differential waveform, –150 mV to +150 mV 500 – – ps R-F_MATCHING Rise-Fall matching Measured taken from single-ended waveform, rising edge rate to falling edge rate matching, 100 MHz –100 – 100 ps tDC Output duty cycle Measured taken from differential waveform, fOUT = 100 MHz 45 – 55 % tCCJ Cycle to Cycle Jitter Measured taken from differential waveform, 100 MHz – – 50 ps JRMSPCIE Random jitter, PCIE Specification 3.0 100 MHz–130 MHz crystal – – 1 ps (RMS) Min Max Unit 0.01 3000 ms Timing Parameters Parameter [10] Description tPU Supply ramp time (0.5 V to VDD(min)). Power ramp must be monotonic. tWAKEUP Time from minimum specified power supply to < ±0.1 ppm accurate output frequency clock – 10 ms tOEEN Time from OE edge to output enable – 2.5 ms tOEDIS Time for OE edge to output disable – 10 s tFSMALL Frequency change time for small trigger ( ±500 ppm) – 400 s tFLARGE Frequency change time for large trigger (> ±500 ppm) – 2.5 ms Notes 10. Parameters are guaranteed by design and characterization. Not 100% tested in production. 11. Edge rates are higher than 4 V/ns due to jitter performance requirements. Document Number: 001-97768 Rev. *H Page 10 of 23 CY2941x/CY2942x Phase Jitter Characteristics 12 kHz to 20 MHz Integration Bandwidth Parameter[12] Description Condition Min Typ Max Units Non VCXO functionality JRMS RMS jitter FOUT = 644.53 MHz – 110 – fs JRMS RMS jitter FOUT = 622.08 MHz – 120 – fs JRMS RMS jitter FOUT = 156.25 MHz – 145 – fs JRMS RMS jitter FOUT = 2.105 GHz – 145 – fs Modulation bandwidth = 10 kHz, VDD = 3.3 V, FOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 37.9 ppm/V – 151 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 117.4 ppm/V – 158 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 208.3 ppm/V – 170 – fs Modulation bandwidth = 10 kHz, VDD = 2.5 V, FOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 50 ppm/V – 152 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 155 ppm/V – 160 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 275 ppm/V – 175 – fs Modulation bandwidth = 10 kHz, VDD = 1.8 V, FOUT = 622.08 MHz JRMS RMS jitter TPR = 50 ppm, Kv = 69.4 ppm/V – 153 – fs JRMS RMS jitter TPR = 155 ppm, Kv = 215.3 ppm/V – 166 – fs JRMS RMS jitter TPR = 275 ppm, Kv = 381.9 ppm/V – 190 – fs Min Typ Max Units – – 400 kHz I2C Bus Timing Specifications Parameter [12, 13] Description fSCL SCL clock frequency tHD:STA Hold time START condition 0.6 – – s tLOW Low period of SCL 1.3 – – s tHIGH High period of SCL 0.6 – – s tSU:STA Setup time for a repeated START condition 0.6 – – s tHD:DAT Data hold time 0 – – s tSU:DAT Data setup time 100 – – ns tR Rise time – – 300 ns tF Fall time – – 300 ns tSU:STO Setup time for STOP condition 0.6 – – s tBUF Bus-free time between STOP and START conditions 1.3 – – s Notes 12. Parameters are guaranteed by design and characterization. Not 100% tested in production. 13. I2C operation applicable for VDD of 1.8 V and 2.5 V only. Document Number: 001-97768 Rev. *H Page 11 of 23 CY2941x/CY2942x Frequency Stability Parameter Description Test Conditions Min Typ Max Units fTOLERANCE Frequency Tolerance VDD = min to max, TA = +25 °C –20 – +20 ppm fTC Temperature Characteristics VDD = min to max, TA = –40 °C to +85 °C –20 – +20 ppm fTC Temperature Characteristics VDD = min to max, TA = –40 °C to +105 °C –30 – +30 ppm fAGE Frequency Aging –5 – +5 ppm/year Document Number: 001-97768 Rev. *H Page 12 of 23 CY2941x/CY2942x Voltage and Timing Definitions Figure 4. Differential Output Definitions tDC = tPW / tPERIOD VPP OUT-N VDD – 2 V VDD 50 tPERIOD 80% VA 80% 20% 20% tR VB tF BUF tPW OUT-P Figure 7. Output Termination Circuit VOCM = (VA + VB) / 2 50 50 TP 50 TP LVPECL Figure 5. Output Enable/Disable Timing VDD VDD 50 Clock New Clock Clock OE FSx 50 TP 50 TP 50 100 TP 50 TP BUF Original Clock 50 tOEDIS tOEEN CML t VDD Figure 6. Power Ramp and PLL Lock Time VDD(min) BUF Supply Voltage tPU 0.5 V twakeup Stable Output LVDS Output VDD 5” BUF 33 50 33 49.9 TP 2 pF 50 TP 2 pF 49.9 HCSL Figure 8. LVDS Termination for 1.8 V[14] VDD VDD 0.1 µF 50 Ω 50 Ω Transmitter VOCM Receiver 50 Ω 50 Ω 0.1 µF Note 14. The termination circuit shown in this figure is specific to the LVDS output standard for VDD =1.8-V operation. This needs AC coupling (100-nF series capacitor). The 50-ohm termination resistors along with the bias voltage (VOCM) is required to be set at the destination circuit as shown in the figure. Document Number: 001-97768 Rev. *H Page 13 of 23 CY2941x/CY2942x Figure 11. HCSL: Differential Measurement Points for Rise and Fall Time Figure 9. HCSL: Single-ended Measurement Points for Absolute Crossing Point VMAX = 1.15 V REFCLK ‐ VCROSS MAX = 550 mV Rising Edge Rate Falling Edge Rate VIH = +150 mV 0.0 V VIL = ‐150 mV VCROSS MIN = 250 mV REFCLK + VMIN = ‐0.30 V REFCLK + minus Figure 10. HCSL: Single-ended Measurement Points for Delta Crossing Point Figure 12. HCSL: Differential Measurement Points for Ringback REFCLK ‐ TSTABLE VCROSS DELTA = 140 mV VRB REFCLK + VIH = +150 mV VRB = +100 mV VRB = ‐100 mV VIL = ‐150 mV REFCLK + minus VRB TSTABLE Figure 13. I2C Bus Timing Specifications SDA tf tLOW tr tSU;DAT tf tHD;STA tr tBUF SCL tHD;STA S tHD;DAT Document Number: 001-97768 Rev. *H tHIGH tSU;STA tSU;STO Sr P S Page 14 of 23 CY2941x/CY2942x Phase Noise Plots Figure 14. Typical Phase Noise at 156.25 MHz (12 kHz–20 MHz) Document Number: 001-97768 Rev. *H Page 15 of 23 CY2941x/CY2942x Figure 15. Typical Phase Noise at 622.08 MHz (12 kHz–20 MHz) Document Number: 001-97768 Rev. *H Page 16 of 23 CY2941x/CY2942x Figure 16. Typical Phase Noise at 644.53 MHz (12 kHz–20 MHz) Document Number: 001-97768 Rev. *H Page 17 of 23 CY2941x/CY2942x Ordering Information Ordering Code Configuration CY29411FLXIT Field-programmable [15] Package Description 8-pin LCC 7.0 × 5.0 mm – Tape and Reel Product Flow Industrial, –40 °C to +105 °C CY29411LXIxxxT Factory-configured 8-pin LCC 7.0 × 5.0 mm – Tape and Reel Industrial, –40 °C to +105 °C CY29412FLXIT Field-programmable 8-pin LCC 7.0 × 5.0 mm – Tape and Reel Industrial, –40 °C to +105 °C CY29412LXIxxxT Factory-configured[15] 8-pin LCC 7.0 × 5.0 mm – Tape and Reel Industrial, –40 °C to +105 °C CY29421FLXIT Field-programmable Industrial, –40 °C to +105 °C [15] 8-pin LCC 5.0 × 3.2 mm – Tape and Reel CY29421LXIxxxT Factory-configured 8-pin LCC 5.0 × 3.2 mm – Tape and Reel Industrial, –40 °C to +105 °C CY29422FLXIT Field-programmable 8-pin LCC 5.0 × 3.2 mm – Tape and Reel Industrial, –40 °C to +105 °C CY29422LXIxxxT Factory-configured[15] 8-pin LCC 5.0 × 3.2 mm – Tape and Reel Industrial, –40 °C to +105 °C Ordering Code Definitions CY 294xx X - LXI xxx T T = Tape and Reel, Blank = Bulk Customer Part Configuration Code Package Type: LX(LCC), Pb-Free: X and Industrial: I Configuration: F = Field Programmable, Blank = Factory Configured Part Number: 294xx = 29412 or 29422 Company ID: CY = Cypress Note 15. These are factory-programmed customer-specific part numbers. Contact your local Cypress FAE or sales representative for more information. Document Number: 001-97768 Rev. *H Page 18 of 23 CY2941x/CY2942x Package Diagrams Figure 17. 8-pin Ceramic LCC (5.0 × 7.0 × 1.75 mm) Package Outline, 002-10174 002-10174 *A Document Number: 001-97768 Rev. *H Page 19 of 23 CY2941x/CY2942x Figure 18. 8-pin Ceramic LCC (3.2 × 5.0 × 1.45 mm) Package Outline, 002-10273 002-10273 *A Document Number: 001-97768 Rev. *H Page 20 of 23 CY2941x/CY2942x Acronyms Document Conventions Table 5. Acronyms Used in this Document Units of Measure Acronym Description Table 6. Units of Measure AC alternating current ADC analog-to-digital converter °C Degrees Celsius BCL best-fit straight line fs femtoseconds CML current mode logic GHz gigahertz DC direct current k kilohms ESD electrostatic discharge kHz kilohertz FS frequency select MHz megahertz HCSL high-speed current steering logic M megaohms I2C inter-integrated circuit µA microamperes JEDEC Joint Electron Device Engineering Council µm micrometer LDO low dropout (regulator) µs microseconds LVCMOS low voltage complementary metal oxide semiconductor µW microwatts LVDS low-voltage differential signals mA milliamperes LVPECL low-voltage positive emitter-coupled logic mm millimeter NVM non-volatile memory m milliohms OE output enable ms milliseconds PLL phase-locked loop mV millivolts POR power-on reset nH nanohenry PSoC® Programmable System-on-Chip ns nanoseconds QFN quad flat no-lead ohms RMS root mean square % percent SCL serial I2C clock SDA serial I2C data VCXO voltage controlled crystal oscillator VRB voltage ring back XTAL crystal OTP one time programmable Document Number: 001-97768 Rev. *H Symbol Unit of Measure pF picofarads ps picoseconds ppm parts per million ppb parts per billion V volts Page 21 of 23 CY2941x/CY2942x Document History Page Document Title: CY2941x/CY2942x, High-Performance Programmable Oscillators Document Number: 001-97768 Rev. ECN No. Submission Date Orig. of Change *C 5320399 07/18/2016 MGPL Description of Change Changed status from Preliminary to Final. *D 5429121 09/07/2016 MGPL Updated Absolute Maximum Ratings: Added “Supply Current for eFuse Programming”. Replaced “> 2000 V” with “2000 V” in value corresponding to “ESD HBM”. Replaced “> 200 V” with “200 V” in value corresponding to “ESD MM”. Replaced “>500V” with “400 V” in value corresponding to “ESD CDM”. Updated to new template. *E 5518357 11/15/2016 MGPL/ PSR Added Figure 8. *F 5613574 02/03/2017 PSR Added links to ClockWizard 2.1 and technical support, and added reference to related documentation in Functional Description. Updated LVPECL specs in DC Electrical Specifications. Added note clarifying voltage range in AC Electrical Specifications for LVPECL, LVDS, CML Outputs. Updated Ordering Information. *G 5682054 04/03/2017 PSR Updated the template. Deleted VDDO references. Added Clock Tree Services to Sales, Solutions, and Legal Information. *H 5757596 05/31/2017 PSR Updated Cypress logo and Sales information. Updated VCXO Specific Parameters. Document Number: 001-97768 Rev. *H Page 22 of 23 CY2941x/CY2942x Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-97768 Rev. *H Revised May 31, 2017 Page 23 of 23