DA9062 PMIC for applications requiring up to 8.5 A General Description DA9062 is a power management integrated circuit (PMIC) optimized for supplying systems with single- and dual-core processors, I/O, DDR memory, and peripherals. It targets mobile devices, medical equipment, IVI systems, and FPGA based applications. DA9062 features four buck converters providing a total current of 8.5 A. High efficiency is achieved over a wide load range by using automatic Pulse Frequency Modulation (PFM) mode. All power switches are integrated, therefore, external Schottky diodes are not required. Furthermore, lowprofile inductors can be used with DA9062. Two of the buck converters can be used in a dual-phase configuration, and one can be used as a DDR VTT supply. The four LDO regulators with programmable output voltage provide up to 300 mA. Dynamic Voltage Control (DVC) allows dynamic control of DA9062 supply voltages according to the 2 operating point of the system. It is controlled by writing directly to the registers using the I C compatible 2-wire interface or the GPIOs. DA9062 features a programmable power sequencer that handles start-up and shutdown sequences. Power mode transitions can be triggered with software control, GPIOs, or with the on-key. Several types of on-key presses can be detected to trigger different power mode transitions. The Real-Time Clock (RTC), with an external 32 kHz crystal oscillator, provides time keeping and alarm functions. Additionally, the integrated watchdog timer monitors the system. Five GPIOs are able to perform system functions, including: keypad supervision, application wakeup, and timing-controlled external regulators/power switches or other ICs. DA9062 is also available as an automotive AEC-Q100 Grade 3 version. Key Features ■ Input voltage 2.8 V to 5.5 V ■ Four buck converters with dynamic voltage ■ Programmable power mode sequencer ■ System supply and junction temperature control: monitoring □ Buck1: 0.3 V to 1.57 V, 2.5 A □ Buck2: 0.3 V to 1.57 V, 2.5 A Watchdog timer ■ ■ (can be used in dual-phase configuration ■ with Buck1) ■ □ Buck3: 0.8 V to 3.34 V, 2 A ■ □ Buck4: 0.53 V to 1.8 V, 1.5 A ■ (can be used as DDR VTT supply) ■ ■ 3 MHz switching frequency (enables low profile inductors) ■ Four LDO regulators: □ LDO1: 0.9 V to 3.6 V, 100 mA □ LDO2, LDO3, LDO4: 0.9 V to 3.6 V, Five GPIOs Coin cell/super-capacitor charger Ultra-low power RTC with alarm 32 kHz oscillator with external crystal -40 °C to +125 °C junction temperature range 40-pin QFN 6 mm × 6 mm package, 0.5 mm pitch (exposed paddle) ■ Automotive AEC-Q100 Grade 3 version available 300 mA Applications ■ Single core application processors ■ Entry-level FPGAs Datasheet ■ e-Book readers ■ Entry-level car infotainment Revision 3.3 1 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Block Diagram CLDOCORE VDDCORE VDDIO VSYS Buck1 LDO1 CLDO1 VDD_BUCK1 LBUCK1 VDD_LDO2 CBUCK1 Optional LDO2 CLDO2 Buck2 VDD_LDO34 VDD_BUCK2 LBUCK2 LDO3 CLDO3 CBUCK2 LDO4 CLDO4 DA9062 Buck3 VDD_BUCK3 LBUCK3 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 CBUCK3 GPIO Buck4 VDD_BUCK4 LBUCK4 nONKEY nRESETREQ nRESET Control and status registers Power sequencer (VTT) WD CBUCK4 RTC Interrupt control nIRQ VREF CVREF IREF 2-Wire interface RIREF SCL SDA 32 kHz oscillator XTAL_IN BBAT charger VBBAT CVBBAT XTAL_OUT + - TP Figure 1: DA9062 Block Diagram Datasheet Revision 3.3 2 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Contents General Description ............................................................................................................................ 1 Key Features ........................................................................................................................................ 1 Applications ......................................................................................................................................... 1 Block Diagram ..................................................................................................................................... 2 Contents ............................................................................................................................................... 3 1 Package Information ..................................................................................................................... 6 1.1 Pin List................................................................................................................................... 6 1.2 Package Outline Drawing...................................................................................................... 8 2 Absolute Maximum Ratings ......................................................................................................... 9 3 Recommended Operating Conditions ......................................................................................... 9 4 Electrical Characteristics ........................................................................................................... 10 4.1 Digital I/O ............................................................................................................................ 10 4.2 Watchdog ............................................................................................................................ 11 4.3 2-Wire Interface................................................................................................................... 11 4.4 LDOs ................................................................................................................................... 13 4.4.1 LDO1.................................................................................................................... 13 4.4.2 LDO2, LDO3, LDO4............................................................................................. 14 4.4.3 LDOCORE ........................................................................................................... 15 4.5 Buck Converters .................................................................................................................. 16 4.5.1 Buck1, Buck2 ....................................................................................................... 16 4.5.2 Buck3 ................................................................................................................... 18 4.5.3 Buck4 ................................................................................................................... 20 4.6 Backup Battery Charger ...................................................................................................... 23 4.7 32 kHz Crystal Oscillator ..................................................................................................... 23 4.8 Internal Oscillator ................................................................................................................ 24 4.9 System Supply Voltage Supervision ................................................................................... 24 4.10 Junction Temperature Supervision ..................................................................................... 25 4.11 Current Consumption .......................................................................................................... 25 5 Typical Characteristics ............................................................................................................... 26 6 System Block Diagram ............................................................................................................... 29 6.1 DDR Power Management ................................................................................................... 30 7 Functional Description ............................................................................................................... 31 7.1 Control Signals .................................................................................................................... 31 7.1.1 nONKEY .............................................................................................................. 31 7.1.2 nRESETREQ ....................................................................................................... 31 7.1.3 nRESET ............................................................................................................... 32 7.1.4 nIRQ..................................................................................................................... 32 7.2 2-Wire Interface................................................................................................................... 32 7.2.1 Register Map Paging ........................................................................................... 33 7.2.2 Details of the 2-Wire Protocol .............................................................................. 33 7.3 GPIOs.................................................................................................................................. 35 7.3.1 GPI Functionality ................................................................................................. 36 7.3.2 GPO Functionality................................................................................................ 37 7.3.3 Alternate Functions .............................................................................................. 37 Datasheet Revision 3.3 3 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.3.4 GPIO Forwarding ................................................................................................. 38 7.3.5 Analog Functions ................................................................................................. 38 Dynamic Voltage Control .................................................................................................... 38 Regulator Voltage A And B Selection ................................................................................. 38 LDOs ................................................................................................................................... 39 7.6.1 Control ................................................................................................................. 39 7.6.2 Current Limit ........................................................................................................ 39 7.6.3 Output Pull-Down ................................................................................................. 39 Switching Regulators .......................................................................................................... 40 7.7.1 Control ................................................................................................................. 40 7.7.2 Output Voltage Slewing ....................................................................................... 40 7.7.3 Soft-Start .............................................................................................................. 40 7.7.4 Active Discharge .................................................................................................. 40 7.7.5 Peak Current Limit ............................................................................................... 40 7.7.6 Operating Mode ................................................................................................... 41 7.7.7 Half-Current Mode ............................................................................................... 41 7.7.8 Buck1 and Buck2 in Dual-Phase Mode ............................................................... 41 7.7.9 Buck4 in DDR Memory Bus Termination Mode ................................................... 41 Power Modes ...................................................................................................................... 42 7.8.1 NO-POWER Mode ............................................................................................... 43 7.8.2 RTC Mode ........................................................................................................... 43 7.8.3 RESET Mode ....................................................................................................... 43 7.8.4 POWERDOWN Mode .......................................................................................... 44 7.8.5 Power-Up, Power-Down, and Shutdown Sequences .......................................... 45 7.8.6 ACTIVE Mode ...................................................................................................... 45 Power Supply Sequencer.................................................................................................... 46 7.9.1 Sub-Sequences ................................................................................................... 47 7.9.2 Regulator Control ................................................................................................. 47 7.9.3 GPO Control ........................................................................................................ 48 7.9.4 Wait Step ............................................................................................................. 49 7.9.5 32 kHz Clock Output ............................................................................................ 49 7.9.6 Power-Down Disable ........................................................................................... 49 Junction Temperature Supervision ..................................................................................... 49 System Supply Voltage Supervision ................................................................................... 49 Backup Battery Charger ...................................................................................................... 50 Real-Time Clock (RTC) ....................................................................................................... 50 7.13.1 32 kHz Crystal Oscillator ..................................................................................... 50 Internal Oscillator ................................................................................................................ 51 Watchdog ............................................................................................................................ 51 8 Register Map ................................................................................................................................ 52 8.1 Register Page Control ......................................................................................................... 52 8.2 Overview ............................................................................................................................. 52 9 Application Information .............................................................................................................. 55 9.1 Component Selection .......................................................................................................... 55 9.1.1 Resistors .............................................................................................................. 55 9.1.2 Capacitors ............................................................................................................ 55 9.1.3 Inductors .............................................................................................................. 56 Datasheet Revision 3.3 4 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 9.2 9.1.4 Crystal .................................................................................................................. 56 9.1.5 Backup Battery .................................................................................................... 57 PCB Layout ......................................................................................................................... 57 9.2.1 General Recommendations ................................................................................. 58 9.2.2 LDOs and Switched Mode Supplies .................................................................... 58 9.2.3 32 kHz Crystal Oscillator ..................................................................................... 58 9.2.4 Optimising Thermal Performance ........................................................................ 58 10 Ordering Information .................................................................................................................. 59 Appendix A Register Descriptions .................................................................................................. 60 A.1 PAGE 0 ............................................................................................................................... 60 A.1.1 Page Control ........................................................................................................ 60 A.1.2 Power Manager Control and Monitoring .............................................................. 60 A.1.3 IRQ Events .......................................................................................................... 61 A.1.4 IRQ Masks ........................................................................................................... 62 A.1.5 System Control .................................................................................................... 63 A.1.6 GPIO Control ....................................................................................................... 66 A.1.7 Power Supply Control .......................................................................................... 69 A.1.8 RTC Calendar and Alarm .................................................................................... 74 A.2 PAGE 1 ............................................................................................................................... 77 A.2.1 Power Supply Sequencer .................................................................................... 77 A.2.2 Power Supply Control .......................................................................................... 82 A.2.3 BBAT Charger Control ......................................................................................... 86 A.3 PAGE 2 ............................................................................................................................... 87 A.3.1 Customer Trim and Configuration ....................................................................... 87 A.3.2 Customer Device Specific.................................................................................... 90 Revision History ................................................................................................................................ 93 Datasheet Revision 3.3 5 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 1 Package Information 1.1 Pin List Table 1: DA9062 Pin Description Pin No. Pin Name Type Table 2 Description Paddle GND GND Power grounds of the bucks, digital ground 1 VLDO1 AO LDO1 output voltage 2 VLDO2 AO LDO2 output voltage 3 VDD_LDO2 PS LDO2 supply 4 IREF AO Reference current 5 VREF AIO Reference voltage 6 XTAL_IN AI Crystal connection 7 VSS_ANA GND Analog ground 8 XTAL_OUT AO Crystal connection 9 VLDO3 AO LDO3 output voltage 10 VDD_LDO34 PS LDO3 and LDO4 supply 11 VLDO4 AO LDO4 output voltage 12 VBBAT AO Backup battery connection 13 SDA DIO Data signal of the 2-wire interface 14 SCL DI Clock signal of the 2-wire interface 15 nONKEY DI Input for power-on key 16 nRESETREQ DI Reset request input 17 VLX_BUCK4 AO Switching node of Buck4 18 VDD_BUCK4 PS Buck4 supply 19 VDD_BUCK3 PS Buck3 supply 20 VLX_BUCK3 AO Switching node of Buck3 21 GPIO0 DIO General purpose I/O, VDDQ reference, WDKICK 22 GPIO1 DIO General purpose I/O, VTTR 23 VDDIO PS IO supply 24 VBUCK4 AI Voltage feedback of Buck4 25 VBUCK3 AI Voltage feedback of Buck3 26 VBUCK1 AI Voltage feedback of Buck1 27 VBUCK2 AI Voltage feedback of Buck2 28 GPIO2 DIO General purpose I/O, PWR_EN 29 GPIO3 DIO General purpose I/O 30 GPIO4 DIO General purpose I/O, SYS_EN 31 VLX_BUCK1 AO Switching node of Buck1 32 VDD_BUCK1 PS Buck1 supply 33 VDD_BUCK2 PS Buck2 supply Datasheet Revision 3.3 6 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Pin No. Pin Name Type Table 2 Description 34 VLX_BUCK2_A AO Switching node of Buck2 35 VLX_BUCK2_B AO Switching node of Buck2 36 TP DIO Test pin 37 nIRQ DO Interrupt signal to host processor 38 nRESET DO Reset output 39 VDDCORE AO Internal supply 40 VSYS PS System supply, LDO1 supply Table 2: Pin Type Definition Pin Type Description Pin Type Description DI Digital Input AI Analog Input DO Digital Output AO Analog Output DIO Digital Input/Output AIO Analog Input/Output PS Power Supply GND Ground connection Datasheet Revision 3.3 7 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 1.2 Package Outline Drawing Figure 2: DA9062 Package Outline Drawing Datasheet Revision 3.3 8 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 2 Absolute Maximum Ratings Table 3 lists the absolute maximum ratings of the device. Exceeding these ratings may cause permanent damage to the device. Device functionality is only guaranteed under the conditions listed in Sections 3 and 4. Operating the device in conditions exceeding those listed in Sections 3 and 4, but compliant with the absolute maximum ratings listed in Table 3, for extended periods of time may affect device reliability. Table 3: Absolute Maximum Ratings Parameter Symbol Note Min Storage temperature Typ Max Unit -65 +150 °C Junction temperature TJ -40 +150 Note 1 °C Supply voltage VSYS -0.3 5.5 V All other pins -0.3 VSYS + 0.3 Note 2 V ESD protection HBM VESD_HBM 2000 V ESD protection CDM VESD_CDM Corner pins 750 V All other pins 500 Note 1 See Sections 4.10 and 7.10 for more details. Note 2 Voltage must not exceed 5.5 V. 3 Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Symbol Note Min Operating junction temperature TJ Supply voltage VSYS Supply voltage IO VDDIO IO supply voltage Note 1 Maximum power dissipation Note 2 PDISS Derating factor above TA = 70 °C: 56 mW/°C Typ Max Unit -40 +125 °C 0 5.5 V 1.2 3.6 V 3000 mW Note 1 VDDIO must not exceed VSYS. Note 2 Obtained from package thermal simulation, board dimension 76 mm x 114 mm x 1.6 mm (JEDEC), 6layer board, 35 μm thick copper top/bottom layers, 17 μm thick copper inside layers, natural convection (still air). Datasheet Revision 3.3 9 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4 4.1 Electrical Characteristics Digital I/O Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 5: Digital I/O Electrical Characteristics Parameter Symbol Test Conditions Min Input high voltage (GPI0-GPI4, nRESETREQ) VIH VDDCORE mode Max Unit 1.0 VSYS V 0.7 * VDDIO VSYS Input low voltage (GPI0–GPI4, nRESETREQ) VIL VDDCORE mode -0.3 0.4 VDDIO mode -0.3 0.3 * VDDIO Input high voltage (nONKEY) VIH RTC mode 1.0 VSYS VDDCORE mode 1.0 VSYS VDDIO mode VDDIO mode Input low voltage (nONKEY) VIL Typ V V 0.7 * VDDIO RTC mode -0.3 0.4 VDDCORE mode -0.3 0.4 VDDIO mode -0.3 0.3 * VDDIO VDDCORE mode 1.0 V Input high voltage (SCL, SDA) VIH Input low voltage (SCL, SDA) VIL Output high voltage (GPO0–GPO4, nRESET, nIRQ) VOH ILOAD = 1 mA Push-pull mode Output low voltage (GPO0–GPO4, nRESET, nIRQ) VOL ILOAD = 1 mA 0.3 V Output low voltage (SDA) VOL ILOAD = 20 mA 0.4 V ILOAD = 3 mA 0.24 Source current capability (GPO0–GPO4) IOH VOUT = 0.7 * VDDIO VDDIO ≥ 1.8 V -1 mA Sink current capability (GPO0–GPO4) IOL VOUT = 0.3 V 1 mA Input capacitance (SCL, SDA) CIN Pull-down resistance (GPI0–GPI4) RPD Pull-up resistance (GPO0–GPO4) RPU Datasheet VDDIO mode V 0.7 * VDDIO VDDCORE mode 0.4 VDDIO mode V 0.3 * VDDIO 0.7 * VDDIO V 10 pF 50 100 250 kΩ VDDIO = 1.5 V 60 180 310 k VDDIO = 1.8 V 45 120 190 VDDIO = 3.3 V 20 40 60 Revision 3.3 10 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.2 Watchdog Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 6: Watchdog Electrical Characteristics Parameter Symbol Test Conditions Minimum watchdog time tWDMIN Maximum watchdog time tWDMAX Minimum assert time of WDKICK 4.3 Min Typ Max Unit External 32 kHz oscillator 110 ms Internal 25 kHz oscillator 200 ms External 32 kHz oscillator 2 s Internal 25 kHz oscillator 2.5 s tWDKICKMIN 150 µs 2-Wire Interface START tF ACK STOP tR VIH SDA VIL tF tSU_D tH_D tHIGH tVD_D tVD_ACK tSU_STO VIH SCL VIL tH_STA 1/fSCL tLOW Figure 3: 2-Wire Interface Timing Datasheet Revision 3.3 11 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 7: 2-Wire Interface Electrical Characteristics Parameter Symbol Bus free time STOP to START tBUF Bus line capacitive load CB Test Conditions Min Typ Max 0.5 Unit µs 150 pF 1000 kHz Standard/Fast/Fast+ Mode SCL clock frequency fSCL Note 1 0 Start condition set-up time tSU_STA 0.26 µs Start condition hold time tH_STA 0.26 µs SCL low time tW_CL 0.5 µs SCL high time tW_CH 0.26 µs 2-WIRE SCL and SDA rise time tR (input requirement) 1000 ns 2-WIRE SCL and SDA fall time tF (input requirement) 300 ns Data set-up time tSU_D 50 ns Data hold-time tH_D 0 ns Data valid time tVD_D 0.45 µs Data valid time acknowledge tVD_ACK 0.45 µs Stop condition set-up time tSU_STO 0.26 µs High Speed Mode Requires VDDIO ≥ 1.8 V Note 1 SCL clock frequency fSCL Start condition set-up time tSU_STA 160 ns Start condition hold time tH_STA 160 ns SCL low time tW_CL 160 ns SCL high time tW_CH 60 ns 2-wire SCL and SDA rise time tR (input requirement) 160 ns 2-wire SCL and SDA fall time tF (input requirement) 160 ns Data set-up time tSU_D 10 ns Data hold-time tH_D 0 ns Stop condition set-up time tSU_STO 160 ns Note 1 0 3400 kHz Minimum clock frequency is 10 kHz if 2WIRE_TO is enabled. Datasheet Revision 3.3 12 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.4 LDOs 4.4.1 LDO1 Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC. Table 8: LDO1 Electrical Characteristics Parameter Symbol Test Conditions Min Input voltage VDD VDD = VSYS (Internally connected) 2.8 Maximum output current IOUT_MAX Output voltage VLDO Output accuracy Typ Max Unit 5.5 V 100 mA Programmable in 50 mV steps 0.9 3.6 IOUT = IOUT_MAX including static line/load regulation -3% +3% -55% Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Short circuit current ISHORT Dropout voltage VDROPOUT VLDO = 3.3 V IOUT = IOUT_MAX Static line regulation VS_LINE Static load regulation 1.0 0 V +35% µF 300 mΩ 200 mA 100 150 mV VDD = 3.0 V to 5.5 V IOUT = IOUT_MAX 5 20 mV VS_LOAD IOUT = 1 mA to IOUT_MAX 5 20 mV Line transient response VTR_LINE VDD = 3.0 V to 3.6 V IOUT = IOUT_MAX tr = tf = 10 µs 5 20 mV Load transient response VTR_LOAD VDD = 3.6 V, VLDO = 3.3 V IOUT = 1 mA to IOUT_MAX tr = tf = 1 µs 30 50 mV Power supply rejection ratio PSRR VDD = 3.6 V VDD - VLDO ≥ 0.6 V IOUT = IOUT_MAX/2 f = fVDD_LDO f = 10 Hz to 10 kHz Output noise N VDD = 3.6 V, VLDO = 2.8 V IOUT = 5 mA to IOUT_MAX f = 10 Hz to 100 kHz 40 60 dB 70 μV rms TA = 25 ºC Quiescent current in ON mode IQ_ON TA = 25 ºC 9+ 0.9% IOUT μA Quiescent current in SLEEP mode IQ_SLEEP TA = 25 ºC 1.5 + 1.6% IOUT μA Quiescent current in OFF mode IQ_OFF VLDO < 0.5 V TA = 25 ºC 1 μA Turn-on time tON 10 % to 90 % 350 μs SLEEP mode 450 Turn-off time Datasheet tOFF 90 % to 10% Pull-down enabled Revision 3.3 13 of 96 1 ms 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Pull-down resistance in OFF mode ROFF VLDO = 0.5 V Can be disabled via LDO1_PD_DIS 4.4.2 Min Typ Max Unit Ω 100 LDO2, LDO3, LDO4 Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC. Table 9: LDO2, LDO3, LDO4 Electrical Characteristics Parameter Symbol Test Conditions Min Input voltage VDD VDD = VSYS 2.8 Supplied from buck converter 1.5 Typ Max Unit 5.5 V Maximum output current IOUT_MAX VDD ≥ 1.8 V (IOUT = IOUT_MAX/3 VDD < 1.8 V) 300 Output voltage VLDO Programmable in 50 mV steps 0.9 3.6 IOUT = IOUT_MAX including static line/load regulation -3% +3% -55% Output accuracy Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Short circuit current ISHORT Dropout voltage VDROPOUT IOUT = IOUT_MAX (VDD < 1.8 V IOUT = IOUT_MAX/3) Note 1 Static line regulation VS_LINE Static load regulation mA 2.2 0 V +35% µF 300 mΩ 600 mA 100 150 mV VDD = 3.0 V to 5.5 V IOUT = IOUT_MAX 5 20 mV VS_LOAD IOUT = 1 mA to IOUT_MAX 5 20 mV Line transient response VTR_LINE VDD = 3.0 V to 3.6 V IOUT = IOUT_MAX tR = tF = 10 µs 5 20 mV Load transient response VTR_LOAD VDD = 3.6 V IOUT = 1 mA to IOUT_MAX tR = tF = 1 µs 30 50 mV Power supply rejection ratio PSRR VDD = 3.6 V VDD - VLDO ≥ 0.6 V IOUT = IOUT_MAX/2 f = fVDD_LDO f = 10 Hz to 1 kHz f = 1 kHz to 10 kHz f = 10 kHz to 100 kHz Output noise Datasheet N VDD = 3.6 V, VLDO = 2.8 V IOUT = 5 mA to IOUT_MAX f = 10 Hz to 100 kHz Revision 3.3 14 of 96 70 60 40 80 70 50 dB 50 μV rms 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Quiescent current in ON mode IQ_ON TA = 25 ºC 9+ 0.34% IOUT μA Quiescent current in SLEEP mode IQ_SLEEP TA = 25 ºC 2+ 0.7% IOUT μA Quiescent current in OFF mode IQ_OFF VLDO < 0.5 V TA = 25 ºC 1 μA Turn-on time TON 10 % to 90 % 200 µs SLEEP mode 300 Turn-off time TOFF 90 % to 10 % Pull-down enabled Pull-down resistance in OFF mode ROFF VLDO = 0.5 V Can be disabled via LDO<x>_PD_DIS Note 1 Min Typ Max 1 Unit ms Ω 100 At VDD = 1.8 V, the dropout voltage at IOUT_MAX increases by 70%. 4.4.3 LDOCORE Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 10: LDOCORE Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Output voltage VDDCORE Note 1 2.45 2.5 2.55 V RESET mode Stabilisation capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 1 MHz including wiring parasitics Dropout voltage VDROPOUT Note 2 2.2 -55% 2.2 0 50 Note 1 Setting VDD_FAULT_LOWER ≥ 2.65 V avoids LDOCORE dropout, see Section 4.9. Note 2 The LDOCORE supply, VSYS, must be maintained above VDDCORE + VDROPOUT. V +35% µF 300 mΩ 100 mV Note LDOCORE is only used to supply internal circuits. Datasheet Revision 3.3 15 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.5 Buck Converters 4.5.1 Buck1, Buck2 Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC. Table 11: Buck1, Buck2 Electrical Characteristics Parameter Symbol Test Conditions Min Input voltage VDD VDD = VSYS 2.8 Output capacitor COUT Half-current mode including voltage and temperature coefficient -50% Full-current mode including voltage and temperature coefficient -50% Output capacitor ESR RCOUT_ESR Inductor value LBUCK Inductor resistance RL_DCR Max Unit 5.5 V 2 * 22 +30% µF 2 * 47 +30% COUT = 2 * 22 µF f > 100 kHz including wiring parasitics 15 50 COUT = 2 * 47 µF f > 100 kHz including wiring parasitics 7.5 25 1.0 1.3 µH 55 100 m V Including current and temperature dependence 0.7 Typ m PWM mode Output voltage VBUCK Programmable in 10 mV steps Note 1 0.3 1.57 Output voltage accuracy VBUCK_ACC VDD = 4.2 V, VBUCK = 1.03 V excluding static line/load regulation and voltage ripple TA = 25 ºC -1% +1% Including static line/load regulation and voltage ripple Note 2 -3% +3% Transient load regulation VTR_LOAD VDD = 3.6 V, VBUCK = 1.15 V IOUT = 200 mA to 1000 mA dI/dt = 3 A/µs L = 1 µH 30 45 mV Transient line regulation VTR_LINE VDD = 3.0 V to 3.6 V IOUT = 500 mA tR = tF = 10 µs 0.2 3 mV Output current IOUT Half-current mode 1250 Full-current mode 2500 Current limit ILIM Current limit accuracy ILIM_ACC Quiescent current in OFF mode IQ_OFF Datasheet mA Half-current mode controlled in BUCK<x>_ILIM in 100 mA steps 700 2200 Full-current mode controlled in BUCK<x>_ILIM in 200 mA steps 1400 4400 -20% 20% 1 Revision 3.3 16 of 96 mA µA 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Quiescent current in PWM mode IQ_ON Half-current mode VDD = 3.6 V IOUT = 0 mA TA = 25 ºC 9 Full-current mode VDD = 3.6 V IOUT = 0 mA TA = 25 ºC 11 OSC_FRQ = ‘0000’ Min Unit mA f Switching duty cycle DC Turn-on time tON VBUCK = 1.15 V BUCK_SLOWSTART = disabled SLEW_RATE = 10 mV/1 µs BUCK<x>_ILIM = 1500 mA 0.37 1.2 ms Output pull-down resistance RPD VBUCK = 0.5 V Disabled via BUCK<x>_PD_DIS 100 200 Ω PMOS ON resistance RPMOS Half-current mode Including pin and routing VDD = 3.6 V 160 Full-current mode Including pin and routing VDD = 3.6 V 80 Half-current mode Including pin and routing VDD = 3.6 V 60 Full-current mode Including pin and routing VDD = 3.6 V 30 RNMOS 3 Max Switching frequency Note 3 NMOS ON resistance 2.85 Typ 14% 3.15 MHz 83% mΩ mΩ PFM mode Output voltage VBUCK_PFM Programmable in 10 mV steps Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VDD = 3.6 V, VBUCK = 1.15 V RTRACK 45 mΩ including bondwire, PCB, inductor ESR Output current IOUT_PFM Forced PFM mode Current limit ILIM_PFM Quiescent current IQ_PFM Mode transition time tAUTO 0.3 1.57 400 mA 300 1000 Forced PFM mode IOUT = 0 mA 27 32 AUTO mode IOUT = 0 mA 35 42 AUTO mode 6 Note 2 Minimum tolerance 35 mV. Note 3 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see Section 7.14. 17 of 96 µA µs If control BUCK<x>_MODE = ‘10’ (Synchronous) then the buck operates in PFM mode for VBUCK < 0.7 V. For complete control of the buck mode (PWM versus PFM) use BUCK<x>_MODE = ‘00’. Revision 3.3 mA mA Note 1 Datasheet V 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.5.2 Buck3 Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC. Table 12: Buck3 Electrical Characteristics Parameter Symbol Test Conditions Min Input voltage VDD VDD = VSYS IOUT ≤ 1.5 A VDD = VSYS IOUT > 1.5 A Output capacitor Output capacitor ESR COUT RCOUT_ESR Inductor value LBUCK Inductor resistance RL_DCR Typ Max Unit 2.8 5.5 V 3.3 5.5 IOUT ≤ 1.5 A Including voltage and temperature coefficient -50% 2 * 22 +30% IOUT > 1.5 A Including voltage and temperature coefficient -50% 2 * 47 +30% COUT = 2 * 22 µF f > 100 kHz Including wiring parasitics 15 50 COUT = 2 * 47 µF f > 100 kHz Including wiring parasitics 7.5 25 1.0 1.3 µH 55 100 m V Including current and temperature dependence 0.7 µF m PWM Mode Output voltage VBUCK Programmable in 20 mV steps 0.8 3.34 Output voltage accuracy VBUCK_ACC Including static line and load regulation and voltage ripple Note 1 -3% +3% Transient load regulation VTR_LOAD VDD = 3.6 V, VBUCK = 1.8 V IOUT = 200 mA to 1000 mA dI/dt = 3 A/µs L = 1 µH 30 45 VDD = 3.6 V, VBUCK = 1.8 V IOUT = 200 to 2000 mA dI/dt = 3 A/µs L = 1 µH 60 90 VDD = 5.0 V, VBUCK = 3.34 V IOUT = 200 mA to 2000 mA dI/dt = 3 A/µs L = 1 µH 60 90 0.2 3 mV mA Transient line regulation VTR_LINE VDD = 3.0 V to 3.6 V IOUT = 500 mA tr = tf = 10 µs Output current IOUT VDD - VBUCK ≥ 1.25 V 2000 VDD - VBUCK ≥ 1.00 V 1250 VDD - VBUCK ≥ 0.75 V 900 Current limit ILIM Current limit accuracy ILIM_ACC Datasheet Controlled in BUCK3_ILIM in 100 mA steps Revision 3.3 18 of 96 1700 3200 -20% 20% mV mA 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Min Typ Max Unit Quiescent current in OFF mode IQ_OFF 1 µA Quiescent current in PWM mode IQ_ON IOUT = 0 mA TA = 25 ºC Switching frequency Note 2 f OSC_FRQ = ‘0000’ Switching duty cycle DC Turn-on time tON VBUCK = 1.8 V BUCK_SLOWSTART = disabled SLEW_RATE = 20 mV/2 µs BUCK3_ILIM = 2500 mA 0.44 1.5 ms Output pull-down resistance RPD VBUCK = 0.5 V Disabled via BUCK3_PD_DIS 100 200 Ω PMOS ON resistance RPMOS Including pin and routing VDD = 3.6 V 150 mΩ NMOS ON resistance RNMOS Including pin and routing VDD = 3.6 V 60 mΩ Output voltage VBUCK_PFM Programmable in 20 mV steps Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VDD = 3.6 V, VBUCK = 1.8 V RTRACK 45 mΩ including bondwire, PCB, inductor ESR Output current IOUT_PFM Forced PFM mode Current limit ILIM_PFM Quiescent current IQ_PFM 9 2.85 3 15% mA 3.15 MHz 100% PFM Mode Mode transition time tAUTO 0.8 3.34 400 V mA 300 1000 mA mA Forced PFM mode IOUT = 0 mA 22 25 AUTO mode IOUT = 0 mA 30 35 AUTO mode 6 µA µs Note 1 Minimum tolerance 35 mV. Note 2 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see Section 7.14. Datasheet Revision 3.3 19 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.5.3 Buck4 Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC. Table 13: Buck4 Electrical Characteristics Parameter Symbol Test Conditions Min Input voltage VDD VDD = VSYS 2.8 Output capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 100 kHz Including wiring parasitics Inductor value LBUCK Including current and temperature dependence Inductor resistance RL_DCR -50% 0.7 Typ Max Unit 5.5 V 2 * 22 +30% µF 15 50 m 1.0 1.3 µH 55 100 m V PWM Mode Output voltage VBUCK Programmable in 10 mV steps Note 1 0.53 1.8 Output voltage accuracy VBUCK_ACC Including static line/load regulation and voltage ripple Note 2 -3% +3% Transient load regulation VTR_LOAD VDD = 3.6 V, VBUCK = 1.35 V IOUT = 200 mA to 1000 mA dI/dt = 3 A/µs L = 1 µH 25 40 VDD = 3.6 V, VBUCK = 1.35 V IOUT = 200 mA to 1500 mA dI/dt = 3 A/µs L = 1 µH 40 60 0.2 3 mV mA Transient line regulation VTR_LINE VDD = 3.0 V to 3.6 V IOUT = 500 mA tR = tF = 10 µs Output current IOUT VDD - VBUCK ≥ 1.25 V 1500 VDD - VBUCK ≥ 1.00 V 1250 Current limit ILIM Controlled in BUCK4_ILIM in 100 mA steps 700 2200 Current limit accuracy ILIM_ACC ILIM = 700 mA to 1400 mA -15% +25% ILIM = 1400 mA to 2200 mA -10% +15% mA Quiescent current in OFF mode IQ_OFF Quiescent current in PWM mode IQ_ON IOUT = 0 mA TA = 25 ºC Switching frequency Note 3 f OSC_FRQ = ‘0000’ Switching duty cycle DC Turn-on time tON VBUCK = 1.35 V BUCK_SLOWSTART = disabled SLEW_RATE = 10 mV/1 µs BUCK4_ILIM = 1500 mA 0.39 1.2 ms Output pull-down resistance RPD VBUCK = 0.5 V Disabled via BUCK4_PD_DIS 100 200 Ω Datasheet 1 mV 9 2.85 3 14% Revision 3.3 20 of 96 µA mA 3.15 MHz 83% 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Min Typ Max Unit PMOS ON resistance RPMOS Including pin and routing VDD = 3.6 V 150 mΩ NMOS ON resistance RNMOS Including pin and routing VDD = 3.6 V 60 mΩ Output voltage VBUCK_PFM Programmable in 10 mV steps. Mode transition current threshold (PFM to PWM) in AUTO mode IAUTO_THR VDD = 3.6 V, VBUCK = 1.35 V RTRACK 45 mΩ including bondwire, PCB, inductor ESR Output current IOUT_PFM Current limit ILIM_PFM Quiescent current IQ_PFM PFM Mode Mode transition time tAUTO 0.53 1.8 400 V mA 300 1000 mA mA Forced PFM mode IOUT = 0 mA 22 25 AUTO mode IOUT = 0 mA 30 35 AUTO mode 6 µA µs VTT Mode Input voltage VDD Output capacitor COUT Including voltage and temperature coefficient Output capacitor ESR RCOUT_ESR f > 100 kHz Including wiring parasitics Inductor value LBUCK 0.25 Inductor resistance RL_DCR 80 Output voltage VBUCK VBUCK = VDDQ/2 Output voltage accuracy VBUCK_ACC Relative to VTTR Including static line/load regulation and voltage ripple. Output current IOUT VBUCK = 0.675 V ±450 VBUCK = 0.700 V ±550 VBUCK = 0.750 V ±700 Transient load regulation Datasheet VTR_LOAD 2.8 -50% 5.5 V 2 * 47 +30% µF 7.5 25 m µH 120 m 0.675 1.3 V -3% +4% mA VDD = 3.6 V, VBUCK = 0.675 V IOUT = +10 mA to +1.0 A IOUT = -450 mA to -10 mA dI/dt = 3 A/µs L = 0.25 µH 25 40 VDD = 3.6 V, VBUCK = 0.675 V IOUT = +1 A to +10 mA IOUT = -10 mA to -450 mA dI/dt = 3 A/µs L = 0.25 µH 35 50 VDD = 3.6 V, VBUCK = 0.75 V IOUT = +10 mA to +1.0 A IOUT = -700 mA to -10 mA dI/dt = 3 A/µs L = 0.25 µH 25 40 Revision 3.3 21 of 96 mV 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Parameter Symbol Test Conditions Min Typ Max 35 50 0.33 1.2 ms 1.35 2.6 V V VDD = 3.6 V VBUCK = 0.75 V IOUT = +1 A to +10 mA IOUT = -10 mA to -700 mA dI/dt = 3 A/µs L = 0.25 µH Turn-on time tON VBUCK = 0.75 V BUCK_SLOWSTART = disabled SLEW_RATE = 10 mV/1 µs BUCK4_ILIM = 1500 mA Unit VTTR Buffer Feedback voltage VDDQ VTTR output voltage VTTR VTTR = VDDQ/2 0.675 1.3 VTTR voltage accuracy VTTR_ACC Relative to VDDQ input voltage -49% +51% VTTR output capacitor CVTTR Including voltage and temperature coefficient -50% VTTR output current IVTTR Sink/source -10 0.1 +30% µF +10 mA Note 1 If control BUCK4_MODE = ‘10’ (Synchronous) then the buck operates in PFM mode for VBUCK < 0.7 V. For complete control of the buck mode (PWM versus PFM) use BUCK4_MODE = ‘00’. Note 2 Minimum tolerance 35 mV. Note 3 Generated from internal 6 MHz oscillator and can be adjusted by ±10 % via control OSC_FRQ, see Section 7.14. Datasheet Revision 3.3 22 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.6 Backup Battery Charger Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 14: Backup Battery Charger Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Backup battery charging current ISET_BCHG VSYS = 3.6 V VBBAT = 2.5 V 100 Note 1 6000 µA Charger termination voltage VSET_BCHG VSYS = 3.6 V 1.1 Note 2 3.1 V Backup battery short circuit current ISHORT VBBAT = 0 V Stabilisation capacitor COUT Output capacitor ESR RCOUT_ESR f > 1 MHz Dropout voltage VDROPOUT IOUT = 5 mA 6.5 -55% 470 mA +35% nF 100 m 200 mV 150 Note 1 Can be set in 100 µA steps from 100 µA to 1000 µA and 1 mA steps from 1 mA to 6 mA via BCHG_ISET in register BBAT_CONT. Note 2 Can be set in 100/200 mV steps via BCHG_VSET in register BBAT_CONT. 4.7 32 kHz Crystal Oscillator Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 15: 32 kHz Crystal Oscillator Electrical Characteristics Parameter Symbol Test Conditions Min Supply voltage VDDRTC Derived from VBBAT or VDDCORE 1.5 Oscillator frequency fOSC Clock jitter Typ Max Unit 2.75 V 32.768 Cycle to cycle 1000 cycles 20 35 ns 100 k Crystal ESR RXTAL 50 Crystal CAP CXTAL 2 Start-up time tSTART VDDRTC = 1.5 V to 2.75 V kHz pF 0.5 2 s 32 +5% kHz Bypass Mode Input frequency fIN -5% Input duty cycle DC 40% 60% XTAL_IN Input high voltage VIH RTC_EN = 0 1.8 VSYS RTC_EN = 1 VBBAT < VSYS 1.1 RTC_EN = 1 VBBAT > VSYS 0.7 * VBBAT VBBAT RTC_EN = 0 -0.3 0.6 XTAL_OUT Input low voltage Input slew rate Datasheet VIL SR RTC_EN = 1 VBBAT < VSYS 0.4 RTC_EN = 1 VBBAT > VSYS 0.2 * VBBAT 2 pF input capacitance Revision 3.3 23 of 96 0.1 V V V/ns 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.8 Internal Oscillator Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 16: Internal Oscillator Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit Oscillator frequency fOSC OSC_FRQ = ‘0000’ 5.7 6 6.3 MHz Note 1 4.9 Oscillator frequency can be further adjusted by about ±10 %, see Section 7.14. System Supply Voltage Supervision Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 17: System Supply Voltage Supervision Electrical Characteristics Parameter Symbol Test Conditions Min Typ Under-voltage lockout lower threshold VPOR_LOWER 2.0 V Under-voltage lockout upper threshold VPOR_UPPER 2.3 V VSYS under-voltage lower threshold VDD_FAULT_LOWER Note 1 2.5 VSYS under-voltage lower threshold accuracy VSYS_LOWER -2% VSYS hysteresis VDD_FAULT_HYS 100 200 450 2.8 Max 3.25 Unit V +2% mV Note 2 VSYS upper threshold VDD_FAULT_UPPER -2% VDD_FAULT_LOWER + VDD_FAULT_HYS +2% Reference voltage VREF -1% 1.2 +1% VREF decoupling capacitor CVREF Reference current resistor RIREF 2.2 -1% 200 Note 1 Can be set in 50 mV steps via control VDD_FAULT_ADJ in register CONFIG_B, setting VDD_FAULT_LOWER ≥ 2.65 V avoids LDOCORE dropout, see Section 4.4.3. Note 2 Can be set in 50 mV steps via control VDD_HYST_ADJ in register CONFIG_B. Datasheet Revision 3.3 24 of 96 V µF +1% k 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 4.10 Junction Temperature Supervision Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 18: Junction Temperature Supervision Electrical Characteristics Parameter Symbol Test Conditions Min Typ Max Unit POR temperature threshold Note 1 TPOR Note 2 135 150 165 °C Critical temperature threshold Note 1 TCRIT Note 2 125 140 155 °C Warning temperature threshold Note 1 TWARN Note 2 110 125 140 °C Note 1 See Section 7.10. Note 2 Thermal thresholds are non-overlapping. 4.11 Current Consumption Unless otherwise noted, the following is valid for TJ = -40 °C to +125 ºC, VSYS = 2.8 V to 5.5 V. Table 19: Current Consumption Electrical Characteristics Operating Mode Symbol Test Conditions VBBAT (Typ) VSYS (Typ) Unit RTC mode IDDRTC VSYS > 2.0 V VBBAT > VSYS 1.5 Note 1 1.0 µA VSYS > 2.0 V VBBAT < VSYS 0.5 7 Note 2 µA POWERDOWN mode IDDPD VSYS > 3.0 V LDOCORE enabled Bucks and LDOs disabled 40 µA ACTIVE mode IDDACT Bucks and LDOs enabled 400 µA Note 1 Maximum current is 2.5 μA for TA 85 C and VBBAT 3.1 V. Note 2 Maximum current is 10 μA for TA 85 C and VSYS 5.0 V. Datasheet Revision 3.3 25 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 5 Typical Characteristics Figure 4: Buck1 Efficiency in AUTO Mode Figure 5: Buck2 Efficiency in AUTO Mode Datasheet Revision 3.3 26 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Figure 6: Buck3 Efficiency in AUTO Mode (VIN = 3.60 V, VOUT = 1.80 V) Figure 7: Buck3 Efficiency in AUTO Mode (VIN = 5.00 V, VOUT = 3.34 V) Datasheet Revision 3.3 27 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Figure 8: Buck4 Efficiency in AUTO Mode Datasheet Revision 3.3 28 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 6 System Block Diagram A block diagram for a typical application is illustrated in Figure 9. VDD_BUCK1 VDDQ 1.5 V (2.5 A) Buck1 DDR3 memory VDDQ(GPIO0) VDD_BUCK4 VTT 0.75 V (±700 mA) Buck4 VDD_BUCK2 0.7 V to 1.57 V (2.5 A) Buck2 VDD_BUCK3 0.8 V to 3.3 V (2 A) Buck3 DA9062 VSYS LDOCORE Application processor 0.9 V to 3.6 V (100 mA) LDO1 VDD_LDO2 0.9 V to 3.6 V (300 mA) LDO2 VDD_LDO34 0.9 V to 3.6 V (300 mA) LDO3 0.9 V to 3.6 V (300 mA) LDO4 RTC BBAT charger Coin cell Figure 9: DA9062 Typical System Block Diagram Datasheet Revision 3.3 29 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 6.1 DDR Power Management Using DA9062 for DDR power management is illustrated in Figure 10. 5V VDD_BUCK4 VDD_BUCK1 Buck1/2 VDDQ (2.5 A) VBUCK1 DAC Buck control VLX_BUCK1 VBUCK1 Buck4 VTT (±700 mA) VBUCK4 DAC Buck control VDDQ VLX_BUCK4 VBUCK4 VTTR (±10 mA) Figure 10: DA9062 DDR Power Management Datasheet Revision 3.3 30 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7 7.1 Functional Description Control Signals Each of the input signals described below feature a debounce filter. They share a common debounce time control (DEBOUNCING). 7.1.1 nONKEY nONKEY is an edge-sensitive signal that controls the power mode of DA9062. Both falling and rising edges are detected and the time between the edges is measured. This enables different lengths of key press detection. The detection circuitry is enabled in all power modes of the device. The status of the signal after debouncing can be read from NONKEY (reg. STATUS_A). The mask bit M_NONKEY prevents interrupt and wakeup events that would normally be caused by an nONKEY event. nONKEY has four modes of operation, see Table 20, which can be selected by NONKEY_PIN. NONKEY_LOCK controls the wakeup event generation of the nONKEY. If NONKEY_LOCK is asserted (depends on NONKEY_PIN), a short nONKEY press (shorter than KEY_DELAY) will not generate a wakeup. Table 20: nONKEY Functions NONKEY_PIN Function 00 An event (E_nONKEY) is generated when nONKEY is asserted. If not masked, the event causes an interrupt. A wakeup is triggered if the device is in POWERDOWN mode. 01 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the signal stays asserted and the timer reaches the programmed value, an event is generated and nONKEY_LOCK is asserted. 10 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge. If the signal stays asserted and the timer reaches the programmed value, an event is generated, nONKEY_LOCK is asserted, and a power-down sequence is triggered by automatically clearing SYSTEM_EN. 11 A timer is started when nONKEY is asserted. If the signal is de-asserted before the time programmed in KEY_DELAY, an event (E_nONKEY) is generated at the rising edge, SYSTEM_EN is cleared, and STANDBY is asserted. If the signal stays asserted and the timer reaches the programmed value, an event is generated, nONKEY_LOCK is asserted, and SYSTEM_EN and STANDBY are cleared. Whenever nONKEY_LOCK is asserted, a long key press (longer than the time programmed in KEY_DELAY) is required to wakeup from POWERDOWN mode. If the wakeup is also desired after a short key press, nONKEY_LOCK has to be cleared before entering the POWERDOWN mode. 7.1.2 nRESETREQ nRESETREQ is an active-low reset request that causes DA9062 to enter RESET mode. The transition to the RESET mode is handled by the power sequencer and it can be sped up by setting the HOST_SD_MODE bit. Before entering the RESET mode, a fault log bit is set (nRESETREQ) and nRESET is asserted. nRESETREQ should be tied to an always-on rail that is supplied in all modes of the DA9062 such as VSYS. It is not recommended to tie nRESETREQ to any of the regulator outputs. Datasheet Revision 3.3 31 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.1.3 nRESET nRESET is an active-low reset output intended for resetting the host processor of the system. The signal can be configured as either push-pull or open drain output (PM_O_TYPE). nRESET is always asserted upon a cold boot from the no-power mode. It is always asserted at the beginning of a shutdown sequence to the RESET mode. nRESET may also be asserted at the beginning of the sequence to the POWERDOWN mode, if configured in control NRES_MODE. De-assertion of nRESET is controlled by a reset timer. After being asserted, nRESET remains low until the reset timer, which was started from the selected trigger signal, expires. The reset timer trigger can be selected via RESET_EVENT and set to one of the following: an external signal triggering the wakeup (EXT_WAKEUP), an internal signal indicating the end of the first power-up sub-sequence (SYS_UP), an internal signal indicating the end of the second power-up sub-sequence (PWR_UP), or the transition of DA9062 from reset to POWERDOWN mode. The expiry time can be configured via RESET_TIMER from 1 ms to 1 s. If RESET_TIMER is set to 0 ms, nRESET is deasserted immediately after the trigger selected with RESET_EVENT. 7.1.4 nIRQ nIRQ is a level-sensitive interrupt signal. It can be configured either as a push-pull or an open drain output (selected via PM_O_TYPE). The polarity of nIRQ can be selected with IRQ_TYPE. nIRQ is asserted when an unmasked event has occurred. The nIRQ will not be released until all event registers have been cleared. New events that occur while reading an event register are saved until the event register is cleared, ensuring that the host processor captures them. The same will happen to all events occurring when the power sequencer is in transition. 7.2 2-Wire Interface The 2-wire interface provides access to the control and status registers. The interface supports 2 operations compatible to the standard, fast, fast-plus, and high-speed modes of the I C bus specification Rev. 3. Communication on the 2-wire bus is always between two devices; one acting as the master and the other as the slave. The DA9062 only operates as a slave. SCL transmits 2-wire clock data and SDA transmits the bidirectional data. The 2-wire interface is open-drain supporting multiple devices on one line. The bus lines have to be pulled high by an external pull-up resistor (2 kΩ to 20 kΩ). The attached devices drive the bus lines low by connecting them to ground. As a result, two devices can drive the bus simultaneously without conflict. In standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application and it does not have any relation to the DA9062 internal clock signals. DA9062 stays within the described host clock speed limitations and does not initiate clock slowdown. An automatic interface reset is triggered when the clock signal ceases toggling for >35 ms (controlled in TWOWIRE_TO). When the SDA is stuck, the bus clears after receiving nine clock pulses. Operation in high-speed mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order to enable slope-control. The high-speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000 1XXX) at the beginning of the transfer. The DA9062 does not make use of clock stretching and delivers read data without delay up to 3.4 MHz. Alternatively, the interface can be configured to use high-speed mode continuously via PM_IF_HSM, so that the master code is not required at the beginning of every transfer. This reduces communication overhead on the bus and limits the attachable bus slaves to compatible devices. Datasheet Revision 3.3 32 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.2.1 Register Map Paging The 2-wire interface has direct access to two pages of the DA9062 register map (up to 256 addresses). The register at address zero on each page is used as a page control register (the LSB of control PAGE is ignored). Writing to the page control register changes the active page for all subsequent read/write operations unless an automatic return to page 0 is selected using control REVERT. Unless REVERT was asserted after modifying the active page, it is recommended to read back the page control register to ensure that future data exchange is accessing the intended registers. DA9062 also offers an alternative way to access register pages which avoids writing explicitly to PAGE. DA9062 responds to multiple consecutive slave addresses and updates PAGE automatically based on the slave address. For example, when IF_BASE_ADDR[7:4] = 0xB the slave address changes PAGE as follows: Slave address = 0xB0 PAGE = 0x00 Slave address = 0xB2 PAGE = 0x02 7.2.2 Details of the 2-Wire Protocol All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit, the SDA line is driven at the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and then low. This pulse on SCL stores the SDA bit in the receiver’s shift register. A 2-byte serial protocol is used: one address byte and one data byte. Data and address transfer transmits the MSB first for both read and write operations. All transmissions begin with the START condition from the master during which the bus is in IDLE state (the bus is free). It is initiated by a high-to-low transition on the SDA line while the SCL is in high state. A STOP condition is indicated by a low-to-high transition on the SDA line while the SCL is in high state. The START and STOP conditions are illustrated in Figure 11. SDA SCL START Transaction STOP Figure 11: Timing of the START and STOP Conditions DA9062 monitors the 2-wire bus for a valid slave address whenever the interface is enabled. It responds immediately when it receives its own slave address. This is acknowledged by pulling the SDA line low during the following clock cycle (white blocks marked with ‘A’ in the following figures). The protocol for a register write from master to slave consists of a START condition, a slave address, a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9062 responds to all bytes with an ACK. A register write operation is illustrated in Figure 12. S SLAVEadr 7-bits W A 1-bit REGadr 8-bits Master to Slave S = START condition P = STOP condition A DATA A P 8-bits Slave to Master A = Acknowledge (low) W = Write (low) Figure 12: Byte Write Operation Datasheet Revision 3.3 33 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A When the host reads register data the DA9062 first has to access the target register address with write access and then with read access and a repeated START, or alternatively a second START, condition. After receiving the data, the host sends NACK and terminates the transmission with a STOP condition, see Figure 13. S SLAVEadr W A 7-bits S 1-bit SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr 8-bits 7-bits REGadr A P S A * DATA A P 8-bits SLAVEadr 8-bits Master to Slave R 1-bit 7-bits R A 1-bit * DATA A P 8-bits Slave to Master S = START condition Sr = Repeated START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 13: Examples of Byte Read Operations Consecutive (page) read-out mode is initiated from the master by sending an ACK instead of NACK after receiving a byte, see Figure 14. The 2-wire control block then increments the address pointer to the next register address and sends the data to the master. The data bytes are read continuously until the master sends a NACK followed by a subsequent STOP condition directly after receiving the data. If a non-existent 2-wire address is read out then the DA9062 will return code zero. S SLAVEadr W A 7-bits 1 bit S SLAVEadr W A 7-bits 1-bit REGadr A Sr SLAVEadr R A 8-bits REGadr 7-bits 1-bit A DATA 8-bits 7-bits A 8-bits S SLAVEadr R A A P 8-bits Master to Slave DATA DATA 1-bit * DATA A P 8-bits A DATA 8-bits * A P 8-bits Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 14: 2-Wire Page Read The slave address after the repeated START condition must be the same as the previous slave address. Consecutive (page) write mode is supported if the master sends several data bytes after sending the register address. The 2-wire control block then increments the address pointer to the next 2-wire address, stores the received data, and sends an ACK until the master sends a STOP condition. The page write mode is illustrated in Figure 15. S SLAVEadr W A 7-bits 1 bit REGadr 8-bits Master to Slave S = START condition Sr = Repeat START condition P = STOP condition A DATA 8-bits A DATA 1-bit A 8-bits DATA 8-bits A ………. A P Repeated writes Slave to Master A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 15: 2-Wire Page Write Datasheet Revision 3.3 34 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A repeated write mode can be enabled with WRITE_MODE control. In this mode, the master can execute back-to-back write operations to non-consecutive addresses by transmitting register addresses and data pairs. The data is stored in the address specified by the preceding byte. The repeated write mode is illustrated in Figure 16. S SLAVEadr W A 7-bits 1 bit REGadr A DATA 8-bits Master to Slave 8-bits A REGadr 1-bit 8-bits A DATA ………. A 8-bits A P Repeated writes Slave to Master S = START condition Sr = Repeat START condition P = STOP condition A = Acknowledge (low) * A = No Acknowledge W = Write (low) R = Read (high) Figure 16: 2-Wire Repeated Write If a new START or STOP condition occurs within a message, the bus returns to idle mode. 7.3 GPIOs DA9062 features five general purpose IO pins. The basic structure of the GPIOs is depicted in Figure 17. As illustrated, there are several additional functions: ● ● ● ● ● ● analog function alternate function forwarding regulator control sequencer WAIT_STEP interrupt and wakeup generation The GPIOs are operational in POWERDOWN and ACTIVE modes. However, GPIs can be configured as disabled in POWERDOWN mode in register PD_DIS (control GPI_DIS). In other modes, the GPIO is disabled and all ports are configured as open drain outputs in high impedance state. The level transitions on inputs will no longer be detected, but I/O drivers will keep their configuration and programmed levels. Alternate function Analog function Forwarding output Sequencer (WAIT_STEP), regulator control Interrupt GPIOx_MODE GPIOx_PIN GPIOx_TYPE Debounce GPI Edge detection GPIx GPIOx_PUPD M_GPIOx E_GPIOx Mask GPIOx_PIN GPIOx_WKUP_MODE Wakeup selection VDDIO Wakeup enable Wakeup GPIOx_WEN GPIOx_OUT GPIOx_PUPD GPIOx_MODE GPO OD 0 1 Forwarding input Sequencer CLK_32K VDD_FAULT Output function VDDIO GPO push-pull Figure 17: General GPIO Block Diagram The functionality of a GPIO is configured in GPIO<x>_PIN, as listed in Table 21. Datasheet Revision 3.3 35 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 21: GPIO Functions GPIO<X>_ PIN Function GPIO<X>_MOD E GPIO<X>_TY PE GPIO<X>_WKUP_MO DE GPIO<X>_WEN 0 Alternate function No effect No effect No effect No effect 1 GPI 0: Debounce off 1: Debounce on 0: Active low 1: Active high 0: Edge-sensitive wakeup 0: Wakeup disabled 1: Level-sensitive wakeup 1: Wakeup enabled 2 GPO Open drain 0: Output low 1: Output high No effect No effect No effect 3 GPO Push-pull 0: Output low 1: Output high No effect No effect No effect 7.3.1 GPI Functionality In GPI mode, the polarity of the input can be selected with GPIO<x>_TYPE. A debouncing filter can be applied on the input signals with a configurable debouncing time (control DEBOUNCING). An event is generated at the active edge of the input. The active edge is determined by the signal polarity configured in GPIO<x>_TYPE. The event can be further configured to generate a wakeup via GPIO<x>_WKUP_MODE and GPIO<x>_WEN. An internal pull-down can be activated for the inputs in GPIO<x>_PUPD. A level sensitive wakeup event can also be configured for each GPI via GPIO<x>_WKUP_MODE and GPIO<x>_WEN. The functionality of the level-sensitive wakeup is described in Table 26. 7.3.1.1 Regulator Control GPIO1, GPIO2, and GPIO3 can be used for controlling DA9062 regulators. When configured as GPIs, they can be used to enable regulators or select between their two output voltage settings. As seen in Figure 17, the regulator control is branched after the GPIO<x>_TYPE control allowing active edge delegation for the regulator control. Finally, the functionality for the GPI is selected with the regulator controls BUCK<x>_GPI, LDO<x>_GPI, VBUCK<x>_GPI, and VLDO<x>_GPI. One GPI can be used to control the same function on multiple regulators simultaneously. When a regulator is controlled by a GPI, the same function (on/off or voltage selection) can no longer be controlled by the power supply sequencer. The regulator still responds normally to register writes to the control bit. Enable/Disable Control A GPI is used for enabling/disabling regulators when it is selected in one of the BUCK<x>_GPI or LDO<x>_GPI controls. A passive to active transition sets the regulator enable bit (BUCK<x>_EN, LDO<x>_EN), and an active to passive transition clears it. Output Voltage Control A GPI is used for the output voltage selection when it is selected in one of the VBUCK<x>_GPI or VLDO<x>_GPI controls. A passive to active transition sets the voltage selection bit (VBUCK<x>_SEL, VLDO<x>_SEL), and an active to passive edge clears it. 7.3.1.2 Sequencer WAIT_STEP GPIO3 can be used for the WAIT_STEP functionality. The power sequencer can be programmed to wait for either a rising or falling edge of the WAIT_STEP input, see Section 7.9.4. The active edge is selected from GPIO<x>_TYPE. Datasheet Revision 3.3 36 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.3.2 GPO Functionality The outputs can be configured as push-pull or open drain outputs, see Table 21. An internal pull-up can be enabled/disabled from GPIO<x>_PUPD (open drain mode). The GPIO<x>_MODE settings can control the output state. Instead of controlling the output with GPIO<x>_MODE, a selection of alternatives is available in the GPIO<x>_OUT controls. These include: the forwarding function, see Section 7.3.4, the power supply sequencer, see Section 7.9, the 32 kHz clock (OUT_32K), and the status of the supply voltage supervision (nVDD_FAULT). When the GPIO is configured as an output and GPIO<x>_OUT is set to 0x0, the GPIO<x>_MODE determines the state of the ouput. 7.3.2.1 nVDD_FAULT nVDD_FAULT gives the status of the system supply monitoring, see Section 7.11. The assertion of nVDD_FAULT indicates that the main supply input voltage is low (VSYS < VDD_FAULT_UPPER) and therefore informs the host processor that the power will soon shut down. It can be configured to drive a GPO from the GPIO<x>_OUT controls. The driver type (push-pull, open drain) selection and pullup resistor control function normally. The GPIO<x>_MODE can be used to invert the incoming nVDD_FAULT signal. 7.3.2.2 OUT_32K OUT_32K feeds a buffered 32 kHz clock signal that is derived from the internal oscillator. The signal output buffer can be controlled either with the power sequencer or manually via EN_32KOUT, and paused automatically during POWERDOWN mode with the OUT_32K_PAUSE bit. Glitch-free switching between a 32 kHz clock output and another GPIO configuration is not guaranteed. Therefore, configuring a GPIO for 32 kHz clock output should only be done in OTP. However, enabling and disabling the buffer is still dynamic as described above. 7.3.3 Alternate Functions GPIO0, GPIO2, and GPIO4 can be used for alternate functions. These are digital control signals that don’t employ the debouncing, event detection, or interrupt generation functions. Only the input buffer of the GPIO block is employed. The alternate functions of DA9062 are listed in Table 22 and described in the following subsections. A debouncing filter can be applied also on the alternate functions with a configurable debouncing time (control DEBOUNCING). Table 22: GPIO Alternate Input Functions Gpio Alternate Function Description GPIO0 WDKICK Watchdog kick or disable GPIO1 - GPIO2 PWR_EN GPIO3 - GPIO4 SYS_EN 7.3.3.1 Power mode control Power mode control SYS_EN SYS_EN (pin GPIO4) controls the SYSTEM_EN bit and thereby the power mode of DA9062. It is part of the power supply sequencer functionality described in Section 7.9. SYS_EN is an edgesensitive signal and its polarity can be chosen in the GPIO4_TYPE control. Asserting SYS_EN causes an interrupt (E_GPIx) and a wakeup event. De-asserting SYS_EN triggers a power-down sequence but no interrupt. Datasheet Revision 3.3 37 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.3.3.2 PWR_EN PWR_EN (pin GPIO2) controls the POWER_EN bit and thereby the power mode of DA9062. It is part of the power supply sequencer functionality described in Section 7.9. PWR_EN is an edgesensitive signal and its polarity can be chosen in the GPIO2_TYPE control. A wakeup event can be generated after assertion of PWR_EN if so configured in GPIO2_WEN. 7.3.3.3 WDKICK A rising edge of the WDKICK signal resets the watchdog counter. The polarity of the signal can be chosen in the GPIO0_TYPE control. If the signal is kept asserted, the watchdog is disabled as the counter is not incremented (WDG_MODE), see Section 7.15. 7.3.4 GPIO Forwarding GPIO forwarding works between GPIOs 0, 1, 2, and 3. Any of these GPIs can be routed directly to GPO0, 1, and 3 after debouncing. Forwarding is one of the options for the GPIO<x>_OUT control. 7.3.5 Analog Functions GPIO0 and GPIO1 can be used as analog IOs. In this case, the normal GPIO functions are disabled. The analog functions and their corresponding control bits are listed in Table 23. Table 23: GPIO Analog Functions Gpio Analog Function Control GPIO0 VDDQ BUCK4_VTT_EN GPIO1 VTTR BUCK4_VTTR_EN GPIO2 - GPIO3 - GPIO4 - 7.4 Dynamic Voltage Control All of DA9062’s buck converters can be controlled in several ways to achieve dynamic voltage control (DVC). The buck converters feature a voltage ramping feature that enables smooth transition from one voltage setting to another. All output voltages can be controlled with software via the 2-wire interface (VBUCK<x>_A). The 2wire interface is operational when the device is in ACTIVE mode. 7.5 Regulator Voltage A And B Selection In addition, all regulators feature A and B settings which can be programmed with different voltages (VBUCK<x>_A, VBUCK<x>_B), one of which is chosen according to the operating mode of the system (VBUCK<x>_SEL, VLDO<x>_SEL). In addition to the output voltage, the A and B settings include a bit to force the regulator into SLEEP mode which reduces the quiescent current. The selection between the A and B settings can be done either with software via the 2-wire interface or by the power sequencer, see Section 7.9. Furthermore, each regulator can be enabled with a GPI pin, see Section 7.3.1.1, and the selection between the A and B settings done with another GPI. Datasheet Revision 3.3 38 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.6 LDOs All LDOs employ Dialog Semiconductor’s Smart Mirror™ dynamic biasing technology, see Figure 18, which maintains high performance over a wide range of operating conditions and a power saving mode (SLEEP mode) to minimize the quiescent current during very low output current. The circuit technique offers significantly higher gain bandwidth performance than conventional designs, enabling higher power supply rejection performance at higher frequencies. PSRR is maintained across the full operating current range however quiescent current consumption is scaled to demand improved efficiency when current demand is low. Vin Vref Vout Cout Smart Mirror TM LDO ESR Figure 18: Smart Mirror 7.6.1 TM Voltage Regulator Control The LDOs can be enabled by writing directly to a control bit (LDO<x>_EN), controlling it via a GPI, see Section 7.3.1.1, or assigning it to a power sequencer step, see Section 7.9.2. Each LDO features two voltage control registers (VLDO<x>_A/VLDO<x>_B) that allow two output voltage preconfigurations. The active setting can then be selected either with a control bit (VLDO<x>_SEL), via a GPI, see Section 7.3.1.1, or automatically based on the DA9062 power mode. The SLEEP mode of the LDOs can be linked to either the A or B setting (LDO<x>_SL_A/LDO<x>_SL_B). Therefore, the LDO will switch to SLEEP mode when the setting is active. LDO1 differs from the other LDOs because it can be configured as an always-on regulator. This means that it is also enabled in RESET mode, see Section 7.8.3. 7.6.2 Current Limit Each LDO provides over-current detection. The current limit is fixed for each LDO based on their current capability. If any of the LDOs’ current limit is exceeded for longer than 10 ms, an event, E_LDO_LIM, is triggered. The status of the limit comparator can be observed from LDO<x>_ILIM (reg. STATUS_D). If an LDO’s current limit is exceeded for longer than 200 ms, the LDO is automatically disabled. This shutdown feature can be disabled by clearing the LDO_SD control. Once disabled due to an over-current, the LDO must be re-enabled by one of the sources described in Section 7.6.1. 7.6.3 Output Pull-Down When over-voltage (1.06 * VLDO<x>) occurs, the voltage regulators enable an internal load to discharge the output back to its configured voltage. This feature can be disabled in LDO<x>_PD_DIS. Datasheet Revision 3.3 39 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.7 Switching Regulators DA9062 includes four step-down switching regulators operating at 3 MHz. All switching regulators employ a synchronous topology with an internal NFET, thus eliminating the need for an external Schottky diode. The output voltage can be set in 10 mV steps (20 mV steps for Buck3) and the regulation accuracy is ±3 % over the whole operating temperature range. Static line and load regulation are also considered in this accuracy. The switching frequency (3 MHz) is high enough to warrant the use of a small 1.0 µH inductor. The programming of the converter current limit depends on the coil parameters, as illustrated in Table 24. Table 24: Buck Current Limit 7.7.1 Min. ISAT (mA) Frequency (MHz) Buck current limit (mA) 1750 3 1500 1460 3 1200 1180 3 950 940 3 750 Control The buck can be enabled manually by writing directly to a control register, with an external signal connected to GPI, see Section 7.3.1.1, or by assigning it to a power sequencer step, see Section 7.9.2. Each buck converter features two voltage control registers (VBUCK<x>_A/VBUCK<x>_B) which can be programmed with two different voltages. The active setting can then be selected via a control bit (VBUCK<x>_SEL), via a GPI, see Section 7.3.1.1, or automatically based on the power mode of DA9062. 7.7.2 Output Voltage Slewing To limit in-rush current from the input supply, the buck converters can achieve a new output voltage with controlled ramping. Ramping is achieved by stepping through all the VBUCK values between the old and new settings, at a rate defined by SLEW_RATE. The actual output slew rate, in mV/µs, for a particular buck converter is then defined by the minimum voltage step of that buck and the common step time programmed in SLEW_RATE. During PFM mode, the negative slew rate is load dependent and might be lower than the one mentioned above. An event E_DVC_RDY is triggered when all buck converters have reached their target voltage. 7.7.3 Soft-Start The buck converter supports two options for starting up. The normal start-up option ramps up the power rail as fast as possible, typically within 1 ms. This implies a high in-rush current. The slow start-up is selected by setting BUCK_SLOWSTART, which increases the start-up time and limits the input current. 7.7.4 Active Discharge When switching off a buck converter the output rail can be actively discharged. This feature is enabled by setting BUCK_ACTV_DISCHRG. The discharge is implemented by ramping down the output voltage using DVC. 7.7.5 Peak Current Limit All buck converters feature a programmable current limit (BUCK<x>_ILIM). The current limit protects the inductor and the pass devices from excessive current. If the current limit is exceeded, the buck continues to run normally but the duty cycle is limited. Datasheet Revision 3.3 40 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.7.6 Operating Mode The operating mode of each converter can be set via the buck control (BUCK<x>_MODE) to synchronous (PWM), sleep (PFM), or auto. In auto mode the buck converter switches between PWM and PFM depending on the load current. This mode is recommended for applications that require fast transitions from synchronous to sleep operation. The current consumption during PWM operation is 10 mA and drops to <1 µA in shutdown. In addition, the buck mode can be controlled with the A and B setting. If BUCK<x>_SL_B is set, the buck is forced to SLEEP mode when the B setting is active. Similarly, if BUCK<x>_SL_A is set, the buck is forced to SLEEP mode when the A setting is active. 7.7.7 Half-Current Mode Buck1 and Buck2 can operate in half-current mode where the quiescent current is reduced by disabling half of the pass devices. As the name implies, enabling this option halves the output current, and therefore, this feature is valuable in applications where quiescent current is critical and full current is not needed. This feature is controlled with BUCK1_FCM and BUCK2_FCM. If the bit is asserted (BUCK<x>_FCM = 1), the corresponding buck is in full-current mode and the full current is available. If the bit is de-asserted, the corresponding buck is in half-current mode. Operating the bucks in full-current mode requires twice as much output capacitance (2 x 47 µF) as the half-current mode (2 x 22 µF). 7.7.8 Buck1 and Buck2 in Dual-Phase Mode Buck1 and Buck2 can be merged as a dual-phase buck, with up to 5 A output current. If enabled in OTP via BUCK1_2_MERGE, the outputs from both inductors must be routed together. The controls for Buck2 are automatically disabled in this configuration, except for BUCK2_PD_DIS. 7.7.9 Buck4 in DDR Memory Bus Termination Mode Buck4 can be used to generate the DDR memory termination voltage, VTT. In this mode, Buck4 tracks the divided VDDQ voltage and it is able to both sink and source current. As described in Section 7.3.5, GPIO0 can be configured to carry the VDDQ and GPIO1 can be configured to carry the VTTR signal. The VTTR output provides buffered version of the VDDQ/2 voltage with ±10 mA source/sink capability (requires 0.1 µF stabilisation capacitor), see Figure 19. When used for memory termination, Buck4 has to be forced in the synchronous (PWM) mode from the BUCK4_MODE control. If BUCK4_VTT_EN and BUCK4_VTTR_EN are asserted at the same time, the VTTR provides a buffered VTT reference, but otherwise Buck4 is running in a normal output voltage control mode. VDD_BUCK4 Buck4 BUCK4_VTT_EN VBUCK4 DAC VLX_BUCK4 VTT (±700 mA) Buck control VDDQ GPIO0 VBUCK4 + - VTTR (±10 mA) GPIO1 Figure 19: Buck4 DDR Memory Bus Termination Mode Datasheet Revision 3.3 41 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 25: Buck4 VTT Mode Control BUCK4_VTT_EN BUCK4_VTTR_EN Mode Buck4 VREF GPIO0 GPIO1 0 0 Normal VDAC Digital I/O Digital I/O 0 1 Normal VDAC VDDQ VTTR 1 0 VTT VDDQ/2 un-buffered VDDQ Digital I/O 1 1 VTT VDDQ/2 buffered VDDQ VTTR 7.8 Power Modes VDDCORE < VPOR_UPPER NO-POWER VDDCORE > VPOR_UPPER Active functions · VDDCORE comparator RTC Any state Active functions · VDDCORE comparator · 32 kHz oscillator · RTC counter · nONKEY ( nONKEY press || RTC alarm) && ( ! Temp error && ! VSYS error ) RESET RTC_MODE_SD Sequence done || timeout Active functions · VDDCORE comparator · 32 kHz oscillator · RTC counter · nONKEY · Internal supplies · LDO1 Shutdown sequence VSYS error · nRESET asserted Any state time > RESET_DURATION && ( ! Temp error && ! VSYS error ) nRESETREQ || nONKEY (long) Shutdown sequence POWERDOWN RTC_MODE_PD Temp error Active functions · VDDCORE comparator · 32 kHz oscillator · RTC counter · nONKEY · Internal supplies · LDO1 · Selected supplies Any state Sequence done || timeout Retry count != 0 Power-down sequence Sequence done || timeout Retry count == 0 nRESETREQ || nONKEY (long) nONKEY press || GPIO wake-up event POWERDOWN (Freeze) Shutdown sequence nRESETREQ || nONKEY (long) Power-up sequence nONKEY (short) || GPIO power-down event || Watchdog timeout Sequence done || timeout ACTIVE Active functions · VDDCORE comparator · 32 kHz oscillator · RTC counter · nONKEY · Internal supplies · All supplies · Watchdog Watchdog alive Figure 20: DA9062 Power Modes (State Transition Conditions Follow C-Language Syntax) Datasheet Revision 3.3 42 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.8.1 NO-POWER Mode The NO-POWER mode is initial state when powering up the DA9062 for the first time. When the system supply rises above a threshold, DA9062 enters RESET mode. 7.8.2 RTC Mode The RTC mode is a low-power mode with only a minimum set of functions to maintain the system time. All supplies are disabled. RTC mode is entered either after a software request or when the backup battery is the only supply. If enabled in control RTC_MODE_PD, the power sequencer proceeds automatically from the POWERDOWN state to RTC mode. If the system supply is removed, DA9062 will also enter RTC mode. Supply recovery will trigger an exit from RTC mode automatically. DA9062 will exit RTC mode when nONKEY is asserted, or an RTC alarm is raised. GPIOs are not operational in RTC mode. 7.8.3 RESET Mode In RESET mode, the internal supplies, and LDO1 (if configured as an always-on supply) are enabled. All other DA9062 supplies are disabled. DA9062 is in RESET mode whenever a complete application shutdown is required. RESET mode can be triggered by the user, a host processor, or an internal event. RESET mode can be triggered by the user: ● from a long press of nONKEY (interruptible by host) defined by control SHUT_DELAY. ● by pressing a reset switch that is connected to port nRESETREQ (non-interruptible) RESET mode can be forced from the host processor (non-interruptible): ● by asserting nRESETREQ (falling edge) ● by writing to control SHUTDOWN DA9062 error conditions that force RESET mode (non-interruptible) are: ● no WATCHDOG write (WDKICK signal assertion) from the host inside the watchdog time window (if watchdog was enabled) ● an under-voltage detected on VSYS (VSYS < VDD_FAULT_LOWER) ● an internal junction over-temperature With the INT_SD_MODE, HOST_SD_MODE and KEY_SD_MODE controls, the shutdown sequences from internal fault, host or user triggered, are individually configured to either implement the reverse timing of the power-up sequence or transfer immediately to the RESET mode by skipping any delay from sequencer or dummy slot timers. For the host to determine the reason for the reset a FAULT_LOG register stores the root cause (either KEY_RESET or NRESETREQ). The host processor resets this register by writing asserted bits with ‘1’. KEY_SD_MODE = 1 triggers a complete power on reset (POR) (instead of entering RESET mode) after the related keys are pressed extendedly. If an OTP read is aborted, DA9062 enters RESET mode without an asserted bit inside register FAULT_LOG. A shutdown sequence to RESET mode will start with the assertion of the nRESET port. After the sequencer completes the power-down sequence (sequencer position 0), DA9062 continues to RESET mode with only the following active circuits: LDOCORE (at reduced output voltage 2.2 V), control interfaces and GPIOs, BCD counter, band-gap and over-temperature/VSYS comparators. All regulators, except for LDO1 and the backup battery charger, are automatically disabled to avoid battery drainage. As described in Section 7.1.3, nRESET is always asserted at the beginning of a shutdown sequence to RESET mode, and remains asserted when DA9062 is in RESET mode. When entering RESET mode, all user and system events are cleared. The DA9062’s register configuration will be re-loaded from OTP when leaving the RESET mode (with the exception of control AUTO_BOOT in case of a VDD_START fault). Datasheet Revision 3.3 43 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A FAULT_LOG, GP_ID_10 to GP_ID_19 and other non-OTP loaded registers, for example the RTC calendar and alarm, will not be changed when leaving the RESET mode. Some reset conditions such as writing a ‘1’ to control SHUTDOWN, a watchdog error, or a junction over-temperature will be automatically cleared. Other reset triggers, such as asserting nRESETREQ, need to be released to proceed from RESET to POWERDOWN mode. If the application requires regulators to discharge completely before a power-up sequence, a minimum duration of the RESET mode can be selected via RESET_DURATION. If the reset was initiated by a user’s long press of nONKEY, initially only KEY_RESET is set and the nIRQ port will be asserted. KEY_RESET signals the host that a shutdown sequence is started. If the host does not then clear KEY_RESET within 1 second by writing a ‘1’ to the related bit in register FAULT_LOG, the shutdown sequence will complete. When the reset condition has disappeared, DA9062 requires a supply (VSYS > VDD_FAULT_UPPER) that provides enough power to start-up from the POWERDOWN mode. RESET mode also allows automatic transition to RTC mode where all features of DA9062, except the RTC oscillator and calendar (including LDOCORE), are disabled. This mode is selected in control RTC_MODE_SD. 7.8.4 POWERDOWN Mode The POWERDOWN mode is a low-power state where most of the regulators are disabled. The transition from active to POWERDOWN mode (and vice versa) is handled by the programmable sequencer. Entry to POWERDOWN mode from ACTIVE mode is triggered by the de-assertion of SYSTEM_EN (either via SYS_EN or register access) or by a short press of nONKEY. The POWERDOWN mode is also passed during start-up and shutdown to RESET mode sequences. In POWERDOWN mode the internal supplies are enabled, and the control interface and GPIOs are operational. The power state machine features a retry counter that limits the number of transitions from POWERDOWN to ACTIVE under certain conditions. A watchdog timeout triggers POWERDOWN mode entry, but it does not necessarily clear the conditions that trigger a transition back to the ACTIVE mode. This could cause an endless loop between the ACTIVE and POWERDOWN modes. Therefore, after each watchdog timeout the retry counter is decremented, and after the retry counter reaches zero, DA9062 blocks all wakeup events and stays in POWERDOWN mode. This freeze function can be regarded as a substate of the POWERDOWN mode that is undetectable from outside the DA9062. Table 26 describes the state transitions with a level-sensitive wakeup and the freeze function. Table 26: State Transitions With a Level-Sensitive (LS) GPI Current State LS GPI SYS_EN PWR_EN Freeze Note 1 Next State POWERDOWN x x x 1 POWERDOWN POWERDOWN 0 0 x 0 POWERDOWN POWERDOWN x 1 0 0 SYSTEM POWERDOWN x 1 1 0 ACTIVE POWERDOWN 1 x 0 0 SYSTEM POWERDOWN 1 x 1 0 ACTIVE SYSTEM 0 0 x x POWERDOWN SYSTEM x 1 0 x SYSTEM SYSTEM x 1 1 x ACTIVE SYSTEM 1 x 0 x SYSTEM SYSTEM 1 x 1 x ACTIVE Datasheet Revision 3.3 44 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Current State LS GPI SYS_EN PWR_EN Freeze Note 1 Next State ACTIVE 0 0 x x POWERDOWN ACTIVE x 1 0 x SYSTEM ACTIVE x 1 1 x ACTIVE ACTIVE 1 x 0 x SYSTEM ACTIVE 1 x 1 x ACTIVE Note 1 In this table, “Freeze” represents the result of the comparison retry count = 0. The following events will reset the retry counter and release the state machine from the freeze state: ● De-assertion of all blocked level-sensitive wakeup conditions ● Entry to the RESET mode (over-temperature error, nRESETREQ or long press of nONKEY) ● Entry to the RTC mode (system supply error) The freeze operation is illustrated in Figure 21. Once the freeze state is cleared, DA9062 continues operating normally. The freeze function can be enabled in the FREEZE_EN register and the number of retries triggering the freeze can be configured in NFREEZE. Retry count 1 Power mode ACTIVE 0 NFREEZE POWERDOWN ACTIVE TWD_ERROR GPI The level sensitive wake-up condition is blocked The watchdog expires The retry count is decremented and reaches zero The level sensitive wake-up condition is de-asserted which resets the retry count The system operates normally upon the next wake-up event Figure 21: Freeze Function 7.8.5 Power-Up, Power-Down, and Shutdown Sequences The power-up, power-down, and shutdown sequences, see Figure 20, are handled by the power supply sequencer, see Section 7.9. All power-up sequences are identical, and the power-down sequences mirror the power-up sequences. The shutdown sequences are also identical to the power-down sequence, but after reaching POWERDOWN mode, the state machine automatically proceeds to RESET mode. The shutdown sequences caused by an internal error or nRESETREQ can be sped up from the INT_SD_MODE and HOST_SD_MODE controls: see Section 7.8.3. 7.8.6 ACTIVE Mode In the ACTIVE mode, all supplies and functions are active. The transition from POWERDOWN to ACTIVE mode is handled by the programmable sequencer. DA9062 enters ACTIVE mode after the sequence has completed and the watchdog is enabled (if configured to use watchdog). Status information can be read from the host processor via the 2-wire interface and DA9062 can flag interrupt requests to the host via a dedicated interrupt port (nIRQ). Datasheet Revision 3.3 45 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.9 Power Supply Sequencer DA9062 features a programmable Power Supply Sequencer that handles the system power-up, power-down, and shutdown sequences. The sequencer has a step-up counter, a timer that controls the step period, and a set of comparators that trigger power-on/off events at specific steps of the counter. The structure of the sequencer is depicted in Figure 22. The sequencer is composed of 16 steps, and the step time can be programmed between 32 µs and 8.192 ms. The sequencer will step until it reaches a programmable maximum value (MAX_COUNT), whereupon an interrupt is issued. At each step, the sequencer will enable all the functions that are pointing to that particular step. The power-up and -down sequences cannot be configured separately. When DA9062 is powering down, the sequencer will execute whatever was configured for the power-up sequence but in reverse order. Supplies can also be configured to stay on in POWERDOWN mode. In this case, the sequencer does not disable the regulator but switches to its B-configuration, see Section 7.5. If any pointer is programmed to a step higher than MAX_COUNT, the function is no longer controlled by the sequencer. Only the regulator control pointers (LDO<x>_STEP, BUCK<x>_STEP) are allowed to point to step 0. Setting any other pointer to step 0, effectively disables that function. POWERDOWN mode STANDBY mode ACTIVE mode Wake-up Watchdog alive System Power Power1 10 11 MAX_COUNT 12 13 14 15 BUCK4 9 BUCK3 8 POWER1_EN POWER_END 7 BUCK2 PD_DIS_STEP 6 BUCK1 WAIT_STEP 5 LDO4 4 LDO3 3 LDO2 2 LDO1 1 POWER_EN SYSTEM_END PART_DOWN SYSTEM_EN GPx_RISE 0 GPx_FALL OTPREAD_EN OTP_RD2 Figure 22: Structure of the Power Supply Sequencer Note STANDBY mode can only be reached on power-down, not power-up. Datasheet Revision 3.3 46 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.9.1 Sub-Sequences As illustrated in Figure 22, the sequencer is partitioned into three sub-sequences. These three subsequences can be used to define three power modes for the target application and to move between them in a controlled sequence as a response to control signals or register writes. The first sub-sequence starts from step 0 and ends at a step defined by the SYSTEM_END pointer. After the power-up is triggered, DA9062 performs a partial OTP read (OTP_RD2) if OTPREAD_EN is set. It then waits for control SYSTEM_EN to trigger the first sub-sequence. If SYSTEM_EN is already set in the OTP the first sub-sequence starts automatically after the power-up trigger. Alternatively, SYSTEM_EN can be asserted through the SYS_EN input. When the sequencer reaches the SYSTEM_END step the first sub-sequence is completed and the sequencer starts waiting for control POWER_EN to trigger the second sub-sequence. If POWER_EN is already set in the OTP, the sequencer does not stop after the first sub-sequence. Alternatively, POWER_EN can be asserted through the PWR_EN input or via a register access. The second sub-sequence starts from the step following SYSTEM_END and stops at a step defined by the POWER_END pointer. When the sequencer reaches the POWER_END step (and the watchdog is active), DA9062 enters ACTIVE mode. The final sub-sequence is triggered by asserting POWER1_EN via a register write. The third sub-sequence starts from the step following POWER_END and stops at a step defined by the MAX_COUNT pointer. If MAX_COUNT points to an earlier step than SYSTEM_END or POWER_END the remaining steps of the sequencer are disabled. The power-down sequences are executed in reverse order to the power-up sequences. If the powerdown sequence is triggered from the ACTIVE mode by de-asserting POWER_EN, the sequencer stops after reversing to the SYSTEM_END step. However, if the power-down sequence is triggered by de-asserting SYSTEM_EN, the sequencer does not stop and reverses back to step 0. Furthermore, if the power-down sequence is triggered by a watchdog timeout, the sequencer reverses to step 0 immediately. A partial power-down can be achieved by setting control STANDBY. This makes the sequencer stop at the step pointed to by the PART_DOWN pointer. The next power-up will then start from the PART_DOWN step, instead of step 0. The PART_DOWN pointer has to point to a step smaller than the SYSTEM_END pointer. 7.9.2 Regulator Control Each of DA9062’s buck converters and LDOs can be assigned to any of the sequencer steps. In general, when the sequencer reaches a step to which a regulator is assigned, that regulator is enabled by the sequencer. Likewise, when the sequencer reaches the same step on the way down, the regulator is disabled. Multiple supplies can point to the same counter step, however, enabling multiple regulators in the same slot can lead to increased in-rush currents. In the simplest scheme, the sequencer enables regulators during a power-up, and disables them during a power-down. This functionality is achieved by setting BUCK<x>_AUTO/LDO<x>_AUTO and clearing BUCK<x>_CONF/LDO<x>_CONF. Alternatively, the sequencer can be configured to keep the regulator enabled, but switch between the A and B settings in ACTIVE and POWERDOWN modes. The functionality of the BUCK<x>_AUTO/LDO<x>_AUTO and BUCK<x>_CONF/LDO<x>_CONF controls is summarized in Table 27. Datasheet Revision 3.3 47 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 27: Regulator Control Functionality of the Power Supply Sequencer Power-Up (Sequencer Direction Up) POWERDOWN Mode (Before) ACTIVE Mode (After) Auto Conf En Sel En Sel Sequencer Functionality 0 0 x x 0 0 The regulator is disabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. x 1 x x 1 0 1 x x x 1 0 The regulator is enabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. Power-Down (Sequencer Direction Down) ACTIVE Mode (Before) POWERDOWN Mode (After) Auto Conf En Sel En Sel x 0 x x 0 0 The regulator is disabled at the step pointed to by BUCK<x>_STEP/LDO<x>_STEP and the A-setting (VBUCK<x>_A/VLDO<x>_A) is activated. x 1 x x 1 1 The regulator stays enabled but it is switched to the B-setting (VBUCK<x>_B/VLDO<x>_B). Step 0 of the sequencer has a special meaning. If control DEF_SUPPLY is set, the sequencer treats all regulators pointing to step 0 as default supplies. This means that the regulators are enabled automatically when entering the POWERDOWN mode. Regulators assigned to other steps are only enabled after a wakeup condition occurs. Apart from this, step 0 acts the same as steps 1 to 15. If control DEF_SUPPLY is ‘0’, step 0 of the sequencer does not have any affect. As mentioned in Section 7.6.1, LDO1 can be programmed as an always-on supply. This is achieved by setting controls DEF_SUPPLY, LDO1_CONF, and LDO1_EN in the OTP. In normal operation, when the sequencer moves between ACTIVE and POWERDOWN modes, LDO1 behaves as presented in Table 27. However, if DA9062 moves to the RESET mode, this configuration keeps LDO1 enabled. This is not the case for any other regulator. 7.9.3 GPO Control Any GPO can be asserted or de-asserted in a sequencer step (GP_RISE<x>_STEP, GP_FALL<x>_STEP). The GPO control is summarized in Table 28. If a GPO is controlled by the sequencer, it is driven to its inactive state when DA9062 is in RESET mode. The GPIO control only works in sequencer steps greater than zero. Table 28: GPO Control Functionality of the Power Supply Sequencer GPIO<x>_MODE GPO State After Reset Sequencer Direction Previous GPO State GPO Transition At GP_RISE<x> GPO Transition At GP_FALL<x> 0 (active low) High Up High High to low - Low - Low to high High - High to low Low Low to high - High - High to low Low Low to high - High High to low - Low - Low to high Down 1 (active high) Low Up Down Datasheet Revision 3.3 48 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 7.9.4 Wait Step One of the sequencer steps (any step greater than zero) can be configured as a wait step, in which the sequencer stays until an event is detected in the GPI3 input, see Section 7.3.1.2. Note The E_GPI3 event has to be cleared after the power-up sequence completes. Otherwise, the wait step in the next power-up sequence will be ineffective. The wait step features an optional 500 ms timeout, which can be used when the wait event never occurs. If the timeout occurs, the steps following the wait step are not executed and a shutdown sequence to RESET mode is triggered. The shutdown reason is signalled with the WAIT_SHUT bit. Alternatively, the wait step can be used as a configurable delay in the sequence (WAIT_MODE, WAIT_TIME). 7.9.5 32 kHz Clock Output If a GPO is used as a 32 kHz clock output see Section 7.3.2.2, the clock buffer can be enabled/disabled in one of the sequencer steps (any step greater than zero). The clock buffer is enabled when, during power-up, the sequencer reaches the step EN32K_STEP. Likewise, the buffer is disabled when the sequencer reaches the step EN32K_STEP on the way down. 7.9.6 Power-Down Disable The PD_DIS_STEP pointer can be used to define a step in the power-up sequence above which a group of functions will be enabled. The functions concerned can be controlled in the PD_DIS register. Similarly, in the power-down sequence, the same groups of functions will be disabled when the sequencer proceeds below the PD_DIS_STEP. 7.10 Junction Temperature Supervision To protect DA9062 from damage due to excessive power dissipation, the junction temperature is continuously monitored. The monitoring is split into three thresholds TWARN (125 °C), TCRIT (140 °C), and TPOR (150 °C). If the junction temperature rises above the first threshold (TWARN), the event E_TEMP is asserted. If the event is not masked, this will issue an interrupt. This first level of temperature supervision is intended for non-invasive temperature control, where the necessary measures for cooling the system down are left to the host software. If the junction temperature increases even further and crosses the second threshold (T CRIT), the temperature error flag TEMP_CRIT (in register FAULT_LOG) is issued and a shutdown sequence to RESET mode is triggered, see Section 7.8.3. The nRESET output is asserted at the beginning of the shutdown sequence. Therefore, the second level of the temperature supervision does not rely on the host software to take counter-measures. The fault flag can be evaluated by the application after the next power-up. There is also a third temperature threshold (T POR) which causes DA9062 to enter RESET mode without any sequencing and stop all functions except the RTC. This prevents possible permanent damage due to fast temperature increases. 7.11 System Supply Voltage Supervision Two comparators supervise the system supply VSYS. One is monitoring the under-voltage level (VDD_FAULT_LOWER) and the other is indicating a good system supply (V DD_FAULT_UPPER). The VDD_FAULT_LOWER threshold is OTP configurable and can be set via the VDD_FAULT_ADJ control from 2.5 V to 3.25 V in 50 mV steps. The VDD_FAULT_UPPER threshold is also OTP configurable and can be set via the VDD_HYST_ADJ control from 100 mV to 450 mV higher than the VDD_FAULT_LOWER threshold. VSYS dropping below the VDD_FAULT_UPPER threshold asserts the event E_VDD_WARN. If the event is not masked, this will issue an interrupt, which can be used by the host processor as an indication to Datasheet Revision 3.3 49 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A decrease its activity. The status can also be signalled with a dedicated nVDD_FAULT signal, see Section 7.3.2.1. If VSYS drops below VDD_FAULT_LOWER, the supply error flag VDD_FAULT (in register FAULT_LOG) is asserted and a shutdown sequence to RESET mode is triggered, see Section 7.8.3. The nRESET output is asserted at the beginning of the shutdown sequence. 7.12 Backup Battery Charger The backup battery charger is designed to charge Lithium-Manganese coin cell batteries and super capacitors. The charger provides a constant charge current with a programmable target voltage. The charging current is programmable from 100 µA to 1000 µA in 100 µA steps and from 1 mA to 6 mA in 1 mA steps. The end-of-charge termination voltage is programmable in 100/200 mV steps from 1.1 V to 3.1 V. When enabled, the charger will always keep the backup battery charged at its target voltage. The backup battery charger can be temporarily disabled in POWERDOWN mode via control BBAT_DIS. The backup battery charger includes a reverse current protection and can also be used as an always-on supply for low-power rails. The backup battery provides an internal supply voltage for the 32 kHz crystal oscillator and RTC. 7.13 Real-Time Clock (RTC) The RTC provides a real-time clock and alarm function that can be supplied from the backup battery. RTC mode is described in Section 7.8.2. The RTC counter will count the number of 32 kHz clock periods, providing a seconds, minutes, hours, days, months, and years output. Year 0 corresponds to 2000. It is able to count up to 63 years. The value of the RTC calendar is read- and writeable via the 2-wire interface. A read of COUNT_S (seconds) saves the current RTC calendar count into registers COUNT_S to COUNT_Y. Registers are only valid when the RTC_READ status bit is asserted (assertion may take several ms from leaving POR). After MONITOR has been set, host writing to CRYSTAL and RTC_EN is prohibited to ensure that the RTC registers SECOND_A to SECOND_D are never stopped. There is an alarm register containing min, hrs, day, month, and year. When the RTC counter register value corresponds to the value set in the alarm an interrupt and a wakeup event are generated. The trigger will also set a bit in an event register to notify that an alarm has occurred. The alarm can alternatively be asserted from a periodic tick signal that, depending on control TICK_TYPE, is either asserted every second or minute. After modifying TICK_TYPE or TICK_WAKE, a write to register ALARM_Y is required to activate the new settings. The power manager controls, ALARM_ON and TICK_ON, enable/disable the alarm/tick. The power manager register bit MONITOR is set to 0 each time the RTC is powered up. Software sets this bit to ‘1’ when setting the time and date, which allows detection of a subsequent loss of the clock. Values written to the RTC calendar and alarm registers have to comply with the allowed value range (see register description, for example, less than 60 for seconds or minutes). 7.13.1 32 kHz Crystal Oscillator The oscillator is used to drive the real time clock (RTC) counter. It works with an external piezoelectric oscillator crystal at 32 kHz. The oscillator output can be fed to a GPIO and used as a clock source in the platform. The buffer can be enabled/disabled from a control register or with the power sequencer. In order to achieve the desired crystal frequency an external capacitor (10 pF to 20 pF, depending on the parasitic capacitance of the board) is connected to ground from each of the crystal pins. The start-up time of the oscillator is typically between 0.5 s and 1 s over the voltage range. When the crystal is not mounted, the XTAL pins should be grounded. The oscillator can be enabled from control CRYSTAL. A stabilisation timer can be used to blank the clock output during the start-up. The timer can be started simultaneously with the oscillator or it can be configured to wait until the clock’s duty cycle is within the range 30 % to 70 %. The start is Datasheet Revision 3.3 50 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A configured from the DELAY_MODE control and the stabilisation time is programmed in the STABILISATION_TIME control. OUT_CLOCK controls whether the clock feed to the OUT_32K output (GPIO) is affected by the stabilisation timer. The RTC_CLOCK control provides a similar gating function for the clock feed to the internal RTC counter. The clock feed to the OUT_32K output can be controlled with the power sequencer, as described in Section 7.9.5. In addition, the clock output is one of the features that can be disabled in the POWERDOWN mode, as described in Section 7.9.6. When the OUT32K_PAUSE control is set, the clock output is disabled in POWERDOWN. 7.14 Internal Oscillator An internal oscillator provides a nominal 6.0 MHz clock that is divided to 3.0 MHz for the buck converters. The frequency of the internal oscillator is adjusted during the initial start-up sequence of DA9062 to within 5 % of the nominal 6.0 MHz. Some applications require that the software is able to modify the oscillator frequency at runtime, for example to avoid interference effects caused by harmonics of the buck converter operating frequency. This can be achieved by writing a non-zero value to control OSC_FRQ. This control is a signed 4-bit value where each step changes the frequency by about 1.33 %, which gives a range from -10.65 % (-8) to +9.33 % (+7). The tolerance of this frequency will affect most absolute timer values and PWM repetition rates. 7.15 Watchdog The watchdog provides system monitoring functionality. A watchdog timeout triggers shutdown to POWERDOWN mode, signalled in register FAULT_LOG. The watchdog can also be configured to control a secondary reset output in addition to nRESET. This requires that one of the GPIOs is configured as a GPO, controlled by the sequencer. The assertion/de-assertion is used as a reset, and the GPIO is configured as a sequencer controlled GPO. This way, after the watchdog triggers the power-down, the reset output is asserted by the sequencer during the power-down sequence. Once enabled, the watchdog cannot be stopped and it runs in ACTIVE mode (this feature can be bypassed with an OTP configuration). The source clock of the watchdog is automatically chosen between the 32 kHz clock generated from the crystal oscillator and an internally generated slow frequency clock. After a cold boot, the watchdog is activated when entering ACTIVE mode. This first watchdog kick is required for DA9062 to move to the ACTIVE mode after a cold boot, as illustrated in Figure 20. After the watchdog is activated, the host must kick the watchdog periodically within the watchdog period programmed with the TWDSCALE control. An interrupt can be generated to warn the host processor of the watchdog timeout. The time for the warning interrupt is half of the watchdog period. The kick can be done by a register write to control WATCHDOG (reg. CONTROL_F) or with the GPIO0 pin configured as a WDKICK input. With control WDG_MODE = 1, the behavior of the WDKICK input is modified so that either a pulse or a permanently asserted input prevents a watchdog timeout. In this mode the parameter tWDMIN is not applicable. If the host processor fails to feed the watchdog, DA9062 asserts a fault bit and enters POWERDOWN mode. The watchdog timeout can also be configured to assert a reset output. This requires that one of the GPIOs is configured as a reset output and assigned to a power sequencer step, see Section 7.9. After each watchdog timeout a retry counter is decremented. If the retry counter reaches zero, DA9062 will stay in POWERDOWN mode, as described in Section 7.8.4. The number of allowed retries can be programmed in the NFREEZE control. Datasheet Revision 3.3 51 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 8 Register Map 8.1 Register Page Control The device register map is larger than the address range directly addressable from the host interface. The page control register provides the higher address bits and control for using the paging mechanism. There are several copies of this register, one per host interface. These copies are mirrored to addresses 0x080, 0x100 and 0x180. 8.2 Overview Table 29 provides a summary of the registers. A description of each register is provided in Appendix A. Table 29: Register Summary Address Name 7 6 5 REVERT WRITE_MODE PAGE 4 3 2 1 0 GPI4 GPI3 DVC_BUSY Reserved NONKEY GPI2 GPI1 GPI0 LDO4_ILIM LDO3_ILIM LDO2_ILIM LDO1_ILIM Page Control 0x000 PAGE_CON Power Manager Control and Monitoring · 0x001 STATUS_A 0x002 STATUS_B Reserved Reserved 0x004 STATUS_D Reserved 0x005 FAULT_LOG WAIT_SHUT NRESETREQ KEY_RESET TEMP_CRIT VDD_START VDD_FAULT POR TWD_ERROR 0x006 EVENT_A Reserved EVENTS_C EVENTS_B E_SEQ_RDY E_WDG_WARN Reserved E_ALARM E_NONKEY 0x007 EVENT_B E_VDD_WARN Reserved E_DVC_RDY Reserved E_LDO_LIM Reserved E_TEMP Reserved 0x008 EVENT_C Reserved E_GPI4 E_GPI3 E_GPI2 E_GPI1 E_GPI0 0x00A IRQ_MASK_A Reserved M_SEQ_RDY M_WDG_WARN Reserved M_ALARM M_NONKEY 0x00B IRQ_MASK_B M_VDD_WARN Reserved M_LDO_LIM Reserved M_TEMP Reserved 0x00C IRQ_MASK_C Reserved M_GPI4 M_GPI3 M_GPI2 M_GPI1 M_GPI0 M_SYSTEM_EN STANDBY POWER1_EN POWER_EN SYSTEM_EN NFREEZE nONKEY_LOCK NRES_MODE FREEZE_EN WATCHDOG_PD Reserved SLEW_RATE OTPREAD_EN AUTO_BOOT DEBOUNCING RTC_EN RTC_MODE_SD RTC_MODE_PD WAKE_UP SHUTDOWN WATCHDOG Reserved PMIF_DIS Reserved GPI_DIS IRQ Events IRQ Masks Reserved M_DVC_RDY System Control 0x00E CONTROL_A Reserved BUCK_SLOWST M_POWER1_EN M_POWER_EN 0x00F CONTROL_B 0x010 CONTROL_C DEF_SUPPLY 0x011 CONTROL_D Reserved 0x012 CONTROL_E V_LOCK 0x013 CONTROL_F Reserved 0x014 PD_DIS PMCONT_DIS OUT32K_PAUSE BBAT_DIS ART TWDSCALE Reserved CLDR_PAUSE GPIO Control 0x015 GPIO_0_1 GPIO1_WEN GPIO1_TYPE GPIO1_PIN GPIO0_WEN GPIO0_TYPE GPIO0_PIN 0x016 GPIO_2_3 GPIO3_WEN GPIO3_TYPE GPIO3_PIN GPIO2_WEN GPIO2_TYPE GPIO2_PIN 0x017 GPIO_4 Reserved GPIO4_WEN GPIO4_TYPE GPIO4_PIN 0x01C 0x01D GPIO_WKUP_ MODE GPIO_MODE0_ 4 Reserved Reserved 0x01E GPIO_OUT0_2 GPIO2_OUT 0x01F GPIO_OUT3_4 Reserved GPIO4_WKUP_M GPIO3_WKUP_M GPIO2_WKUP_MO GPIO1_WKUP_MO GPIO0_WKUP_MOD ODE ODE DE DE E GPIO4_MODE GPIO3_MODE GPIO2_MODE GPIO1_MODE GPIO0_MODE GPIO1_OUT GPIO0_OUT GPIO4_OUT GPIO3_OUT Power Supply Control 0x020 BUCK2_CONT Reserved VBUCK2_GPI Reserved BUCK2_CONF BUCK2_GPI BUCK2_EN 0x021 BUCK1_CONT Reserved VBUCK1_GPI Reserved BUCK1_CONF BUCK1_GPI BUCK1_EN 0x022 BUCK4_CONT Reserved VBUCK4_GPI Reserved BUCK4_CONF BUCK4_GPI BUCK4_EN 0x024 BUCK3_CONT Reserved VBUCK3_GPI Reserved BUCK3_CONF BUCK3_GPI BUCK3_EN 0x026 LDO1_CONT LDO1_CONF VLDO1_GPI Reserved LDO1_PD_DIS LDO1_GPI LDO1_EN 0x027 LDO2_CONT LDO2_CONF VLDO2_GPI Reserved LDO2_PD_DIS LDO2_GPI LDO2_EN 0x028 LDO3_CONT LDO3_CONF VLDO3_GPI Reserved LDO3_PD_DIS LDO3_GPI LDO3_EN 0x029 LDO4_CONT LDO4_CONF VLDO4_GPI Reserved LDO4_PD_DIS LDO4_GPI 0x032 DVC_1 VLDO4_SEL VLDO3_SEL VLDO1_SEL VBUCK3_SEL VBUCK4_SEL Datasheet VLDO2_SEL Revision 3.3 52 of 96 LDO4_EN VBUCK2_SEL VBUCK1_SEL 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Address Name 7 6 5 4 RTC_READ Reserved COUNT_SEC Reserved COUNT_MIN 3 2 1 0 RTC Calendar and Alarm 0x040 COUNT_S 0x041 COUNT_MI 0x042 COUNT_H Reserved COUNT_HOUR 0x043 COUNT_D Reserved COUNT_DAY 0x044 COUNT_MO Reserved 0x045 COUNT_Y Reserved 0x046 ALARM_S ALARM_STATUS ALARM_SEC 0x047 ALARM_MI Reserved ALARM_MIN 0x048 ALARM_H Reserved 0x049 ALARM_D Reserved 0x04A ALARM_MO Reserved 0x04B ALARM_Y TICK_ON 0x04C SECOND_A SECONDS_A 0x04D SECOND_B SECONDS_B 0x04E SECOND_C SECONDS_C 0x04F SECOND_D SECONDS_D COUNT_MONTH MONITOR COUNT_YEAR ALARM_HOUR ALARM_DAY TICK_WAKE ALARM_ON TICK_TYPE ALARM_MONTH ALARM_YEAR Power Sequencer 0x081 SEQ Reserved SEQ_POINTER 0x082 SEQ_TIMER SEQ_DUMMY SEQ_TIME 0x083 ID_2_1 LDO2_STEP LDO1_STEP 0x084 ID_4_3 LDO4_STEP LDO3_STEP 0x088 ID_12_11 PD_DIS_STEP Reserved 0x089 ID_14_13 BUCK2_STEP BUCK1_STEP 0x08A ID_16_15 BUCK3_STEP BUCK4_STEP 0x08D ID_22_21 GP_FALL1_STEP GP_RISE1_STEP 0x08E ID_24_23 GP_FALL2_STEP GP_RISE2_STEP 0x08F ID_26_25 GP_FALL3_STEP GP_RISE3_STEP 0x090 ID_28_27 GP_FALL4_STEP GP_RISE4_STEP 0x091 ID_30_29 GP_FALL5_STEP GP_RISE5_STEP 0x092 ID_32_31 EN32K_STEP WAIT_STEP 0x095 SEQ_A POWER_END SYSTEM_END 0x096 SEQ_B PART_DOWN 0x097 WAIT WAIT_DIR 0x098 EN_32K EN_32KOUT 0x099 RESET RESET_EVENT MAX_COUNT Reserved TIME_OUT WAIT_MODE WAIT_TIME OUT_CLOCK DELAY_MODE CRYSTAL STABILISATION_TIME RESET_TIMER Power Supply Control 0x09A BUCK_ILIM_A Reserved BUCK3_ILIM 0x09B BUCK_ILIM_B Reserved BUCK4_ILIM 0x09C BUCK_ILIM_C BUCK2_ILIM 0x09D BUCK2_CFG BUCK2_MODE BUCK2_PD_DIS Reserved 0x09E BUCK1_CFG BUCK1_MODE BUCK1_PD_DIS Reserved 0x09F BUCK4_CFG BUCK4_MODE BUCK4_PD_DIS BUCK4_VTT_EN 0x0A0 BUCK3_CFG BUCK3_MODE BUCK3_PD_DIS Reserved 0x0A3 VBUCK2_A BUCK2_SL_A VBUCK2_A 0x0A4 VBUCK1_A BUCK1_SL_A VBUCK1_A 0x0A5 VBUCK4_A BUCK4_SL_A VBUCK4_A 0x0A7 VBUCK3_A BUCK3_SL_A VBUCK3_A 0x0A9 VLDO1_A LDO1_SL_A Reserved VLDO1_A 0x0AA VLDO2_A LDO2_SL_A Reserved VLDO2_A 0x0AB VLDO3_A LDO3_SL_A Reserved VLDO3_A 0x0AC VLDO4_A LDO4_SL_A Reserved VLDO4_A 0x0B4 VBUCK2_B BUCK2_SL_B VBUCK2_B 0x0B5 VBUCK1_B BUCK1_SL_B VBUCK1_B 0x0B6 VBUCK4_B BUCK4_SL_B VBUCK4_B 0x0B8 VBUCK3_B BUCK3_SL_B VBUCK3_B 0x0BA VLDO1_B LDO1_SL_B Reserved VLDO1_B 0x0BB VLDO2_B LDO2_SL_B Reserved VLDO2_B 0x0BC VLDO3_B LDO3_SL_B Reserved VLDO3_B 0x0BD VLDO4_B LDO4_SL_B Reserved VLDO4_B BUCK1_ILIM BUCK4_VTTR_E N Reserved BBAT Charger Control Datasheet Revision 3.3 53 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Address Name 7 0x0C5 BBAT_CONT BCHG_ISET 6 5 4 3 2 1 0 PM_O_TYPE Reserved PM_I_V BCHG_VSET Customer Trim and Configuration 0x105 INTERFACE IF_BASE_ADDR 0x106 CONFIG_A Reserved PM_IF_HSM Reserved 0x107 CONFIG_B Reserved VDD_HYST_ADJ 0x108 CONFIG_C Reserved BUCK3_CLK_INV Reserved 0x109 CONFIG_D Reserved 0x10A CONFIG_E Reserved 0x10C CONFIG_G Reserved 0x10D CONFIG_H Reserved BUCK1_FCM BUCK2_FCM 0x10E CONFIG_I LDO_SD INT_SD_MODE 0x10F CONFIG_J IF_RESET TWOWIRE_TO 0x110 CONFIG_K Reserved 0x112 CONFIG_M OSC_FRQ PM_IF_FMP PM_IF_V IRQ_TYPE VDD_FAULT_ADJ BUCK4_CLK_INV BUCK1_CLK_INV FORCE_RESET Reserved BUCK_ACTV_DISC HRG Reserved SYSTEM_EN_RD NIRQ_MODE GPI_V Reserved BUCK4_AUTO BUCK2_AUTO BUCK1_AUTO LDO4_AUTO LDO3_AUTO LDO2_AUTO LDO1_AUTO BUCK_MERGE Reserved HOST_SD_MODE KEY_SD_MODE WATCHDOG_SD NONKEY_SD RESET_DURATION SHUT_DELAY BUCK3_AUTO Reserved GPIO4_PUPD NONKEY_PIN KEY_DELAY GPIO3_PUPD GPIO2_PUPD GPIO1_PUPD GPIO0_PUPD WDG_MODE Reserved Reserved Reserved Customer Device Specific 0x121 GP_ID_0 GP_0 0x122 GP_ID_1 GP_1 0x123 GP_ID_2 GP_2 0x124 GP_ID_3 GP_3 0x125 GP_ID_4 GP_4 0x126 GP_ID_5 GP_5 0x127 GP_ID_6 GP_6 0x128 GP_ID_7 GP_7 0x129 GP_ID_8 GP_8 0x12A GP_ID_9 GP_9 0x12B GP_ID_10 GP_10 0x12C GP_ID_11 GP_11 0x12D GP_ID_12 GP_12 0x12E GP_ID_13 GP_13 0x12F GP_ID_14 GP_14 0x130 GP_ID_15 GP_15 0x131 GP_ID_16 GP_16 0x132 GP_ID_17 GP_17 0x133 GP_ID_18 GP_18 0x134 GP_ID_19 GP_19 0x181 DEVICE_ID DEV_ID 0x182 VARIANT_ID MRC 0x183 0x184 CUSTOMER_I D CONFIG_ID Datasheet VRC CUST_ID CONFIG_REV Revision 3.3 54 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 9 Application Information 9.1 Component Selection The following recommended components are examples selected from requirements of a typical application. The final component selection will be dependent on the specific application. The electrical characteristics (for example, supported voltage/current range) have to be cross-checked and component types may need to be adapted from the individual needs of the target circuitry. 9.1.1 Resistors Table 30: Recommended Resistors Pin Value Tol. Size (mm) Rating (mW) Part IREF 200 kΩ ±1% 1005 100 Panasonic ERJ2RKF2003x 9.1.2 Capacitors Ceramic capacitors are used as bypass capacitors at all VDD and output rails. When selecting a capacitor, especially ones with high capacitance and small size, the DC bias characteristic has to be taken into account. On the VSYS main supply rail, a minimum distributed capacitance of 40 μF (actual capacitance after voltage and temperature derating) is required. Buck input capacitors should be within 1.5 mm distance from the supply pin, and the output capacitor should be close to the inductor. Table 31: Recommended Capacitors Pin Value Tol. Size (mm) Height (mm) Temp. Char. Rating (V) Part VLDO1 1 µF ±10% 1005 0.55 X5R 10 GRM155R61A105KE15 VLDOx 2.2 µF ±20% 1005 0.55 X5R 10 GRM155R60J225ME95# VBUCK3 2 x 22 µF ±20% 2012 0.95 X5R 6.3 GRM219R60J226M*** ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC ±20% 2012 0.95 X5R 4.0 GRM219R60G476M*** ±20% 1608 0.8 X5R 4.0 CL10A476MR8NZN ±20% 1608 1 X5R 6.3 GRM188R60J226MEA0 ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC ±20% 2012 0.95 X5R 4.0 GRM219R60G476M***61 ±20% 1608 0.8 X5R 4.0 CL10A476MR8NZN ±20% 1608 1 X5R 6.3 GRM188R60J226MEA0 ±20% 1005 0.5 X5R 4.0 CL05A226MR5NZNC ±20% 2012 0.95 X5R 4.0 GRM219R60G476M***61 ±20% 1608 0.8 X5R 4.0 CL10A476MR8NZN IOUT ≤ 1.5 A VBUCK3 IOUT > 1.5 A 2 x 47 µF VBUCK4 2 x 22 µF VBUCK4 2 x 47 µF (VTT mode) VBUCK1, VBUCK2 (half-current mode) 2 x 22 µF VBUCK1, VBUCK2 (full-current mode) 2 x 47 µF VSYS 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D VDD_BUCKx 2 x 22 µF ±20% 2012 1.25 X5R 10 LMK212BJ226MG-T 4 x 10 µF ±20% 1005 0.5 X5R 10 GRM155R61A106ME21 Datasheet Revision 3.3 55 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Pin Value Tol. Size (mm) Height (mm) Temp. Char. Rating (V) Part VDD_LDO2 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D VDD_LDO34 1 x 1 µF ±10% 1005 0.5 X5R 10 GRM155R61A105KE15D VBBAT 470 nF ±10% 1005 0.55 X5R 10 GRM155R61A474KE15# VDDCORE, VREF 2.2 µF ±20% 1005 0.55 X5R 6.3 GRM155R60J225ME95# XTAL_IN, XTAL_OUT 12 pF ±5% 1005 0.55 U2J 50 GRM1557U1H120JZ01# 9.1.3 Inductors Inductors should be selected based upon the following parameters: ● ISAT specifies the current causing a reduction in the inductance by a specific amount, typically 30 % ● IRMS specifies the current causing a temperature rise of a specific amount ● DC resistance (DCR) is critical for converter efficiency and should be therefore minimized. ● ESR at the buck switching frequency is critical to converter efficiency in PFM mode and should be therefore minimized. Inductance is given in Table 32. Table 32: Recommended Inductors Buck Value ISAT (A) IRMS (A) DCR (Typ. mΩ) Size (W×L×H) mm Part Buck1 and Buck2 (half-current mode), Buck3, Buck4 1 µH 2.7 2.3 55 2.0×1.6×1.0 Toko 1285AS-H-1R0M 2.65 2.45 60 2.0×1.6×1.0 Tayo Yuden MAKK2016T1R0M 2.9 2.2 60 2.0×1.6×1.0 TDK TFM201610A-1R0M Buck4 0.24 µH 1.65 2.3 43 1.6×0.8×1.0 Taiyo Yuden MBKK1608TR24N (VTT mode) 0.25 µH 9.7 11.45 7.64 4.0×4.0×1.2 Coilcraft XFL4012-251ME Buck1, Buck2 (full-current mode) 1 µH 3.4 3 60 2.5×2.0×1.0 Toko1269AS-H-1R0M 3.6 3.1 45 2.5×2.0×1.2 Tayo Yuden MAMK2520T1R0M 3.8 3.5 45 2.5×2.0×1.2 Toko 1239AS-H-1R0M 3.9 3.1 48 3.2×2.5×1.0 Toko1276AS-H-1R0M 3.5 2.5 54 2.5×2.0×1.0 TDK TFM252010A-1R0M 3.35 2.5 52 3.0×3.0×1.2 Cyntec PST031B-1R0MS 5.4 11 10.8 4.0×4.0×2.1 Coilcraft XFL4020-102ME 9.1.4 Crystal The real-time clock module requires an external 32.768 kHz crystal. For correct component selection, the effective load capacitance must to be taken into account. This includes external capacitors on pins XTAL_IN and XTAL_OUT in series combination, plus the PCB and stray capacitances. For example, if two 12 pF external capacitors are used, resulting in a total capacitance of 6 pF, and assuming the stray capacitances are 3 pF, then a crystal that specifies a load capacitance of 9 pF Datasheet Revision 3.3 56 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A should be chosen. Different stray capacitances may require different external capacitors and/or a different crystal type. Furthermore, the series resistance of the crystal must not exceed 100 kΩ. Table 33: Recommended Crystal Type Size (W×L×H) mm Manufacturer CC7V-T1A 32.768 kHz 9.0 pF ±30 ppm 3.2×1.5×0.9 Micro Crystal 9.1.5 Backup Battery The backup battery charger supports lithium coin cells as well as Supercaps/Goldcaps. Table 34: Recommended Backup Battery Type Size (mm) Manufacturer Lithium battery (rechargeable) ML414, 1.0 mAh, 3.1 V 4.8 (ø), 1.4 (h) Sanyo, Panasonic Starcap SC SM 2R8, 0.1 F, 2.8 V 4.8 (ø), 1.4 (h) Korchip Electric double layer capacitor (Gold Capacitor) EECEP0E333A, 0.033 F, 2.6 V 3.8 (ø), 1.5 (h) Panasonic 9.2 PCB Layout 2016 1005 1005 1005 2016 1608 VLX BUCK1 VDD BUCK1 VDD BUCK2 VLX BUCK2 TP LX1 VLDO1 GPIO4 VLDO2 GPIO3 1005 VDD LDO2 GPIO2 1005 IREF VBUCK2 1005 GND VREF 1005 CM7V-T1A VLX BUCK2 nIRQ nRST VSYS 1005 1005 Quiet ground VDDCO RE LX2 Quiet ground VBUCK1 XIN VBUCK3 VSS ANA VBUCK4 XOUT VDDIO VLDO3 GPIO1 VDD LDO34 GPIO0 VBUCK3 VLX BUCK3 VDD BUCK3 VDD BUCK4 VLX BUCK4 nRESET REQ nONKEY SCL SDA VBBAT 1005 VLDO4 1005 1005 2016 1608 1005 2016 1005 1005 VBUCK4 1608 Figure 23: PCB Layout for DA9062 Datasheet Revision 3.3 57 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 9.2.1 General Recommendations Appropriate trace width and quantity of vias should be used for all power supply paths. Too high trace resistances can prevent the system from achieving the best performance, for example, the efficiency and the current ratings of switching converters might be degraded. Furthermore, the PCB may be exposed to thermal hot spots, which can lead to critical overheating due to the positive temperature coefficient of copper. Special care must be taken with the DA9062 pad connections. The traces connecting the pads should of the same width as the pads and they should become wider as soon as possible. It is recommended to create a separate quiet ground to which the VREF capacitor, IREF resistor, and the crystal capacitors are connected. The PCB layout should ensure these component grounds are kept quiet, that is, they should be separated from the main ground return path for the noisy power ground. The quiet ground can then be connected to the main ground at the paddle, as shown in Figure 23. All traces carrying high discontinuous currents should be kept as short as possible. Noise sensitive analog signals, such as feedback lines or crystal connections, should be kept away from traces carrying pulsed analog or digital signals. This can be achieved by separation or shielding with quiet signals or ground traces. 9.2.2 LDOs and Switched Mode Supplies The placement of the distributed capacitors on the VSYS rail must ensure that all VDD inputs and VSYS are connected to a bypass capacitor close to the pad. It is recommended placing at least two 1 µF capacitors close to the VDD_LDOx pads and at least one 10 µF close to the VDD_BUCKx pads. Using a local power plane underneath the device for VSYS might be considered. Transient current loops in the area of the switching converters should be minimized. The common references (IREF, VREF) should be placed close to the device and cross-coupling to any noisy digital or analog trace must be avoided. Output capacitors of the LDOs can be placed close to the input pins of the supplied devices (remote from the DA9062). Care must be taken with trace routing to ensure that no current is carried on feedback lines of the buck output voltages (VBUCKx). The inductor placement is less critical since parasitic inductances have negligible effect. 9.2.3 32 kHz Crystal Oscillator The crystal and its load capacitors should be placed as close as possible to the IC with short and symmetrical traces. The traces must be isolated from noisy signals, especially from clocked digital ones. Ideally the lines should be buried between two ground layers, surrounded by additional ground traces. 9.2.4 Optimising Thermal Performance DA9062 features a ground paddle which should be connected with as many vias as possible to the PCB’s main ground plane in order to achieve good thermal performance. Solder mask openings for the ball landing pads must be arranged to prohibit solder balls flowing into vias. Datasheet Revision 3.3 58 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A 10 Ordering Information The ordering number consists of the part number followed by a suffix indicating the packing method. The “xx” represents a placeholder for the specific OTP variant. For details and availability, please consult Dialog Semiconductor’s customer portal or your local sales representative. Table 35: Ordering Information Part Number Package (mm) Package Description DA9062-xxAM1 QFN40, 6 x 6 Tray, 490 pcs DA9062-xxAM1-A QFN40, 6 x 6 Tray, 490 pcs DA9062-xxAM2 QFN40, 6 x 6 T&R, 4000 pcs DA9062-xxAM2-A QFN40, 6 x 6 T&R, 4000 pcs Datasheet Revision 3.3 59 of 96 Comment Automotive AEC-Q100 Grade 3 Automotive AEC-Q100 Grade 3 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Appendix A Register Descriptions This appendix describes the registers summarized in Section 8. A.1 PAGE 0 A.1.1 Page Control Table 36: PAGE_CON (0x000) Field Bit Type Description REVERT 7:7 R/W 0: PAGE switches the regmap page until rewritten. 1: PAGE reverts to 0 after one access. WRITE_MODE 6:6 R/W 2-WIRE sequential write style. 0: Write data to consecutive addresses 1: Write data to random addresses using address/data pairs PAGE 5:0 R/W The top 6 bits of the register address. For 2-WIRE, PAGE[0] is ignored. A.1.2 Power Manager Control and Monitoring Table 37: STATUS_A (0x001) Field Bit Type Description Reserved 7:3 R Reserved DVC_BUSY 2:2 R One or more DVC capable supplies are ramping Reserved 1:1 R Reserved NONKEY 0:0 R nONKEY level Table 38: STATUS_B (0x002) Field Bit Type Description Reserved 7:5 R Reserved GPI4 4:4 R GPI4 level GPI3 3:3 R GPI3 level GPI2 2:2 R GPI2 level GPI1 1:1 R GPI1 level GPI0 0:0 R GPI0 level Table 39: STATUS_D (0x004) Field Bit Type Description Reserved 7:4 R Reserved LDO4_ILIM 3:3 R LDO4 over-current indicator LDO3_ILIM 2:2 R LDO3 over-current indicator LDO2_ILIM 1:1 R LDO2 over-current indicator LDO1_ILIM 0:0 R LDO1 over-current indicator Datasheet Revision 3.3 60 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 40: FAULT_LOG (0x005) Field Bit Type Description WAIT_SHUT 7:7 R Note 1 Power-down due to sequencer WAIT_STEP timeout. See section 7.9.4 for further information. NRESETREQ 6:6 R Note 1 Power-down due to nRESETREQ pin or control SHUTDOWN. KEY_RESET 5:5 R Note 1 Power-down due to nONKEY TEMP_CRIT 4:4 R Note 1 Junction over-temperature VDD_START 3:3 R Note 1 Power-down due to VSYS under-voltage before or within 16 seconds after release of nRESET. VDD_FAULT 2:2 R Note 1 Power-down due to VSYS under-voltage. POR 1:1 R Note 1 DA9062 starts up from NO-POWER or RTC / DELIVERY mode. TWD_ERROR 0:0 R Note 1 Watchdog timeout Note 1 Cleared from the host by writing back the read value. A.1.3 IRQ Events Table 41: EVENT_A (0x006) Field Bit Type Description Reserved 7:7 R Reserved EVENTS_C 6:6 R Event in register EVENT_C is active. EVENTS_B 5:5 R Event in register EVENT_B is active. E_SEQ_RDY 4:4 R Note 1 Sequencer reached final position. E_WDG_WARN 3:3 R Note 1 Watchdog timeout warning E_TICK 2:2 R RTC tick E_ALARM 1:1 R Note 1 RTC alarm E_NONKEY 0:0 R Note 1 nONKEY event Note 1 Cleared from the host by writing back the read value. Datasheet Revision 3.3 61 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 42: EVENT_B (0x007) Field Bit Type Description E_VDD_WARN 7:7 R Note 1 VSYS under-voltage (VSYS < VDD_FAULT_UPPER) Reserved 6:6 E_DVC_RDY 5:5 Reserved 4:4 E_LDO_LIM 3:3 Reserved 2:2 E_TEMP 1:1 Reserved 0:0 Note 1 · R Reserved R Note 1 All supplies have finished DVC ramping · R Reserved R Note 1 LDO over-current · R Reserved R Note 1 Junction over-temperature (TJ > TWARN) · R Reserved Cleared from the host by writing back the read value. Table 43: EVENT_C (0x008) Field Bit Type Description Reserved 7:5 R Reserved E_GPI4 4:4 R Note 1 GPI4 event E_GPI3 3:3 R Note 1 GPI3 event E_GPI2 2:2 R Note 1 GPI2 event E_GPI1 1:1 R Note 1 GPI1 event E_GPI0 0:0 R Note 1 GPI0 event Note 1 Cleared from the host by writing back the read value. A.1.4 IRQ Masks Table 44: IRQ_MASK_A (0x00A) Field Bit Type Description Reserved 7:5 R/W Reserved M_SEQ_RDY 4:4 R/W IRQ mask for sequencer final position indication (E_SEQ_RDY) M_WDG_WARN 3:3 R/W IRQ mask for watchdog timeout warning (E_WDG_WARN) M_TICK 2:2 R/W IRQ mask for RTC tick event (E_TICK) M_ALARM 1:1 R/W IRQ mask for RTC alarm (E_ALARM) M_NONKEY 0:0 R/W IRQ mask for nONKEY event (E_NONKEY) Datasheet Revision 3.3 62 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 45: IRQ_MASK_B (0x00B) Field Bit Type Description M_VDD_WARN 7:7 R/W IRQ mask for under-voltage event (E_VDD_WARN) VSYS < VDD_FAULT_UPPER Reserved 6:6 M_DVC_RDY 5:5 Reserved 4:4 M_LDO_LIM 3:3 Reserved 2:2 M_TEMP 1:1 Reserved 0:0 · R Reserved / W R/W All supplies have finished DVC ramping. · R Reserved / W R/W IRQ mask for LDO over-current event (E_LDO_LIM) · R Reserved / W R/W IRQ mask for junction over-temperature event (E_TEMP) · R Reserved / W Table 46: IRQ_MASK_C (0x00C) Field Bit Type Description Reserved 7:5 R/W Reserved M_GPI4 4:4 R/W IRQ mask for GPI4 event (E_GPI4) M_GPI3 3:3 R/W IRQ mask for GPI3 event (E_GPI3) M_GPI2 2:2 R/W IRQ mask for GPI2 event (E_GPI2) M_GPI1 1:1 R/W IRQ mask for GPI1 event (E_GPI1) M_GPI0 0:0 R/W IRQ mask for GPI0 event (E_GPI0) A.1.5 System Control Table 47: CONTROL_A (0x00E) Field Bit Type Description Reserved 7:7 R/W Reserved M_POWER1_EN 6:6 R/W Write mask for POWER1_EN M_POWER_EN 5:5 R/W Write mask for POWER_EN M_SYSTEM_EN 4:4 R/W Write mask for SYSTEM_EN STANDBY 3:3 R/W Clearing control SYSTEM_EN or releasing SYS_EN (GPIO4 alternate function) or a long press of nONKEYwill: 0: Power-down to slot 0. 1: Power-down as far as defined by the PART_DOWN pointer. POWER1_EN 2:2 R/W Target status of power domain POWER1. Bus write masked with M_POWER1_EN. POWER_EN 1:1 R/W Target status of power domain POWER. Bus write masked with M_POWER_EN. SYSTEM_EN 0:0 R/W Target status of power domain SYSTEM. Bus write masked with M_SYSTEM_EN. Datasheet Revision 3.3 63 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 48: CONTROL_B (0x00F) Field Bit Type Description BUCK_SLOWSTART 7:7 R/W Enable buck slow start (reduced inrush current; increased start-up time). NFREEZE 6:5 R/W Block all wakeups after NFREEZE watchdog restart trials. nONKEY_LOCK 4:4 R/W 0: normal POWERDOWN mode 1: Power-down controlled by KEY_DELAY NRES_MODE 3:3 R/W If powering down / up:0: Keep nRESET not asserted 1: Assert / clear nRESET when entering / leaving POWERDOWN FREEZE_EN 2:2 R/W Enable watchdog restart limit NFREEZE. WATCHDOG_PD 1:1 R/W Watchdog timer is on (1) / off (0) in POWERDOWN mode. Reserved 0:0 R/W Reserved Table 49: CONTROL_C (0x010) Field Bit Type Description DEF_SUPPLY 7:7 R/W 1: OTP enables / disables all supplies (except LDOCORE) when sequencer enters slot 0. SLEW_RATE 6:5 R/W Buck DVC slew rate step width [10 mV/step (20 mV/step for Buck3)] 00: 4 µs 01: 2 µs 10: 1 µs 11: 0.5 µs OTPREAD_EN 4:4 R/W When leaving POWERDOWN mode supplies are configured from OTP. AUTO_BOOT 3:3 R/W After progressing from RESET mode, the sequencer: 0: requires a wakeup event to start up. 1: starts up automatically. DEBOUNCING 2:0 R/W GPI, nONKEY and nRESETREQ debounce time 000: no debouncing 001: 0.1 ms 010: 1.0 ms 011: 10.24 ms 100: 51.2 ms 101: 256 ms 110: 512 ms 111: 1024 ms Table 50: CONTROL_D (0x011) Field Bit Type Description Reserved 7:3 R/W Reserved TWDSCALE 2:0 R/W Watchdog timeout scaling: 0: Watchdog disabled Other: Timeout = 2.5 * 2^(TWDSCALE-1) s Datasheet Revision 3.3 64 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 51: CONTROL_E (0x012) Field Bit Type Description V_LOCK 7:7 R/W Prevent host from writing to registers 0x81 - 0x120 except 0x100. Reserved 6:3 R/W Reserved RTC_EN 2:2 R/W Enable Real Time Clock and alarm. RTC_MODE_SD 1:1 R/W Disable all supplies and blocks and LDOCORE if PSM enters RESET mode. RTC_MODE_PD 0:0 R/W Disable all supplies and blocks and LDOCORE if PSM enters POWERDOWN mode. Table 52: CONTROL_F (0x013) Field Bit Type Description Reserved 7:3 R/W Reserved WAKE_UP 2:2 R/W Wakeup from POWERDOWN mode. Cleared automatically. SHUTDOWN 1:1 R/W Power-down to RESET mode. Cleared automatically. WATCHDOG 0:0 R/W Reset watchdog timer. Cleared automatically. Table 53: PD_DIS (0x014) Field Bit Type Description PMCONT_DIS 7:7 R/W Disable SYS_EN, PWR_EN and PWR1_EN in POWERDOWN mode. OUT32K_PAUSE 6:6 R/W Disable OUT_32K in POWERDOWN mode. BBAT_DIS 5:5 R/W Disable backup battery charger in POWERDOWN mode. CLDR_PAUSE 4:4 R/W Disable calendar update in POWERDOWN mode. Reserved 3:3 R/W Reserved PMIF_DIS 2:2 R/W Disable 2-WIRE interface in POWERDOWN mode. Reserved 1:1 R/W Reserved GPI_DIS 0:0 R/W Disable E_GPI<x> events in POWERDOWN mode. Datasheet Revision 3.3 65 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.1.6 GPIO Control Table 54: GPIO_0_1 (0x015) Field Bit Type Description GPIO1_WEN 7:7 R/W 0: Passive-to-active transition triggers wakeup. 1: No wakeup GPIO1_TYPE 6:6 R/W GPI: active high (1) / low (0) GPIO1_PIN 5:4 R/W Function of GPIO1 pin (see GPIO1_OUT if output) 00: Reserved 01: Input (opt. regul. HW ctrl.) 10: Output (open drain) 11: Output (push-pull) GPIO0_WEN 3:3 R/W 0: Passive-to-active transition triggers wakeup. 1: No wakeup GPIO0_TYPE 2:2 R/W GPI: active high (1) / low (0) GPIO0_PIN 1:0 R/W Function of GPIO0 pin (see GPIO0_OUT if output) 00: Watchdog trigger input 01: Input 10: Output (open drain) 11: Output (push-pull) Table 55: GPIO_2_3 (0x016) Field Bit Type Description GPIO3_WEN 7:7 R/W 0: Passive-to-active transition triggers wakeup. 1: No wakeup GPIO3_TYPE 6:6 R/W GPI: active high (1) / low (0) GPIO3_PIN 5:4 R/W Function of GPIO3 pin (see GPIO3_OUT if output) 00: Reserved 01: Input (opt. regul. HW ctrl.) 10: Output (open drain) 11: Output (push-pull) GPIO2_WEN 3:3 R/W 0: Passive-to-active transition triggers wakeup. 1: No wakeup GPIO2_TYPE 2:2 R/W GPI: active high (1) / low (0) GPIO2_PIN 1:0 R/W Function of GPIO2 pin (see GPIO2_OUT if output) 00: GPI as PWR_EN 01: Input (opt. regul. HW ctrl.) 10: Output (open drain) 11: nVDD_FAULT Datasheet Revision 3.3 66 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 56: GPIO_4 (0x017) Field Bit Type Description Reserved 7:4 R/W Reserved GPIO4_WEN 3:3 R/W 0: Passive-to-active transition triggers wakeup. 1: No wakeup GPIO4_TYPE 2:2 R/W GPI: active high (1) / low (0) GPIO4_PIN 1:0 R/W Function of GPIO pad (see GPIO4_OUT if output) 00: GPI as SYS_EN 01: Input 10: Output (open drain) 11: Output (push-pull) Table 57: GPIO_WKUP_MODE (0x01C) Field Bit Type Description Reserved 7:5 R/W Reserved GPIO4_WKUP_MODE 4:4 R/W GPI4 wakeup is edge (0) / level (1) sensitive. GPIO3_WKUP_MODE 3:3 R/W GPI3 wakeup is edge (0) / level (1) sensitive. GPIO2_WKUP_MODE 2:2 R/W GPI2 wakeup is edge (0) / level (1) sensitive. GPIO1_WKUP_MODE 1:1 R/W GPI1 wakeup is edge (0) / level (1) sensitive. GPIO0_WKUP_MODE 0:0 R/W GPI0 wakeup is edge (0) / level (1) sensitive. Table 58: GPIO_MODE0_4 (0x01D) Field Bit Type Description Reserved 7:5 R/W Reserved GPIO4_MODE 4:4 R/W Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) GPIO3_MODE 3:3 R/W Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) GPIO2_MODE 2:2 R/W Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) GPIO1_MODE 1:1 R/W Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) GPIO0_MODE 0:0 R/W Output, STATIC: the output value Output, other: active low (0) / high (1) Input: debouncing off (0) / on (1) Datasheet Revision 3.3 67 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 59: GPIO_OUT0_2 (0x01E) Field Bit Type Description GPIO2_OUT 7:6 R/W GPIO output function 00: Static value according GPIO2_MODE 01: nVDD_FAULT 10: 32 kHz crystal clock (OUT_32K) 11: Sequencer controlled GPIO1_OUT 5:3 R/W GPIO output function 000: Static value according GPIO1_MODE 001: nVDD_FAULT 010: 32 kHz crystal clock (OUT_32K) 011: Sequencer controlled 100: Forward GPI0 101: Reserved 110: Forward GPI2 111: Forward GPI3 GPIO0_OUT 2:0 R/W GPIO output function 000: Static value according GPIO0_MODE 001: nVDD_FAULT 010: 32 kHz crystal clock (OUT_32K) 011: Sequencer controlled 100: Reserved 101: Forward GPI1 110: Forward GPI2 111: Forward GPI3 Table 60: GPIO_OUT3_4 (0x01F) Field Bit Type Description Reserved 7:5 R/W Reserved GPIO4_OUT 4:3 R/W GPIO output function 00: Static value according GPIO4_MODE 01: nVDD_FAULT 10: 32 kHz crystal clock (OUT_32K) 11: Sequencer controlled GPIO3_OUT 2:0 R/W GPIO output function 000: Static value according GPIO3_MODE 001: nVDD_FAULT 010: 32 kHz crystal clock (OUT_32K) 011: Sequencer controlled 100: Forward GPI0 101: Forward GPI1 110: Forward GPI2 111: Reserved Datasheet Revision 3.3 68 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.1.7 Power Supply Control Table 61: BUCK2_CONT (0x020) Field Bit Type Description Reserved 7:7 R/W Reserved VBUCK2_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) Reserved 4:4 R/W Reserved BUCK2_CONF 3:3 R/W Default supply, or sequenced and on in POWERDOWN BUCK2_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) BUCK2_EN 0:0 R/W Disable (0) / enable (1) the buck (dependent on on/off priority order), except in BUCK1/2 dual-phase mode Table 62: BUCK1_CONT (0x021) Field Bit Type Description Reserved 7:7 R/W Reserved VBUCK1_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved BUCK1_CONF 3:3 R/W Default supply, or sequenced and on in POWERDOWN BUCK1_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 BUCK1_EN 0:0 R/W Disable (0) / enable (1) the buck (dependent on on/off priority order) Datasheet Revision 3.3 69 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 63: BUCK4_CONT (0x022) Field Bit Type Description Reserved 7:7 R/W Reserved VBUCK4_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved BUCK4_CONF 3:3 R/W Default supply, or sequenced and on in POWERDOWN BUCK4_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 BUCK4_EN 0:0 R/W Disable (0) / enable (1) the buck (dependent on on/off priority order) Table 64: BUCK3_CONT (0x024) Field Bit Type Description Reserved 7:7 R/W Reserved VBUCK3_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VB*_B, act. to pas.: VB*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved BUCK3_CONF 3:3 R/W Default supply, or sequenced and on in POWERDOWN BUCK3_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 BUCK3_EN 0:0 R/W Disable (0) / enable (1) the buck (dependent on on/off priority order) Datasheet Revision 3.3 70 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 65: LDO1_CONT (0x026) Field Bit Type Description LDO1_CONF 7:7 R/W Default supply, or sequenced and on in POWERDOWN VLDO1_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved LDO1_PD_DIS 3:3 R/W Disable pull-down resistor when disabled. LDO1_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 LDO1_EN 0:0 R/W Disable (0) / enable (1) the LDO (dependent on on/off priority order) Table 66: LDO2_CONT (0x027) Field Bit Type Description LDO2_CONF 7:7 R/W Default supply, or sequenced and on in POWERDOWN VLDO2_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved LDO2_PD_DIS 3:3 R/W Disable pull-down resistor when disabled. LDO2_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 LDO2_EN 0:0 R/W Disable (0) / enable (1) the LDO (dependent on on/off priority order) Datasheet Revision 3.3 71 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 67: LDO3_CONT (0x028) Field Bit Type Description LDO3_CONF 7:7 R/W Default supply, or sequenced and on in POWERDOWN VLDO3_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved LDO3_PD_DIS 3:3 R/W Disable pull-down resistor when disabled. LDO3_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 LDO3_EN 0:0 R/W Disable (0) / enable (1) the LDO (dependent on on/off priority order) Table 68: LDO4_CONT (0x029) Field Bit Type Description LDO4_CONF 7:7 R/W Default supply, or sequenced and on in POWERDOWN VLDO4_GPI 6:5 R/W Voltage controlling GPI (passive to active transition: VLDO*_B, act. to pas.: VLDO*_A) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 Reserved 4:4 R/W Reserved LDO4_PD_DIS 3:3 R/W Disable pull-down resistor when disabled. LDO4_GPI 2:1 R/W Enabling GPI (passive to active transition: enable, act. to pas.: disable) 00: Sequencer controlled 01: Select GPI1 10: Select GPI2 11: Select GPI3 LDO4_EN 0:0 R/W Disable (0) / enable (1) the LDO (dependent on on/off priority order) Datasheet Revision 3.3 72 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 69: DVC_1 (0x032) Field Bit Type Description VLDO4_SEL 7:7 R/W Select VLDO4_A (0) / VLDO4_B (1). VLDO3_SEL 6:6 R/W Select VLDO3_A (0) / VLDO3_B (1). VLDO2_SEL 5:5 R/W Select VLDO2_A (0) / VLDO2_B (1). VLDO1_SEL 4:4 R/W Select VLDO1_A (0) / VLDO1_B (1). VBUCK3_SEL 3:3 R/W Select VBUCK3_A (0) / VBUCK3_B (1). VBUCK4_SEL 2:2 R/W Select VBUCK4_A (0) / VBUCK4_B (1). VBUCK2_SEL 1:1 R/W Select VBUCK2_A (0) / VBUCK2_B (1). VBUCK1_SEL 0:0 R/W Select VBUCK1_A (0) / VBUCK1_B (1). Datasheet Revision 3.3 73 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.1.8 RTC Calendar and Alarm Table 70: COUNT_S (0x040) Field Bit Type Description RTC_READ 7:7 R Indicates that RTC calendar is ready to be read by the host. Reserved 6:6 COUNT_SEC 5:0 · R Reserved R/W Calendar seconds Bus write is snapshot and updated on a write to COUNT_YEAR. Bus read loads RTC calendar into 0x104-0x109. Table 71: COUNT_MI (0x041) Field Bit Type Description Reserved 7:6 R Reserved COUNT_MIN 5:0 R/W Calendar minutes 0-59 Bus write is snapshot and updated on a write to COUNT_YEAR. Bus read is snapshot and updated on a read from COUNT_SEC. Table 72: COUNT_H (0x042) Field Bit Type Description Reserved 7:5 R Reserved COUNT_HOUR 4:0 R/W Calendar hours 0-23 Bus write is snapshot and updated on a write to COUNT_YEAR. Bus read is snapshot and updated on a read from COUNT_SEC. Table 73: COUNT_D (0x043) Field Bit Type Description Reserved 7:5 R Reserved COUNT_DAY 4:0 R/W Calendar days 1-31 Bus write is snapshot and updated on a write to COUNT_YEAR. Bus read is snapshot and updated on a read from COUNT_SEC. Table 74: COUNT_MO (0x044) Field Bit Type Description Reserved 7:4 R Reserved COUNT_MONTH 3:0 R/W Calendar months 1-12 Bus write is snapshot and updated on a write to COUNT_YEAR. Bus read is snapshot and updated on a read from COUNT_SEC. Datasheet Revision 3.3 74 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 75: COUNT_Y (0x045) Field Bit Type Description Reserved 7:7 R Reserved MONITOR 6:6 R/W Read: RTC power has been lost (0) / RTC clock okay (1). Write: RTC_EN and CRYSTAL writing enabled (0) / disabled (1). Fetched from VDDRTC domain at VDDCORE POR. If set, host writes to this register are ignored; thus the host cannot clear it. COUNT_YEAR 5:0 R/W Calendar year 2000 - 2063 Bus write turns on the RTC clock and sets RTC calendar. Bus read is snapshot and updated on a read from COUNT_SEC. Table 76: ALARM_S (0x046) Field Bit Type Description ALARM_STATUS 7:6 R Alarm reason 00: No alarm 01: Tick 10: Timer 11: Tick + Timer ALARM_SEC 5:0 R/W Alarm seconds 0-59 Bus write is snapshot and updated on a write to ALARM_YEAR. Table 77: ALARM_MI (0x047) Field Bit Type Description Reserved 7:6 R Reserved ALARM_MIN 5:0 R/W Alarm minutes 0-59 Bus write is snapshot and updated on a write to ALARM_YEAR. Table 78: ALARM_H (0x048) Field Bit Type Description Reserved 7:5 R Reserved ALARM_HOUR 4:0 R/W Alarm hours 0-23 Bus write is snapshot and updated on a write to ALARM_YEAR. Table 79: ALARM_D (0x049) Field Bit Type Description Reserved 7:5 R Reserved ALARM_DAY 4:0 R/W Alarm days 1-31 Bus write is snapshot and updated on a write to ALARM_YEAR. Datasheet Revision 3.3 75 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 80: ALARM_MO (0x04A) Field Bit Type Description Reserved 7:6 R Reserved TICK_WAKE 5:5 R/W Allows a tick to wake the chip from RTC mode TICK_TYPE 4:4 R/W Tick period 0: every second 1: every minute ALARM_MONTH 3:0 R/W Alarm months 1-12 Bus write is snapshot and updated on a write to ALARM_YEAR. Table 81: ALARM_Y (0x04B) Field Bit Type Description TICK_ON 7:7 R/W Enable the tick function. ALARM_ON 6:6 R/W Enable the alarm function. Alarm time is set with the ALARM_* registers ALARM_YEAR 5:0 R/W Alarm years 2000 - 2063 Table 82: SECOND_A (0x04C) Field Bit Type Description SECONDS_A 7:0 R RTC seconds counter least significant byte Table 83: SECOND_B (0x04D) Field Bit Type Description SECONDS_B 7:0 R RTC seconds counter byte Bus read is snapshot and updated on a read from SECONDS_A. Table 84: SECOND_C (0x04E) Field Bit Type Description SECONDS_C 7:0 R RTC seconds counter byte Bus read is snapshot and updated on a read from SECONDS_A. Table 85: SECOND_D (0x04F) Field Bit Type Description SECONDS_D 7:0 R RTC seconds counter most significant byte Bus read is snapshot and updated on a read from SECONDS_A. Datasheet Revision 3.3 76 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.2 PAGE 1 A.2.1 Power Supply Sequencer Table 86: SEQ (0x081) Field Bit Type Description Reserved 7:4 R/W Reserved SEQ_POINTER 3:0 R Actual power sequencer position Table 87: SEQ_TIMER (0x082) Field Bit Type Description SEQ_DUMMY 7:4 R/W Waiting time for power sequencer slots which do not have an associated power supply. 0000: 32 µs 0001: 64 µs 0010: 96 µs 0011: 128 µs 0100: 160 µs 0101: 192 µs 0110: 224 µs 0111: 256 µs 1000: 288 µs 1001: 384 µs 1010: 448 µs 1011: 512 µs 1100: 1.024 ms 1101: 2.048 ms 1110: 4.096 ms 1111: 8.192 ms SEQ_TIME 3:0 R/W Length of each sequencer time slot 0000: 32 µs 0001: 64 µs 0010: 96 µs 0011: 128 µs 0100: 160 µs 0101: 192 µs 0110: 224 µs 0111: 256 µs 1000: 288 µs 1001: 384 µs 1010: 448 µs 1011: 512 µs 1100: 1.024 ms 1101: 2.048 ms 1110: 4.096 ms 1111: 8.192 ms Datasheet Revision 3.3 77 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 88: ID_2_1 (0x083) Field Bit Type Description LDO2_STEP 7:4 R/W Sequencer step for LDO2 LDO1_STEP 3:0 R/W Sequencer step for LDO1 Table 89: ID_4_3 (0x084) Field Bit Type Description LDO4_STEP 7:4 R/W Sequencer step for LDO4 LDO3_STEP 3:0 R/W Sequencer step for LDO3 Table 90: ID_12_11 (0x088) Field Bit Type Description PD_DIS_STEP 7:4 R/W Sequencer step for PD_DIS register functionality. Reserved 3:0 R/W Reserved Table 91: ID_14_13 (0x089) Field Bit Type Description BUCK2_STEP 7:4 R/W Sequencer step for Buck2 BUCK1_STEP 3:0 R/W Sequencer step for Buck1 Table 92: ID_16_15 (0x08A) Field Bit Type Description BUCK3_STEP 7:4 R/W Sequencer step for Buck3 BUCK4_STEP 3:0 R/W Sequencer step for Buck4 Table 93: ID_22_21 (0x08D) Field Bit Type Description GP_FALL1_STEP 7:4 R/W Sequencer step to de-assert GPO0 GP_RISE0_STEP 3:0 R/W Sequencer step to assert GPO0 Table 94: ID_24_23 (0x08E) Field Bit Type Description GP_FALL2_STEP 7:4 R/W Sequencer step to de-assert GPO1 GP_RISE1_STEP 3:0 R/W Sequencer step to assert GPO1 Table 95: ID_26_25 (0x08F) Field Bit Type Description GP_FALL3_STEP 7:4 R/W Sequencer step to de-assert GPO2 GP_RISE2_STEP 3:0 R/W Sequencer step to assert GPO2 Datasheet Revision 3.3 78 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 96: ID_28_27 (0x090) Field Bit Type Description GP_FALL4_STEP 7:4 R/W Sequencer step to de-assert GPO3 GP_RISE3_STEP 3:0 R/W Sequencer step to assert GPO3 Table 97: ID_30_29 (0x091) Field Bit Type Description GP_FALL5_STEP 7:4 R/W Sequencer step to de-assert GPO4 GP_RISE4_STEP 3:0 R/W Sequencer step to assert GPO4 Table 98: ID_32_31 (0x092) Field Bit Type Description EN32K_STEP 7:4 R/W Sequencer step to enable GPO and RTC clock WAIT_STEP 3:0 R/W Sequencer step for WAIT register functionality Table 99: SEQ_A (0x095) Field Bit Type Description POWER_END 7:4 R/W End of POWER power domain in the sequencer SYSTEM_END <= POWER_END <= MAX_COUNT must be true. SYSTEM_END 3:0 R/W End of SYSTEM power domain in the sequencer PART_DOWN <= SYSTEM_END <= POWER_END must be true. Table 100: SEQ_B (0x096) Field Bit Type Description PART_DOWN 7:4 R/W Sequencer slot to stop at, when going down into STANDBY state. 1 <= PART_DOWN <= SYSTEM_END must be true. MAX_COUNT 3:0 R/W End of POWER1 power domain in the sequencer POWER_END <= MAX_COUNT must be true. Datasheet Revision 3.3 79 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 101: WAIT (0x097) Field Bit Type Description WAIT_DIR 7:6 R/W WAIT_STEP power sequence selection 00: Do not wait during WAIT_STEP of power sequencer except for normal slot time. 01: Wait during up sequence. 10: Wait during down sequence. 11: Wait during up and down sequence. TIME_OUT 5:5 R/W Timeout when WAIT_MODE = 0 0: no timeout when waiting for external signal (GPIO3). 1: 500 ms timeout when waiting for external signal (GPIO3). WAIT_MODE 4:4 R/W 0: Wait for external signal (GPIO3) to be active. 1: Start timer and wait for expiration. WAIT_TIME 3:0 R/W Wait timer during WAIT STEP of power sequencer (+/- 10%) 0000: Do not wait during WAIT_STEP of power sequencer except for normal slot time. 0001: 512 µs 0010: 1.0 ms 0011: 2.0 ms 0100: 4.1 ms 0101: 8.2 ms 0110: 16.4 ms 0111: 32.8 ms 1000: 65.5 ms 1001: 128 ms 1010: 256 ms 1011: 512 ms 1100: 1.0 s 1101: 2.0 s 1110: 4.1 s 1111: 8.2 s Datasheet Revision 3.3 80 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 102: EN_32K (0x098) Field Bit Type Description EN_32KOUT 7:7 R/W Enable OUT_32K on the GPOs (may be delayed depending on OUT32K_PAUSE). RTC_CLOCK 6:6 R/W Disable clock to RTC counter until stabilisation timer has expired. OUT_CLOCK 5:5 R/W Disable clock to GPOs configured as OUT_32K until stabilization timer has expired. DELAY_MODE 4:4 R/W Start stabilization timer: 0: when oscillator signal is available (third falling edge) 1: when oscillator has been switched on (CRYSTAL risen) CRYSTAL 3:3 R/W External RTC crystal is present. Fetched from VDDRTC domain at VDDCORE POR. STABILISATION_TIME 2:0 R/W Time to allow crystal oscillator to stabilize. 000: Delay off 001: 0.52 s 010: 1.0 s 011: 1.5 s 100: 2.1 s 101: 2.6 s 110: 3.1 s 111: 3.6 s Table 103: RESET (0x099) Field Bit Type Description RESET_EVENT 7:6 R/W Reset timer started by: 00: EXT_WAKEUP 01: SYS_UP (register control or pin) 10: PWR_UP (register control or pin) 11: Leaving PMIC RESET mode RESET_TIMER 5:0 R/W 0: Release nRESET immediately after the event selected by RESET_EVENT. 1 - 31: 1.024 ms * RESET_TIMER 32-63: 1.024 ms * 32 * (RESET_TIMER-31) Datasheet Revision 3.3 81 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.2.2 Power Supply Control Table 104: BUCK_ILIM_A (0x09A) Field Bit Type Description Reserved 7:4 R/W Reserved BUCK3_ILIM 3:0 R/W Buck3 current limit = (1700 + BUCK3_ILIM * 100) mA Table 105: BUCK_ILIM_B (0x09B) Field Bit Type Description Reserved 7:4 R/W Reserved BUCK4_ILIM 3:0 R/W Buck4 current limit = (700 + BUCK4_ILIM * 100) mA Table 106: BUCK_ILIM_C (0x09C) Field Bit Type Description BUCK2_ILIM 7:4 R/W Buck2 current limit = (700 + BUCK2_ILIM * 100) mA In full-current mode the limit is internally doubled. BUCK1_ILIM 3:0 R/W Buck1 current limit = (700 + BUCK1_ILIM * 100) mA In full-current mode the limit is internally doubled. Table 107: BUCK2_CFG (0x09D) Field Bit Type Description BUCK2_MODE 7:6 R/W Controls the mode of the buck: 00: Controlled by BUCK2_SL_A and BUCK2_SL_B 01: Sleep (PFM) 10: Synchronous (PWM) 11: Automatic BUCK2_PD_DIS 5:5 R/W Disable pull-down resistor when disabled. Reserved 4:0 R/W Reserved Table 108: BUCK1_CFG (0x09E) Field Bit Type Description BUCK1_MODE 7:6 R/W Controls the mode of the buck: 00: Controlled by BUCK1_SL_A and BUCK1_SL_B 01: Sleep (PFM) 10: Synchronous (PWM) 11: Automatic BUCK1_PD_DIS 5:5 R/W Disable pull-down resistor when disabled. Reserved 4:1 R/W Reserved Reserved 0:0 R/W Reserved Datasheet Revision 3.3 82 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 109: BUCK4_CFG (0x09F) Field Bit Type Description BUCK4_MODE 7:6 R/W Controls the mode of the buck: 00: Controlled by BUCK4_SL_A and BUCK4_SL_B 01: Sleep (PFM) 10: Synchronous (PWM) 11: Automatic BUCK4_PD_DIS 5:5 R/W Disable pull-down resistor when disabled. BUCK4_VTT_EN 4:4 R/W Enable Buck4 memory bus termination mode. BUCK4_VTTR_EN 3:3 R/W Enable Buck4 memory bus termination reference voltage output. Reserved 2:0 R/W Reserved Table 110: BUCK3_CFG (0x0A0) Field Bit Type Description BUCK3_MODE 7:6 R/W Controls the mode of the buck: 00: Controlled by BUCK3_SL_A and BUCK3_SL_B 01: Sleep (PFM) 10: Synchronous (PWM) 11: Automatic BUCK3_PD_DIS 5:5 R/W Disable pull-down resistor when disabled. Reserved 4:0 R/W Reserved Table 111: VBUCK2_A (0x0A3) Field Bit Type Description BUCK2_SL_A 7:7 R/W This control is only effective when BUCK2_MODE = 0 0: forced to synchronous mode (PWM) when 'A' setting is active. 1: forced to sleep mode (PFM) when 'A' setting is active. VBUCK2_A 6:0 R/W From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV Table 112: VBUCK1_A (0x0A4) Field Bit Type Description BUCK1_SL_A 7:7 R/W This control is only effective when BUCK1_MODE = 0 0: forced to synchronous mode (PWM) when 'A' setting is active. 1: forced to sleep mode (PFM) when 'A' setting is active. VBUCK1_A 6:0 R/W From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV Table 113: VBUCK4_A (0x0A5) Field Bit Type Description BUCK4_SL_A 7:7 R/W This control is only effective when BUCK4_MODE = 0 0: forced to synchronous mode (PWM) when 'A' setting is active. 1: forced to sleep mode (PFM) when 'A' setting is active. VBUCK4_A 6:0 R/W From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV Datasheet Revision 3.3 83 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 114: VBUCK3_A (0x0A7) Field Bit Type Description BUCK3_SL_A 7:7 R/W This control is only effective when BUCK3_MODE = 0 0: forced to synchronous mode (PWM) when 'A' setting is active. 1: forced to sleep mode (PFM) when 'A' setting is active. VBUCK3_A 6:0 R/W From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV Table 115: VLDO1_A (0x0A9) Field Bit Type Description LDO1_SL_A 7:7 R/W Force LDO sleep mode if VLDO1_A is active. Reserved 6:6 R/W Reserved VLDO1_A 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 116: VLDO2_A (0x0AA) Field Bit Type Description LDO2_SL_A 7:7 R/W Force LDO sleep mode if VLDO2_A is selected. Reserved 6:6 R/W Reserved VLDO2_A 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 117: VLDO3_A (0x0AB) Field Bit Type Description LDO3_SL_A 7:7 R/W Force LDO sleep mode if VLDO3_A is selected. Reserved 6:6 R/W Reserved VLDO3_A 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 118: VLDO4_A (0x0AC) Field Bit Type Description LDO4_SL_A 7:7 R/W Force LDO sleep mode if VLDO4_A is selected. Reserved 6:6 R/W Reserved VLDO4_A 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 119: VBUCK2_B (0x0B4) Field Bit Type Description BUCK2_SL_B 7:7 R/W This control is only effective when BUCK2_MODE = 0 0: forced to synchronous mode (PWM) when 'B' setting is active. 1: forced to sleep mode (PFM) when 'B' setting is active. VBUCK2_B 6:0 R/W From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV Datasheet Revision 3.3 84 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 120: VBUCK1_B (0x0B5) Field Bit Type Description BUCK1_SL_B 7:7 R/W This control is only effective when BUCK1_MODE = 0 0: forced to synchronous mode (PWM) when 'B' setting is active. 1: forced to sleep mode (PFM) when 'B' setting is active. VBUCK1_B 6:0 R/W From 0.3 V (0x00) to 1.57 V (0x7F) in steps of 10 mV Table 121: VBUCK4_B (0x0B6) Field Bit Type Description BUCK4_SL_B 7:7 R/W This control is only effective when BUCK4_MODE = 0 0: forced to synchronous mode (PWM) when 'B' setting is active. 1: forced to sleep mode (PFM) when 'B' setting is active. VBUCK4_B 6:0 R/W From 0.53 V (0x00) to 1.8 V (0x7F) in steps of 10 mV Table 122: VBUCK3_B (0x0B8) Field Bit Type Description BUCK3_SL_B 7:7 R/W This control is only effective when BUCK3_MODE = 0 0: forced to synchronous mode (PWM) when 'B' setting is active. 1: forced to sleep mode (PFM) when 'B' setting is active. VBUCK3_B 6:0 R/W From 0.80 V (0x00) to 3.34 V (0x7F) in steps of 20 mV Table 123: VLDO1_B (0x0BA) Field Bit Type Description LDO1_SL_B 7:7 R/W Force LDO sleep mode when ‘B’ setting is active. Reserved 6:6 R/W Reserved VLDO1_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 124: VLDO2_B (0x0BB) Field Bit Type Description LDO2_SL_B 7:7 R/W Force LDO sleep mode if VLDO2_B is selected. Reserved 6:6 R/W Reserved VLDO2_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Table 125: VLDO3_B (0x0BC) Field Bit Type Description LDO3_SL_B 7:7 R/W Force LDO sleep mode if VLDO3_B is selected. Reserved 6:6 R/W Reserved VLDO3_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V Datasheet Revision 3.3 85 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 126: VLDO4_B (0x0BD) Field Bit Type Description LDO4_SL_B 7:7 R/W Force LDO sleep mode if VLDO4_B is selected. Reserved 6:6 R/W Reserved VLDO4_B 5:0 R/W From 0.90 V (0x02) to 3.60 V (0x38) in steps of 50 mV Less than 0x02: 0.90 V; greater than 0x38: 3.60 V A.2.3 BBAT Charger Control Table 127: BBAT_CONT (0x0C5) Field Bit Type Description BCHG_ISET 7:4 R/W Charging current setting: 0000: Disabled 0001: 100 µA 0010: 200 µA 0011: 300 µA 0100: 400 µA 0101: 500 µA 0110: 600 µA 0111: 700 µA 1000: 800 µA 1001: 900 µA 1010: 1 mA 1011: 2 mA 1100: 3 mA 1101: 4 mA 1110: 5 mA 1111: 6 mA BCHG_VSET 3:0 R/W Termination voltage setting: 0000: Disabled 0001: 1.1 V 0010: 1.2 V 0011: 1.4 V 0100: 1.6 V 0101: 1.8 V 0110: 2.0 V 0111: 2.2 V 1000: 2.4 V 1001: 2.5 V 1010: 2.6 V 1011: 2.7 V 1100: 2.8 V 1101: 2.9 V 1110: 3.0 V 1111: 3.1 V Datasheet Revision 3.3 86 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A A.3 PAGE 2 A.3.1 Customer Trim and Configuration Table 128: INTERFACE (0x105) Field Bit Type Description IF_BASE_ADDR 7:4 R Note 1 2-WIRE slave address MSBs. The LSBs of the slave address are 3 “000”. The complete slave address is then IF_BASE_ADDR * 2 . 3 However, the device also responds to IF_BASE_ADDR * 2 +1. Reserved 3:0 Note 1 · R Reserved The interface configuration can be written/modified only for unmarked samples which do not have the control OTP_APPS_LOCK asserted/fused. Table 129: CONFIG_A (0x106) Field Bit Type Description Reserved 7:7 R Reserved PM_IF_HSM 6:6 R/W 2-WIRE interface permanently in high speed mode PM_IF_FMP 5:5 R/W 2-WIRE interface selects fast mode+ timings PM_IF_V 4:4 R/W 2-WIRE supplied from VDDCORE (0) / VDDIO (1). IRQ_TYPE 3:3 R/W nIRQ is active low (0) / high (1). PM_O_TYPE 2:2 R/W nRESET and nIRQ are push pull (0) / open drain (1). Reserved 1:1 R/W Reserved PM_I_V 0:0 R/W nRESETREQ, SYS_EN, PWR_EN and KEEPACT supplied from VDDCORE (0) / VDDIO (1). Table 130: CONFIG_B (0x107) Field Bit Type Description Reserved 7:7 R/W Reserved VDD_HYST_ADJ 6:4 R/W nVDD_FAULT comparator hysteresis from 100 mV (0x0) to 450 mV (0x7) in 50 mV steps VDD_FAULT_ADJ 3:0 R/W nVDD_FAULT comparator level from 2.5 V (0x0) to 3.25 V (0xF) in 50 mV steps Table 131: CONFIG_C (0x108) Field Bit Type Description Reserved 7:7 R/W Reserved BUCK3_CLK_INV 6:6 R/W Invert Buck3 clock polarity. Reserved 5:5 R/W Reserved BUCK4_CLK_INV 4:4 R/W Invert Buck4 clock polarity. BUCK1_CLK_INV 3:3 R/W Invert Buck1 clock polarity with respect to Buck2. BUCK_ACTV_DISCHRG 2:2 R/W Enable active discharging of buck rails. Reserved 1:0 R/W Reserved Datasheet Revision 3.3 87 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 132: CONFIG_D (0x109) Field Bit Type Description Reserved 7:6 R/W Reserved FORCE_RESET 5:5 R/W Keep nRESET always asserted Reserved 4:3 R/W Reserved SYSTEM_EN_RD 2:2 R/W Suppress loading SYSTEM_EN during OTP_RD2 NIRQ_MODE 1:1 R/W nIRQ will be asserted from events during POWERDOWN GPI_V 0:0 R/W GPIs, except power manager controls, supplied from VDDCORE (0) / VDDIO (1). Table 133: CONFIG_E (0x10A) Field Bit Type Description Reserved 7:5 R/W Reserved BUCK3_AUTO 4:4 R/W When powering up, enable and select VBUCK3_A. Reserved 3:3 R/W Reserved BUCK4_AUTO 2:2 R/W Enable and select VBUCK4_A when powering up. BUCK2_AUTO 1:1 R/W Enable and select VBUCK2_A when powering up. BUCK1_AUTO 0:0 R/W Enable and select VBUCK1_A when powering up. Table 134: CONFIG_G (0x10C) Field Bit Type Description Reserved 7:4 R/W Reserved LDO4_AUTO 3:3 R/W Enable and select VLDO4_A when powering up. LDO3_AUTO 2:2 R/W Enable and select VLDO3_A when powering up. LDO2_AUTO 1:1 R/W Enable and select VLDO2_A when powering up. LDO1_AUTO 0:0 R/W Enable and select VLDO1_A when powering up. Table 135: CONFIG_H (0x10D) Field Bit Type Description Reserved 7:7 R/W Reserved BUCK1_FCM 6:6 R/W Buck full-current mode (double pass device and current limit). BUCK2_FCM 5:5 R/W Buck full-current mode (double pass device and current limit). Reserved 4:4 R/W Reserved BUCK_MERGE 3:3 R/W Buck1/2 dual-phase configuration. Reserved 2:0 R/W Reserved Datasheet Revision 3.3 88 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 136: CONFIG_I (0x10E) Field Bit Type Description LDO_SD 7:7 R/W Enable switching off an LDO if an over-current is detected longer than 200 ms. INT_SD_MODE 6:6 R/W Skip sequencer and dummy slots on shutdown from internal fault. HOST_SD_MODE 5:5 R/W Skip sequencer and dummy slots on shutdown from control SHUTDOWN or nRESETREQ pin. KEY_SD_MODE 4:4 R/W Enable power-on reset on shutdown from nONKEY. WATCHDOG_SD 3:3 R/W Enable shutdown instead of power-down on watchdog timeout. NONKEY_SD 2:2 R/W Enable shutdown via long press of nONKEY. NONKEY_PIN 1:0 R/W nONKEY function See section 7.1.1 for further information. Table 137: CONFIG_J (0x10F) Field Bit Type Description IF_RESET 7:7 R/W Enable host interface reset via nRESETREQ pin TWOWIRE_TO 6:6 R/W Enable 35 ms timeout for 2-wire interfaces RESET_DURATION 5:4 R/W Minimum RESET mode duration: 00: 22 ms 01: 100 ms 10: 500 ms 11: 1 s SHUT_DELAY 3:2 R/W Shutdown delay (+ KEY_DELAY) for nONKEY KEY_DELAY 1:0 R/W nONKEY locking threshold Table 138: CONFIG_K (0x110) Field Bit Type Description Reserved 7:5 R/W Reserved GPIO4_PUPD 4:4 R/W GPI: pull-down enabled open drain GPO: pull-up enabled GPIO3_PUPD 3:3 R/W GPI: pull-down enabled open drain GPO: pull-up enabled GPIO2_PUPD 2:2 R/W GPI: pull-down enabled open drain GPO: pull-up enabled GPIO1_PUPD 1:1 R/W GPI: pull-down enabled open drain GPO: pull-up enabled GPIO0_PUPD 0:0 R/W GPI: pull-down enabled open drain GPO: pull-up enabled Datasheet Revision 3.3 89 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 139: CONFIG_M (0x112) Field Bit Type Description OSC_FRQ 7:4 R/W Adjust internal oscillator frequency: 1000: -10.67 % … 1111: -1.33 % 0000: 0.00 % 0001: +1.33 % … 0111: +9.33 % WDG_MODE 3:3 R/W Activate watchdog Halt operation mode. Reserved 2:2 R/W Reserved Reserved 1:1 R/W Reserved Reserved 0:0 R/W Reserved A.3.2 Customer Device Specific Table 140: GP_ID_0 (0x121) Field Bit Type Description GP_0 7:0 R/W General purpose register Note 1 Note 1 Initial value at start-up is the OTP ini file version number. Table 141: GP_ID_1 (0x122) Field Bit Type Description GP_1 7:0 R/W General purpose register Table 142: GP_ID_2 (0x123) Field Bit Type Description GP_2 7:0 R/W General purpose register Table 143: GP_ID_3 (0x124) Field Bit Type Description GP_3 7:0 R/W General purpose register Table 144: GP_ID_4 (0x125) Field Bit Type Description GP_4 7:0 R/W General purpose register Table 145: GP_ID_5 (0x126) Field Bit Type Description GP_5 7:0 R/W General purpose register Table 146: GP_ID_6 (0x127) Field Bit Type Description GP_6 7:0 R/W General purpose register Datasheet Revision 3.3 90 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 147: GP_ID_7 (0x128) Field Bit Type Description GP_7 7:0 R/W General purpose register Table 148: GP_ID_8 (0x129) Field Bit Type Description GP_8 7:0 R/W General purpose register Table 149: GP_ID_9 (0x12A) Field Bit Type Description GP_9 7:0 R/W General purpose register Table 150: GP_ID_10 (0x12B) Field Bit Type Description GP_10 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 151: GP_ID_11 (0x12C) Field Bit Type Description GP_11 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 152: GP_ID_12 (0x12D) Field Bit Type Description GP_12 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 153: GP_ID_13 (0x12E) Field Bit Type Description GP_13 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 154: GP_ID_14 (0x12F) Field Bit Type Description GP_14 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Datasheet Revision 3.3 91 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Table 155: GP_ID_15 (0x130) Field Bit Type Description GP_15 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 156: GP_ID_16 (0x131) Field Bit Type Description GP_16 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 157: GP_ID_17 (0x132) Field Bit Type Description GP_17 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 158: GP_ID_18 (0x133) Field Bit Type Description GP_18 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 159: GP_ID_19 (0x134) Field Bit Type Description GP_19 7:0 R/W General purpose register Note 1 Note 1 The value is persistent through a warm reset such as triggered by the nRESETREQ pin or by the SHUTDOWN control in register CONTROL_F. Table 160: DEVICE_ID (0x181) Field Bit Type Description DEV_ID 7:0 R Device ID Table 161: VARIANT_ID (0x182) Field Bit Type Description MRC 7:4 R Mask revision code VRC 3:0 R/W Chip variant code Table 162: CUSTOMER_ID (0x183) Field Bit Type Description CUST_ID 7:0 R Customer ID Table 163: CONFIG_ID (0x184) Field Bit Type Description CONFIG_REV 7:0 R OTP settings revision Datasheet Revision 3.3 92 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Revision History Table 164: Revision History Revision Date Changes 3.3 17-Nov-2016 Table 4: Recommended Operating Conditions ● Replaced ambient temperature parameter (TA) with junction temperature (TJ) Section 4: Electrical Characteristics ● Replaced ambient temperature parameter (TA) with junction temperature (TJ) Table 8: LDO1 Electrical Characteristics ● ● Renamed parameter IOUT to IOUT_MAX Revised conditions: ○ ○ VDROPOUT: Removed IOUT for VDD = 1.5 V condition VTR_LOAD: Added VLDO = 3.3 V ● Added TA to N, IQ_ON, and IQ_SLEEP conditions Table 9: LDO2, LDO3, LDO4 Electrical Characteristics ● ● Renamed parameter IOUT to IOUT_MAX Revised conditions: ○ ○ ○ VDD: Added VDD = VSYS IOUT_MAX and VDROPOUT: Added 1.8 V condition VTR_LOAD: Added VLDO = 3.3 V ● ● Added TA to IQ_ON and IQ_SLEEP conditions Added Note 1 Table 11: Buck1, Buck2 Electrical Characteristics ● Revised conditions: ○ ○ ○ ○ ○ ● ● IOUT: Removed inductor condition IQ_ON: Added VDD = 3.6 V and TA f: Added OSC_FRQ = ‘0000’ RPMOS and RNMOS: VSYS to VDD IAUTO_THR: VIN to VDD, RTRACK 45 mΩ VBUCK: Min from 0.7 V to 0.3 V Revised conditions and limits: ○ LBUCK: Removed half/full-current mode, Min = 0.7 µH ○ ○ ○ RL_DCR: Removed half/full-current mode, Typ = 55 mΩ IOUT: Removed half-current mode L > 0.6 µH ILIM: Split into half/full-current modes: Min/Max 700 mA/2200 mA and 1400 mA/4400 mA ● Added Note 1 and Note 3 Table 12: Buck3 Electrical Characteristics ● Revised conditions: ○ ○ ○ ○ ○ ● Datasheet VDD: Added VDD = VSYS IOUT: Removed inductor condition IQ_ON: Added TA f: Added OSC_FRQ = ‘0000’ RPMOS and RNMOS: VSYS to VDD Revised limits: ○ LBUCK: Min from 0.6 µH to 0.7 µH ○ RL_DCR: Min/Max from 80 mΩ/120 mΩ to 55 mΩ/100 mΩ Revision 3.3 93 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Revision Date Changes ○ ILIM: Min/Max from 1500 mA/3000 mA to 1700 mA/3200 mA ● Added Note 2 Table 13: Buck4 Electrical Characteristics ● Revised conditions: ○ ○ ○ ○ ○ ○ ○ ● VDD: Added VDD = VSYS IOUT: Removed inductor from condition and L > 0.6 µH condition IQ_ON: Added TA f: Added OSC_FRQ = ‘0000’ RPMOS and RNMOS: VSYS to VDD VBUCK_PFM: Removed output voltages below 0.7 V IAUTO_THR: VIN to VDD, RTRACK 45 mΩ Revised limits: ○ ILIM: Min/Max from 500 mA/2000 mA to 700 mA/2200 mA ○ ILIM_ACC: Split into 1400 mA/2200 mA, Min/Max: -15%/25% and -10%/15% ● Added Note 1 and Note 3 Table 16: Added Note 1 Table 18: Added Note 1 Table 19: Current Consumption Electrical Characteristics ● IDDRTC: ○ Revised condition from VSYS > 2.2 V to > 2.0 V and removed supplies and RTC condition ● Added Note 1 and Note 2 Section 7.1.2: Removed internal pull-up from description Section 7.7.8: New Section 7.14: Added application oscillator information Section 7.15: Revised WDKICK description Section 8: Register Map ● Table 29: CONFIG_A control names corrected to PM_IF_HSM, PM_IF_FMP, and PM_IF_V, added Reserved to reserved registers ● ● Table 41: Added E_TICK Table 44: Added M_TICK Appendix A: Updated part numbers, revised register descriptions, added register Type column Other: ● Datasheet Editorial changes Revision 3.3 94 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Revision Date Changes 3.2 17-Feb-2016 Table 3: Absolute Maximum Ratings ● replaced TA parameter with TJ ● replaced Note 1 ● ESD tolerance renamed to ESD protection HBM and moved the value to Min ● added ESD protection CDM parameters Table 4: Recommended Operating Conditions ● added Maximum power dissipation ● added Note 2 Table 5: Digital I/O Electrical Characteristics ● RPU: values aligned with characterisation results: ○ VDDIO = 1.5 V: Min value changed from 100 kΩ to 60 kΩ ○ ○ ○ ○ VDDIO = 1.5 V: Max value changed from 340 kΩ to 310 kΩ VDDIO = 1.8 V: Min value changed from 65 kΩ to 45 kΩ VDDIO = 1.8 V: Max value changed from 175 kΩ to 190 kΩ VDDIO = 3.3 V: Min value changed from 25 kΩ to 20 kΩ Table 10: LDOCORE Electrical Characteristics ● removed VDD parameter ● added VDROPOUT parameter ● added Note 1 and Note 2 ● added NOTE Table 11, Table 12, Table 13: Buck1 to Buck4 electrical characteristics ● VBUCK_ACC: added Note 1 Table 13: Buck4 Electrical Characteristics ● VTTR: removed IOUT test condition ● COUT: renamed to CVTTR Table 14: Backup Battery Charger Electrical Characteristics ● ISET_BCHG: removed 1 mA to 6 mA test condition ● added COUT, RCOUT_ESR, VDROPOUT parameters ● added Note 1 and Note 2 Table 17: System Supply Voltage Supervision Electrical Characteristics ● added Note 1 and Note 2 ● VDD_FAULT_LOWER: removed test condition ● VHYS: renamed to VDD_FAULT_HYS and removed test condition ● added VREF, CVREF, RIREF parameters Table 18: Junction Temperature Supervision Electrical Characteristics ● added Note 1 Figure 22: Structure of the Power Supply Sequencer ● added STANDBY mode ● added NOTE Register Map ● Table 29 CONFIG_A control names corrected to PM_IF_HSM, PM_IF_FMP, and PM_IF_V ● Table 49: SLEW_RATE: 20 mV/step for Buck3 added ● Table 105: BUCK_ILIM_B and BUCK4_ILIM: Note removed regarding full-current mode Other: ● REG_PAGE corrected to PAGE ● NSHUTDOWN corrected to NRESETREQ ● Editorial changes 3.1 Datasheet 30-Oct-2015 First production datasheet release Revision 3.3 95 of 96 24-Nov-2016 © 2016 Dialog Semiconductor DA9062 PMIC for applications requiring up to 8.5 A Status Definitions Revision Datasheet Status Product Status Definition 1.<n> Target Development This datasheet contains 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Specifications may be changed in any manner without notice. 2.<n> Preliminary Qualification This datasheet contains the specifications and preliminary characterization data for products in pre-production. Specifications may be changed at any time without notice in order to improve the design. 3.<n> Final Production This datasheet contains the final specifications for products in volume production. The specifications may be changed at any time in order to improve the design, manufacturing and supply. Major specification changes are communicated via Customer Product Notifications. Datasheet changes are communicated via www.dialog-semiconductor.com. 4.<n> Obsolete Archived This datasheet contains the specifications for discontinued products. The information is provided for reference only. Disclaimer Information in this document is believed to be accurate and reliable. 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Phone: +31 73 640 8822 Taiwan Dialog Semiconductor Taiwan Phone: +886 281 786 222 Korea Dialog Semiconductor Korea Phone: +82 2 3469 8200 Email: [email protected] Web site: www.dialog-semiconductor.com Datasheet Revision 3.3 96 of 96 24-Nov-2016 © 2016 Dialog Semiconductor