ON MTP52N06VLG Nâ channel power mosfet Datasheet

MTP52N06VL
Preferred Device
Power MOSFET
52 Amps, 60 Volts, Logic Level
N−Channel TO−220
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
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52 AMPERES, 60 VOLTS
RDS(on) = 25 mW
N−Channel
D
Features
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
• This is a Pb−Free Device*
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tp ≤ 10 ms)
VGS
VGSM
± 15
± 25
Vdc
Vpk
ID
ID
52
41
182
Adc
PD
188
1.25
W
W/°C
TJ, Tstg
−55 to 175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5 Vdc, Peak
IL = 52 Apk, L = 0.3 mH, RG = 25 W)
EAS
406
mJ
Thermal Resistance − Junction−to−Case
− Junction−to−Ambient
RqJC
RqJA
0.8
62.5
°C/W
TL
260
°C
Drain Current
− Continuous
− Continuous @ 100°C
− Single Pulse (tp ≤ 10 ms)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
IDM
MARKING DIAGRAM
AND PIN ASSIGNMENT
TO−220AB
CASE 221A
STYLE 5
Apk
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
4
Drain
4
1
2
MT
P52N06VLG
AYWW
3
1
Gate
A
Y
WW
G
2
Drain
3
Source
= Location Code
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping
MTP52N06VLG
TO−220AB
(Pb−Free)
50 Units/Rail
Preferred devices are recommended choices for future use
and best overall value.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 7
1
Publication Order Number:
MTP52N06VL/D
MTP52N06VL
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
−
65
−
−
Vdc
mV/°C
−
−
−
−
10
100
−
−
100
nAdc
1.0
−
1.5
4.5
2.0
−
Vdc
mV/°C
−
0.022
0.025
−
−
−
−
1.6
1.4
gFS
17
30
−
Mhos
Ciss
−
1900
2660
pF
Coss
−
550
770
Crss
−
170
340
td(on)
−
15
30
tr
−
500
1000
td(off)
−
100
200
tf
−
200
400
QT
−
62
90
Q1
−
4.0
−
Q2
−
31
−
Q3
−
16
−
−
−
1.03
0.9
1.5
−
trr
−
104
−
ta
−
63
−
tb
−
41
−
QRR
−
0.28
−
−
−
3.5
4.5
−
−
−
7.5
−
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = .25 mAdc)
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 3)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc)
IGSS
mAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
(Cpk ≥ 2.0) (Note 3)
VGS(th)
Static Drain−to−Source On−Resistance
(VGS = 5 Vdc, ID = 26 Adc)
(Cpk ≥ 2.0) (Note 3)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 5 Vdc, ID = 52 Adc)
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)
W
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
Rise Time
(VDD = 30 Vdc, ID = 52 Adc,
VGS = 5 Vdc, RG = 9.1 W)
Turn−Off Delay Time
Fall Time
Gate Charge (See Figure 8)
(VDS = 48 Vdc, ID = 52 Adc, VGS = 5 Vdc)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 52 Adc, VGS = 0 Vdc)
(IS = 52 Adc, VGS = 0 Vdc,
TJ = 150 °C)
Reverse Recovery Time
(IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
VSD
Vdc
ns
mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
LD
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
Max limit − Typ
3. Reflects typical values.
Cpk =
3 x SIGMA
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2
nH
nH
MTP52N06VL
TYPICAL ELECTRICAL CHARACTERISTICS
VGS = 10 V
I D , DRAIN CURRENT (AMPS)
8V
7V
90
80
70
60
4V
50
40
30
2
1
4
3
6
5
8
7
9
10
50
40
30
1.0
1.5
2.5
2
3
3.5
4
4.5
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
.060
.050
.040
TJ = 100°C
.030
25°C
.020
− 55°C
.010
10
20
30
40
50
60
70
80
90
100 110
.040
5.5
TJ = 25°C
.030
VGS = 5 V
.025
.020
10 V
.015
.010
.005
0
0
10
20
30
40
60
50
70
80
90
100 110
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.8
1.6
6
.035
1000
VGS = 5 V
ID = 26 A
VGS = 0 V
TJ = 125°C
1.4
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
25°C
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 5 V
0
70
60
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
.070
0
100°C
80
10
0
0.5
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
0
TJ = − 55°C
90
20
3V
10
0
VDS ≥ 10 V
100
5V
20
R DS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
110
TJ = 25°C
6V
I D , DRAIN CURRENT (AMPS)
110
100
1.2
1
0.8
0.6
100
100°C
10
0.4
0.2
0
− 50
− 25
0
25
50
75
100
125
150
1
175
0
TJ, JUNCTION TEMPERATURE (°C)
10
20
30
40
50
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
60
MTP52N06VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
8000
VDS = 0 V
C, CAPACITANCE (pF)
7000
VGS = 0 V
TJ = 25°C
Ciss
6000
5000
Crss
4000
3000
Ciss
2000
Coss
1000
0
Crss
10
5
5
0
VGS
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
30
QT
9
27
8
24
VGS
7
21
6
18
Q2
Q1
5
15
4
12
3
9
ID = 52 A
TJ = 25°C
2
1
0
Q3
0
10
3
VDS
20
6
30
40
50
QT, TOTAL CHARGE (nC)
0
70
60
1000
t, TIME (ns)
10
VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
MTP52N06VL
VDD = 30 V
ID = 52 A
VGS = 5 V
TJ = 25°C
100
tr
tf
td(off)
10
td(on)
1
1
10
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
55
I S , SOURCE CURRENT (AMPS)
50
45
VGS = 0 V
TJ = 25°C
40
35
30
25
20
15
10
5
0
0.5 0.55
0.6 0.65
0.7 0.75
0.8 0.85
0.9 0.95
1
1.05
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTP52N06VL
SAFE OPERATING AREA
450
VGS = 15 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
1000
10ms
100
100ms
1ms
10
10ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
dc
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.1
ID = 52 A
400
350
300
250
200
150
100
50
0
100
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
175
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.2
0.1
0.1 0.05
P(pk)
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E+00
1.0E+01
MTP52N06VL
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AB
−T−
B
F
SEATING
PLANE
C
T
S
4
A
Q
1 2 3
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.020
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
0.508
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
E−FET is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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