MPM3630 18V/3A DC/DC Module Synchronous Step-Down Regulator with Integrated Inductor DESCRIPTION FEATURES The MPM3630 is a synchronous rectified, stepdown module regulator with built-in power MOSFETs, inductor, and two capacitors. It offers a very compact solution to achieve a 3A continuous output current with excellent load and line regulation over a wide input supply range. The MPM3630 has a 1.4MHz switching frequency, which provides fast load transient response. Full protection features include over-current protection (OCP) and thermal shutdown (TSD). The MPM3630 eliminates manufacturing risks while improving time-to-market. design and dramatically Complete Switch Mode Power Supply 4.5V to 18V Wide Operating Input Range 3A Continuous Load Current 50mΩ/22mΩ Low RDS(ON) Internal Power MOSFETs Integrated Inductor Fixed 1.4MHz Switching Frequency 1MHz-2MHz Frequency Sync Internal Power Save Mode for Light Load Power Good Indicator OCP Protection and Hiccup Thermal Shutdown Output Adjustable from 0.6V Available in QFN20 (3x5x1.6mm) Package APPLICATIONS The MPM3630 is available in a space-saving QFN20 (3mmx5mmx1.6mm) package. Industrial Controls Medical and Imaging Equipment Telecom Applications LDO Replacement Space and Resource-Limited Applications Distributed Power Systems All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION BST VOUT 3.3V/3A SW VIN 12V IN C1 22µF EN R3 100k MPM3630 OUT C2 22µFx2 EN/SYNC R1 51k FB VCC NC PG PGND R2 11.3k AGND MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 1 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR ORDERING INFORMATION Part Number* Package QFN-20 (3mmx5mmx1.6mm) MPM3630GQV Top Marking See Below * For Tape & Reel, add suffix –Z (e.g. MPM3630GQV–Z) TOP MARKING MP: MPS prefix Y: Year code W: Week code 3630: First four digits of the part number LLL: Lot number M: Module PACKAGE REFERENCE EN/ PG SYNC IN 18 FB 1 VCC 2 17 16 19 NC PGND PGND 15 14 13 12 PGND 11 BST 10 NC 20 AGND 3 SW 4 9 OUT SW 5 8 OUT SW 6 7 OUT NC NC All “NC” pins must be left floating MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 2 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance VIN ................................................ -0.3V to 20V VOUT ............................................... -0.3V to 20V VSW .................................................................... -0.3V (-5V for <10ns) to 20V (22V for <10ns) VBST ....................................................VSW+5.5V All other pins ..............................-0.3V to 5.5V (2) (3) Continuous power dissipation (TA = +25°C) ............................................................2.7W Junction temperature ............................... 150°C Lead temperature .................................... 260°C Storage temperature .................. -65°C to 150°C QFN-20 (3mmx5mmx1.6mm) . 46 ...... 10 ... °C/W Recommended Operating Conditions (4) Supply voltage (VIN) ........................ 4.5V to 18V Output voltage (VOUT) …………………………….. ………………………...……...0.6V to VIN *DMAX (5) Operating junction temp. (TJ). .. -40°C to +125°C (6) θJA θJC Notes: 1) Exceeding these ratings may damage the device. 2) For additional details on EN pin’s ABS MAX rating, please refer to the “Enable/SYNC Control” section. 3) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/θJA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 4) The device is not guaranteed to function outside of its operating conditions. 5) In practical design, the minimum VOUT is limited by the minimum on-time. To allow a margin, a 50ns on-time is recommended for calculating. To set the output voltage above 5.5V, please refer to the application information. 6) Measured on JESD51-7, 4-layer PCB. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 3 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR ELECTRICAL CHARACTERISTICS VIN = 12V, TJ = -40°C to +125°C(7), typical value is tested at TJ = 25°C, unless otherwise noted. Parameter Symbol Supply current (shutdown) Supply current (quiescent) HS switch on resistance LS switch on resistance Inductor DC resistance Switch leakage (8) Current limit Oscillator frequency Foldback frequency Maximum duty cycle (8) Minimum on time Feedback voltage Feedback voltage Feedback current IIN Iq HSRDS-ON LSRDS-ON LDCR SW LKG ILIMIT fSW fFB DMAX τON_MIN VFB VFB IFB Condition Min VEN = 0V VFB = 0.7V VBST-SW = 5V VCC = 5V VEN = 0V, VSW = 0V 30% Duty cycle VFB = 0.5V VFB = 200mV VFB = 500mV TA = 25°C 5 1100 85 Typ Max Units 5.5 320 50 22 40 8 420 μA μA mΩ mΩ mΩ 1 μA A kHz fSW % ns 6.5 1400 0.4 90 50 1600 594 591 600 600 10 606 609 50 mV mV nA VFB = 620mV EN Rising threshold VEN_RISING 1.2 1.4 1.6 V EN Falling threshold VEN_FALLING 1.1 1.25 1.4 V EN input current IEN (8) EN turn off delay VEN = 2V ENTd-off SYNC frequency range μA 2.5 μs 1000 VIN under-voltage lockout threshold—rising INUVVth VIN under-voltage lockout threshold—hysteresis INUVHYS PG rising threshold PG falling threshold PG rising delay PG falling delay PG sink current capability PG leakage current VCC regulator PGVth-Hi PGVth-Lo PGTd PGTd VPG IPG-LEAK VCC VCC load regulation Soft-start time 1.8 tSS 3.9 4.1 2000 kHz 4.3 V 740 0.87 0.76 Rising edge Falling edge Sink 2mA 4.5V ICC = 5mA VOUT from 10% to 90% (8) Thermal shutdown (8) Thermal hysteresis 0.92 0.81 110 26 mV 0.97 0.86 VFB VFB μs 0.4 V μA V 3 % 2 5 2.2 ms 150 20 °C °C Notes: 7) Not tested in production. Guaranteed by over-temperature correlation. 8) Guaranteed by engineering sample characterization test. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 4 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR TYPICAL CHARACTERISTICS VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted. w MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 5 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR TYPICAL CHARACTERISTICS (continued) VIN = 12V, VOUT = 3.3V, TA = 25°C, unless otherwise noted. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 6 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are captured from the evaluation board discussed in the Design Example section.VIN = 12V, VOUT = 3.3V, COUT = 22µFx2, TA = 25°C, unless otherwise noted. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 7 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR TYPICAL PERFORMANCE CHARACTERISTICS Performance waveforms are captured from the evaluation board discussed in the Design Example section.VIN = 12V, VOUT = 3.3V, COUT = 22µFx2, TA = 25°C, unless otherwise noted. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 8 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR PIN FUNCTIONS Package Pin # Name 1 FB 2 VCC 3 AGND 4, 5, 6 SW 7, 8, 9 10, 15, 19, 20 OUT 11 12, 13, 14 16 17 18 NC Description Feedback. Connect FB to the tap of an external resistor divider from the output to AGND to set the output voltage. To prevent current-limit runaway during a short-circuit fault, the frequency foldback comparator lowers the oscillator frequency when the FB voltage is below 240mV. Place the resistor divider as close as possible to FB. Avoid placing vias on the FB traces. Internal 5V LDO output. The internal circuit integrates an LDO output capacitor, so there is no need to add an external capacitor. Analog ground. Reference ground of the logic circuit. AGND is connected internally to PGND. There is no need to add external connections to PGND. Switch Output. There is no needed connection for the SW pins, but a large copper plane is recommended on pins 4, 5, and 6 for improved heat sink. Power output. Connect the load to OUT. An output capacitor is needed. DO NOT CONNECT. NC must be left floating. Bootstrap. The bootstrap capacitor is integrated internally. There is no need for external connections. Power ground. Reference ground of the power device. PCB layout requires extra care PGND (see Page 15). For best results, connect to PGND with copper and vias. Supply voltage. IN supplies power for the internal MOSFET and regulator. The MPM3630 operates from a +4.5V to +18V input rail. It requires a low ESR and lowIN inductance capacitor to decouple the input rail. Place the input capacitor very close to IN and connect it with wide PCB traces and multiple vias. Enable/Sync. EN = high to enable the module. Floating EN or connecting it to ground EN/SYN will disable the converter. Apply an external clock to EN to change the switching C frequency. Power good indicator. Open drain structure. PG BST MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 9 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR FUNCTIONAL BLOCK DIAGRAM EN/SYNC OUT 55pF AGND PG PGND Figure 1: Functional Block Diagram MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 10 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR OPERATION The MPM3630 is a high frequency, synchronous, rectified, step-down, switch-mode converter with built-in power MOSFETs, integrated inductor, and two capacitors. It offers a very compact solution that achieves a 3A continuous output current with excellent load and line regulation over a 4.5V to 18V input supply range. The MPM3630 has three working modes: advanced asynchronous modulation (AAM), similar to PFM mode, discontinuous conduction mode (DCM), and continuous conduction mode (CCM). The load current increases as the device transitions from AAM mode to DCM to CCM. AAM Operation In a light-load condition, the MPM3630 operates in AAM mode (see Figure 2). VCOMP is the erroramplifier output, which represents the peak inductor current information. When VCOMP is lower than VAAM, the internal clock is blocked. This causes the MPM3630 to skip pulses, achieving the light-load power save. Refer to AN032 for additional details. The internal clock re-sets every time VCOMP exceeds VAAM. Simultaneously, the high-side MOSFET (HS-FET) turns on and remains on until VILsense reaches the value set by VCOMP. until the inductor-current value decreases to zero. The device repeats the same operation in every clock cycle to regulate the output voltage (see Figure 3). HS-FET is on HS/LS-FETs are off VSW VOUT LS-FET is on A Clock Cycle IL IOUT Zero Current Detect Figure 3: DCM Control Operation CCM Control Operation The device enters CCM from DCM once the inductor current no longer drops to zero in a clock cycle. In CCM, the internal 1.4MHz clock initiates the PWM cycle, the HS-FET turns on and remains on until VILsense reaches the value set by VCOMP (after a period of dead time), and then the LS-FET turns on and remains on until the next clock cycle starts. The device repeats the same operation in every clock cycle to regulate the output voltage. If VILsense does not reach the value set by VCOMP within 90% of one PWM period, the HS-FET will be forced off. Internal VCC Regulator 55pF 4 R1 17.5k R2 Figure 2: Simplified AAM Control Logic DCM Control Operation The VCOMP ramps up as the output current increases. When its minimum value exceeds VAAM, the device enters DCM. In this mode the internal 1.4MHz clock initiates the PWM cycle, the HS-FET turns on and remains on until VILsense reaches the value set by VCOMP (after a period of dead time), and then the low-side MOSFET (LS-FET) turns on and remains on A 5V internal regulator powers most of the internal circuitries. This regulator takes VIN and operates in the full VIN range. After EN pulls high, when VIN exceeds 5V, the output of the regulator is in full regulation. When VIN is less than 5V, the output decreases, and the part integrates an internal decoupling capacitor. There is no need to add an external VCC output capacitor. Error Amplifier (EA) The error amplifier compares the FB pin voltage to the internal 0.6V reference (VREF) and outputs a current proportional to the difference between the two. This output current then charges or discharges the internal compensation network to form the COMP voltage, which controls the power MOSFET MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 11 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) protects the chip from operating at an insufficient supply voltage. The MPM3630 UVLO comparator monitors the output voltage of the internal regulator (VCC). The UVLO rising threshold is about 4.1V while its falling threshold is 3.36V. ENABLE/SYNC Control (EN) EN turns the converter on and off. Drive EN high to turn on the converter; drive EN low to turn off the converter. An internal 1.1MΩ resistor from EN to GND allows EN to be floated to shut down the chip. EN is clamped internally using a 5.6V seriesZener-diode (see Figure 4). 5.6 1.1MΩ soft-start voltage (SS) that ramps up from 0V to 5V. When SS is lower than REF, the error amplifier uses SS as the reference. When SS is higher than REF, the error amplifier uses REF as the reference. The SS time is set to 2.2ms internally. Power Good Indicator (PG) The MPM3630 has power good (PG) output to indicate whether the output voltage of the module is ready. PG is an open-drain output. Connect PG to VCC (or another voltage source) through a pull-up resistor (e.g. 10 kΩ). When the input voltage is applied, PG is pulled down to GND before the internal VSS > 1V. Once VSS > 1V (when VFB is above 92% of VREF), PG is pulled high (after a 110 μs delay). During normal operation, PG is pulled low when the VFB drops below 81% of VREF (after a 26μs delay). Since the MPM3630 doesn’t implement dedicated output over-voltage protection, PG will not respond to an output over-voltage condition. Over-Current Protection (OCP) and Hiccup Figure 4: 5.6V Zener Diode Connection Connecting EN to a voltage source directly without a pull-up resistor requires limiting the amplitude of the voltage source to ≤ 5V to prevent damage to the Zener diode. Connecting the EN input through a pull-up resistor to the voltage on VIN limits the EN input current to less than 100µA. For example, with 12V connected to VIN, RPULLUP ≥ (12V – 5.6V) ÷ 100µA = 64kΩ. For external clock synchronization, connect a clock with a frequency range between 1MHz and 2MHz. 2.2ms after the output voltage is set, the internal clock rising edge will synchronize with the external clock rising edge. Meanwhile the width of the high level should be longer than 250ns, and the width of the low level should be longer than 100ns. Internal Soft Start (SS) The soft start prevents the converter output voltage from overshooting during startup. When the chip starts, the internal circuitry generates a The MPM3630 has a cycle-by-cycle overcurrent limiting control. When the inductor current peak value exceeds the internal peak current limit threshold, the HS-FET turns off and the LS-FET turns on, remaining on until the inductor current falls below the internal valley current limit threshold. The valley current limit circuit is employed to decrease the operation frequency (after the peak current limit threshold is triggered). Meanwhile, the output voltage drops until VFB is below the under-voltage (UV) threshold (240mV, typically). Once UV is triggered, the MPM3630 enters hiccup mode to re-start the part periodically. This protection mode is useful when the output is dead-shorted to ground and greatly reduces the average short-circuit current to alleviate thermal issues and protect the converter. The MPM3630 exits hiccup mode once the over-current condition is removed. Thermal Shutdown (TSD) Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the silicon die reaches temperatures that exceed 150°C, it shuts down the whole chip. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 12 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR When the temperature drops below its lower threshold, typically 130°C, the chip is enabled again. Floating Driver and Bootstrap Charging An internal bootstrap capacitor powers the floating power MOSFET driver. This floating driver has its own UVLO protection. This UVLO’s rising threshold is 2.2V with a hysteresis of 150mV. The bootstrap capacitor voltage is regulated internally by VIN through D1, M1, C4, L1, and C2 (see Figure 5). If (VINVSW) exceeds 5V, U1 will regulate M1 to maintain a 5V BST voltage across C4. The power dissipation of the RC snubber circuit is estimated using Equation (1): PLoss fS CS VIN2 (1) Where fS is the switching frequency, Cs is the snubber capacitor, and VIN is the input voltage. For improved efficiency, the value of CS should not be set too high. Generally, a 4.99Ω RS and a 470pF CS are recommended to generate the RC snubber circuit (see Figure 6). RS 4.99 SW CS 470pF Figure 6: Additional RC Snubber Circuit Figure 5: Internal Bootstrap Charging Circuit Startup and Shutdown If both VIN and VEN exceed their respective thresholds, the chip starts up. The reference block starts first, generating stable reference voltage, and then the internal regulator is enabled. The regulator provides a stable supply for the remaining circuitries. Three events shut down the chip: VIN low, VEN low, and thermal shutdown. During the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. The COMP voltage and the internal supply rail are then pulled down. The floating driver is not subject to this shutdown command. Additional RC Snubber Circuit An additional RC snubber circuit can be chosen to clamp the voltage spike and damp the ringing voltage for better EMI performance. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 13 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR APPLICATION INFORMATION downgrade when the output voltage is higher than 5.5V due to thermal concerns. Setting the Output Voltage The external resistor divider sets the output voltage (see Typical Application on page 1). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation capacitor (see Figure 7). R2 is then given using Equation (2): Selecting the Input Capacitor The input current to the step-down converter is discontinuous, therefore it requires a capacitor to supply the AC current to the step-down converter while maintaining the DC input voltage. Use low ESR capacitors for the best performance. Use ceramic capacitors with X5R or X7R dielectrics for best results because of their low ESR and small temperature coefficients. For most applications, use a 22µF capacitor. R2 R1 VOUT (2) 1 0.6V Since the capacitor absorbs the input switching current, it requires an adequate ripple current rating. The C3 R3 OUT FB R2 R1 RMS current in the input capacitor can be estimated using Equation (3) and Equation (4): IC1 ILOAD Figure 7: Feedback Network Table 1 lists the recommended resistor values for common output voltages. Table 1: Resistor Selection for Common Output Voltages VOUT R1 R2 R3 C3 COUT (V) (kΩ) (kΩ) (kΩ) (pF) (µF) 1.0 51 76.8 51 3x22 1.2 51 51 51 3x22 1.5 51 34 51 3x22 1.8 51 25.5 0 2.5 51 16 0 2x22 3.3 51 11.3 0 2x22 5 51 6.98 0 2x22 22 2x22 Normally, it is recommended to set the output voltage from 0.6V to 5.5V. However, it can be set higher than 5.5V. In this case, the outputvoltage ripple is larger due to a larger inductor ripple current. An additional output capacitor is needed to reduce the output ripple voltage. If the output voltage is high, heat dissipation becomes more important. Please refer to the “PCB Layout Guidelines” section to achieve better thermal performance. Also, the output will VOUT VOUT 1 VIN VIN (3) The worst case condition occurs at VIN = 2VOUT, where: IC1 ILOAD 2 (4) To simplifiy, choose an input capacitor with an RMS current rating greater than half of the maximum load current. The input capacitor can be electrolytic, tantalum, or ceramic. When using electrolytic or tantalum capacitors, add a small, high-quality ceramic capacitor (e.g. 0.1μF) placed as close to the IC as possible. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated with Equation (5): VIN ILOAD V V OUT 1 OUT fS C1 VIN VIN (5) Selecting the Output Capacitor The output capacitor (C2) maintains the DC output voltage. Use ceramic, tantalum, or lowESR electrolytic capacitors. For best results, use low ESR capacitors to keep the output voltage ripple low. The output voltage ripple can be estimated using Equation (6): MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 14 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR VOUT VOUT VOUT 1 fS L1 VIN 1 RESR 8 f C2 S (6) VIN GND VOUT Where L1 is the inductor value and RESR is the equivalent series resistance (ESR) value of the output capacitor, and L1=1µH. OUT 8 fS2 L1 C2 VIN For tantalum or electrolytic capacitors, the ESR dominates the impedance at the switching frequency. To simlpify, the output ripple can be approximated with Equation (8): ΔVOUT VOUT V 1 OUT fS L1 VIN RESR PGND NC FB NC BST NC VCC AGND C2 NC SW C2B R2 PGND IN NC PGND EN PG R4 C1 R1 C3 For ceramic capacitors, the capacitance dominates the impedance at the switching frequency, and the capacitance causes the majority of the output voltage ripple. For simplification, the output voltage ripple can be estimated using Equation (7): V VOUT (7) ΔV 1 OUT OUT Top Layer (8) The characteristics of the output capacitor also affect the stability of the regulation system. The MPM3630 can be optimized for a wide range of capacitance and ESR values. GND VOUT PCB Layout (9) Efficient PCB layout is critical to achieve stable operation, especially for input capacitor placement. For best results, see Figure 8 and follow the guidelines below: 1. 2. Place the high current paths GND and IN very close to the device with short, direct, and wide traces. Use a large ground plane to connect directly to PGND. Add vias near PGND if the bottom layer is ground plane. 3. Place the ceramic input capacitor close to IN and the PGND pins. Keep the connection of the input capacitor and IN as short and wide as possible. 4. Place the external feedback resistors next to FB. 5. Keep the feedback network away from the switching node. Bottom Layer Figure 8: Recommended PCB Layout Notes: 9) The recommended layout is based on the Figure 14 Typical Application circuit. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 15 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR Design Example Below is a design example following the application guidelines for the specifications below: Table 2: Design Example VIN VOUT Io 12V 3.3V 3A The detailed application schematic is shown in Figure 14. The typical performance and circuit waveforms have been shown in the Typical Performance Characteristics section. For more device applications, please refer to the related Evaluation Board Datasheets. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 16 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR TYPICAL APPLICATION CIRCUITS BST SW VOUT 12V 1V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF R3 51K EN/SYNC EN C2A 22µF C2B 22µF FB VCC R5 10k C2 22µF R1 51K R2 76.8K PG AGND PGND Figure 9: Vo = 1V, Io = 3A BST SW VOUT 12V 1.2V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF R3 51K EN/SYNC EN C2A 22µF C2B 22µF FB VCC R5 10k C2 22µF R1 51K R2 51K PG AGND PGND Figure 10: Vo = 1.2V, Io = 3A BST SW VOUT 12V 1.5V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF R3 51K EN/SYNC EN R5 10k C2 22µF C2A 22µF C2B 22µF FB VCC R1 51K R2 34K PG AGND PGND Figure 11: Vo = 1.5V, Io = 3A MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 17 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR BST SW VOUT 12V 1.8V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF EN/SYNC EN C2A 22µF FB VCC R5 10k C2 22µF R1 51K R2 25.5K PG AGND PGND Figure 12: Vo = 1.8V, Io = 3A BST SW VOUT 12V 2.5V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF EN/SYNC EN C2A 22µF FB VCC R5 10k C2 22µF R1 51K R2 16K PG AGND PGND Figure 13: Vo = 2.5V, Io = 3A BST SW VOUT 12V 3.3V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF EN/SYNC EN R5 10k C2 22µF C2A 22µF FB VCC R1 51K R2 11.3K PG AGND PGND Figure 14: Vo = 3.3V, Io = 3A MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 18 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR BST SW VOUT 12V 5V/3A IN VIN C1 22µF R4 100k MPM3630 OUT C3 22pF EN/SYNC EN R5 10k C2 22µF C2A 22µF FB VCC R1 51K R2 6.98K PG AGND PGND Figure 15: Vo = 5, Io = 3A MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 19 MPM3630 – SYNCHRONOUS STEP-DOWN MODULE WITH INTEGRATED INDUCTOR PACKAGE OUTLINE DRAWING FOR 20L FCMQFN (3X5MM) PACKAGE INFORMATIONMF-PO-D-0175 revision 4.0 QFN-20 (3mmx5mmx1.6mm) PIN 1 ID 0.125X45º TYP PIN 1 ID MARKING NOTE 2 PIN 1 ID INDEX AREA BOTTOM VIEW TOP VIEW SIDE VIEW NOTE: 0.125X45º NOTE 2 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) SHADED AREA IS THE KEEP-OUT ZONE. ANY PCB METAL TRACE AND VIA ARE NOT ALLOWED TO CONNECT TO THIS AREA ELECTRICALLY OR MECHANICALLY. 3) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 4) LEAD COPLANARITY SHALL BE 0.10 MILLIMETERS MAX. 5) JEDEC REFERENCE IS MO-220. 6) DRAWING IS NOT TO SCALE. RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MPM3630 Rev. 1.0 www.MonolithicPower.com 6/21/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 20