16-Bit, 2 MSPS/1 MSPS, Precision, Differential SAR ADCs AD4001/AD4005 Data Sheet FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS/1 MSPS options INL: ±0.4 LSB maximum Guaranteed 16-bit no missing codes Low power 9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS (VDD only) 80 μW at 10 kSPS, 16 mW at 2 MSPS (total) SNR: 96.2 dB typical at 1 kHz, VREF = 5 V; 95.5 dB typical at 100 kHz THD: −123 dB typical at 1 kHz, VREF = 5 V; −99 dB typical at 100 kHz Ease of use features reduce system power and complexity Input overvoltage clamp circuit Reduced nonlinear input charge kickback High-Z mode Long acquisition phase Input span compression Fast conversion time allows low SPI clock rates SPI-programmable modes, read/write capability, status word Differential analog input range: ±VREF 0 V to VREF with VREF from 2.4 V to 5.1 V Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface SAR architecture: no latency/pipeline delay, valid first conversion First accurate conversion Guaranteed operation: −40°C to +125°C SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface Ability to daisy-chain multiple ADCs and busy indicator 10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP The AD4001/AD4005 are low noise, low power, high speed, 16-bit, precision successive approximation register (SAR) analog-to-digital converters (ADCs). The AD4001 offers a 2 MSPS throughput, and the AD4005 offers a 1 MSPS throughput. They incorporate ease of use features that reduce signal chain power consumption, reduce signal chain complexity, and enable higher channel density. The high-Z mode, coupled with a long acquisition phase, eliminates the need for a dedicated high power, high speed ADC driver, thus broadening the range of low power precision amplifiers that can drive these ADCs directly, while still achieving optimum performance. The input span compression feature enables the ADC driver amplifier and the ADC to operate off common supply rails without the need for a negative supply while preserving the full ADC code range. The low serial peripheral interface (SPI) clock rate requirement reduces the digital input/output power consumption, broadens processor options, and simplifies the task of sending data across digital isolation. Operating from a 1.8 V supply, the AD4001/AD4005 have a ±VREF fully differential input range with VREF ranging from 2.4 V to 5.1 V. The AD4001 consumes only 16 mW at 2 MSPS with a minimum SCK rate of 70 MHz in turbo mode, and the AD4005 consumes only 8 mW at 1 MSPS. The AD4001/AD4005 both achieve ±0.4 LSB integral nonlinearity error (INL) maximum, guaranteed no missing codes at 16 bits with 96.2 dB typical signal-to-noise ratio (SNR) for 1 kHz inputs. The reference voltage is applied externally and can be set independently of the supply voltage. APPLICATIONS Automatic test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems The SPI-compatible, versatile serial interface features seven different modes including the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus, and provides an optional busy indicator. The AD4001/AD4005 are compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD4001/AD4005 are available in a 10-lead MSOP or LFCSP with operation specified from −40°C to +125°C. The devices are pin compatible with the 18-bit, 2 MSPS AD4003 (see Table 8). FUNCTIONAL BLOCK DIAGRAM 2.4V TO 5.1V 10µF 1.8V REF VREF VREF /2 0 HIGH-Z MODE VIO 1.8V TO 5V TURBO MODE IN+ 16-BIT SAR ADC IN– SERIAL INTERFACE STATUS BITS SPAN CLAMP COMPRESSION GND SDI SCK SDO CNV 3-WIRE OR 4-WIRE SPI INTERFACE (DAISY CHAIN, CS) 15368-001 VREF VREF /2 0 VDD AD4001/ AD4005 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD4001/AD4005 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Inputs ............................................................................. 20 Applications ....................................................................................... 1 Driver Amplifier Choice ........................................................... 22 General Description ......................................................................... 1 Ease of Drive Features ............................................................... 23 Functional Block Diagram .............................................................. 1 Voltage Reference Input ............................................................ 24 Revision History ............................................................................... 2 Power Supply............................................................................... 24 Specifications..................................................................................... 4 Digital Interface .......................................................................... 25 Timing Specifications .................................................................. 7 Register Read/Write Functionality........................................... 26 Absolute Maximum Ratings............................................................ 9 Status Word ................................................................................. 28 Thermal Resistance ...................................................................... 9 CS Mode, 3-Wire Turbo Mode ................................................. 29 ESD Caution .................................................................................. 9 CS Mode, 3-Wire Without Busy Indicator ............................. 30 Pin Configurations and Function Descriptions ......................... 10 CS Mode, 3-Wire with Busy Indicator .................................... 31 Typical Performance Characteristics ........................................... 11 CS Mode, 4-Wire Turbo Mode ................................................. 32 Terminology .................................................................................... 16 CS Mode, 4-Wire Without Busy Indicator ............................. 33 Theory of Operation ...................................................................... 17 Circuit Information .................................................................... 17 Converter Operation .................................................................. 18 Transfer Functions...................................................................... 18 Applications Information .............................................................. 19 Typical Application Diagrams .................................................. 19 CS Mode, 4-Wire with Busy Indicator .................................... 34 Daisy-Chain Mode ..................................................................... 35 Layout Guidelines....................................................................... 36 Evaluating the AD4001/AD4005 Performance.......................... 36 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37 REVISION HISTORY 8/2017—Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Table 1 ............................................................................ 6 Changes to Endnote 3, Table 2 ........................................................ 7 Changes to Table 4 ............................................................................ 8 Change to Pin 3 Description and Pin 4 Description, Table 7 ... 10 Reorganized Typical Performance Characteristics Section ...... 13 Changes to Figure 17, Figure 19, and Figure 21 ......................... 13 Added Figure 23; Renumbered Sequentially .............................. 14 Changes to Figure 27 ...................................................................... 15 Changes to Circuit Information Section and Table 8 ................ 17 Changes to Endnote 1 and Endnote 2, Table 9 ........................... 18 Changes to Figure 37 Caption and RC Filter Values Section ... 21 Changes to High Frequency Input Signals Section, Figure 38 Caption, and Figure 39 Caption ................................................... 22 Added Multiplexed Applications Section and Figure 40 ........... 22 Changes to Figure 41 and Figure 42 Caption ............................. 23 Changes to Figure 43, Figure 44 Caption, Figure 45, and Voltage Reference Input Section ................................................................. 24 Changes to Power Supply Section, Figure 46, Figure 47, Digital Interface Section, and Table 11 ..................................................... 25 Changes to CS Mode, 3-Wire Turbo Mode Section................... 29 Changes to CS Mode, 3-Wire with Busy Induction Section and Figure 56 .......................................................................................... 31 Changes to CS Mode, 4-Wire Turbo Mode Section and Figure 58 .......................................................................................... 32 Changes to CS Mode, 4-Wire with Busy Indicator Section and Figure 62 .......................................................................................... 34 4/2017—Rev. 0 to Rev. A Added AD4005 ................................................................... Universal Changes to Title, Features Section, General Description Section, and Figure 1 ........................................................................................1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................6 Changes to Table 4.............................................................................7 Changes to Figure 19 Caption and Figure 21 ............................. 12 Changes to Figure 24...................................................................... 13 Added Figure 25; Renumbered Sequentially .............................. 13 Changes to Circuit Information Section and Table 8 ................ 16 Changes to RC Filter Values Section............................................ 20 Changes to High Frequency Input Signals Section.................... 21 Changes to High-Z Mode Section and Figure 41....................... 22 Changes to Long Acquisition Phase Section .............................. 23 Changes to Digital Interface Section and Register Read/Write Functionality Section ..................................................................... 24 Changes to CS Mode, 3-Wire Turbo Mode Section .................. 27 Changes to CS Mode, 4-Wire Turbo Mode Section .................. 30 Rev. B | Page 2 of 37 Data Sheet AD4001/AD4005 Changes to Layout Guidelines Section and Evaluating the AD4001/AD4005 Performance Section .......................................34 Updated Outline Dimensions ........................................................35 Changes to Ordering Guide ...........................................................35 1/2017—Revision 0: Initial Version Rev. B | Page 3 of 37 AD4001/AD4005 Data Sheet SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. Table 1. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio (CMRR) Analog Input Current THROUGHPUT Complete Cycle AD4001 AD4005 Conversion Time Acquisition Phase 1 AD4001 AD4005 Throughput Rate 2 AD4001 AD4005 Transient Response 3 DC ACCURACY No Missing Codes Integral Nonlinearity Error (INL) Differential Nonlinearity Error (DNL) Transition Noise Zero Error Zero Error Drift 4 Gain Error Gain Error Drift4 Power Supply Sensitivity 1/f Noise 5 AC ACCURACY Dynamic Range Total RMS Noise fIN = 1 kHz, −0.5 dBFS, VREF = 5 V Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Ratio (SINAD) Oversampled Dynamic Range Test Conditions/Comments Min 16 VIN+ − VIN− Span compression enabled VIN+, VIN− to GND Span compression enabled −VREF −VREF × 0.8 −0.1 0.1 × VREF VREF/2 − 0.125 fIN = 500 kHz Acquisition phase, T = 25°C High-Z mode enabled, converting dc input at 2 MSPS Typ VREF/2 68 0.3 1 Max Unit Bits +VREF +VREF × 0.8 VREF + 0.1 0.9 × VREF VREF/2 + 0.125 V V V V V dB nA µA 500 1000 290 320 290 790 ns ns 0 0 2 1 250 16 −0.4 −0.5 −1.5 −0.28 −16.5 −0.23 VDD = 1.8 V ± 5% Bandwidth = 0.1 Hz to 10 Hz 95.6 95.5 Oversampling ratio (OSR) = 256, VREF = 5 V Rev. B | Page 4 of 37 ns ns ns MSPS MSPS ns 0.25 6 Bits LSB LSB LSB LSB ppm/°C LSB ppm/°C LSB µV p-p 96.3 54 dB µV rms 96.2 122 −123 96 dB dB dB dB 120 dB ±0.2 ±0.2 0.35 ±0.1 ±0.4 +0.4 +0.5 +1.5 +0.28 +16.5 +0.23 Data Sheet Parameter fIN = 1 kHz, −0.5 dBFS, VREF = 2.5 V SNR SFDR THD SINAD fIN = 100 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD fIN = 400 kHz, −0.5 dBFS, VREF = 5 V SNR THD SINAD −3 dB Input Bandwidth Aperture Delay Aperture Jitter REFERENCE Voltage Range, VREF Current AD4001 AD4005 INPUT OVERVOLTAGE CLAMP IN+/IN− Current, IIN+/IIN− VIN+/VIN− at Maximum IIN+/IIN− VIN+/VIN− Clamp On/Off Threshold Deactivation Time REF Current at Maximum IIN+/IIN− DIGITAL INPUTS Logic Levels Input Low Voltage, VIL Input High Voltage, VIH AD4001/AD4005 Test Conditions/Comments Typ 92.1 93.2 118 −117 93 dB dB dB dB 95.5 −99 93.8 dB dB dB 91 −92 89 10 1 1 dB dB dB MHz ns ps rms 92 2.4 VREF = 5 V 2 MSPS 1 MSPS Max 5.1 1.1 0.5 VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V VREF = 5 V VREF = 2.5 V 5.25 2.68 VIN+/VIN− > VREF VIO > 2.7 V VIO ≤ 2.7 V VIO > 2.7 V VIO ≤ 2.7 V mA mA V V V V ns µA +0.3 × VIO +0.2 × VIO VIO + 0.3 VIO + 0.3 +1 +1 V V V V µA µA pF Serial 16 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 1.71 1.71 VDD = 1.8 V, VIO = 1.8 V, T = 25°C Rev. B | Page 5 of 37 1.8 1.6 V 50 50 6 ISINK = 500 µA ISOURCE = −500 µA Unit mA mA 5.4 3.1 5.4 2.8 360 100 −0.3 −0.3 0.7 × VIO 0.8 × VIO −1 −1 Input Low Current, IIL Input High Current, IIH Input Pin Capacitance DIGITAL OUTPUTS Data Format Pipeline Delay Output Low Voltage, VOL Output High Voltage, VOH POWER SUPPLIES VDD VIO Standby Current Min 1.89 5.5 V V V V µA AD4001/AD4005 Parameter Power Dissipation VDD Only REF Only VIO Only Energy per Conversion TEMPERATURE RANGE Specified Performance Data Sheet Test Conditions/Comments VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode enabled 2 MSPS, high-Z mode enabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled 1 MSPS, high-Z mode disabled 2 MSPS, high-Z mode disabled Min TMIN to TMAX −40 Typ 80 8 16 10 20 4.9 9.5 2.8 5.5 0.4 1.0 8 Max 9.3 18.5 12.3 24.5 +125 Unit µW mW mW mW mW mW mW mW mW mW mW nJ/sample °C The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 23. 1 Rev. B | Page 6 of 37 Data Sheet AD4001/AD4005 TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, VIO = 1.71 V to 5.5 V, VREF = 5 V, all specifications TMIN to TMAX, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. See Figure 2 for the timing voltage levels. Table 2. Digital Interface Timing Parameter CONVERSION TIME—CNV RISING EDGE TO DATA AVAILABLE ACQUISITION PHASE 1 AD4001 AD4005 TIME BETWEEN CONVERSIONS AD4001 AD4005 CNV PULSE WIDTH (CS MODE) 2 Symbol tCONV tACQ Min 270 Typ 290 Max 320 Unit ns SCK PERIOD (CS MODE) VIO > 2.7 V VIO > 1.7 V SCK PERIOD (DAISY-CHAIN MODE) 4 VIO > 2.7 V VIO > 1.7 V SCK LOW TIME SCK HIGH TIME SCK FALLING EDGE TO DATA REMAINS VALID DELAY SCK FALLING EDGE TO DATA VALID DELAY VIO > 2.7 V VIO > 1.7 V CNV OR SDI LOW TO SDO D15 MOST SIGNIFICANT BIT (MSB) VALID DELAY (CS MODE) VIO > 2.7 V VIO > 1.7 V CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY LAST SCK FALLING EDGE TO CNV RISING EDGE DELAY 5 CNV OR SDI HIGH OR LAST SCK FALLING EDGE TO SDO HIGH IMPEDANCE (CS MODE) tSCK tQUIET1 tQUIET2 tDIS 190 60 SDI VALID SETUP TIME FROM CNV RISING EDGE SDI VALID HOLD TIME FROM CNV RISING EDGE (CS MODE) tSSDICNV tHSDICNV 2 2 ns ns SCK VALID HOLD TIME FROM CNV RISING EDGE (DAISY-CHAIN MODE) SDI VALID SETUP TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) SDI VALID HOLD TIME FROM SCK RISING EDGE (DAISY-CHAIN MODE) tHSCKCNV tSSDISCK tHSDISCK 12 2 2 ns ns ns 290 790 ns ns 500 1000 10 ns ns ns 9.8 12.3 ns ns 20 25 3 3 1.5 ns ns ns ns ns tCYC tCNVH 3 tSCK tSCKL tSCKH tHSDO tDSDO 7.5 10.5 ns ns 10 13 ns ns ns ns ns tEN 20 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4001 and 1 MSPS for the AD4005. 2 For turbo mode, tCNVH must match the tQUIET1 minimum. 3 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 70 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 4 A 50% duty cycle is assumed for SCK. 5 See Figure 22 for SINAD vs. tQUIET2. 1 Y% VIO1 X% VIO1 tDELAY VIH2 VIL2 VIH2 VIL2 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 1. Figure 2. Voltage Levels for Timing Rev. B | Page 7 of 37 15368-002 tDELAY AD4001/AD4005 Data Sheet Table 3. Register Read/Write Timing Parameter READ/WRITE OPERATION CNV Pulse Width 1 SCK Period VIO > 2.7 V VIO > 1.7 V SCK Low Time SCK High Time READ OPERATION CNV Low to SDO D15 MSB Valid Delay VIO > 2.7 V VIO > 1.7 V SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO > 2.7 V VIO > 1.7 V CNV Rising Edge to SDO High Impedance WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge SDI Valid Hold Time from SCK Rising Edge CNV Rising Edge to SCK Edge Hold Time CNV Falling Edge to SCK Active Edge Setup Time 1 Symbol Min tCNVH tSCK 10 ns 9.8 12.3 3 3 ns ns ns ns tSCKL tSCKH Typ Max Unit tEN tHSDO tDSDO ns ns ns 7.5 10.5 20 ns ns ns 1.5 tDIS tSSDISCK tHSDISCK tHCNVSCK tSCNVSCK 10 13 2 2 0 6 ns ns ns ns For turbo mode, tCNVH must match the tQUIET1 minimum. Table 4. Achievable Throughput for Different Modes of Operation Parameter THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode 3-Wire and 4-Wire Turbo Mode and Six Status Bits 3-Wire and 4-Wire Mode 3-Wire and 4-Wire Mode and Six Status Bits Test Conditions/Comments fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V fSCK = 100 MHz, VIO ≥ 2.7 V fSCK = 80 MHz, VIO < 2.7 V Rev. B | Page 8 of 37 Min Typ Max Unit 2 2 2 1.86 1.82 1.69 1.64 1.5 MSPS MSPS MSPS MSPS MSPS MSPS MSPS MSPS Data Sheet AD4001/AD4005 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Note that the input overvoltage clamp cannot sustain the overvoltage condition for an indefinite amount of time. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 5. Parameter Analog Inputs IN+, IN− to GND1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Soldering ESD Ratings Human Body Model Machine Model Field Induced Charged Device Model 1 Rating −0.3 V to VREF + 0.4 V or ±50 mA −0.3 V to +6.0 V −0.3 V to +2.1 V −6 V to +2.4 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C 260°C reflow as per JEDEC J-STD-020 Table 6. Thermal Resistance Package Type1 RM-10 CP-10-9 θJA2 147 114 θJC3 38 33 Unit °C/W °C/W Test Condition 1: thermal impedance simulated values are based upon use of 2S2P JEDEC PCB. See the Ordering Guide. 2 θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure. 3 θJC is the junction-to-case thermal resistance. 1 ESD CAUTION 4 kV 200 V 1.25 kV See the Analog Inputs section for an explanation of IN+ and IN−. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 37 AD4001/AD4005 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 IN+ 3 IN+ 3 AD4001/ AD4005 IN– 4 TOP VIEW (Not to Scale) VDD 2 GND 5 10 VIO IN– 4 9 SDI GND 5 8 SCK 7 SDO 6 CNV TOP VIEW (Not to Scale) 9 SDI 8 SCK 7 SDO 6 CNV NOTES 1. CONNECT THE EXPOSED PAD TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE SPECIFIED PERFORMANCE. 15368-003 REF 1 10 VIO AD4001/ AD4005 Figure 3. 10-Lead MSOP Pin Configuration 15368-004 VDD 2 Figure 4. 10-Lead LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 VDD P 3 4 5 6 IN+ IN− GND CNV AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P N/A 2 EPAD P 1 2 Description Reference Input Voltage. The VREF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and must be decoupled closely to the GND pin with a 10 µF, X7R ceramic capacitor. 1.8 V Power Supply. The VDD range is 1.71 V to 1.89 V. Bypass VDD to GND with a 0.1 µF ceramic capacitor. Differential Positive Analog Input. See the Differential Input Considerations section. Differential Negative Analog Input. See the Differential Input Considerations section. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the device: daisy-chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In daisy-chain mode, the data is read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the device is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Daisy-chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. With CNV low, the device can be programmed by clocking in a 16-bit word on SDI on the rising edge of SCK. Input/Output Interface Digital Power. Nominally, this pin is at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Bypass VIO to GND with a 0.1 μF ceramic capacitor. Exposed Pad (LFCSP Only). Connect the exposed pad to GND. This connection is not required to meet the specified performance. AI is analog input, P is power, DI is digital input, and DO is digital output. N/A means not applicable. Rev. B | Page 10 of 37 Data Sheet AD4001/AD4005 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, T = 25°C, high-Z mode disabled, span compression disabled, turbo mode enabled, and sampling frequency (fS) = 2 MSPS for the AD4001 and fS = 1 MSPS for the AD4005, unless otherwise noted. 0.3 0.2 0.2 0.1 0.1 0 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE –0.4 15368-200 0 40960 49152 57344 65536 0.2 0.2 0.1 0.1 0 –0.1 –0.1 –0.2 –0.2 –0.3 –0.3 16384 24576 32768 40960 49152 57344 65536 CODE –0.4 15368-201 8192 0.2 0.1 0.1 DNL (LSB) 0.2 0 –0.1 –0.2 –0.2 –0.3 –0.3 CODE 40960 49152 57344 65536 –0.4 15368-407 32768 40960 49152 57344 65536 0 –0.1 24576 32768 HIGH-Z ENABLED SPAN COMPRESSION ENABLED 0.3 16384 24576 0.4 0.3 8192 16384 Figure 9. DNL vs. Code for Various Temperatures, VREF = 2.5 V HIGH-Z ENABLED SPAN COMPRESSION ENABLED 0 8192 CODE Figure 6. INL vs. Code for Various Temperatures, VREF = 2.5 V 0.4 0 15368-204 0 0 –40°C +25°C +125°C 0.3 DNL (LSB) INL (LSB) 32768 0.4 –40°C +25°C +125°C 0.3 INL (LSB) 24576 Figure 8. DNL vs. Code for Various Temperatures, VREF = 5 V 0.4 –0.4 16384 CODE Figure 5. INL vs. Code for Various Temperatures, VREF = 5 V –0.4 8192 Figure 7. INL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V 0 8192 16384 24576 32768 CODE 40960 49152 57344 65536 15368-410 –0.4 –40°C +25°C +125°C 0.3 DNL (LSB) INL (LSB) 0.4 –40°C +25°C +125°C 15368-203 0.4 Figure 10. DNL vs. Code, High-Z and Span Compression Modes Enabled, VREF = 5 V Rev. B | Page 11 of 37 AD4001/AD4005 Data Sheet 1200000 600000 VREF = 5V VREF = 2.5V 500000 800000 400000 600000 400000 200000 200000 100000 0 32766 32767 32769 32768 32770 CODE 0 0 FUNDAMENTAL AMPLITUDE (dB) 32770 VREF = 2.5V SNR = 93.12dB THD = –118.26dB SINAD = 93.11dB –100 –120 –140 –60 –80 –100 –120 –140 –160 1k 10k 100k 1M FREQUENCY (Hz) –180 100 15368-207 –180 100 10k 100k 1M FREQUENCY (Hz) Figure 12. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 5 V Figure 15. 1 kHz, −0.5 dBFS Input Tone FFT, Wide View, VREF = 2.5 V 0 FUNDAMENTAL AMPLITUDE (dB) VREF = 5V SNR = 95.48dB THD = –98.63dB SINAD = 93.84dB –60 –80 –100 –120 –140 –160 VREF = 5V SNR = 91.04dB –20 THD = –91.47dB SINAD = 88.85dB –40 –60 –80 –100 –120 –140 –160 10k 100k FREQUENCY (Hz) 1M 15368-210 –180 1k 1k 15368-209 –160 –40 Figure 13. 100 kHz, −0.5 dBFS Input Tone FFT, Wide View –180 1k 10k 100k FREQUENCY (Hz) Figure 16. 400 kHz, −0.5 dBFS Input Tone FFT, Wide View Rev. B | Page 12 of 37 1M 15368-213 FUNDAMENTAL AMPLITUDE (dB) –80 –40 32769 –20 –60 –20 32768 0 –40 0 32767 Figure 14. Histogram of a DC Input at Code Transition, VREF = 2.5 V and VREF = 5 V VREF = 5V SNR = 96.25dB THD = –124.30dB SINAD = 96.23dB –20 32766 CODE Figure 11. Histogram of a DC Input at Code Center, VREF = 2.5 V and VREF = 5 V FUNDAMENTAL AMPLITUDE (dB) 300000 15368-208 CODE COUNT 1000000 15368-205 CODE COUNT VREF = 5V VREF = 2.5V Data Sheet 96.5 AD4001/AD4005 15.8 ENOB SNR SINAD 96.0 128 –118 15.7 127 –120 15.6 126 15.4 94.0 SFDR (dB) 94.5 –122 THD (dB) 15.5 ENOB (Bits) 95.0 125 –124 124 –126 123 –128 15.2 3.0 3.3 3.6 3.9 4.2 4.5 4.8 REFERENCE VOLTAGE (V) –132 2.4 96.4 15.73 –118 15.72 –119 15.71 –120 15.68 15.67 96.1 95.9 –40 –20 0 20 40 60 80 100 120 120 5.1 4.8 127.1 127.0 126.9 126.8 –123 126.7 –124 126.6 126.5 –127 15.64 –128 15.63 –129 –40 126.4 126.3 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 18. SNR, SINAD, and ENOB vs. Temperature, fIN = 1 kHz Figure 21. THD and SFDR vs. Temperature, fIN = 1 kHz 130 97 DYNAMIC RANGE FREQUENCY = 1kHz FREQUENCY = 10kHz 96 95 SINAD (dB) 120 SNR (dB) 4.5 –126 TEMPERATURE (°C) 125 4.2 THD SFDR 15.65 15368-222 SNR SINAD ENOB 3.9 –125 15.66 96.0 3.6 –122 THD (dB) 96.2 3.3 –121 ENOB (Bits) 15.69 3.0 Figure 20. THD and SFDR vs. Reference Voltage, fIN = 1 kHz 15.70 96.3 2.7 REFERENCE VOLTAGE (V) Figure 17. SNR, SINAD, and ENOB vs. Reference Voltage, fIN = 1 kHz 96.5 121 115 110 94 93 92 105 91 1 2 4 8 16 32 64 DECIMATION RATE 128 256 512 1024 15368-212 95 90 Figure 19. SNR vs. Decimation Rate for Various Input Frequencies, 2 MSPS Rev. B | Page 13 of 37 89 VIO = 1.89V VIO = 3.6V VIO = 5.5V 0 20 40 60 tQUIET2 (ns) Figure 22. SINAD vs. tQUIET2 80 100 15368-215 100 SFDR (dB) 2.7 15.1 5.1 15368-219 92.5 2.4 122 –130 15368-225 93.0 15368-216 15.3 93.5 SRN, SINAD (dB) 129 SFDR THD 95.5 SNR, SINAD (dB) –116 AD4001/AD4005 Data Sheet 1.0 60 ZERO ERROR, GAIN ERROR (LSB) 0.8 ADC OUTPUT READING (µV) 59 58 57 56 55 ZERO ERROR PFS ERROR NFS ERROR 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) Figure 23. 1/f Noise for 0.1 Hz to 10 Hz Bandwidth, 50 kSPS, 2500 Samples Averaged per Reading 4.5 7 4.0 5 VDD HIGH-Z DISABLED VDD HIGH-Z ENABLED REF HIGH-Z DISABLED REF HIGH-Z ENABLED VIO HIGH-Z DISABLED VIO HIGH-Z ENABLED 4 3 2 1 20 40 60 80 100 120 3.5 3.0 2.5 2.0 1.5 VDD HIGH-Z ENABLED VDD HIGH-Z DISABLED REF HIGH-Z ENABLED REF HIGH-Z DISABLED VIO HIGH-Z ENABLED VIO HIGH-Z DISABLED 1.0 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 24. Operating Current vs. Temperature, AD4001, 2 MSPS Figure 26. Operating Current vs. Temperature, AD4005, 1 MSPS Rev. B | Page 14 of 37 15368-325 0.5 15368-223 0 –40 0 Figure 25. Zero Error and Gain Error vs. Temperature, Positive Full Scale (PFS) and Negative Full Scale (NFS) 8 6 –20 TEMPERATURE (°C) OPERATING CURRENT (mA) OPERATING CURRENT (mA) –1.0 –40 15368-217 0 15368-221 –0.8 54 Data Sheet 1.1 25.0 2MSPS 1MSPS 1.0 22.5 20.0 0.9 STANDBY CURRENT (µA) 0.8 0.7 0.6 0.5 0.4 12.5 10.0 7.5 2.5 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 REFERENCE VOLTAGE (V) 0 –40 15368-218 0.2 2.4 VIO = 5V VIO = 3.3V VIO = 1.8V 19 17 15 13 11 9 20 40 60 80 100 120 140 160 180 LOAD CAPACITANCE (pF) 200 220 15368-224 7 0 0 20 40 60 80 100 Figure 29. Standby Current vs. Temperature 23 21 –20 TEMPERATURE (°C) Figure 27. Reference Current vs. Reference Voltage tDSDO (ns) 15.0 5.0 0.3 5 17.5 Figure 28. tDSDO vs. Load Capacitance Rev. B | Page 15 of 37 120 15368-226 REFERENCE CURRENT (mA) AD4001/AD4005 AD4001/AD4005 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL is the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 31). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) occurs at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) occurs for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBFS so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. Common-Mode Rejection Ratio (CMRR) CMRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the common-mode voltage of IN+ and IN− of frequency, f. CMRR (dB) = 10log(PADC_IN/PADC_OUT) Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows: where: PADC_IN is the common-mode power at the frequency, f, applied to the IN+ and IN− inputs. PADC_OUT is the power at the frequency, f, in the ADC output. ENOB = (SINADdB − 1.76)/6.02 ENOB is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Power Supply Rejection Ratio (PSRR) PSRR is the ratio of the power in the ADC output at the frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC VDD supply of frequency, f. PSRR (dB) = 10 log(PVDD_IN/PADC_OUT) where: PVDD_IN is the power at the frequency, f, at the VDD pin. PADC_OUT is the power at the frequency, f, in the ADC output. Rev. B | Page 16 of 37 Data Sheet AD4001/AD4005 THEORY OF OPERATION IN+ SWITCHES CONTROL LSB MSB REF 32,768C 16,384C 4C 2C C SW+ C BUSY COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 15368-007 CNV IN– Figure 30. ADC Simplified Schematic CIRCUIT INFORMATION The AD4001/AD4005 are high speed, low power, single-supply, precise, 16-bit ADCs based on a SAR architecture. The AD4001 is capable of converting 2,000,000 samples per second (2 MSPS), the AD4005 is capable of converting 1,000,000 samples per second (1 MSPS). The power consumption of the AD4001/AD4005 scales with throughput because they power down in between conversions. When operating at 10 kSPS, for example, they typically consume 80 µW, making them ideal for battery-powered applications. The AD4001/AD4005 also have a valid first conversion after being powered down for long periods, which can further reduce power consumed in applications in which the ADC does not need to be constantly converting. The AD4001/AD4005 provide the user with an on-chip trackand-hold and do not exhibit any pipeline delay or latency, making them ideal for multiplexed applications. The AD4001/AD4005 incorporate a multitude of unique ease of use features that result in a lower system power and footprint. The AD4001/AD4005 each have an internal voltage clamp that protects the device from overvoltage damage on the analog inputs. The analog input incorporates circuitry that reduces the nonlinear charge kickback seen from a typical switched capacitor SAR input. This reduction in kickback, combined with a longer acquisition phase, means reduced settling requirements on the driving amplifier. This combination allows the use of lower bandwidth and lower power amplifiers as drivers. It has the additional benefit of allowing a larger resistor value in the input RC filter and a corresponding smaller capacitor, which results in a smaller RC load for the amplifier, improving stability and power dissipation. High-Z mode can be enabled via the SPI interface by programming a register bit (see Table 14). When high-Z mode is enabled, the ADC input has a low input charging current at low input signal frequencies, as well as improved distortion over a wide frequency range up to 100 kHz. For frequencies greater than 100 kHz and multiplexing, disable high-Z mode. For single-supply applications, a span compression feature creates additional headroom and footroom for the driving amplifier to access the full range of the ADC. The fast conversion time of the AD4001/AD4005, along with turbo mode, allows low clock rates to read back conversions even when running at their maximum throughput rates of 2 MSPS/1 MSPS. Note that, for the AD4001, a throughput rate of 2 MSPS can be achieved only with turbo mode enabled. The AD4001/AD4005 can interface with any 1.8 V to 5 V digital logic family. They are available in a 10-lead MSOP or a tiny 10-lead LFCSP that allows space savings and flexible configurations. The AD4001/AD4005 are pin for pin compatible with some of the 14-/16-/18-/20-bit precision SAR ADCs listed in Table 8. Table 8. MSOP and LFCSP 14-/16-/18-/20-Bit Precision SAR ADCs 400 kSPS to 500 kSPS Bits 201 181 100 kSPS 250 kSPS AD7989-12 AD76912 AD76902, AD7989-52, AD40112 161 AD7684 AD76872 163 AD7680, AD7683, AD7988-12 AD76852, AD7694 AD76882, AD76932, AD79162 AD76862, AD7988-52 143 AD7940 AD79422 AD79462 True differential. Pin for pin compatible. 3 Pseudo differential. 1 2 Rev. B | Page 17 of 37 ≥1000 kSPS AD40202 AD40032, AD40072, AD79822, AD79842 AD4001, AD4005, AD79152 AD40002, AD40042, AD7980,2 AD79832 Not applicable AD4001/AD4005 Data Sheet During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via the SW+ and SW− switches. All independent switches connect the other terminal of each capacitor to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. Because the AD4001 and the AD4005 have on-board conversion clocks, the serial clock, SCK, is not required for the conversion process. TRANSFER FUNCTIONS The ideal transfer characteristics for the AD4001/AD4005 are shown in Figure 31 and Table 9. When the acquisition phase is complete and the CNV input goes high, a conversion phase initiates. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. The differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and VREF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …, VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT 15368-008 The AD4001/AD4005 are SAR-based ADCs using a charge redistribution sampling digital-to-analog converter (DAC). Figure 30 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the comparator inputs. the completion of this process, the control logic generates the ADC output code and a busy signal indicator. ADC CODE (TWOS COMPLEMENT) CONVERTER OPERATION Figure 31. ADC Ideal Transfer Function (FSR Is Full-Scale Range) Table 9. Output Codes and Ideal Input Voltages Description +FSR − 1 LSB Midscale + 1 LSB Midscale Midscale − 1 LSB −FSR + 1 LSB −FSR Analog Input, VREF = 5 V +4.999847 V +152.6 µV 0V −152.6 µV −4.999847 V −5 V VREF = 5 V with Span Compression Enabled +3.999878 V +122.1 µV 0V −122.1 µV −3.999878 V −4 V Digital Output Code (Hex) 0x7FFF 1 0x0001 0x0000 0xFFFF 0x8001 0x8000 2 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with span compression disabled and above 0.8 × VREF with span compression enabled). 2 This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with span compression disabled and below −0.8 × VREF with span compression enabled). 1 Rev. B | Page 18 of 37 Data Sheet AD4001/AD4005 APPLICATIONS INFORMATION TYPICAL APPLICATION DIAGRAMS Figure 33 shows a recommended connection diagram when using a single-supply system. This setup is preferable when only a limited number of rails are available in the system and power dissipation is of critical importance. Figure 32 shows an example of the recommended connection diagram for the AD4001/AD4005 when multiple supplies are available. This configuration is used for best performance because the amplifier supplies can be selected to allow the maximum signal range. Figure 34 shows a recommended connection diagram when using a fully differential amplifier. V+ ≥ +6.5V REF LDO 1.8V AMP VCM = VREF /2 5V 10kΩ 0.1µF 10kΩ 1.8V TO 5V 0.1µF HOST SUPPLY 10µF V+ R AMP VREF VCM = VREF /2 REF C 0V VDD VIO SDI IN+ V– AD4001/AD4005 DIGITAL HOST (MICROPROCESSOR/ FPGA) SDO V+ IN– CNV R AMP VREF SCK VCM = VREF /2 GND 3-WIRE/4-WIRE INTERFACE C 0V 15368-009 V– V– ≤ –0.5V Figure 32. Typical Application Diagram with Multiple Supplies V+ = +5V REF1 LDO AMP VCM = VREF /2 4.096V 1.8V 10kΩ 10kΩ 0.1µF 0.1µF 100nF 100nF 1.8V TO 5V HOST SUPPLY 10µF1 R AMP 0.9 × VREF VCM = VREF /2 0.1 × VREF REF C VDD VIO SDI IN+ AD4001/AD40052 SCK SDO IN– AMP 0.9 × VREF VCM = VREF /2 0.1 × VREF R DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV GND 3-WIRE/4-WIRE INTERFACE C 1 SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE 2 SPAN COMPRESSION MODE ENABLED. 3 SEE TABLE 10 FOR RC FILTER AND AMPLIFIER SELECTION. SELECTION. CREF IS USUALLY A 10µF CERAMIC CAPACITOR (X7R). Figure 33. Typical Application Diagram with a Single Supply Rev. B | Page 19 of 37 15368-010 3 AD4001/AD4005 Data Sheet V+ = +5V REF LDO AMP VCM = VREF /2 VCM = VREF /2 R4 1kΩ R3 1kΩ VREF 10kΩ 0 4.096V 1.8V 1.8V TO 5V 0.1µF 0.1µF 10kΩ 10µF HOST SUPPLY V+ +IN REF R –OUT VDD VIO SDI IN+ C VCM = VREF /2 VOCM 0.1µF –IN AD4001/AD4005 C +OUT SDO IN– R DIFFERENTIAL AMPLIFIER SCK CNV GND 3-WIRE/4-WIRE INTERFACE V– R1 1kΩ VREF 0 15368-011 VCM = VREF /2 DIGITAL HOST (MICROPROCESSOR/ FPGA) R2 1kΩ Figure 34. Typical Application Diagram with a Fully Differential Amplifier V+ = +5V REF LDO AMP 0V R4 1kΩ R3 1kΩ +VREF VCM = VREF /2 10kΩ –VREF 4.096V 10kΩ 10µF 1.8V 0.1µF 0.1µF 1.8V TO 5V HOST SUPPLY V+ +IN REF –OUT R VDD VIO SDI IN+ C VREF /2 VOCM C +OUT 0.1µF –IN DIFFERENTIAL AMPLIFIER R AD4001/AD4005 IN– GND SCK SDO DIGITAL HOST (MICROPROCESSOR/ FPGA) CNV 3-WIRE/4-WIRE INTERFACE V– 15368-012 R1 1kΩ R2 1kΩ Figure 35. Typical Application Diagram for Single-Ended to Differential Conversion with a Fully Differential Amplifier ANALOG INPUTS Input Overvoltage Clamp Circuit Figure 36 shows an equivalent circuit of the analog input structure, including the overvoltage clamp of the AD4001/AD4005. Most ADC analog inputs, IN+ and IN−, have no overvoltage protection circuitry apart from ESD protection diodes. During an overvoltage event, an ESD protection diode from an analog input (IN+ or IN−) pin to REF forward biases and shorts the input pin to REF, potentially overloading the reference or causing damage to the device. The AD4001/AD4005 internal overvoltage clamp circuit with a larger external resistor (REXT = 200 Ω) eliminates the need for external protection diodes and protects the ADC inputs against dc overvoltages. REF D1 VIN REXT RIN CIN IN+/IN– CEXT CPIN D2 CLAMP GND Figure 36. Equivalent Analog Input Circuit 15368-013 0V TO 15V In applications where the amplifier rails are greater than VREF and less than ground, it is possible for the output to exceed the input voltage range of the device. In this case, the AD4001/AD4005 internal voltage clamp circuit ensures that the voltage on the input pin does not exceed VREF + 0.4 V and prevents damage to Rev. B | Page 20 of 37 Data Sheet AD4001/AD4005 the device by clamping the input voltage in a safe operating range and avoiding disturbance of the reference, which is particularly important for systems that share the reference among multiple ADCs. 72 71 The external RC filter is usually present at the ADC input to band limit the input signal. During an overvoltage event, excessive voltage is dropped across REXT, and REXT becomes part of a protection circuit. The REXT value can vary from 200 Ω to 20 kΩ for 15 V protection. The CEXT value can be as low as 100 pF for correct operation of the clamp. See Table 1 for input overvoltage clamp specifications. Differential Input Considerations The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. Figure 37 shows the common-mode rejection capability of the AD4001/ AD4005 over frequency. It is important to note that the differential input signals must be truly antiphase in nature, 180° out of phase, which is required to keep the common-mode voltage of the input signal within the specified range around VREF/2 as shown in Table 1. 69 68 67 66 100 1k 10k FREQUENCY (Hz) 100k 1M 15368-303 When the clamp is active, it sets the OV clamp flag bit in the register that can be read back (see Table 14), which is a sticky bit that must be read to be cleared. The status of the clamp can also be checked in the status bits using an overvoltage clamp flag (see Table 15). The clamp circuit does not dissipate static power in the off state. Note that the clamp cannot sustain the overvoltage condition for an indefinite amount of time. 70 CMRR (dB) If the analog input exceeds the reference voltage by 0.4 V, the internal clamp circuit turns on and the current flows through the clamp into ground, preventing the input from rising further and potentially causing damage to the device. The clamp turns on before D1 (see Figure 36) and can sink up to 50 mA of current. Figure 37. CMRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Switched Capacitor Input During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 40 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are open, the input impedance is limited to CPIN. RIN and CIN make a singlepole, low-pass filter that reduces undesirable aliasing effects and limits noise. RC Filter Values The RC filter value (represented by R and C in Figure 32 to Figure 35) and driving amplifier can be selected depending on the input signal bandwidth of interest at the full throughput. Lower input signal bandwidth means that the RC cutoff can be lower, thereby reducing noise into the converter. For optimum performance at various throughputs, use the recommended RC values (200 Ω, 180 pF) and the ADA4807-1. The RC values shown in Table 10 are chosen for ease of drive considerations and greater ADC input protection. The combination of a large R value (200 Ω) and small C value results in a reduced dynamic load for the amplifier to drive. The smaller value of C means fewer stability and phase margin concerns with the amplifier. The large value of R limits the current into the ADC input when the amplifier output exceeds the ADC input range. Table 10. RC Filter and Amplifier Selection for Various Input Bandwidths Input Signal Bandwidth (kHz) <10 <200 >200 Multiplexed R (Ω) C (pF) 200 200 200 180 120 120 Recommended Amplifier See the High-Z Mode section ADA4807-1 ADA4897-1 ADA4897-1 Rev. B | Page 21 of 37 Recommended Fully Differential Amplifier ADA4940-1 ADA4940-1 ADA4932-1 ADA4932-1 AD4001/AD4005 Data Sheet 97 15.8 Although the AD4001/AD4005 are easy to drive, the driver amplifier must meet the following requirements: 96 15.6 95 15.4 • 94 15.2 93 15.0 92 14.8 91 14.6 90 14.4 10k 1k 14.0 1M 100k INPUT FREQUENCY (Hz) Single to Differential Driver For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4940-1 single-ended to differential driver allows a differential input to the device. The schematic is shown in Figure 35. High Frequency Input Signals The AD4001/AD4005 ac performance over a wide input frequency range (using a 5 V reference voltage) is shown in Figure 38 and Figure 39. Unlike other traditional SAR ADCs, the AD4001/ AD4005 maintain exceptional ac performance for input frequencies up to the Nyquist frequency with minimal performance degradation. Note that the input frequency is limited to the Nyquist frequency of the sample rate in use. 125 –95 120 THD SFDR 115 –105 110 –110 105 –115 100 –120 95 –125 1k 10k SFDR (dB) THD (dB) –100 90 1M 100k 15368-214 For ac applications, the driver must have a THD performance commensurate with the AD4001/AD4005. For multichannel multiplexed applications, the driver amplifier and the analog input circuit of the AD4001/AD4005 must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0001525%, 15.25 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This settling may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection. –90 INPUT FREQUENCY (Hz) Figure 39. THD and SFDR vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Multiplexed Applications The AD4001/AD4005 significantly reduce system complexity and cost for multiplexed applications that require superior performance in terms of noise, power, and throughput. Figure 40 shows a simplified block diagram of a multiplexed data acquisition system including a multiplexer, an ADC driver, and the precision SAR ADC. MULTIPLEXER R ADC DRIVER C SAR ADC R C R C C 15368-539 • 14.2 Figure 38. SNR, SINAD, and ENOB vs. Input Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C where: f−3 dB is the input bandwidth, in megahertz, of the AD4001/ AD4005 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp in nV/√Hz. • 88 SENSORS SNRLOSS 54µV = 20 log 2 π 2 54µV + f − 3 dB (NeN ) 2 SNR SINAD ENOB 89 15368-211 The noise generated by the driver amplifier must be kept low enough to preserve the SNR and transition noise performance of the AD4001/AD4005. The noise from the driver is filtered by the single-pole, low-pass filter of the AD4001/AD4005 analog input circuit made by RIN and CIN, or by the external filter, if one is used. Because the typical noise of the AD4001/AD4005 is 54 µV rms, the SNR degradation due to the amplifier is SRN, SINAD (dB) DRIVER AMPLIFIER CHOICE Figure 40. Multiplexed Data Acquisition Signal Chain Using the AD4001/AD4005 Switching multiplexer channels typically results in large voltage steps at the ADC inputs. To ensure an accurate conversion result, the step must be given adequate time to settle before the ADC samples its inputs (on the rising edge of CNV). The settling time error is dependent on the drive circuitry (multiplexer and ADC driver), RC filter values, and the time when the multiplexer Rev. B | Page 22 of 37 Data Sheet AD4001/AD4005 EASE OF DRIVE FEATURES 15 HIGH-Z HIGH-Z HIGH-Z HIGH-Z 12 9 INPUT CURRENT (μA) channels are switched. Switch the multiplexer channels immediately after tQUIET1 has elapsed from the start of the conversion to maximize settling time while preventing corruption of the conversion result. To avoid conversion corruption, do not switch the channels during the tQUIET1 time. If the analog inputs are multiplexed during the quiet conversion time (tQUIET1), the current conversion may be corrupted. Input Span Compression DISABLED, 2MSPS DISABLED, 1MSPS ENABLED, 2MSPS ENABLED, 1MSPS 6 3 0 –3 –6 –9 90% OF VREF = 3.69V 10% OF VREF = 0.41V DIGITAL OUTPUT +FSR ALL 2N CODES ADC IN+/IN– ANALOG INPUT –FSR 15368-300 VREF = 4.096V 5V Figure 41. Span Compression High-Z Mode The AD4001/AD4005 incorporate high-Z mode, which reduces the nonlinear charge kickback when the capacitor DAC switches back to the input at the start of acquisition. Figure 42 shows the input current of the AD4001/AD4005 with high-Z mode enabled and disabled. The low input current makes the ADC easier to drive than the traditional SAR ADCs available in the market, even with high-Z mode disabled. The input current reduces further to submicroampere range when high-Z mode is enabled. The high-Z mode is disabled by default but can be enabled by writing to the register (see Table 14). Disable high-Z mode for input frequencies above 100 kHz or when multiplexing. –12 –15 –5 –4 –3 –2 –1 0 1 2 INPUT DIFFERENTIAL VOLTAGE (V) 3 4 5 15368-301 In single-supply applications, it is desirable to use the full range of the ADC; however, the amplifier can have some headroom and footroom requirements, which can be a problem, even if it is a rail-to-rail input and output amplifier. The AD4001/ AD4005 include a span compression increases the headroom and footroom available to the amplifier by reducing the input range by 10% from the top and bottom of the range while still accessing all available ADC codes (see Figure 41). The SNR decreases by approximately 1.9 dB (20 × log(8/10)) for the reduced input range when span compression is enabled. Span compression is disabled by default but can be enabled by writing to the relevant register bit (see the Digital Interface section). Figure 42. Input Current vs. Input Differential Voltage, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C To achieve the optimum data sheet performance from high resolution precision SAR ADCs, system designers are often forced to use a dedicated high power, high speed amplifier to drive the traditional switched capacitor SAR ADC inputs for their precision applications, which is commonly encountered in designing a precision data acquisition signal chain. The benefits of high-Z mode are low input current for slow (<10 kHz) or dc type signals and improved distortion (THD) performance over a frequency range of up to 100 kHz. High-Z mode allows a choice of lower power and lower bandwidth precision amplifiers with a lower RC filter cutoff to drive the ADC, removing the need for dedicated high speed ADC drivers, which saves system power, size, and cost in precision, low bandwidth applications. High-Z mode allows the amplifier and RC filter in front of the ADC to be chosen based on the signal bandwidth of interest and not based on the settling requirements of the switched capacitor SAR ADC inputs. Additionally, the AD4001/AD4005 can be driven with a much higher source impedance than traditional SARs, which means the resistor in the RC filter can have a value 10 times larger than previous SAR designs and, with high-Z mode enabled, can tolerate even larger impedance. Figure 43 shows the THD performance for various source impedances with high-Z mode disabled and enabled. Rev. B | Page 23 of 37 AD4001/AD4005 Data Sheet –80 –85 –85 –90 –90 –95 –95 THD (dB) –80 –100 –110 –115 150Ω HIGH-Z DISABLED 150Ω HIGH-Z ENABLED 510Ω HIGH-Z DISABLED 510Ω HIGH-Z ENABLED 1kΩ HIGH-Z DISABLED 1kΩ HIGH-Z ENABLED –115 –120 1 10 –125 15368-228 –125 20 INPUT FREQUENCY (kHz) Figure 43. THD vs. Input Frequency for Various Source Impedances, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C ADA4077-1 HIGH-Z ADA4077-1 HIGH-Z ADA4610-1 HIGH-Z ADA4610-1 HIGH-Z 260kHz 1.3kΩ 470pF 498kHz 680Ω 470pF DISABLED ENABLED DISABLED ENABLED 1.3MHz 680Ω 180pF 2.27MHz 390Ω 180pF 4.42MHz 200Ω 180pF RC FILTER BANDWIDTHS (Hz), RESISTOR (Ω), CAPACITOR (pF) Figure 44 and Figure 45 show the AD4001/AD4005 SNR and THD performance using the ADA4077-1 (supply current per amplifier (ISY) = 400 µA) and ADA4610-1 (ISY = 1.50 mA) precision amplifiers when driving the AD4001/AD4005 at full throughput for high-Z mode enabled and disabled with various RC filter values. These amplifiers achieve 93 dB to 96 dB typical SNR and better than −110 dB THD with high-Z mode enabled. THD is approximately 10 dB better with high-Z mode enabled, even for large R values. SNR maintains close to 96 dB, even with a very low RC bandwidth cutoff. When high-Z mode is enabled, the ADC consumes approximately 2 mW per MSPS extra power; however, this power is still significantly lower than using dedicated ADC drivers like the ADA4807-1. For any system, the front end usually limits the overall ac/dc performance of the signal chain. It is evident from the data sheets of the selected precision amplifiers, shown in Figure 44 and Figure 45, that their own noise and distortion performance dominates the SNR and THD specification at a certain input frequency. 97 Figure 45. THD vs. RC Filter Bandwidths for Various Precision ADC Drivers, fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C Long Acquisition Phase The AD4001/AD4005 also feature a very fast conversion time of 290 ns, which results in a long acquisition phase. The acquisition is further extended by a key feature of the AD4001/AD4005: the ADC returns to the acquisition phase typically 100 ns before the end of the conversion. This feature provides an even longer time for the ADC to acquire the new input voltage. A longer acquisition phase reduces the settling requirement on the driving amplifier, and a lower power/bandwidth amplifier can be chosen. The longer acquisition phase means that a lower RC filter (represented by R and C in Figure 32 to Figure 35) cutoff can be used, which means a noisier amplifier can also be tolerated. A larger value of R can be used in the RC filter with a corresponding smaller value of C, reducing amplifier stability concerns without affecting distortion performance significantly. A larger value of R also results in reduced dynamic power dissipation in the amplifier. See Table 10 for details on setting the RC filter bandwidth and choosing a suitable amplifier. VOLTAGE REFERENCE INPUT 94 A 10 µF (X7R, 0805 size) ceramic chip capacitor is appropriate for the optimum performance of the reference input. 91 88 SNR (dB) –105 –110 –120 For higher performance and lower drift, use a reference such as the ADR4550. Use a low power reference such as the ADR3450 at the expense of a slight decrease in the noise performance. It is recommended to use a reference buffer, such as the ADA4807-1, between the reference and the ADC reference input. It is important to consider the optimum capacitance necessary to keep the reference buffer stable as well as to meet the minimum ADC requirement previously stated in this section (that is, a 10 µF ceramic chip capacitor, CREF). 85 82 79 260kHz 1.3kΩ 470pF 498kHz 680Ω 470pF 1.3MHz 680Ω 180pF 2.27MHz 390Ω 180pF 4.42MHz 200Ω 180pF RC FILTER BANDWIDTHS (Hz), RESISTOR (Ω), CAPACITOR (pF) 15368-439 ADA4077-1 HIGH-Z DISABLED ADA4077-1 HIGH-Z ENABLED ADA4610-1 HIGH-Z DISABLED ADA4610-1 HIGH-Z ENABLED 76 73 –100 15368-440 –105 Figure 44. SNR vs. RC Filter Bandwidths for Various Precision ADC Drivers, fIN = 1 kHz (Turbo Mode On, High-Z Enabled/Disabled), VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C POWER SUPPLY The AD4001/AD4005 use two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. Rev. B | Page 24 of 37 Data Sheet AD4001/AD4005 To reduce the number of supplies needed, VIO and VDD can be tied together for 1.8 V operation. The ADP7118 low noise, CMOS, low dropout (LDO) linear regulator is recommended to power the VDD and VIO pins. The AD4001/AD4005 are independent of power supply sequencing between VIO and VDD. Additionally, the AD4001/AD4005 are insensitive to power supply variations over a wide frequency range, as shown in Figure 46. 80 The AD4001/AD4005 provide a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line, similar to a shift register. 75 The mode in which the device operates depends on the SDI level when the CNV rising edge occurs. CS mode is selected if SDI is high, and daisy-chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, daisy-chain mode is always selected. PSRR (dB) 70 65 60 50 100 1k 10k 100k 1M FREQUENCY (Hz) 15368-302 55 Figure 46. PSRR vs. Frequency, VDD = 1.8 V, VIO = 3.3 V, VREF = 5 V, 25°C The AD4001/AD4005 power down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This feature makes the device ideal for low sampling rates (even a few samples per second) and batterypowered applications. Figure 47 shows the AD4001/AD4005 total power dissipation and individual power dissipation for each rail. 100k 10k VDD VIO REF TOTAL POWER In either 3-wire or 4-wire mode, the AD4001/AD4005 offer the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. The busy indicator feature is enabled in CS mode if CNV or SDI is low when the ADC conversion ends. The state of SDO on power-up is either low or high-Z depending on the states of CNV and SDI, as shown in in Table 11. Table 11. State of SDO on Power-Up CNV 0 0 1 1 SDI 0 1 0 1 SDO Low Low Low High-Z 1k The AD4001/AD4005 have turbo mode capability in both 3-wire and 4-wire mode. Turbo mode is enabled by writing to the configuration register and replaces the busy indicator feature when enabled. Turbo mode allows a slower SPI clock rate, making interfacing simpler. The maximum throughput of 2 MSPS for the AD4001 can be achieved only with turbo mode enabled and a minimum SCK rate of 70 MHz. 100 10 1 0.1 0.01 10 POWER DISSIPATION MEASUREMENTS APPLY TO EACH PRODUCT OVER ITS SPECIFIED THROUGHPUT RANGE. 100 1k 10k THROUGHPUT (SPS) 100k 1M 2M 15368-220 POWER DISSIPATION (µW) interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections, which is useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This interface is useful in low jitter sampling or simultaneous sampling applications. Figure 47. Power Dissipation vs. Throughput, VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V, 25°C DIGITAL INTERFACE Although the AD4001/AD4005 have a reduced number of pins, they offer flexibility in their serial interface modes. The AD4001/ AD4005 can also be programmed via 16-bit SPI writes to the configuration registers. When in CS mode, the AD4001/AD4005 are compatible with SPI, QSPI™, MICROWIRE®, digital hosts, and DSPs. In this mode, the AD4001/AD4005 can use either a 3-wire or 4-wire The SCK rate must be sufficiently fast to ensure the conversion result is clocked out before another conversion initiates. The minimum required SCK rate for an application can be derived based on the sample period (tCYC), the number of bits that must be read (including data and optional status bits), and which digital interface mode is used. Timing diagrams and explanations for each digital interface mode are given in the digital modes of operation sections (see the CS Mode, 3-Wire Turbo Mode section through the Daisy-Chain Mode section). Status bits can also be clocked out at the end of the conversion data if the status bits are enabled in the configuration register. There are six status bits in total, as described in Table 12. Rev. B | Page 25 of 37 AD4001/AD4005 Data Sheet Table 13. Command Register The AD4001/AD4005 are configured by 16-bit SPI writes to the desired configuration register. The 16-bit word can be written via the SDI line while CNV is held low. The 16-bit word consists of an 8-bit header and 8-bit register data. For isolated systems, the ADuM141D is recommended, which can support the 70 MHz SCK rate required to run the AD4001 at its full throughput of 2 MSPS. Bit 7 WEN Bit 5 0 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 0 Bit 0 0 All register read/writes must occur while CNV is low. Data on SDI is clocked in on the rising edge of SCK. Data on SDO is clocked out on the falling edge of SCK. At the end of the data transfer, SDO is put in a high impedance state on the rising edge of CNV if daisy-chain mode is not enabled. If daisy-chain mode is enabled, SDO goes low on the rising edge of CNV. Register reads are not allowed in daisy-chain mode. REGISTER READ/WRITE FUNCTIONALITY The AD4001/AD4005 register bits are programmable, and their default statuses are shown in Table 12. The register map is shown in Table 14. The overvoltage clamp flag (OV) is a read only sticky bit, and it is cleared only if the register is read and the overvoltage condition is no longer present. It gives an indication of overvoltage condition when it is set to 0. A register write requires three signal lines: SCK, CNV, and SDI. During a register write, to read the current conversion results on SDO, the CNV pin must be brought low after the conversion is completed; otherwise, the conversion results may be incorrect on SDO. However, the register write occurs regardless. Table 12. Register Bits Register Bits Overvoltage (OV) Clamp Flag Span Compression High-Z Mode Turbo Mode Enable Six Status Bits Bit 6 R/W The LSB of each configuration register is reserved because a user reading 16-bit conversion data may be limited to a 16-bit SPI frame. The state of SDI on the last bit in the SDI frame may be the state that then persists when CNV rises. Because interface mode is partly set based on the SDI state when CNV rises, in this scenario, the user may need to set the final SDI state. Default Status 1 bit, 1 = inactive (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) 1 bit, 0 = disabled (default) The timing diagrams in Figure 48 through Figure 50 show how data is read and written when the AD4001/AD4005 are configured in register read, write, and daisy-chain mode. All access to the register map must start with a write to the 8-bit command register in the SPI interface block. The AD4001/AD4005 ignore all 1s until the first 0 is clocked in; the value loaded into the command register is always a 0 followed by seven command bits. This command determines whether that operation is a write or a read. The AD4001/AD4005 command register is shown in Table 13. Table 14. Register Map ADDR[1:0] 0x0 Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Enable six status bits Bit 3 Span compression Bit 2 High-Z mode Bit 1 Turbo mode Bit 0 Overvoltage (OV) clamp flag (read only sticky bit) Reset 0xE1 tCYC tCNVH tSCK CNV tSCNVSCK 1 2 3 4 5 6 8 7 9 10 11 tHSDISCK 1 WEN R/W 0 1 0 1 ADDR[1:0] 1 0 1 0 1 0 0 0 D17 D16 D15 14 15 16 tHSDO tDSDO tEN SDO 13 tSCKH tSSDISCK SDI 12 D14 D13 D12 D11 D10 B7 B6 tDIS B5 B4 Figure 48. Register Read Timing Diagram (X Means Don’t Care) Rev. B | Page 26 of 37 B3 B2 B1 B0 X 15368-021 SCK tSCKL Data Sheet AD4001/AD4005 tCYC tSCK tCNVH 1 tHCNVSCK CNV tSCNVSCK SCK 1 tSCKL 2 3 4 5 9 10 tHSDISCK 11 12 13 14 15 16 tSCKH tSSDISCK SDI 1 WEN R/W 0 1 0 1 0 0 1 0 1 0 B7 ADDR[1:0] 0 B6 0 D15 D14 D13 D12 D11 D10 D9 B4 B3 B2 B1 1 B0 tHSDO tDSDO EN SDO B5 D8 D7 D6 D5 D4 D3 D2 D1 D0 15368-022 CONVERSION RESULT ON D[15:0] 1THE USER MUST WAIT tCONV WHEN READING BACK THE CONVERSION RESULT AND PERFORMING A REGISTER WRITE AT THE SAME TIME. Figure 49. Register Write Timing Diagram tCYC tCNVH tSCK CNV tSCNVSCK SCK tSCKL 1 24 tSCKH SDIA SDOA/SDIB 0 COMMAND (0x14) 0 DATA (0xAB) COMMAND (0x14) 0 DATA (0xAB) 0 0 COMMAND (0x14) Figure 50. Register Write Timing Diagram, Daisy-Chain Mode Rev. B | Page 27 of 37 0 15368-023 tDIS SDOB AD4001/AD4005 Data Sheet STATUS WORD The SDO line goes to high-Z after the sixth status bit is clocked out (except in daisy-chain mode). The user is not required to clock out all status bits to start the next conversion. The serial interface timing for CS mode, 3-wire without busy indicator, including status bits, is shown in Figure 51. The 6-bit status word can be appended to the end of a conversion result, and the default conditions of these bits are shown in Table 15. The status bits must be enabled in the register setting. When the overvoltage clamp flag (OV) is a 0, it indicates an overvoltage condition. The overvoltage clamp flag status bit updates on a per conversion basis. Table 15. Status Bits (Default Conditions) Bit 5 Overvoltage (OV) clamp flag Bit 4 Span compression Bit 3 High-Z mode Bit 2 Turbo mode Bit 1 Reserved Bit 0 Reserved SDI = 1 tCYC tCNVH CN V ACQ ACQUISITION CONVERSION ACQUISITION tSCK tCONV tQUIET2 tSCKL 1 2 3 14 21 22 tSCKH tHSDO tEN SDO 20 16 15 tDSDO D15 D14 D13 tDIS D1 D0 B1 STATUS BITS B[5:0] Figure 51. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram, Including Status Bits (SDI High) Rev. B | Page 28 of 37 B0 15368-024 SCK Data Sheet AD4001/AD4005 When SDI is forced high, a rising edge on CNV initiates a conversion. The previous conversion data is available to read after the CNV rising edge. The user must wait tQUIET1 time after CNV is brought high before bringing CNV low to clock out the previous conversion result. The user must also wait tQUIET2 time after the last falling edge of SCK to when CNV is brought high. CS MODE, 3-WIRE TURBO MODE This mode is typically used when a single AD4001/AD4005 device is connected to an SPI-compatible digital host. It provides additional time during the end of the ADC conversion process to clock out the previous conversion result, providing a lower SCK rate. The AD4001 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 70 MHz. With turbo mode enabled, the AD4005 can also achieve its maximum throughput rate of 1 MSPS with a minimum SCK rate of 22 MHz. The connection diagram is shown in Figure 52, and the corresponding timing diagram is shown in Figure 53. When the conversion is complete, the AD4001/AD4005 enter the acquisition phase and power down. When CNV goes low, the MSB is output to SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. This mode replaces the 3-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14). CONVERT DIGITAL HOST CNV VIO SDI AD4001/ AD4005 DATA IN SDO 15368-125 SCK CLK Figure 52. CS Mode, 3-Wire Turbo Mode Connection Diagram (SDI High) SDI = 1 tCYC CNV tACQ ACQUISITION ACQUISITION CONVERSION tSCK CONV tSCKL QUIET2 tQUIET1 1 2 3 14 15 tSCKH tHSDO tEN SDO 16 tDSDO D15 D14 D13 tDIS D1 D0 Figure 53. CS Mode, 3-Wire Turbo Mode Serial Interface Timing Diagram (SDI High) Rev. B | Page 29 of 37 15368-029 SCK AD4001/AD4005 Data Sheet When the conversion is complete, the AD4001/AD4005 enter the acquisition phase and power down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is typically used when a single AD4001/AD4005 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 54, and the corresponding timing diagram is shown in Figure 55. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. After a conversion is initiated, it continues until completion irrespective of the state of CNV. This feature can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. There must not be any digital activity on SCK during the conversion. CONVERT DIGITAL HOST CNV VIO AD4001/ AD4005 SDI SDO DATA IN 15368-025 SCK CLK Figure 54. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL SCK 1 2 3 14 15 16 tSCKH HSDO tDSDO tEN SDO tQUIET2 D15 D14 D13 tDIS D1 Figure 55. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing Diagram (SDI High) Rev. B | Page 30 of 37 D0 15368-026 ACQUISITION Data Sheet AD4001/AD4005 When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD4001/AD4005 then enter the acquisition phase and power down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is typically used when a single AD4001/AD4005 is connected to an SPI-compatible digital host with an interrupt input (IRQ). The connection diagram is shown in Figure 56, and the corresponding timing diagram is shown in Figure 57. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can select other SPI devices, such as analog multiplexers; however, CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple AD4001/AD4005 devices are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. There must not be any digital activity on the SCK during the conversion. CONVERT VIO DIGITAL HOST CNV VIO 1kΩ AD4001/ AD4005 SDO DATA IN IRQ SCK 15368-027 SDI CLK Figure 56. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL SCK 1 2 3 tQUIET2 15 tHSDO 16 17 tSCKH tDSDO SDO D15 D14 tDIS D1 Figure 57. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing Diagram (SDI High) Rev. B | Page 31 of 37 D0 15368-028 ACQUISITION AD4001/AD4005 Data Sheet rising edge. The user must wait tQUIET1 time after CNV is brought high before bringing SDI low to clock out the previous conversion result. The user must also wait tQUIET2 time after the last falling edge of SCK to when CNV is brought high. CS MODE, 4-WIRE TURBO MODE This mode is typically used when a single AD4001/AD4005 device is connected to an SPI-compatible digital host. It provides additional time during the end of the ADC conversion process to clock out the previous conversion result, giving a lower SCK rate. The AD4001 can achieve a throughput rate of 2 MSPS only when turbo mode is enabled and using a minimum SCK rate of 70 MHz. With turbo mode enabled, the AD4005 can also achieve its maximum throughput rate of 1 MSPS with a minimum SCK rate of 22 MHz. The connection diagram is shown in Figure 58, and the corresponding timing diagram is shown in Figure 59. When the conversion is complete, the AD4001/AD4005 enter the acquisition phase and power down. The ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance. This mode replaces the 4-wire with busy indicator mode by programming the turbo mode bit, Bit 1 (see Table 14). With SDI high, a rising edge on CNV initiates a conversion. The previous conversion data is available to read after the CNV CS1 CONVERT VIO DIGITAL HOST CNV 1kΩ AD4001/ AD4005 SDO DATA IN IRQ SCK 15368-032 SDI CLK Figure 58. CS Mode, 4-Wire Turbo Mode Connection Diagram CNV tCYC tSSDICNV SDI tHSDICNV ACQUISITION tACQ CONVERSION ACQUISITION tSCK tCONV tSCKL tQUIET2 tQUIET1 1 2 3 14 tHSDO 16 tSCKH tEN SDO 15 tDIS tDSDO D15 D14 D13 Figure 59. CS Mode, 4-Wire Turbo Mode Timing Diagram Rev. B | Page 32 of 37 D1 D0 15368-034 SCK Data Sheet AD4001/AD4005 When the conversion is complete, the AD4001/AD4005 enter the acquisition phase and power down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD4001/AD4005 can be read. CS MODE, 4-WIRE WITHOUT BUSY INDICATOR This mode is typically used when multiple AD4001/AD4005 devices are connected to an SPI-compatible digital host. A connection diagram example using two AD4001/AD4005 devices is shown in Figure 60, and the corresponding timing diagram is shown in Figure 61. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers; however, SDI must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. CS2 CS1 CONVERT CNV CNV AD4001/ AD4005 SDI SDO SDI AD4001/ AD4005 DEVICE A DEVICE B SCK SCK DIGITAL HOST SDO 15368-030 DATA IN CLK Figure 60. CS Mode, 4-Wire Without Busy Indicator Connection Diagram CYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tQUIET2 tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 3 14 tHSDO 16 17 18 30 31 32 tSCKH tDSDO tEN SDO 15 D15 D14 D13 tDIS D1 D0 D15 D14 Figure 61. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram Rev. B | Page 33 of 37 D1 D0 15368-031 SCK AD4001/AD4005 Data Sheet SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. CS MODE, 4-WIRE WITH BUSY INDICATOR This mode is typically used when a AD4001/AD4005 device is connected to an SPI-compatible digital host with an interrupt input (IRQ), and when it is desired to keep CNV, which samples the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up resistor of 1 kΩ on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD4001/AD4005 then enter the acquisition phase and power down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance. The connection diagram is shown in Figure 62, and the corresponding timing diagram is shown in Figure 63. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. If SDI and CNV are low, SDO is driven low. Prior to the minimum conversion time, SDI can select other SPI devices, such as analog multiplexers; however, CS1 CONVERT VIO DIGITAL HOST CNV 1kΩ AD4001/ AD4005 SDO DATA IN IRQ SCK 15368-132 SDI CLK Figure 62. CS Mode, 4-Wire with Busy Indicator Connection Diagram tCYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV tQUIET2 tSSDICNV SDI tSCK tHSDICNV tSCKL SCK 1 2 3 15 16 17 tSCKH tHSDO tDSDO tDIS SDO D15 D14 D1 Figure 63. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram Rev. B | Page 34 of 37 D0 15368-033 tEN Data Sheet AD4001/AD4005 the daisy-chain outputs its data MSB first, and 16 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. The maximum conversion rate is reduced because of the total readback time. DAISY-CHAIN MODE Use this mode to daisy-chain multiple AD4001/AD4005 devices on a 3-wire or 4-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. It is possible to write to each ADC register in daisy-chain mode. The timing diagram is shown in Figure 50. This mode requires 4-wire operation because data is clocked in on the SDI line with CNV held low. The same command byte and register data can be shifted through the entire chain to program all ADCs in the chain with the same register contents, which requires 8 × (N + 1) clocks for N ADCs. It is possible to write different register contents to each ADC in the chain by writing to the furthest ADC in the chain, first using 8 × (N + 1) clocks, and then the second furthest ADC with 8 × N clocks, and so forth until reaching the nearest ADC in the chain, which requires 16 clocks for the command and register data. It is not possible to read register contents in daisy-chain mode; however, the six status bits can be enabled if the user wants to determine the ADC configuration. Note that enabling the status bits requires six extra clocks to clock out the ADC result and the status bits per ADC in the chain. Turbo mode cannot be used in daisy-chain mode. A connection diagram example using two AD4001/AD4005 devices is shown in Figure 64, and the corresponding timing diagram is shown in Figure 65. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects daisy-chain mode, and disables the busy indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO, and the AD4001/AD4005 enter the acquisition phase and power down. The remaining data bits stored in the internal shift register are clocked out of SDO by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK rising edges. Each ADC in CONVERT SDI CNV AD4001/ AD4005 SDO DIGITAL HOST AD4001/ AD4005 SDI DEVICE A DEVICE B SCK SCK SDO DATA IN 15368-036 CNV CLK Figure 64. Daisy-Chain Mode Connection Diagram SDIA = 0 tCYC CNV tACQ ACQUISITION CONVERSION tCONV tSCK tQUIET2 tSCKL tQUIET2 SCK 2 1 3 14 15 tSSDISCK tHSCKCNV 16 17 18 30 31 32 tSCKH tHSDISCK tEN DA15 SDOA = SDIB DA14 DA13 DA1 DA0 tHSDO tDIS tDSDO SDOB DB15 DB14 DB13 DB1 DB0 DA15 Figure 65. Daisy-Chain Mode Serial Interface Timing Diagram Rev. B | Page 35 of 37 DA14 DA1 DA0 15368-037 ACQUISITION AD4001/AD4005 Data Sheet LAYOUT GUIDELINES The PCB that houses the AD4001/AD4005 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD4001/AD4005, with its analog signals on the left side and its digital signals on the right side, eases this task. 15368-039 Avoid running digital lines under the device because they couple noise onto the die, unless a ground plane under the AD4001/ AD4005 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals. At least one ground plane must be used. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD4001/AD4005 devices. The AD4001/AD4005 voltage reference input (REF) has a dynamic input impedance. Decouple the REF pin with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to (ideally right up against) the REF and GND pins and connect them with wide, low impedance traces. Finally, decouple the VDD and VIO power supplies of the AD4001/AD4005 with ceramic capacitors, typically 0.1 µF, placed close to the AD4001/AD4005 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Figure 67. Example Layout of the AD4001 (Bottom Layer) EVALUATING THE AD4001/AD4005 PERFORMANCE Other recommended layouts for the AD4001/AD4005 are outlined in the user guide of the evaluation board for the AD4001 (EVAL-AD4001FMCZ). The evaluation board package includes a fully assembled and tested evaluation board with the AD4001 documentation, and software for controlling the board from a PC via the EVAL-SDP-CH1Z. The EVAL-AD4001FMCZ can also be used to evaluate the AD4005 by limiting the throughput to 1 MSPS in its software (see UG-1042). 15368-038 An example of the AD4001 layout following these rules is shown in Figure 66 and Figure 67. Note that the AD4005 layout is equivalent to the AD4001 layout. Figure 66. Example Layout of the AD4001 (Top Layer) Rev. B | Page 36 of 37 Data Sheet AD4001/AD4005 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 68. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIE W TOP VIEW PKG-004362 0.80 0.75 0.70 SEATING PLANE 0.05 MAX 0.02 NOM COPLANARITY 0.08 SIDE VIEW 0.30 0.25 0.20 0.20 MIN PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-07-2017-C PIN 1 INDEX AREA 0.20 REF Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD4001BCPZ-RL7 AD4001BRMZ AD4001BRMZ-RL7 AD4005BCPZ-RL7 AD4005BRMZ AD4005BRMZ-RL7 EVAL-AD4001FMCZ 1 2 Integral Nonlinearity (INL) ±0.4 LSB ±0.4 LSB ±0.4 LSB ±0.4 LSB ±0.4 LSB ±0.4 LSB Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 10-Lead LFCSP, Reel 10-Lead MSOP, Tube 10-Lead MSOP, Reel 10-Lead LFCSP, Reel 10-Lead MSOP, Tube 10-Lead MSOP, Reel AD4001 Evaluation Board Compatible with EVAL-SDP-CH1Z Ordering Quantity 1500 50 1000 1500 50 1000 Z = RoHS Compliant Part. The EVAL-AD4001FMCZ can also be used to evaluate the AD4005 by setting the throughput to 1 MSPS in its software (see UG-1042). ©2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15368-0-8/17(B) Rev. B | Page 37 of 37 Package Option CP-10-9 RM-10 RM-10 CP-10-9 RM-10 RM-10 Branding C8H C8H C8H C8T C8T C8T