ISSI IS61NLF204836B 100 percent bus utilization Datasheet

IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
2M x 36 and 4M x 18
72Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
ADVANCED INFORMATION
FEBRUARY 2013
FEATURES
DESCRIPTION
• 100 percent bus utilization
The 72 Meg product family features high-speed, low-power
synchronous static RAMs designed to provide a burstable,
high-performance, 'no wait' state, device for networking
and communications applications. They are organized as
2,096,952 words by 36 bits and 4,193,904 words by 18
bits, fabricated with ISSI's advanced CMOS technology.
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single Read/Write control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, and 165ball PBGA packages
• Power supply:
NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%)
NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%)
NVVF: Vdd 1.8V (± 5%), Vddq 1.8V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV
input. When the ADV is HIGH the internal burst counter
is incremented. New external addresses can be loaded
when ADV is LOW.
Write cycles are internally self-timed and are initiated
by the rising edge of the clock inputs and when WE is
LOW. Separate byte enables allow individual bytes to be
written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tkq
tkc
Parameter
Clock Access Time
Cycle Time
Frequency
6.5
6.5
7.5
133
7.5
7.5
8.5
117
Units
ns
ns
MHz
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
1
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
BLOCK DIAGRAM
A0-20 ( A0-21)
Address
Registers
MODE
ADV
2Mx36;
4Mx18
Memory Array
Burst Logic
A0-A1
A'0-A'1
K
K
Address
Registers
CLK
A0-20 ( A0-21)
A2-20(A2-A21)
A0-20(A0-21)
Address
Registers
/CKE
Data-In
Register
K
/CE
Control register
CE2
/CE2
ADV
/WE
/BWx
(X=a,b,c,d or a,b)
Data-In
Register
Control Logic
K
/OE
Output
Buffers
ZZ
36(18)
K
DQx/DQPx
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
165-PIN BGA
165-Ball, 13x15 mm BGA
165-Ball, 15x17 mm BGA
1mm Ball Pitch, 11x15 Ball Array
119-PIN BGA
119-Ball, 14x22 mm BGA
1.27mm Ball Pitch, 7x17 Ball Array
BOTTOM VIEW
BOTTOM VIEW
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
3
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION —
­ 2M x 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWc
BWb
CE2
CKE
ADV
A
A
NC
B
NC
A
CE2
BWd
BWa
CLK
WE
OE
A
A
NC
C
DQPc
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPb
D
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N
DQPd
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
DQPa
P
NC
A
A
A
TDI
A1*
TDO
A
A
A
NC
R
MODE
A
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE, CE2, CE2
BWa-BWd
OE
ZZ
4
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control Input
Synchronous Clock
Synchronous Clock Enable
Synchronous Chip Enable
Synchronous Byte Write Inputs
Asynchronous Output Enable
Asynchronous Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQd
DQPa-DQPd
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN PBGA PACKAGE CONFIGURATION
2M x 36 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WE
VSS
DQb
DQb
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
CKE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1*
VSS
DQa
DQa
P
DQd
DQPd
VSS
A0*
VSS
DQPa
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
NC
A
A
A
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWd
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQd
DQPa-DQPd
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
5
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
165-PIN PBGA PACKAGE CONFIGURATION
4M x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
CKE
ADV
A
A
A
B
NC
A
CE2
NC
BWa
CLK
WE
OE
A
A
NC
C
NC
NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPa
D
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
H
NC
NC
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
N
DQPb
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
P
NC
A
A
A
TDI
A1*
TDO
A
A
A
NC
R
MODE
A
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWb
OE
ZZ
6
Synchronous Byte Write Inputs
Asynchronous Output Enable
Asynchronous Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQb
DQPa-DQPb
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
119-PIN PBGA PACKAGE CONFIGURATION
4M x 18 (TOP VIEW)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
NC
CE2
A
ADV
A
CE2
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
NC
DQb
VSS
CE
VSS
NC
DQa
F
VDDQ
NC
VSS
OE
VSS
DQa
VDDQ
G
NC
DQb
BWb
A
NC
NC
DQa
H
DQb
NC
VSS
WE
VSS
DQa
NC
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
NC
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
CKE
VSS
NC
VDDQ
N
DQb
NC
VSS
A1*
VSS
DQa
NC
P
NC
DQPb
VSS
A0*
VSS
NC
DQa
R
NC
A
MODE
VDD
NC
A
NC
T
A
A
A
A
A
A
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWb
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQb
DQPa-DQPb
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
7
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
MODE
DQd
DQd
DQPd
A
OE
ADV
A
CKE
CLK
WE
CE2
VDD
Vss
BWa
BWc
BWb
BWd
CE2
CE
A
A
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
A
A
DQd
A
NC
Vss
A
DQc
NC
VDD
A
DQc
A
A
A
VDDQ
A
Vss
Vss
DQc
VDD
DQc
NC
NC
DQc
DQc
A1
A0
Vss
A
VDDQ
A
DQc
A
DQc
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
DQPc
A
A
100-Pin TQFP
2M x 36
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWd
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
8
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQd
DQPa-DQPd
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
PIN CONFIGURATION
DQb
DQPb
NC
Vss
VDDQ
MODE
NC
NC
NC
A
ADV
A
OE
CLK
WE
CKE
CE2
VDD
Vss
BWa
NC
BWb
NC
CE2
CE
A
A
A
NC
NC
VDDQ
Vss
NC
DQPa
DQa
DQa
Vss
VDDQ
DQa
DQa
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
NC
NC
Vss
VDDQ
NC
NC
NC
A
A
Vss
DQb
A
DQb
VDDQ
A
DQb
A
NC
Vss
A
A
A
DQb
NC
VDD
A
DQb
VDD
VDDQ
Vss
DQb
Vss
NC
NC
DQb
A1
A0
NC
NC
A
VDDQ
Vss
A
NC
A
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
A
A
100-Pin TQFP
4M x 18
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
Pin Name
Synchronous Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWa-BWb
Synchronous Byte Write Inputs
OE
Asynchronous Output Enable
ZZ
Asynchronous Power Sleep Mode
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQa-DQb
DQPa-DQPb
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
Power Supply
No Connect
Synchronous Data Inputs/Outputs
Synchronous Parity Data Inputs/Outputs
I/O Power Supply
Ground
9
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
STATE DIAGRAM
READ
READ
READ
BURST
WRITE
BEGIN
READ
DS
DS
READ
WRITE
DESELECT
BURST
BURST
READ
BEGIN
WRITE
BURST
DS
BURST
DS
DS
WRITE
READ
BURST
WRITE
WRITE
WRITE
BURST
SYNCHRONOUS TRUTH TABLE(1)
Operation
Not Selected
Not Selected
Not Selected
Not Selected Continue
Begin Burst Read
Continue Burst Read
NOP/Dummy Read
Dummy Read
Begin Burst Write
Continue Burst Write
NOP/Write Abort
Write Abort
Ignore Clock
Notes:
Address
Used
N/A
N/A
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
CE
H
X
X
X
L
X
L
X
L
X
L
X
X
CE2
X
L
X
X
H
X
H
X
H
X
H
X
X
CE2
X
X
H
X
L
X
L
X
L
X
L
X
X
ADV
L
L
L
H
L
H
L
H
L
H
L
H
X
WE
X
X
X
X
H
X
H
X
L
X
L
X
X
BWx
X
X
X
X
X
X
X
X
L
L
H
H
X
OE
X
X
X
X
L
L
H
H
X
X
X
X
X
CKE
L
L
L
L
L
L
L
L
L
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
1.
2.
3.
4.
"X" means don't care.
The rising edge of clock is symbolized by ↑
A continue deselect cycle can only be entered if a deselect cycle is executed first.
WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
ASYNCHRONOUS TRUTH TABLE(1)
Operation
Sleep Mode
Read
Write
Deselected
Notes:
ZZ
H
L
L
L
L
I/O STATUS
High-Z
DQ
High-Z
Din, High-Z
High-Z
OE
X
L
H
X
X
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE ALL BYTEs
WRITE ABORT/NOP
Notes:
WE
H
L
L
L
L
BWa
X
L
H
L
H
BWb
X
H
L
L
H
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
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11
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
WRITE TRUTH TABLE (x36)
Operation
READ
WRITE BYTE a
WRITE BYTE b
WRITE BYTE c
WRITE BYTE d
WRITE ALL BYTEs
WRITE ABORT/NOP
Notes:
WE
H
L
L
L
L
L
L
BWa
X
L
H
H
H
L
H
BWb
X
H
L
H
H
L
H
BWc
X
H
H
L
H
L
H
BWd
X
H
H
H
L
L
H
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
POWER UP SEQUENCE
Vddq → Vdd1 → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is ready. The inputs of the I/O pins can be applied at the
same time as Vddq provided Vih (level of I/O pins) is lower than Vddq.
POWER-UP INITIALIZATION TIMING
VDD
power > 1ms
VDD
VDDQ
Device Initialization
Device ready for
normal operation
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
A1 A0
00
01
10
11
12
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Tstg
Pd
Iout
Vin, Vout
Vin
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for for Address and Control Inputs
NLF Value
–65 to +150
1.6
100
–0.5 to Vddq + 0.3
–0.3 to Vdd + 0.5
NVF/NVVF Value
–65 to +150
1.6
100
–0.5 to Vddq + 0.3
–0.3 to Vdd + 0.3
Unit
°C
W
mA
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLFx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
Vdd
3.3V ± 5%
3.3V ± 5%
Vddq
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
Vdd
2.5V ± 5%
2.5V ± 5%
Vddq
2.5V ± 5%
2.5V ± 5%
Vdd
1.8V ± 5%
1.8V ± 5%
Vddq
1.8V ± 5%
1.8V ± 5%
OPERATING RANGE (IS61NVFx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
OPERATING RANGE (IS61NVVFx)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
-40°C to +85°C
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
13
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 1, 2, 3
3.3V2.5V1.8V
Symbol Parameter
Test Conditions
Min. Max.
Min.Max.
Min.Max. Unit
Voh
Output HIGH Voltage
Ioh = –4.0 mA (3.3V)
2.4 —
2.0 —
Vddq - 0.4 —
V
Ioh = –1.0 mA (2.5V, 1.8V)
Vol
Output LOW Voltage
Iol = 8.0 mA (3.3V)
— 0.4
— 0.4
— 0.4
V
Iol = 1.0 mA (2.5V, 1.8V)
Vih
Input HIGH Voltage 2.0Vdd + 0.3
1.7Vdd + 0.3 0.6VddVdd + 0.3 V
Vil
Input LOW Voltage
–0.3 0.8
–0.3 0.7
–0.30.3Vdd V
(1,4)
Ili
Input Leakage Current
Vss ≤ Vin ≤ Vdd
–5 5
–5 5
–5 5
µA
Input Current of MODE
Vss ≤ Vin ≤ Vdd(5)
–30 5
–30 5
–30 5
Input Current of ZZ
Vss ≤ Vin ≤ Vdd(6)
–5 30
–5 30
–5 30
Ilo
Output Leakage Current
Vss ≤ Vout ≤ Vddq, OE = Vih
–5 5
–5 5
–5 5
µA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
4. Except MODE and ZZ.
5. MODE is connected to pull-up resister internally.
6. ZZ is connected to pull-down resister internally
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Icc
AC Operating
Supply Current
Isb
Standby Current
TTL Input
Isbi
Standby Current
CMOS Input
14
Test Conditions
Temp. range
Device Selected,
Com.
OE = Vih, ZZ ≤ Vil,
Ind.
All Inputs ≤ 0.2V or ≥ Vdd – 0.2V,
Cycle Time ≥ tkc min.
Device Deselected,
Com.
Vdd = Max.,
Ind.
All Inputs ≤ Vil or ≥ Vih,
ZZ ≤ Vil, f = Max.
Device Deselected,
Com.
Vdd = Max.,
Ind.
Vin ≤ Vss + 0.2V or ≥Vdd – 0.2V
f=0
6.5
7.5
MAX
MAX
x18
x36
x18
x36
260 260
240 240
270 270
250 250
Unit
mA
130
135
130
135
130
135
130
135
mA
115
120
115
120
115
120
115
120
mA
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CAPACITANCE(1,2)
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317 Ω
+3.3V
Zo= 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
351 Ω
1.5V
Figure 1
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
Figure 2
15
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667 Ω
+2.5V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1,538 Ω
1.25V
Figure 3
Figure 4
1.8V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 1.8V
1.5 ns
0.9V
See Figures 5 and 6
1.8V I/O OUTPUT LOAD EQUIVALENT
1K Ω
+1.8V
ZO = 50Ω
OUTPUT
OUTPUT
50Ω
5 pF
Including
jig and
scope
1K Ω
0.9V
Figure 5
16
Figure 6
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Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
fmax
tkc
tkh
tkl
tkq
tkqx(2)
tkqlz(2,3)
tkqhz(2,3)
toeq
toelz(2,3)
toehz(2,3)
tas
tws
tces
tse
tadvs
tds
tah
the
twh
tceh
tadvh
tdh
tpower(4)
Notes:
1.
2.
3.
4.
Parameter
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
Address Hold Time
Clock Enable Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
Vdd (typical) to First Access
6.5
Min.
—
7.5
2.2
2.2
—
2.5
2.5
—
—
0
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
Max.
133
—
—
—
6.5
—
—
3.8
3.2
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
7.5
Min. Max.
—
117
8.5
—
2.5
—
2.5
—
—
7.5
2.5
—
2.5
—
—
4.0
—
3.4
0
—
—
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Configuration signal MODE is static and must not change during normal operation.
Guaranteed but not 100% tested. This parameter is periodically sampled.
Tested with load in Figure 2.
tpower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
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Rev. 00C
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17
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol Parameter
Conditions Temperature
Range
Isb2
Current during SNOOZE MODE ZZ ≥ Vdd - 0.2V
Com.
Ind.
Auto.
tpds
ZZ active to input ignored
tpus
ZZ inactive to input sampled
tzzi
ZZ active to SNOOZE current
trzzi
ZZ inactive to exit SNOOZE current
Min. Max.
—
—
—
—
2
—
0
Unit
80
mA
90
100
2
cycle
—
cycle
2
cycle
—
ns
SLEEP MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs
(Q)
High-Z
Don't Care
18
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
READ CYCLE TIMING
tKH tKL
CLK
tKC
tADVS tADVH
ADV
tAS tAH
Address
A1
A3
A2
tWS tWH
WRITE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ
tOEHZ
Data Out
Q1-1
tOEHZ
tDS
Q2-1
tKQ
Q2-2
tKQHZ
Q2-3
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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Rev. 00C
02/20/2013
Q2-4
Q3-1
Q3-2
Q3-3
Q3-4
Don't Care
Undefined
19
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
WRITE CYCLE TIMING
tKH tKL
CLK
tKC
ADV
Address
A1
A3
A2
WRITE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1
D2-1
D2-2
D2-4
D2-3
D3-1
tDH
D3-2
D3-3
D3-4
tOEHZ
Data Out
Q0-4
NOTES: WRITE = L means WE = L and BWx = L
WE = L and BWX = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
20
Don't Care
Undefined
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Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
SINGLE READ/WRITE CYCLE TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
CE
ADV
OE
tOEQ
Data Out
tOELZ
Q1
Q3
Q6
Q4
Q7
tDS tDH
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
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Rev. 00C
02/20/2013
D5
Don't Care
Undefined
21
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CKE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CE
ADV
OE
tKQ
Data Out
tKQLZ
tKQHZ
Q1
Q3
Q4
tDS tDH
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
22
D5
Don't Care
Undefined
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Rev. 00C
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
CE OPERATION TIMING
tKH
tKL
CLK
tSE tHE
tKC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CE
ADV
OE
tOEQ
Data Out
tOELZ
tKQHZ
Q1
tKQ
tKQLZ
Q2
Q4
tDS tDH
Data In
D3
NOTES: WRITE = L means WE = L and BWx = L
CE = L means CE1 = L, CE2 = H and CE2 = L
CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
D5
Don't Care
Undefined
23
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
TEST ACCESS PORT (TAP) - TEST CLOCK
The serial boundary scan Test Access Port (TAP) is only
available in the PBGA package. (Not available in TQFP
package.) This port operates in accordance with IEEE
Standard 1149.1-1900, but does not include all functions
required for full 1149.1 compliance. These functions from
the IEEE specification are excluded because they place
added delay in the critical speed path of the SRAM. The
TAP controller operates in a manner that does not conflict
with the performance of other devices using 1149.1 fully
compliant TAPs.
The test clock is only used with the TAP controller. All inputs
are captured on the rising edge of TCK and outputs are
driven from the falling edge of TCK.
DISABLING THE JTAG FEATURE
The TDI pin is used to serially input information to the
registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the
instruction loaded into the TAP instruction register. For
information on instruction register loading, see the TAP
Controller State Diagram. TDI is internally pulled up and
can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB)
on any register.
The SRAM can operate without using the JTAG feature.
To disable the TAP controller, TCK must be tied LOW
(Vss) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be disconnected. They may
alternately be connected to Vdd through a pull-up resistor.
TDO should be left disconnected. On power-up, the device
will start in a reset state which will not interfere with the
device operation.
TEST MODE SELECT (TMS)
The TMS input is used to send commands to the TAP
controller and is sampled on the rising edge of TCK. This
pin may be left disconnected if the TAP is not used. The
pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
TAP CONTROLLER BLOCK DIAGRAM
0
Bypass Register
2
1
0
Instruction Register
TDI
Selection Circuitry
31 30 29
. . .
Selection Circuitry
2
1
0
2
1
0
TDO
Identification Register
x
. . . . .
Boundary Scan Register*
TCK
TMS
24
TAP CONTROLLER
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IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from
the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller
State Diagram). The output changes on the falling edge
of TCK and TDO is connected to the Least Significant Bit
(LSB) of any register.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (Vdd) for five
rising edges of TCK. RESET may be performed while the
SRAM is operating and does not affect its operation. At
power-up, the TAP is internally reset to ensure that TDO
comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins
and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time
through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on
the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed
between the TDI and TDO pins. (See TAP Controller Block
Diagram) At power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the
IDCODE instruction if the controller is placed in a reset
state as previously described.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern
to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers,
it is sometimes advantageous to skip certain states. The
bypass register is a single-bit register that can be placed
between TDI and TDO pins. This allows data to be shifted
through the SRAM with minimal delay. The bypass reg-
ister is set LOW (Vss) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 75-bit-long
register and the x18 configuration also has a 75-bit-long
register. The boundary scan register is loaded with the
contents of the RAM Input and Output ring when the TAP
controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved
to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD
and SAMPLE-Z instructions can be used to capture the
contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which
the bits are connected. Each bit corresponds to one of the
bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Scan Register Sizes
Register
Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
(x18)
3
1
32
75
Bit Size
(x36)
3
1
32
75
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit
code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE
is hardwired into the SRAM and can be shifted out when
the TAP controller is in the Shift-DR state. The ID register
has vendor code and other information described in the
Identification Register Definitions table.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
Defines depth of SRAM. 2M or 4M
Defines Width of the SRAM. x36 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
2M x 36
xxxx
01010
00100
xxxxx
00001010101
1
4M x 18
xxxx
01011
00011
xxxxx
00001010101
1
25
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP INSTRUCTION SET
SAMPLE/PRELOAD
Eight instructions are possible with the three-bit instruction
register and all combinations are listed in the Instruction
Code table. Three instructions are listed as RESERVED
and should not be used and the other five instructions are
described below. The TAP controller used in this SRAM
is not fully compliant with the 1149.1 convention because
some mandatory instructions are not fully implemented.
The TAP controller cannot be used to load address, data or
control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of SAMPLE/
PRELOAD; instead it performs a capture of the Inputs and
Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI
and TDO. During this state, instructions are shifted from
the instruction register through the TDI and TDO pins. To
execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant. When the
SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock
runs more than an order of magnitude faster. Because of
the clock frequency differences, it is possible that during
the Capture-DR state, an input or output will under-go a
transition. The TAP may attempt a signal capture while in
transition (metastable state). The device will not be harmed,
but there is no guarantee of the value that will be captured
or repeatable results.
To guarantee that the boundary scan register will capture
the correct signal value, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up
plus hold times (tcs and tch). To insure that the SRAM
clock input is captured correctly, designs need a way to
stop (or slow) the clock during a SAMPLE/PRELOAD
instruction. If this is not an issue, it is possible to capture
all other signals and simply ignore the value of the CLK
captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data
by putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with
all 0s. Because EXTEST is not implemented in the TAP
controller, this device is not 1149.1 standard compliant.
The TAP controller recognizes an all-0 instruction. When an
EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST
places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO
pins and allows the IDCODE to be shifted out of the device
when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a
test logic reset state.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also places
all SRAM outputs into a High-Z state.
26
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state,
the bypass register is placed between the TDI and TDO
pins. The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instructions are not implemented but are reserved
for future use. Do not use these instructions.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
INSTRUCTION CODES
Code
000
Instruction
EXTEST
001
IDCODE
010
SAMPLE-Z
011
100
RESERVED
SAMPLE/PRELOAD
101
RESERVED
110
111
RESERVED
BYPASS
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between
TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction does not
implement 1149.1 preload function and is therefore not 1149.1 compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset
1
0
Run Test/Idle
1
Select DR
0
0
1
1
1
Capture DR
0
Shift DR
1
Exit1 DR
0
Select IR
0
1
Exit1 IR
0
Pause DR
0
1
0
1
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
Exit2 DR
1
Update DR
0
Capture IR
0
Shift IR
1
0
Pause IR
1
0
1
1
0
1
0
Exit2 IR
1
Update IR
0
27
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP Electrical Characteristics (Vddq = 3.3V Operating Range)
Symbol
Voh1
Voh2
Vol1
Vol2
Vih
Vil
Ix
Parameter
Test Conditions
Min.
Max.
Output HIGH Voltage
Ioh = -4 mA
2.4
—
Output HIGH Voltage
Ioh = -100 µA
2.9
—
Output LOW Voltage
Iol = 8 mA
—
0.4
Output LOW Voltage
Iol = 100 µA
—
0.2
Input HIGH Voltage
2.0
Vdd+0.3
Input LOW Voltage
-0.3
0.8
Input Load Current
Vss ≤ Vin ≤ Vddq
-30
30
TAP Electrical Characteristics (Vddq = 2.5V Operating Range)
Symbol
Voh1
Parameter
Output HIGH Voltage
Test Conditions
Ioh = -1 mA
Voh2
Vol1
Vol2
Vih
Vil
Ix
Output HIGH Voltage
Ioh = -100 µA
2.1
—
Output LOW Voltage
Iol = 1 mA
—
0.4
Output LOW Voltage
Iol = 100 µA
—
0.2
Input HIGH Voltage
1.7
Vdd+0.3
Input LOW Voltage
-0.3
0.7
Input Load Current
Vss ≤ Vin ≤ Vddq
-30
30
TAP Electrical Characteristics (Vddq = 1.8V Operating Range)
Symbol
Voh1
Vol1
Vih
Vil
Ix
28
Min.
2.0
Max.
—
Parameter
Test Conditions
Min.
Max.
Output HIGH Voltage
Ioh = -1 mA
Vdd-0.4
—
Output LOW Voltage
Iol = 1 mA
—
0.5
Input HIGH Voltage
1.3
Vdd+0.3
Input LOW Voltage
-0.3
0.7
Input Load Current
Vss ≤ Vin ≤ Vddq
-30
30
Units
V
V
V
V
V
V
µA
Units
V
V
V
V
V
V
µA
Units
V
V
V
V
µA
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
TAP AC ELECTRICAL CHARACTERISTICS (OVER OPERATING RANGE)
Parameter
Symbol
Min
Max
Units
TCK cycle time
tTHTH
100
–
ns
TCK high pulse width
tTHTL
40
–
ns
TCK low pulse width
tTLTH
40
–
ns
TMS Setup
tMVTH
10
–
ns
TMS Hold
tTHMX
10
–
ns
TDI Setup
tDVTH
10
–
ns
TDI Hold
tTHDX
10
–
ns
TCK Low to Valid Data
tTLOV
–
20
ns
TAP AC TEST CONDITIONS
(1.8V/2.5V/3.3V)Input pulse levels
0 to 1.8V/0 to 2.5V/0 to 3.0V
1.5ns
Input rise and fall times
Input timing reference levels
Output reference levels
Test load termination supply voltage
Vtrig
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
0.9V/1.25V/1.5V
TAP Output Load Equivalent
50Ω
Vtrig
TDO
20 pF
Z0 = 50Ω
GND
TAP TIMING
1
2
tTHTH
3
4
5
6
tTLTH
TCK
tTHTL
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLOV
TDO
tTLOX
DON'T CARE
UNDEFINED
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
29
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
BOUNDARY SCAN ORDER
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X36
Bump ID
N6
N7
N10
P11
P8
R8
R9
P9
P10
R10
R11
H11
N11
M11
L11
K11
J11
M10
L10
K10
J10
H9
H10
G11
F11
E11
D11
G10
F10
E10
D10
C11
A11
B11
A10
B10
A9
B9
C10
A8
B8
A7
B7
B6
165 BGA
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
ZZ
DQa0
DQa1
DQa2
DQa6
DQa7
DQa3
DQa4
DQa5
DQa8
NC
NC
DQb8
DQb7
DQb5
DQb4
DQb6
DQb3
DQb2
DQb1
DQb0
NC
NC
A11
A10
A9
A8
NC
ADV
/OE
/CKE
/WE
CLK
X18
Bump ID
Signal
N6
NC
N7
NC
N10
NC
P11
NC
P8
A18
R8
A17
R9
A16
P9
A15
P10
A14
R10
A13
R11
A12
H11
ZZ
N11
NC
M11
NC
L11
NC
K11
NC
J11
NC
M10
DQa8
L10
DQa7
K10
DQa6
J10
DQa5
H9
NC
H10
NC
G11
DQa4
F11
DQa3
E11
DQa2
D11
DQa1
G10
NC
F10
NC
E10
NC
D10
NC
C11
DQa0
A11
A21
B11
NC
A10
A11
B10
A10
A9
A9
B9
A8
C10
NC
A8
ADV
B8
/OE
A7
/CKE
B7
/WE
B6
CLK
119 BGA
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X36
Bump ID
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
T7
ZZ
P6
DQa0
N7
DQa1
M6
DQa2
L7
DQa6
K6
DQa7
P7
DQa3
N6
DQa4
L6
DQa5
K7
DQa8
NC
NC
H6
DQb8
G7
DQb7
F6
DQb5
E7
DQb4
H7
DQb6
G6
DQb3
E6
DQb2
D7
DQb1
D6
DQb0
T1
NC
NC
A11
A10
G4
A9
A4
A8
NC
B4
ADV
F4
/OE
M4
/CKE
H4
/WE
K4
CLK
X18
Bump ID
Signal
NC
NC
NC
NC
A18
A17
A16
A15
A14
A13
A12
T7
ZZ
P6
NC
N7
NC
M6
NC
L7
NC
K6
NC
P7
DQa8
N6
DQa7
L6
DQa6
K7
DQa5
NC
NC
H6
DQa4
G7
DQa3
F6
DQa2
E7
DQa1
H7
NC
G6
NC
E6
NC
D7
NC
D6
DQa0
T1
A21
NC
A11
A10
G4
A9
A4
A8
NC
B4
ADV
F4
/OE
M4
/CKE
H4
/WE
K4
CLK
Continued on next page
30
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
X36
Bump ID
A6
B5
A5
A4
B4
B3
A3
A2
B2
C2
B1
A1
C1
D1
E1
F1
G1
D2
E2
F2
G2
H1
H2
H3
J1
K1
L1
M1
J2
K2
L2
M2
N1
N2
P1
R1
R2
P3
R3
P2
R4
P4
N5
P6
R6
*
165 BGA
Signal
/CE2
/Bwa
/Bwb
/Bwc
/Bwd
CE2
/CE1
A7
A6
NC
NC
NC
DQc0
DQc1
DQc2
DQc6
DQc7
DQc3
DQc4
DQc5
DQc8
NC
NC
NC
DQd8
DQd7
DQd5
DQd4
DQd6
DQd3
DQd2
DQd1
DQd0
NC
NC
MODE
A4
A3
A2
A5
A19
A20
NC
A1
A0
Int
X18
Bump ID
Signal
A6
/CE2
B5
/Bwa
A5
NC
A4
/Bwb
B4
NC
B3
CE2
A3
/CE1
A2
A7
B2
A6
C2
NC
B1
NC
A1
NC
C1
NC
D1
NC
E1
NC
F1
NC
G1
NC
D2
DQb8
E2
DQb7
F2
DQb6
G2
DQb5
H1
NC
H2
NC
H3
NC
J1
DQb4
K1
DQb3
L1
DQb2
M1
DQb1
J2
NC
K2
NC
L2
NC
M2
NC
N1
DQb0
N2
NC
P1
NC
R1
MODE
R2
A4
P3
A3
R3
A2
P2
A5
R4
A19
P4
A20
N5
NC
P6
A1
R6
A0
*
Int
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
119 BGA
X36
X18
Bump ID
Signal
Bump ID
Signal
B6
/CE2
B6
/CE2
L5
/Bwa
L5
/Bwa
G5
/Bwb
G5
NC
G3
/Bwc
G3
/Bwb
L3
/Bwd
L3
NC
B2
CE2
B2
CE2
E4
/CE1
E4
/CE1
A7
A7
A6
A6
NC
NC
NC
NC
NC
NC
D2
DQc0
D2
NC
E1
DQc1
E1
NC
F2
DQc2
F2
NC
G1
DQc6
G1
NC
H2
DQc7
H2
NC
D1
DQc3
D1
DQb8
E2
DQc4
E2
DQb7
G2
DQc5
G2
DQb6
H1
DQc8
H1
DQb5
NC
NC
NC
NC
NC
NC
K2
DQd8
K2
DQb4
L1
DQd7
L1
DQb3
M2
DQd5
M2
DQb2
N1
DQd4
N1
DQb1
K1
DQd6
K1
NC
L2
DQd3
L2
NC
N2
DQd2
N2
NC
P1
DQd1
P1
NC
P2
DQd0
P2
DQb0
NC
NC
NC
NC
R3
MODE
R3
MODE
A4
A4
A3
A3
A2
A2
A5
A5
A19
A19
T2
A20
T2
A20
NC
NC
N4
A1
N4
A1
P4
A0
P4
A0
*
Int
*
Int
31
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Commercial Range: 0°C to 70°C(VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61NLF204836B-6.5TQ
IS61NLF409618B-6.5TQ
100 TQFP
IS61NLF204836B-6.5B3
IS61NLF409618B-6.5B3
165 PBGA,13x15mm
IS61NLF204836B-6.5M3
IS61NLF409618B-6.5M3
165 PBGA,15x17mm
IS61NLF204836B-6.5B2
IS61NLF409618B-6.5B2
119 PBGA
IS61NLF204836B-6.5TQL
IS61NLF409618B-6.5TQL
100 TQFP, Lead-free
IS61NLF204836B-6.5B3L
IS61NLF409618B-6.5B3L
165 PBGA,13x15mm, Lead-free
IS61NLF204836B-6.5M3L
IS61NLF409618B-6.5M3L
165 PBGA,15x17mm, Lead-free
IS61NLF204836B-6.5B2L
IS61NLF409618B-6.5B2L
119 PBGA, Lead-free
IS61NLF204836B-7.5TQ
IS61NLF409618B-7.5TQ
100 TQFP
IS61NLF204836B-7.5B3
IS61NLF409618B-7.5B3
165 PBGA,13x15mm
IS61NLF204836B-7.5M3
IS61NLF409618B-7.5M3
165 PBGA,15x17mm
IS61NLF204836B-7.5B2
IS61NLF409618B-7.5B2
119 PBGA
IS61NLF204836B-7.5TQL
IS61NLF409618B-7.5TQL
100 TQFP, Lead-free
IS61NLF204836B-7.5B3L
IS61NLF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61NLF204836B-7.5M3L
IS61NLF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61NLF204836B-7.5B2L
IS61NLF409618B-7.5B2L
119 PBGA, Lead-free
Commercial Range: 0°C to 70°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36
6.5MHz
7.5ns
32
x18
Package
IS61NVF204836B-6.5TQ
IS61NVF409618B-6.5TQ
100 TQFP
IS61NVF204836B-6.5B3
IS61NVF409618B-6.5B3
165 PBGA,13x15mm
IS61NVF204836B-6.5M3
IS61NVF409618B-6.5M3
165 PBGA,15x17mm
IS61NVF204836B-6.5B2
IS61NVF409618B-6.5B2
119 PBGA
IS61NVF204836B-6.5TQL
IS61NVF409618B-6.5TQL
100 TQFP, Lead-free
IS61NVF204836B-6.5B3L
IS61NVF409618B-6.5B3L
165 PBGA,13x15mm, Lead-free
IS61NVF204836B-6.5M3L
IS61NVF409618B-6.5M3L
165 PBGA,15x17mm, Lead-free
IS61NVF204836B-6.5B2L
IS61NVF409618B-6.5B2L
119 PBGA, Lead-free
IS61NVF204836B-7.5TQ
IS61NVF409618B-7.5TQ
100 TQFP
IS61NVF204836B-7.5B3
IS61NVF409618B-7.5B3
165 PBGA,13x15mm
IS61NVF204836B-7.5M3
IS61NVF409618B-7.5M3
165 PBGA,15x17mm
IS61NVF204836B-7.5B2
IS61NVF409618B-7.5B2
119 PBGA
IS61NVF204836B-7.5TQL
IS61NVF409618B-7.5TQL
100 TQFP, Lead-free
IS61NVF204836B-7.5B3L
IS61NVF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61NVF204836B-7.5M3L
IS61NVF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61NVF204836B-7.5B2L
IS61NVF409618B-7.5B2L
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Commercial Range: 0°C to 70°C(VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
7.5ns
x18
Package
IS61NVVF204836B-7.5TQ
IS61NVVF409618B-7.5TQ
100 TQFP
IS61NVVF204836B-7.5B3
IS61NVVF409618B-7.5B3
165 PBGA,13x15mm
IS61NVVF204836B-7.5M3
IS61NVVF409618B-7.5M3
165 PBGA,15x17mm
IS61NVVF204836B-7.5B2
IS61NVVF409618B-7.5B2
119 PBGA
IS61NVVF204836B-7.5TQL
IS61NVVF409618B-7.5TQL
100 TQFP, 3CE, Lead-free
IS61NVVF204836B-7.5B3L
IS61NVVF409618B-7.5B3L
165 PBGA,13x15mm, Lead-free
IS61NVVF204836B-7.5M3L
IS61NVVF409618B-7.5M3L
165 PBGA,15x17mm, Lead-free
IS61NVVF204836B-7.5B2L
IS61NVVF409618B-7.5B2L
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61NLF204836B-6.5TQI
IS61NLF409618B-6.5TQI
100 TQFP
IS61NLF204836B-6.5B3I
IS61NLF409618B-6.5B3I
165 PBGA,13x15mm
IS61NLF204836B-6.5M3I
IS61NLF409618B-6.5M3I
165 PBGA,15x17mm
IS61NLF204836B-6.5B2I
IS61NLF409618B-6.5B2I
119 PBGA
IS61NLF204836B-6.5TQLI
IS61NLF409618B-6.5TQLI
100 TQFP, Lead-free
IS61NLF204836B-6.5B3LI
IS61NLF409618B-6.5B3LI
165 PBGA,13x15mm, Lead-free
IS61NLF204836B-6.5M3LI
IS61NLF409618B-6.5M3LI
165 PBGA,15x17mm, Lead-free
IS61NLF204836B-6.5B2LI
IS61NLF409618B-6.5B2LI
119 PBGA, Lead-free
IS61NLF204836B-7.5TQI
IS61NLF409618B-7.5TQI
100 TQFP
IS61NLF204836B-7.5B3I
IS61NLF409618B-7.5B3I
165 PBGA,13x15mm
IS61NLF204836B-7.5M3I
IS61NLF409618B-7.5M3I
165 PBGA,15x17mm
IS61NLF204836B-7.5B2I
IS61NLF409618B-7.5B2I
119 PBGA
IS61NLF204836B-7.5TQLI
IS61NLF409618B-7.5TQLI
100 TQFP, Lead-free
IS61NLF204836B-7.5B3LI
IS61NLF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61NLF204836B-7.5M3LI
IS61NLF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61NLF204836B-7.5B2LI
IS61NLF409618B-7.5B2LI
119 PBGA, Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
33
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Industrial Range: -40°C to +85°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time
6.5ns
7.5ns
x36
x18
Package
IS61NVF204836B-6.5TQI
IS61NVF409618B-6.5TQI
100 TQFP
IS61NVF204836B-6.5B3I
IS61NVF409618B-6.5B3I
165 PBGA,13x15mm
IS61NVF204836B-6.5M3I
IS61NVF409618B-6.5M3I
165 PBGA,15x17mm
IS61NVF204836B-6.5B2I
IS61NVF409618B-6.5B2I
119 PBGA
IS61NVF204836B-6.5TQLI
IS61NVF409618B-6.5TQLI
100 TQFP, Lead-free
IS61NVF204836B-6.5B3LI
IS61NVF409618B-6.5B3LI
165 PBGA,13x15mm, Lead-free
IS61NVF204836B-6.5M3LI
IS61NVF409618B-6.5M3LI
165 PBGA,15x17mm, Lead-free
IS61NVF204836B-6.5B2LI
IS61NVF409618B-6.5B2LI
119 PBGA, Lead-free
IS61NVF204836B-7.5TQI
IS61NVF409618B-7.5TQI
100 TQFP
IS61NVF204836B-7.5B3I
IS61NVF409618B-7.5B3I
165 PBGA,13x15mm
IS61NVF204836B-7.5M3I
IS61NVF409618B-7.5M3I
165 PBGA,15x17mm
IS61NVF204836B-7.5B2I
IS61NVF409618B-7.5B2I
119 PBGA
IS61NVF204836B-7.5TQLI
IS61NVF409618B-7.5TQLI
100 TQFP, Lead-free
IS61NVF204836B-7.5B3LI
IS61NVF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61NVF204836B-7.5M3LI
IS61NVF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61NVF204836B-7.5B2LI
IS61NVF409618B-7.5B2LI
119 PBGA, Lead-free
Industrial Range: -40°C to +85°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
7.5ns
x18
Package
IS61NVVF204836B-7.5TQI
IS61NVVF409618B-7.5TQI
100 TQFP
IS61NVVF204836B-7.5B3I
IS61NVVF409618B-7.5B3I
165 PBGA,13x15mm
IS61NVVF204836B-7.5M3I
IS61NVVF409618B-7.5M3I
165 PBGA,15x17mm
IS61NVVF204836B-7.5B2I
IS61NVVF409618B-7.5B2I
119 PBGA
IS61NVVF204836B-7.5TQLI
IS61NVVF409618B-7.5TQLI
100 TQFP, Lead-free
IS61NVVF204836B-7.5B3LI
IS61NVVF409618B-7.5B3LI
165 PBGA,13x15mm, Lead-free
IS61NVVF204836B-7.5M3LI
IS61NVVF409618B-7.5M3LI
165 PBGA,15x17mm, Lead-free
IS61NVVF204836B-7.5B2LI
IS61NVVF409618B-7.5B2LI
119 PBGA, Lead-free
Automotive(A3) Range: -40°C to +125°C (VDD = 3.3V / VDDQ = 2.5V/3.3V)
Access Time x36
x18
Package
Please contact ISSI ([email protected])
Automotive(A3) Range: -40°C to +125°C (VDD = 2.5V / VDDQ = 2.5V)
Access Time x36
x18
Package
Please contact ISSI ([email protected])
Automotive(A3) Range: -40°C to +125°C (VDD = 1.8V / VDDQ = 1.8V)
Access Time x36
x18
Package
Please contact ISSI ([email protected])
34
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
35
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
36
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
Package Outline
1. CONTROLLING DIMENSION : MM .
NOTE :
08/28/2008
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
37
38
Package Outline
1. Controlling dimension : mm
NOTE :
12/10/2007
IS61NLF204836B/IS61NVF/NVVF204836B
IS61NLF409618B/IS61NVF/NVVF409618B
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00C
02/20/2013
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