ON N34C04MU3ETG 4-kb serial spd eeprom for ddr4 dimm Datasheet

N34C04
4-Kb Serial SPD EEPROM
for DDR4 DIMM
Description
The N34C04 is a 4−Kb serial EEPROM, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
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UDFN8
MU3 SUFFIX
CASE 517AZ
PIN CONFIGURATION
Features
•
•
•
•
•
•
•
•
•
•
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
Temperature Range: −40°C to +125°C
Supply Range: 1.7 V − 3.6 V
I2C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Low Power CMOS Technology
2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
A0
N34C04
A2, A1, A0
A2
WP
WP
(Top View)
SCL
SDA
VSS
UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
D2U
AZZ
YM
G
D2U
A
ZZ
Y
M
G
SDA
VCC
A1
VCC
SCL
1
UDFN8
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
PIN FUNCTIONS
VSS
Pin Name
Figure 1. Functional Symbol
A0, A1, A2
Function
Device Address Input
SDA
Serial Data Input/Output
SCL
Serial Clock Input
WP
Write Protect Input
VCC
Power Supply
VSS
Ground
DAP
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
1
Publication Order Number:
N34C04/D
N34C04
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on any pin (except A0) with respect to Ground (Note 1)
−0.5 to +6.5
V
Voltage on pin A0 with respect to Ground
−0.5 to +10.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for SWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND (Note 2)
Endurance
TDR
Data Retention
Min
Units
1,000,000
Write Cycles
100
Years
2. Page Mode, VCC = 2.5 V, 25°C
Table 3. THERMAL CHARACTERISTICS (Note 3)
Test Conditions/Comments
Parameter
Thermal Resistance qJA
Junction−to−Ambient (Still Air)
Max
Unit
92
°C/W
3. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (Vcc = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICCR
Read Current
Read, fSCL = 400 kHz or 1 MHz
1
mA
ICCW
Write Current
Write, during tWR (Note 4)
1
mA
Standby Current
All I/O Pins at
GND or Vcc
Vcc < 2.2 V
1
mA
Vcc ≥ 2.2 V
2
ISB
IL
I/O Pin Leakage
Pin at GND or VCC
2
mA
VIL
Input Low Voltage
−0.5
0.3*Vcc
V
VIH
Input High Voltage
0.7*Vcc
VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.2 V, IOL = 20 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.2 V, IOL = 6.0 mA
0.2
V
VPOR+
Power On Reset Threshold
(Note 4)
1.3
V
VPOR−
Power Off Reset Threshold
(Note 4)
0.8
V
4. Tested initially and after a design or process change that affects this parameter
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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N34C04
Table 5. A.C. CHARACTERISTICS (Note 6) VCC = 1.7 V to 3.6 V, TA = −40°C to +125°C, unless otherwise specified.
Standard
VCC = 1.7 V − 3.6 V
tHD:STA
Min
Max
10
400
Fast−Plus
VCC = 2.2 V − 3.6 V
Min
Max
Clock Frequency
10
100
START Condition Hold Time
4
0.6
0.26
ms
Parameter
Symbol
FSCL (Note 5)
Fast
VCC = 1.7 V − 3.6 V
Min
Max
Units
10
1,000
kHz
tLOW
Low Period of SCL Clock
4.7
1.3
0.50
ms
tHIGH
High Period of SCL Clock
4
0.6
0.26
ms
4.7
0.6
0.26
ms
0
0
ms
tSU:STA
START Condition Setup Time
tHD:DI
Data In Hold Time
0
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 7)
SDA and SCL Rise Time
1,000
300
120
ns
tF (Note 7)
SDA and SCL Fall Time
300
300
120
ns
tSU:STO
4
0.6
0.26
ms
Bus Free Time Between
STOP and START
4.7
1.3
0.5
ms
Data Out Hold Time
200
STOP Condition Setup Time
tBUF
tHD:DAT
Ti (Note 7)
3450
Noise Pulse Filtered at SCL
and SDA Inputs
200
50
900
0
350
ns
50
ns
50
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
Write Cycle Time
tINIT (Notes 7, 8)
Power-up to Ready Mode
tPOFF (Note 9)
Warm power cycle off time
0.2
Detect clock low timeout
25
tTIMEOUT (Note 10)
4
4
4
ms
0.5
0.5
0.5
ms
0.2
35
25
0.2
35
ms
25
35
ms
5. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency is limited only by the SMBus
time−out. The device also meets the Fast and Standard I2C specifications, except that Ti and tDH are shorter, as required by the 1 MHz Fast
Plus protocol.
6. Test conditions according to “A.C. Test Conditions” table.
7. Tested initially and after a design or process change that affects this parameter.
8. tINIT is the delay between the Power−On Reset threshold (VPOR+) and the device is ready to accept commands.
9. Power−Off delay to ensure a proper Reset when the VCC drops below VPOR−
10. A timeout condition can only be ensured if SCL is driven low for tTIMEOUT(Max) or longer; then, N34C04 is reset and ready to receive a new
START condition. N34C04 does not reset if SCL is driven low for less than tTIMEOUT(Min). The interface will reset itself and will release the
SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out count takes place when SCL is low in the time interval between
START and STOP.
Table 6. A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.3 x VCC, 0.7 x VCC
Output Load
Current Source: IOL = 6 mA; CL = 100 pF
Table 7. PIN CAPACITANCE (TA = 25°C, VCC = 3.6 V, f = 1 MHz)
Symbol
CIN
Parameter
Test Conditions/Comments
Min
Max
Unit
SDA, Pin Capacitance
VIN = 0
8
pF
Input Capacitance (other pins)
VIN = 0
6
pF
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N34C04
Table 8. INPUT IMPEDANCE
Symbol
Parameter
Test Conditions
Min
Max
Unit
ZIL
Input Impedance for A0, A1, A2, WP Pins
VIN < 0.3 * Vcc
30
kW
ZIH
Input Impedance for A0, A1, A2, WP Pins
VIN > 0.7 * Vcc
800
kW
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and transmits
data stored in the memory. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor. The Write Protect pin should be tied
directly either to Vcc or GND.
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
Power−On Reset (POR)
The N34C04 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
undetermined logic state. As VCC exceeds the POR trigger
level, the device will power up into standby mode. The
device will power down into Reset mode when VCC drops
below the POR trigger level. This bi−directional POR
behavior protects the N34C04 against brown−out failure
following a temporary loss of power. The POR trigger level
is set below the minimum operating VCC level.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) determine whether the command is a read/write
command (1010b) or a utility command (0110b), as
described in Table 9. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is being performed.
Device Interface
The N34C04 supports the Inter−Integrated Circuit (I2C)
and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data flow is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The N34C04 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8 N34C04
devices may be present on the bus simultaneously, and can be
individually addressed by matching the logic state of the
address inputs A0, A1, and A2.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9th clock
cycle (Figure 3). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9th clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 4.
I2C/SMBus Protocol
The I2C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the VCC
SDA
SCL
START BIT
STOP BIT
Figure 2. Start/Stop Timing
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N34C04
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 3. Acknowledge Timing
tF
tR
70%
30%
70%
SCL
tHIGH
tLOW
70%
30%
70%
tHD:DAT
tSU:STA
tHD:STA
SDA IN
tSU:STO
tSU:DAT
70%
30%
70%
30%
30%
70%
70%
tBUF
tHD:DAT
70%
SDA OUT
30%
Figure 4. Bus Timing
Table 9. COMMAND SET (Notes 11, 12)
Function Specific Preamble
Select Address
R/W_n
Abbr
b7
b6
b5
b4
b3
b2
b1
b0
Read EE Memory
RSPD
1
0
1
0
LSA2
LSA1
LSA0
1
Write EE Memory
WSPD
Set Write Protection, block 0
SWP0
Set Write Protection, block 1
Set Write Protection, block 2
Function
A0 Pin
0 or 1
0
0
1
1
0
0
0
1
0
VHV
SWP1
1
0
0
0
VHV
SWP2
1
0
1
0
VHV
Set Write Protection, block 3
SWP3
0
0
0
0
VHV
Clear All Write Protection
CWP
0
1
1
0
VHV
Read Protection Status, block 0
RPS0
0
0
1
1
0, 1 or VHV
Read Protection Status, block 1
RPS1
1
0
0
1
0, 1 or VHV
Read Protection Status, block 2
RPS2
1
0
1
1
0, 1 or VHV
Read Protection Status, block 3
RPS3
0
0
0
1
0, 1 or VHV
Set SPD Page Address to 0
(Select Lower Bank)
SPA0
1
1
0
0
0, 1 or VHV
Set SPD Page Address to 1
(Select Upper Bank)
SPA1
1
1
1
0
0, 1 or VHV
Read SPD Page Address
RPA
1
1
0
1
0, 1 or VHV
Reserved
−
All Other Encodings
11. LSAx stands for Logic State of Address pin x.
12. If VHV is not applied on the A0 pin during SWP/CWP commands, the N34C04 will respond with NoACK after the 3rd byte and will not execute
the SWP/CWP instruction. During RPS/SPA/RPA commands the state of pin A0 must be stable for the duration of the sequence.
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N34C04
EEPROM Bank Selection
Upon power−up, the address pointer is initialized to 00h
pointing to the first location in the lower 2−Kb bank (SPD
page 0).
Only one SPD page is visible (active) at any given time.
The lower SPD page is automatically selected at power−up.
The upper SPD page can be activated (and the lower one
implicitly de−activated) by executing the SPA1 utility
command. The SPA0 utility command can then be used to
re−activate the lower SPD page without powering down.
The identity of the active SPD page can be retrieved with the
RPA command.
SPD page selection related command details are
presented in Table 11c, Table 11d, Figure 12 and Figure 13.
OPERATIONS). The N34C04 will not acknowledge the
Slave address as long as internal EEPROM Write is in
progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the N34C04. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the first data
byte (Figure 8). If the WP pin is HIGH during the strobe
interval, the N34C04 will not acknowledge the data byte and
the Write request will be rejected.
Delivery State
The N34C04 is shipped ‘unprotected’, i.e. none of the
Software Write Protection (SWP) flags is set. The entire
memory is erased, i.e. all bytes are 0xFF.
Write Operations
EEPROM Byte Write
To write data to the EEPROM, the Master creates a
START condition on the bus, and then sends out the
appropriate Slave address (with the R/W bit set to ‘0’),
followed by a starting data byte address, followed by data.
The matching Slave will acknowledge the Slave address,
EEPROM byte address and the data byte (Figure 5). The
Master then ends the session by creating a STOP condition
on the bus. The STOP starts the internal Write cycle for the
(non−volatile) EEPROM data (Figure 6).
Read Operations
Immediate Read
A N34C04 presented with a Slave address containing a ‘1’
in the R/W position will acknowledge the Slave address and
will then start transmitting EEPROM data from the current
address pointer location. The Master stops this transmission
by responding with NoACK, followed by a STOP
(Figure 9).
EEPROM Page Write
Selective Read
Each of the two 2−Kb banks is organized as 16 pages of
16 bytes each (not to be confused with the SPD page, which
refers to the entire 2−Kb bank). One of the 16 memory pages
is selected by the 4 most significant bits of the byte address,
while the 4 least significant bits point to the byte position
within the page. Up to 16 bytes can be written in one Write
cycle (Figure 7).
During data load, the internal byte position pointer is
automatically incremented after each data byte is loaded. If
the Master transmits more than 16 data bytes, then earlier
data will be replaced by later data in a ‘wrap−around’
fashion within the 16−byte wide data buffer. The internal
Write cycle then starts following the STOP.
The Read operation can be started from a specific address,
by preceding the Immediate Read sequence with a ‘data less’
Write sequence. The Master sends out a START, Slave
address and byte address, but rather than following up with
data (as in a Write operation), the Master then issues another
START and continuous with an Immediate Read sequence
(Figure 10).
Sequential EEPROM Read
EEPROM data can be read out indefinitely, as long as the
Master responds with ACK (Figure 11). The internal address
pointer is automatically incremented after every data byte
sent to the bus. If the end of the active 2−Kb bank is reached
during continuous Read, then the address count
‘wraps−around’ to the beginning of the active 2−Kb bank,
etc. Sequential Read works with either Immediate Read or
Selective Read, the only difference being that in the latter
case the starting address is intentionally updated.
Acknowledge Polling
Acknowledge polling can be used to determine if the
N34C04 is busy writing to EEPROM, or is ready to accept
commands. Polling is executed by interrogating the device
with a ‘Selective Read’ command (see READ
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
A
C
K
Figure 5. EEPROM Byte Write
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6
A
C
K
N34C04
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 6. EEPROM Write Cycle Timing
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
S
T
O
P
DATA n+P
DATA n+1
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
NOTE: In this example n = XXXX 0000(B); X = 1 or 0
Figure 7. EEPROM Page Write
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
Figure 8. WP Timing
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
S
T
A
R
T
N
OS
AT
CO
KP
SLAVE
ADDRESS
P
S
A
C
K
DATA
Figure 9. EEPROM Immediate Read
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A
C
K
N34C04
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
N
OS
AT
CO
KP
SLAVE
ADDRESS
P
S
S
A
C
K
SLAVE
A
C
K
A
C
K
DATA n
Figure 10. EEPROM Selective Read
N
OS
A T
CO
KP
BUS ACTIVITY:
MASTER
A
C
K
A
C
K
A
C
K
SLAVE
ADDRESS
SDA LINE
SLAVE
P
A
C
K
DATA n
DATA n+2
DATA n+1
DATA n+x
Figure 11. EEPROM Sequential Read
Software Write Protection
Each 1−Kb memory block can be individually protected
against Write requests. Block identities are:
pin A0 before the START and maintained just beyond the
STOP. The D.C. OPERATING CONDITIONS for SWP
operations are shown in Table 10.
SWP command details are listed in Tables 11a and 11b.
SWP Slave addresses follow the standard I2C convention,
i.e. to read the state of a SWP flag, the LSB of the Slave
address must be ‘1’, and to set or clear a flag, it must be ‘0’.
For Set/Clear commands a dummy byte address and dummy
data byte must be provided (Figure 12). In contrast to a
regular memory Read, a SWP Read does not return data.
Instead the N34C04 will respond with NoACK if the flag is
set and with ACK if the flag is not set (Figure 13).
Block 0: byte address 0x00...0x7F (SPD page address = 0)
Block 1: byte address 0x80...0xFF (SPD page address = 0)
Block 2: byte address 0x00...0x7F (SPD page address = 1)
Block 3: byte address 0x80...0xFF (SPD page address = 1)
Block Software Write Protection (SWP) flags can be set
or cleared in the presence of a very high voltage VHV on
address pin A0. The VHV condition must be established on
Table 10. SWPn AND CWP D.C. OPERATION CONDITION
Symbol
Parameter
DVHV
A0 Overdrive (VHV − VCC)
IHVD
A0 High Voltage Detector Current
VHV
A0 Very High Voltage
Test Conditions
Min
Max
4.8
1.7 V < VCC < 3.6 V
7
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8
Units
V
0.1
mA
10
V
N34C04
Table 11a. SWP SET COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Address
Byte
Slave
Response
Data Byte
Slave
Response
Write
Cycle
SWPx(Note 13)
Not Set
ACK
(Dummy)
ACK
(Dummy)
ACK
Yes
Set
NoACK
(Dummy)
NoACK
(Dummy)
NoACK
No
X
ACK
(Dummy)
ACK
(Dummy)
ACK
Yes
CWP
Table 11b. SWP QUERRY COMMAND DETAIL (following Slave Address)
Command
Block(x)
Protection
Slave
Response
Data Byte
Master
(Response)
Data Byte
Master
(Response)
RPSx (Nots 13, 14)
Not Set
ACK
Dummy
(NoACK)
Dummy
(NoACK)
Set
NoACK
Dummy
(NoACK)
Dummy
(NoACK)
Table 11c. SPD PAGE SELECT COMMAND DETAIL (following Slave Address)
Command
SPD Active
Page
Slave
Response
Address
Byte
Slave
Response
Data Byte
Slave
Response
Write
Cycle
SPAx (Notes 15, 16)
X
ACK
(Dummy)
ACK
(Dummy)
NoACK
No
Table 11d. SPD ACTIVE PAGE QUERRY COMMAND DETAIL (following Slave Address)
Command
RPA
(Notes 13, 14, 17)
SPD Active
Page
Slave
Response
Data Byte
Master
(Response)
Data Byte
Master
(Response)
0
ACK
Dummy
(NoACK)
Dummy
(NoACK)
1
NoACK
Dummy
(NoACK)
Dummy
(NoACK)
13. The Master can terminate the sequence by issuing a STOP once the N34C04 responds with NoACK
14. The Master can terminate the sequence by responding with (NoACK) followed by STOP after any dummy data byte.
15. Setting the SPD Page Address to ‘0’ selects the lower 2−Kb EEPROM bank, setting it to ‘1’ selects the upper 2−Kb EEPROM bank.
16. The lower 2−Kb EEPROM bank (corresponding to SPD page address ‘0’) is active (visible) immediately following power−up.
17. The device will respond with ACK when the lower 2−Kb EEPROM bank is active and with NoACK when the upper 2−Kb EEPROM bank is
active.
BUS ACTIVITY: S
T
A
MASTER R
T
Dummy
ADDRESS
SLAVE
ADDRESS
Dummy
DATA
S
T
O
P
SDA LINE
SLAVE
N
A
C or O
A
K
C
K
X = Don’t Care
N
A
C or O
A
K
C
K
N
A
C or O
A
K
C
K
Figure 12. SWP & SPA Timing
BUS ACTIVITY: S
T
A
MASTER R
T
N
O
A
C
K
SLAVE
ADDRESS
N
OS
AT
CO
KP
SDA LINE
SLAVE
X = Don’t Care
N
A
C or O
A
K
C
K
Dummy
DATA
Dummy
DATA
Figure 13. RPS & RPA Timing
www.onsemi.com
9
N34C04
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE A
B
A
D
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L1
PIN ONE
REFERENCE
0.10 C
ÇÇÇ
ÇÇÇ
ÇÇÇ
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
ÉÉ
ÇÇ
EXPOSED Cu
0.10 C TOP VIEW
DETAIL B
A
0.10 C
ÉÉ
ÇÇ
ÇÇ
A3
MOLD CMPD
A1
DETAIL B
A3
DIM
A
A1
A3
b
D
D2
E
E2
e
L
L1
ALTERNATE
CONSTRUCTIONS
0.08 C
NOTE 4
A1
SIDE VIEW
C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
2.00 BSC
1.35
1.45
3.00 BSC
1.25
1.35
0.50 BSC
0.25
0.35
−−−
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
1.56
DETAIL A
1
D2
L
4
8X
0.68
1.45 3.40
E2
8
5
8X
e
BOTTOM VIEW
b
0.10
0.05
1
M
M
8X
C A B
C
0.50
PITCH
NOTE 3
0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
N34C04
Ordering Information
Device Order Number
N34C04MU3ETG
Specific
Device Marking
Package
Type
Temperature
Range
Lead
Finish
D2U
UDFN−8
−40°C to +125°C
NiPdAu
Shipping
Tape & Reel,
4,000 Units / Reel
18. All packages are RoHS−compliant (Lead−free, Halogen−free)
19. The standard lead finish is NiPdAu.
20. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
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11
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N34C04/D