TI1 BQ25121AYFPR Low iq highly integrated battery charge management solution for wearables and iot Datasheet

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BQ25121A
SLUSDA7 – APRIL 2018
BQ25121A Low IQ Highly Integrated Battery Charge Management Solution
for Wearables and IoT
1 Features
2 Applications
•
•
•
•
•
1
•
•
Smart Watches and other Wearable Devices
Fitness Accessories
Health Monitoring Medical Accessories
Rechargeable Toys
3 Description
The BQ25121A is a highly integrated battery charge
management IC that integrates the most common
functions for wearable devices: Linear charger,
regulated output, load switch, manual reset with
timer, and battery voltage monitor. The integrated
buck converter is a high efficiency, low IQ switcher
using DCS-Control™ that extends light load efficiency
down to 10-µA load currents. The low quiescent
current during operation and shutdown enables
maximum battery life. The device supports charge
currents from 5 mA to 300 mA. The input current
limit, charge current, buck converter output voltage,
LDO output voltage, and other parameters are
programmable through the I2C interface.
Device Information(1)
PART NUMBER
BQ25121A
PACKAGE
DSBGA (25)
BODY SIZE (NOM)
2.50 mm x 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
PG
PMID
Unregulated
Load
IN
BQ25121A
GND
VINLS
SYS
SW
CD
HOST
MCU /
SYSTEM
SDA
SCL
INT
LS / LDO
<100mA
Load
RESET
LSCTRL
BAT
MR
IPRETERM
ISET
TS
NTC
-
ILIM
+
Increases System Operation Time Between
Charges
– Configurable 300-mA Buck Regulator
(2.5-V Default)
– 700 nA (typical) Iq with Buck Converter
Enabled (No Load)
– Configurable Load Switch or 100mA LDO
Output (Load Switch by Default)
– Up to 300-mA Charge Current for Fast
Charging
– 0.5% Accurate Battery Voltage Regulation
(Configurable from 3.6 V to 4.65 V in 10-mV
Steps)
– Configurable Termination Current Down to
500 µA
– Simple Voltage Based Battery Monitor
– Watchdog Timer Disabled
Highly Integrated Solution with Small Footprint
– 2.5 mm x 2.5 mm WCSP Package and 6
External Components for Minimal Solution
– Push-Button Wake-Up and Reset with
Adjustable Timers
– Power Path Management for Powering the
System and Charging the Battery
– Power Path Management enables <50 nA Ship
Mode Battery Quiescent Current for Longest
Shelf Life
– Battery Charger Operates from 3.4 V – 5.5 VIN
(5.5-V OVP / 20-V Tolerant)
– Dedicated Pins for Input Current Limit, Charge
Current, Termination Current, and Status
Output
2
I C Communication Control
– Charge Voltage and Current
– Termination Threshold
– Input Current Limit
– VINDPM Threshold
– Timer Options
– Load Switch Control
– Controls for Interrupts for Faults and Status
– System Output Voltage Adjustment
– LDO Output Voltage Adjustment
IN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BQ25121A
SLUSDA7 – APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.4 Device Functional Modes........................................ 31
8.5 Programming .......................................................... 33
8.6 Register Maps ........................................................ 36
1
1
1
2
3
4
6
9
Application and Implementation ........................ 47
9.1 Application Information............................................ 47
9.2 Typical Application ................................................. 47
10 Power Supply Recommendations ..................... 62
11 Layout................................................................... 63
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Electrical Characteristics........................................... 8
Timing Requirements ............................................. 12
Typical Characteristics ............................................ 15
11.1 Layout Guidelines ................................................. 63
11.2 Layout Example .................................................... 63
12 Device and Documentation Support ................. 64
12.1
12.2
12.3
12.4
12.5
12.6
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
64
64
64
64
64
13 Mechanical, Packaging, and Orderable
Information ........................................................... 64
4 Revision History
2
DATE
REVISION
NOTES
April 2018
*
Initial release.
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5 Description (continued)
The battery is charged using a standard Li-Ion charge profile with three phases: precharge, constant current and
constant voltage. A voltage-based JEITA compatible battery pack thermistor monitoring input (TS) is included
that monitors battery temperature and automatically changes charge parameters to prevent the battery from
charging outside of its safe temperature range. The charger is optimized for 5-V USB input, with 20-V tolerance
to withstand line transients. The buck converter is run from the input or battery. When in battery only mode, the
device can run from a battery up to 4.65 V.
A configurable load switch allows system optimization by disconnecting infrequently used devices. The manual
reset with timer allows multiple different configuration options for wake are reset optimization. A simple voltage
based monitor provides battery level information to the host in 2% increments from 60% to 100% of the
programmed V(BATREG).
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6 Pin Configuration and Functions
YFP Package
25-Pin DSBGA
Top View
1
2
3
4
5
A
GND
IN
PMID
SW
PGND
B
BAT
BAT
PMID
VINLS
SYS
C
ISET
ILIM
TS
VINLS
LS/LDO
D
IPRETE
RM
INT
RESET
PG
GND
E
MR
CD
LSCTRL
SDA
SCL
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
IN
A2
I
DC Input Power Supply. IN is connected to the external DC supply. Bypass IN to GND with
at least 1 µF of capacitance using a ceramic capacitor.
PMID
A3, B3
I/O
High Side Bypass Connection. Connect at least 3µF of ceramic capacitance with DC bias
derating from PMID to GND as close to the PMID and GND pins as possible. When entering
Ship Mode, PMID is discharged by a 20-kΩ internal discharge resistor.
GND
A1, D5
Ground connection. Connect to the ground plane of the circuit.
Power ground connection. Connect to the ground plane of the circuit. Connect the output
filter cap from the buck converter to this ground as shown in the layout example.
PGND
A5
CD
E2
I
SDA
E4
I/O
I2C Interface Data. Connect SDA to the logic rail through a 10-kΩ resistor.
SCL
E5
I
I2C Interface Clock. Connect SCL to the logic rail through a 10-kΩ resistor.
Chip Disable. Drive CD low to place the part in High-Z mode with battery only present, or
enable charging when VIN is valid. Drive CD high for Active Battery mode when battery only
is present, and disable charge when VIN is present. CD is pulled low internally with 900 kΩ.
ILIM
C2
I
Adjustable Input Current Limit Programming. Connect a resistor from ILIM to GND to
program the input current limit. The input current includes the system load and the battery
charge current. Connect ILIM to GND to set the input current limit to the internal default
threshold. ILIM can also be updated through I2C.
LSCTRL
E3
I
Load Switch and LDO Control Input. Pull high to enable the LS/LDO output, pull low to
disable the LS/LDO output.
I
Fast-Charge Current Programming Input. Connect a resistor from ISET to GND to program
the fast-charge current level. Connect a resistor from ISET to GND to set the charge current
to the internal default. ISET can also be updated through I2C. While charging, the voltage at
ISET reflects the actual charging current and can be used to monitor charge current if an
ISET resistor is present and the device is not in host mode.
ISET
4
C1
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Pin Functions (continued)
PIN
NAME
IPRETERM
INT
NO.
D1
D2
I/O
DESCRIPTION
I
Termination current programming input. Connect a 0-Ω to 10-kΩ resistor from IPRETERM to
GND to program the termination current between 5% and 20% of the charge current. The
pre-charge current is the same as the termination current setting. Connect IPRETERM to
GND to set the termination current to the internal default threshold. IPRETERM can also be
updated through I2C.
O
Status Output. INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete, disabled,
or the charger is in high impedance mode. When a fault occurs, a 128µs pulse is sent out as
an interrupt for the host. INT charge indicator function is enabled/disabled using the EN_INT
bit in the control register. Connect INT to a logic rail using an LED for visual indication of
charge status or through a 100kΩ resistor to communicate with the host processor.
PG
D4
O
Open-drain Power Good status indication output. PG pulls to GND when VIN is above V(BAT)
+ VSLP and less that VOVP. PG is high-impedance when the input power is not within
specified limits. Connect PG to the desired logic voltage rail using a 1kΩ to 100kΩ resistor,
or use with an LED for visual indication. PG can also be configured as a push-button voltage
shifted output (MRS) in the registers, where the output of the PG pin reflects the status of the
MR input, but pulled up to the desired logic voltage rail using a 1kΩ to 100kΩ resistor.
RESET
D3
O
Reset Output. RESET is an open drain active low output that goes low when MR is held low
for longer than tRESET, which is configurable by the MRRESET registers. RESET is
deasserted after the tRESET_D, typically 400ms.
MR
E1
I
Manual Reset Input. MR is a push-button input that must be held low for greater than tRESET
to assert the reset output. If MR is pressed for a shorter period, there are two programmable
timer events, tWAKE1 and tWAKE2, that trigger an interrupt to the host. The MR input can also
be used to bring the device out of Ship mode.
SW
A4
O
Inductor Connection. Connect to the switched side of the external inductor.
SYS
B5
I
System Voltage Sense Connection. Connect SYS to the system output at the output bulk
capacitors. Bypass SYS locally with at least 4.7 µF of effective ceramic capacitance.
LS/LDO
C5
O
Load Switch or LDO output. Connect 1 µF of effective ceramic capacitance to this pin to
assure stability. Be sure to account for capacitance bias voltage derating when selecting the
capacitor.
VINLS
B4, C4
I
Input to the Load Switch / LDO output. Connect 1 µF of effective ceramic capacitance from
this pin to GND.
BAT
B1, B2
I/O
C3
I
TS
Battery Connection. Connect to the positive terminal of the battery. Bypass BAT to GND with
at least 1 µF of ceramic capacitance.
Battery Pack NTC Monitor. Connect TS to the center tap of a resistor divider from VIN to
GND. The NTC is connected from TS to GND. The TS function provides four thresholds for
JEITA compatibility. TS faults are reported by the I2C interface during charge mode.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Input voltage
(1)
MIN
MAX
UNIT
IN
wrt GND
–0.3
20
V
PMID, VINLS
wrt GND
–0.3
7.7
V
CD, SDA, SCL, ILIM, ISET, IPRETERM, LSCTRL,
INT, RESET, TS
wrt GND
–0.3
5.5
V
Output voltage
SYS
3.6
V
Input current
IN
400
mA
Sink current
INT
10
mA
Sink/Source Current
RESET
10
mA
Output Voltage Continuos
SW
7.7
V
SW
400
mA
SYS, BAT
300
mA
Current
LS/LDO
150
mA
BAT Operating Voltage
VBAT, MR,
6.6
V
125
°C
300
°C
Output Current Continuous
–0.7
Junction Temperature
–40
Storage Temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
NOM
MAX
IN voltage range
3.4
5
20
IN operating voltage range, recommended
3.4
5
5.5
UNIT
V
5.5 (1)
V
5.5 (2)
V
V(BAT)
V(BAT) operating voltage range
V(VINLS)
VINLS voltage range for Load Switch
0.8
V(VINLS)
VINLS voltage range for LDO
2.2
5.5
V
IIN
Input Current, IN input
400
mA
I(SW)
Output Current from SW, DC
300
mA
I(PMID)
Output Current from PMID, DC
300
mA
ILS/LDO
Output Current from LS/LDO
100
mA
I(BAT), I(SYS)
Charging and discharging using internal battery FET
300
mA
TJ
Operating junction temperature range
125
°C
(1)
(2)
6
–40
Any voltage greater than shown should be a transient event.
These inputs will support 6.6 V for less than 10% of the lifetime at V(BAT) or VIN, with a reduced current and/or performance.
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7.4 Thermal Information
BQ25121A
THERMAL METRIC (1)
YFP (DSBGA)
UNIT
25 PINS
RθJA
Junction-to-ambient thermal resistance
60
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
0.3
°C/W
Junction-to-board thermal resistance
12.0
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
12.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Circuit of Figure 1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM
Switching, –40°C < TJ < 85°C
Supply Current for
Control
IIN
1
V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP) PWM NOT
Switching
0°C < TJ < 85°C, VIN = 5 V, Charge Disabled
Battery discharge current
in High Impedance Mode
I(BAT_HIZ)
I(BAT_ACTIVE)
I(BAT_SHIP)
Battery discharge current
in Active Battery Mode
Battery discharge current
in Ship Mode
mA
3
mA
1.5
mA
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 4.65 V
0.7
1.2
µA
0°C < TJ < 60°C, VIN = 0 V, High-Z Mode, PWM Not
Switching, V(BUVLO) < V(BAT) < 6.6 V
0.9
1.5
µA
0°C < TJ < 60°C, VIN = 0 V or floating, High-Z Mode, PWM
Switching, No Load
0.75
3.5
µA
0°C < TJ < 85°C, VIN = 0 V, High-Z Mode, PWM Switching,
LSLDO enabled
1.35
4.25
µA
0°C < TJ < 85°C, VIN = 0 V, Active Battery Mode, PWM
Switching, LSLDO enabled, I2C Enabled, V(BUVLO) < V(BAT) <
4.65 V
6.8
12
µA
0°C < TJ < 85°C, 0 < VIN < VIN(UVLO), Active Battery Mode,
PWM Switching, LSLDO disabled, I2C Enabled, CD = Low,
V(BUVLO) < V(BAT) < 4.65 V
6.2
11
µA
2
150
nA
0°C < TJ < 85°C, VIN = 0 V, Ship Mode
POWER-PATH MANAGEMENT and INPUT CURRENT LIMIT
VDO(IN-PMID)
VIN – V(PMID)
VIN = 5 V, IIN = 300 mA
125
170
mV
VDO(BAT-PMID)
V(BAT) – V(PMID)
VIN = 0 V, V(BAT) > 3 V, Iff = 400 mA
120
160
mV
V(BSUP1)
Enter supplement mode
threshold
V(BAT) > V(BUVLO)
V(PMID) <
V(BAT) – 25
mV
V(BSUP2)
Exit supplement mode
threshold
V(BAT) > V(BUVLO)
V(PMID) <
V(BAT) –
5mV
I(BAT_OCP)
Current Limit, Discharge
Mode
V(BAT) > V(BUVLO)
Input Current Limit
Programmable Range, 50-mA steps
0.85
50
Maximum Input Current
using ILIM
I(ILIM)
1.15
V
V
1.35
A
400
mA
K(ILIM) /
R(ILIM)
IILIM accuracy IILIM
accuracy
50 mA to 100 mA
–12%
100 mA to 400 mA
–5%
K(ILIM)
Maximum input current
factor
I(ILIM) = 50 mA to 100 mA
175
200
225
AΩ
I(ILIM) = 100 mA to 400 mA
190
200
210
AΩ
Programmable Range using VIN(DPM) Registers. Can be
disabled using VIN(DPM_ON)
4.2
4.9
V
VIN(DPM)
Input voltage threshold
when input current is
reduced
–3%
3%
VIN_DPM threshold
accuracy
12%
5%
BATTERY CHARGER
VD(PPM)
PMID voltage threshold
when charge current is
reduced
Above V(BATREG)
0.2
RON(BAT-PMID)
Internal Battery Charger
MOSFET on-resistance
Measured from BAT to PMID, V(BAT) = 4.35 V, High-Z mode
300
Charge Voltage
Operating in voltage regulation, Programmable Range, 10mV steps
Voltage Regulation
Accuracy
TJ = 0°C to 85°C
V(BATREG)
8
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V
400
mΩ
3.6
4.65
V
–0.5%
0.5%
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Electrical Characteristics (continued)
Circuit of Figure 1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETERS
Fast Charge Current
Range
I(CHARGE)
TEST CONDITIONS
MIN
V(BATUVLO) < V(BAT) < V(BATREG)
5
Fast Charge Current
using ISET
–5%
Fast Charge Current
Factor
5 mA > I(CHARGE) > 300 mA
190
Termination charge
current
Termination current programmable range over I2C
0.5
I(CHARGE) < 300 mA, R(ITERM) = 15 kΩ
I(TERM)
Termination Current using I(CHARGE) < 300 mA, R(ITERM) = 4.99 kΩ
IPRETERM
I(CHARGE) < 300 mA, R(ITERM) = 1.65 kΩ
I(CHARGE) < 300 mA, R(ITERM) = 549 Ω
tDGL(TERM)
I(PRE_CHARGE)
UNIT
300
mA
A
5%
200
210
AΩ
37
mA
5
% of ISET
10
% of ISET
15
% of ISET
20
Accuracy
I(TERM) > 4 mA
TERM deglitch time
Both rising and falling, 2-mV over-drive, tRISE, tFALL = 100 ns
Pre-charge current
MAX
K(ISET) /
R(ISET)
Fast Charge Current
Accuracy
K(ISET)
TYP
–10%
2
Pre-charge current programmable range over I C
% of ISET
10%
64
0.5
Pre-charge Current using
IPRETERM
ms
37
I(TERM)
Accuracy
–10%
V(RCH)
Recharge threshold
voltage
Below V(BATREG)
tDGL(RCHG)
Recharge threshold
deglitch time
tFALL = 100 ns typ, V(RCH) falling
100
mA
A
10%
120
140
32
mV
ms
SYS OUTPUT
RDS(ON_HS)
PMID = 3.6 V, I(SYS) =
675
850
mΩ
RDS(ON_LS)
PMID = 3.6 V, I(SYS) =
300
475
mΩ
22
40
Ω
RDS(CH_SYS)
I(LIMF)
I(LIM_SS)
VSYS
MOSFET on-resistance
for SYS discharge
VIN = 3.6 V, IOUT = –10 mA into VOUT pin
SW Current limit HS
2.2 V < V(PMID) < 5.5 V
450
600
675
mA
SW Current limit LS
2.2 V < V(PMID) < 5.5 V
450
700
850
mA
PMOS switch current limit
Current limit is reduced during softstart
during softstart
80
130
200
mA
SYS Output Voltage
Range
Programmable range, 100 mV Steps
1.1
3.3
V
Output Voltage Accuracy
VIN = 5 V, PFM mode, IOUT = 10 mA, V(SYS) = 1.8 V
DC Output Voltage Load
Regulation in PWM mode
VOUT = 2 V, over load range
0.01
%/mA
DC Output Voltage Line
Regulation in PWM mode
VOUT = 2 V, IOUT = 100 mA, over VIN range
0.01
%/V
Input voltage range for
LS/LDO
Load Switch Mode
0.8
6.6
V
Input voltage range for
LS/LDO
LDO Mode
2.2
6.6
V
–2.5%
0
2.5%
LS/LDO OUTPUT
VIN(LS)
TJ = 25°C
–2%
±1%
2%
Over VIN, IOUT, temperature
–3%
±2%
3%
VOUT
DC output accuracy
VLDO
Output range for LS/LDO
Programmable Range, 0.1 V steps
DC Line regulation
VOUT(NOM) + 0.5 V < VIN < 6.6 V, IOUT = 5 mA
DC Load regulation
Load Transient
RDS(ON_LDO)
FET Rdson
V(VINLS) = 3.6 V
R(DSCH_LSLDO)
MOSFET on-resistance
for LS/LDO discharge
1.7 V < V(VINLS) < 6.6 V, ILOAD = –10 mA
ΔVOUT / Δ VIN
0.8
3.3
–1%
1%
0 mA < IOUT < 100 mA
–1%
1%
2 µA to 100 mA, VOUT = 1. 8 V
–120
460
60
mV
600
mΩ
20
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Ω
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Electrical Characteristics (continued)
Circuit of Figure 1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETERS
I(OCL_LDO)
Output Current Limit –
LDO
I(LS/LDO)
Output Current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
275
365
475
mA
V(VINLS) = 3.6 V, VLSLDO = 3.3 V
100
mA
V(VINLS) = 3.3 V, VLSLDO = 0.8 V
100
mA
V(VINLS) = 2.2 V, VLSLDO = 0.8 V
10
mA
VLS/LDO = 0 V
Quiescent current for
VINLS in LDO mode
IIN(LDO)
OFF-state supply current
VIH(LSCTRL)
High-level input voltage
for LSCTRL
1.15 V > V(VINLS) > 6.6 V
VIL(LSCTRL)
Low-level input voltage
for LSCTRL
1.15 V > V(VINLS) > 6.6 V
0.9
µA
0.25
µA
0.75 x
V(SYS)
6.6
V
0.25 x
V(SYS)
V
PUSHBUTTON TIMER (MR)
VIL
Low-level input voltage
RPU
Internal pull-up resistance
VBAT > VBUVLO
0.3
120
V
kΩ
VBAT MONITOR
Battery Voltage Monitor
Accuracy
VBMON
V(BAT) Falling - Including 2% increment
–3.5
3.5 %V(BATREG)
BATTERY-PACK NTC MONITOR
VHOT
High temperature
threshold
VTS falling, 1% VIN Hysteresis
14.5
15
15.2
%VIN
VWARM
Warm temperature
threshold
VTS falling, 1% VIN Hysteresis
20.1
20.5
20.8
%VIN
VCOOL
Cool temperature
threshold
VTS rising, 1% VIN Hysteresis
35.4
36
36.4
%VIN
VCOLD
Low temperature
threshold
VTS rising, 1% VIN Hysteresis
39.3
39.8
40.2
%VIN
TSOFF
TS Disable threshold
VTS rising, 2% VIN Hysteresis
55
60
%VIN
V(UVLO)
IC active threshold
voltage
VIN rising
3.4
3.8
V
VUVLO(HYS)
IC active hysteresis
VIN falling from above VUVLO
Battery Undervoltage
Lockout threshold Range
Programmable Range for V(BUVLO) VBAT falling, 150 mV
Hysteresis
Default Battery
Undervoltage Lockout
Accuracy
V(BAT) falling
V(BATSHORT)
Battery short circuit
threshold
Battery voltage falling
V(BATSHORT_HYS)
Hysteresis for V(BATSHORT)
I(BATSHORT)
Battery short circuit
charge current
V(SLP)
Sleep entry threshold,
VIN – V(BAT)
2 V < VBAT < V(BATREG), VIN falling
V(SLP_HYS)
Sleep-mode exit
hysteresis
VIN rising above V(SLP)
VOVP
Maximum Input Supply
OVP threshold voltage
VIN rising, 100 mV hysteresis
tDGL_OVP
Deglitch time, VIN OVP
falling
VIN falling below VOVP, 1V/us
TSHTDWN
Thermal trip
THYS
Thermal hysteresis
tDGL_SHTDWN
Deglitch time, Thermal
shutdown
TJ rising above TSHTDWN
PROTECTION
V(BUVLO)
10
3.6
150
mV
2.2
3.0
–2.5%
2.5%
2
V
V
100
mV
I(PRETERM)
mA
65
120
mV
40
65
100
mV
5.35
5.55
5.75
V
32
ms
VIN > VUVLO
114
°C
VIN > VUVLO
11
°C
4
µs
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Electrical Characteristics (continued)
Circuit of Figure 1, V(UVLO) < VIN < V(OVP) and VIN > V(BAT) + V(SLP), TJ = –40°C to 85°C and TJ = 25°C for typical values (unless
otherwise noted)
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
400
kHz
I2C INTERFACE
I2C Bus Specification
standard and fast mode
frequency support
100
VIL
Input low threshold level
VPULLUP = 1.1 V, SDA and SCL
VIH
Input high threshold level
VPULLUP = 1.1 V, SDA and SCL
0.825
0.275
VIH
Input high threshold level
VPULLUP = 3.3 V, SDA and SCL
2.475
VOL
Output low threshold level IL = 5 mA, sink current, VPULLUP = 1.1 V
IBIAS
High-Level leakage
current
V
V
V
VPULLUP = 1.8 V, SDA and SCL
0.275
V
1
µA
0.25 x
V(SYS)
V
12
nA
1.15
V
0.25 *
VSYS
V
INT, PG, and RESET OUTPUT (Open Drain)
VOL
Low level output
threshold
Sinking current = 5 mA
IIN
Bias current into pin
Pin is high impedance, IOUT = 0 mA; TJ = –40°C to 60°C
VIN(BAT_DELTA)
Input voltage above
VBAT where PG sends
two 128 µs pulses each
minute to signal the host
of the input voltage status
VUVLO < VIN < VOVP
0.825
1
INPUT PIN (CD LSCTRL)
VIL(/CD_LSCTRL)
Input low threshold
V(PULLUP) = VSYS = 3.3 V
VIH(/CD_LSCTRL)
Input high threshold
V(PULLUP) = VSYS = 3.3 V
RPULLDOWN/CD
Internal pull-down
resistance
900
kΩ
R(LSCTRL)
Internal pull-down
resistance
2
MΩ
0.75 *
VSYS
V
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7.6 Timing Requirements
MIN
TYP
MAX
UNIT
POWER-PATH MANAGEMENT AND INPUT CURRENT LIMIT
tDGL_SC
Deglitch Time, PMID or SW Short Circuit
during Discharge Mode
250
µs
tREC_SC
Recovery time, OUT Short Circuit during
Discharge Mode
2
s
1
ms
BATTERY CHARGER
tDGL_SHORT
Deglitch time transition from ISET short to
I(CHARGE) disable
Clear fault by disconnecting VIN
BATTERY CHARGING TIMERS
tMAXCHG
Charge safety timer
tPRECHG
Precharge safety timer
Programmable range
2
540
min
0.1 x tMAXCHG
SYS OUTPUT
tONMIN
Minimum ON time
VIN = 3.6 V, VOUT = 2 V, IOUT = 0 mA
tOFFMIN
Minimum OFF time
VIN = 4.2 V
225
ns
50
tSTART_SW
SW start up time
VIN = 5 V, from write on EN_SW_OUT
until output starts to rise
ns
5
tSTART_SYS
SYS output time to start switching
From insertion of BAT > V(BUVLO) or VIN
> V(UVLO)
350
tSOFTSTART
Softstart time with reduced current limit
400
25
ms
µs
1200
µs
LS/LDO OUTPUT
tON_LDO
Turn ON time
100-mA load
500
µs
tOFF_LDO
Turn OFF time
100-mA load
5
µs
PUSHBUTTON TIMER
tWAKE1
Push button timer wake 1
tWAKE2
Push button timer wake 2
Programmable Range for wake2
function
tRESET
Push button timer reset
Programmable Range for reset
function
tRESET_D
Reset pulse duration
tDD
Detection delay (from MR, input to
RESET)
For 0s condition
0.08
1
s
1
2
s
5
15
s
400
ms
6
µs
50
ms
700
ms
BATTERY-PACK NTC MONITOR
tDGL(TS)
Deglitch time on TS change
Applies to V(HOT), V(WARM), V(COOL), and
V(COLD)
I2C INTERFACE
tI2CRESET
I2C interface inactive reset timer
tHIZ_ACTIVEBAT
Transition time required to enable the I2C
interface from HiZ to Active BAT
1
ms
1
ms
INPUT PIN
t/CD_DGL
Deglitch for CD
tQUIET
Input quiet time for Ship Mode transition
12
CD rising/falling
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100
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Typical Start-Up Timing and Operation
Remove
Battery
Apply
VIN
Insert
Battery
BAT supplies SYS
when VIN removed
VIN
PMID
VIN > UVLO
PG
SW
SYS
CD
IBAT
After delay of several ms,
switching starts and SYS
starts to rise
Charging
enabled
Charging
0mA
disabled
VBAT>VBUVLO
VBAT
rises
IBAT=ICHRG
Charge
Current
Taper
VBAT = VBATREG
IBAT = ITERM
No SYS Load
VBAT =
VBATREG - VRCHG
SYS Load Applied
VBAT
INT
Shows
Charge
Status
<3uA max
VISET
<4uA max
<3uA max
BAT IQ
<5uA max
<4uA max
nA of leakage with VIN present
Conditions: PGB_MRS = 0, TE = 1, SW_LDO = 1, VINDPM_ON = 0, PG and INT pulled up to SYS, EN_INT = 1
Figure 1. Typical Start-Up Timing and Operation
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Insert Battery <
VBATSHORT
VBAT=VBUVLO
VBAT=VBUVLO
VBAT
IBAT = I BATSHORT
IBAT
IBAT = ICHG
VIN
Device enters Active Battery
Mode after valid /MR
CD
EN_SHIPMODE
MR
MR_WAKE1 time reached
MR_WAKE2 time reached
MRRESET time reached
User depresses button
t RESET
RESET
MR_WAKE1
Interrupt
MR_WAKE2
Interrupt
INT
<1uA max
<3uA max
<1uA max
<3uA max
BAT IQ
After delay of several ms ,
SYS starts to rise
SYS is pulled down shortly
after VBATUVLO is reached
SYS
Conditions: SW_LDO = 1, MRREC = 1, PG and INT pulled up to SYS, ISYS = 10 µA, EN_INT = 1
Figure 2. Battery Operation and Sleep Mode
14
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7.7 Typical Characteristics
12
2.0
10
1.5
BAT IQ (PA)
BAT IQ (PA)
8
6
1.0
4
0.5
2
85qC
60qC
25qC
0qC
85qC
60qC
0
25qC
0qC
0.0
3
3.2
3.4
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
3
3.2
3.4
D016
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
D017
1.8 V System Enabled (No Load)
Figure 3. Active BAT, IQ
Figure 4. Hi-Z BAT, IQ
700
0.14
85qC
60qC
0.12
25qC
0qC
600
500
RDS(ON) (m:)
BAT IQ (PA)
0.10
0.08
0.06
400
300
0.04
200
0.02
100
0
-40
0.00
3
3.2
3.4
3.6
3.8
BAT (V)
4
4.2
4.4
4.6
-25
-10
D018
Figure 5. Ship Mode BAT, IQ
5
20 35 50 65
Temperature (qC)
80
95
110 125
D024
Figure 6. Blocking FET RDS(ON) vs Temperature
400
0.5%
350
0.3%
250
Accuracy
RDS(ON) (m:)
300
200
150
0.1%
-0.1%
4.35 V(BATREG)
4.2 V(BATREG)
4 V(BATREG)
3.8 V(BATREG)
3.6 V(BATREG)
100
-0.3%
50
0
-40
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
-0.5%
-40
-10
D025
Figure 7. Battery Discharge FET RDS(ON) vs Temperature
20
50
Temperature (qC)
80
110 125
D019
Figure 8. V(BATREG) Accuracy vs Temperature
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Typical Characteristics (continued)
5%
5%
-40qC
0qC
25qC
85qC
125qC
4%
3%
3%
1%
Accuracy
Accuracy
2%
0
-1%
-2%
-40qC
0qC
25qC
85qC
125qC
-3%
-4%
-5%
0.05
-1%
-3%
-5%
0.1
0.15
0.2
0.25
0.3
Input Current Limit (A)
0.35
0.4
0
50
100
150
200
Charge Current (mA)
D020
Figure 9. ILIM Accuracy vs Input Current
250
300
D021
Figure 10. Charge Current Accuracy vs Charge Current
10%
1000
-40qC
0qC
25qC
85qC
125qC
8%
6%
900
800
700
RDS(ON) (m:)
4%
Accuracy
1%
2%
0
-2%
600
500
400
-4%
300
-6%
200
-8%
100
-10%
0
5
10
15
20
25
30
Pre-Charge Current (mA)
35
0
-40
40
-25
-10
D022
5
20 35 50 65
Temperature (qC)
80
95
110 125
D024
D026
VIN = 5 V
Figure 12. RDS(ON) of High Side MOSFET vs Temperature
160
350
140
300
120
250
100
PSRR (dB)
RDS(ON) (m:)
Figure 11. Pre-Charge Accuracy vs Pre-Charge Current
400
200
150
50
20
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
100 mA
60
40
-25
10 mA
50 mA
80
100
0
-40
Noise Floor
1 mA
0
10 20
D027
50 100
1000
10000
Frequency (Hz)
100000
1000000
D028
VIN = 5 V
Figure 13. RDS(ON) of Low Side MOSFET vs Temperature
16
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Figure 14. LS/LDO PSRR vs Frequency
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8 Detailed Description
8.1 Overview
The following sections describe in detail the functions provided by the BQ25121A. These include linear charger,
PWM output, configurable LS/LDO output, Push-button input, reset timer, functional modes, battery monitor, I2C
configurability and functions, and safety features.
8.2 Functional Block Diagram
PMID
Q1/Q2
Q3
SW
D
S
IN
G
D
G
GND
S
IINLIM
PWM, LDO, and BAT FET
Control
VIN_DPM
Q4
SYS
VSYSREG
VINLS
IBATREG
LDO
Control
S
VBATREG
Thermal
Shutdown
VSUPPLY
CD
SDA
SCL
Hi-Z
Mode
VIN
I2C
Interface
ILIM
Input Current Limit
Q5
LS/LDO
Termination
Reference
LDO/ Load Switch
Host Control
IPRETERM
D
LDO/ Load Switch
Control
LSCTRL
ISET
G
+
Q7
IBAT
+
Disable
TS COLD
Charge Current
1C/
0.5C
Termination Current
VBATREG
± 140mV
PG
+
TS COOL
TS WARM
VOVP
INT
+
+
Disable
Device Control
BAT
+
TS HOT
+
VIN
VINOVP
VBAT
BATOVP
VBAT
BATSHRT
+
+
VBATSHRT
VBATOVP
VBATREG ± 0.12 V
Recharge
RESET
VBAT(SC)
+
VBAT
Reset and
Timer
MR
TS
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8.3 Feature Description
8.3.1 Ship Mode
Ship Mode is the lowest quiescent current state for the device. Ship Mode latches off the device and BAT FET
until VIN > VBAT + VSLP or the MR button is depressed for tWAKE1 and released. The following list shows the events
that are active during Ship Mode:
1. VIN_UV Comparator
2. MR Input (No clock or delay in this mode for lowest power consumption)
3. PMID active pull down
8.3.1.1 Ship Mode Entry and Exit
The device may only enter Ship Mode when there is not a valid VIN supply present (VIN < VUVLO). Once the IN
supply is removed there are two ways for the device to enter Ship Mode: through I2C command using the
EN_SHIPMODE bit and by doing a long button press when MRREC bit is set to 0. If the EN_SHIPMODE bit is
set while the IN supply is present, the device will enter Ship Mode upon removal of the supply. The
EN_SHIPMODE bit can be cleared using the I2C interface as well while the IN input is valid.
In addition to VIN < VUVLO, CD and MR must be high. Once all of these conditions are met the device will begin
the transition to Ship Mode. All three conditions must remain unchanged for a period of tQUIET to ensure proper
operation. Figure 15 and Figure 16 show the correct sequencing to ensure proper entry into the Ship Mode
through I2C command and MR button press respectively.
tQUIET
CD
MR
VIN
Shipmode
2
I C
Write
xxxxxx
xx xxxxxx
Figure 15. CD, MR and VIN Sequencing for Ship Mode Entry Through I2C Command
18
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Feature Description (continued)
tQUIET
CD
t > tRESET
MR
xxxxxx
xxxxxx
VIN
Shipmode
2
I C
Write
Figure 16. CD, MR and VIN Sequencing for Ship Mode Entry Through Long MR button press
The end user can enable the device (exit Ship Mode) by connecting an adapter to IN (VIN > VBAT + VSLP) or by
toggling the MR button. Note that in the case where an adapter is connected while the MR is still held low and
immediately after the RESET timer has expired (MR low for tRESET), the device will not enter Ship Mode, but may
enter it upon adapter removal (Same behavior as setting the EN_SHIPMODE bit when the adapter is present).
This will not be the case if MR has gone high when the adapter is connected or MR continues to be held low for
a period longer than tWAKE1 after the adapter is connected.
To exit Ship Mode through and MR press the battery voltage must be above the maximum programmable
BUVLO threshold when VIN is not present. Once MR goes low, the device will start to exit Ship Mode, powering
PMID. The device will not complete the transition from Ship Mode until MR has been held low for at least tWAKE1.
Only after the transition is complete may the host start I2C communication if the device has not entered High
Impedance Mode.
8.3.2 High Impedance Mode
High Impedance mode is the lowest quiescent current state while operating from the battery. During Hi-Z mode
the SYS output is powered by BAT, the MR input is active, and the LSCTRL input is active. All other circuits are
in a low power or sleep state. The LS/LDO output can be enabled in Hi-Z mode with the LSCTRL input. If the
LS/LDO output has been enabled through I2C prior to entering Hi-Z mode, it will stay enabled. The CD pin is
used to put the device in a high-impedance mode when battery is present and VIN < VUVLO. Drive CD high to
enable the device and enter active battery operation when VIN is not valid. When the HZ_MODE bit is written by
the host, the I2C interface is disabled if only battery is present. To resume I2C, the CD pin must be toggled. If the
supply for the CD pull up glitches or experiences a brownout condition , it is recommended to toggle the /CD pin
to resume I2C communication.. The functionality of the pin is shown in Table 1.
Table 1. CD, State Table
CD, State
VIN < VUVLO
VIN > VUVLO
L
Hi-Z
Charge Enabled
H
Active Battery
Charge Disabled
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8.3.3 Active Battery Only Connected
When the battery above VBATUVLO is connected with no input source, the battery discharge FET is turned on.
After the battery rises above VBATUVLO and the deglitch time is reached, the SYS output starts to rise. The current
from PMID and SYS is not regulated, but is protected by a short circuit current limit. If the short circuit limit is
reached for the deglitch time (tDGL_SC), the battery discharge FET is turned off for the recovery time (tREC_SC).
After the recovery time, the battery FET is turned on to test if the short has been removed. If it has not, the FET
turns off and the process repeats until the short is removed. This process protects the internal FET from over
current. During this event PMID will likely droop and cause SYS to go out of regulation.
To provide designers the most flexibility in optimizing their system, an adjustable BATUVLO is provided. When
the voltage drops below the VBATUVLO threshold, the battery discharge FET is turned off. Deeper discharge of the
battery enables longer times between charging, but may shorten the battery life. The BATUVLO is adjustable
with a fixed 150-mV hysteresis.
If a valid VIN is connected during active battery mode, VIN > VUVLO, the supplement and battery discharge FET is
turned on when the battery voltage is above the minimum VBATUVLO.
Drive CD high or write the CE register to disable charge when VIN > VUVLO is present. CD is internally pulled
down. When exiting this mode, charging resumes if VIN is present, CD is low and charging is enabled.
All HOST interfaces (CD, SDA/SCL, INT, RESET and LSCTRL) are active no later than 5 ms after SYS reaches
the programmed level.
8.3.4 Voltage Based Battery Monitor
The device implements a simple voltage battery monitor which can be used to determine the depth of discharge.
Prior to entering High-Z mode, the device will initiate a VBMON reading. The host can read the latched value for
the no-load battery voltage, or initiate a reading using VBMON_READ to see the battery voltage under a known
load. The register will be updated and can be read 2ms after a read is initiated. The VBMON voltage threshold is
readable with 2% increments with ±1.5% accuracy between 60% and 100% of VBATREG using the VBMON_TH
registers. Reading the value during charge is possible, but for the most accurate battery voltage indication, it is
recommended to disable charge, initiate a read, and then re-enable charge.
A typical discharge profile for a Li-Ion battery is shown in Table 2. The specific battery to be used in the
application should be fully characterized to determine the thresholds that will indicate the appropriate battery
status to the user. Two typical examples are shown below, assuming the VBMON reading is taken with no load
on the battery.
This function enables a simple 5-bar status indicator with the following typical performance with different
VBATREG settings:
Table 2. Discharge Profile for a Li-Ion Battery
20
95% to 65%
65% to 35%
35% to 5%
REMAINING CAPACITY REMAINING CAPACITY REMAINING CAPACITY
VBATREG
BATTERY FULL
4.35 V
VBMON > 90%
VBMON = 88%
VBMON = 86%
VBMON = 84%
VBMON < 82%
4.2 V
VBMON > 98%
VBMON = 94% or 96%
VBMON = 90% or 92%
VBMON = 86% or 88%
VBMON < 84%
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VREF
S0
-2 % BAT TAP
- 4 % BAT TAP
-6 % BAT TAP
-8 % BAT TAP
- 10 % BAT TAP
90 % VB
S1
S2
70 % VB
S3
VBGUAGE_TH<2:0>
80 % VB
D
E
C
O
D
E
R
60 % VB
VB = 0. 8 VBAT
Figure 17. Voltage Battery Monitor
8.3.5 Sleep Mode
The device enters the low-power sleep mode if the voltage IN falls below the sleep-mode entry threshold and VIN
is higher than the undervoltage lockout threshold. In sleep mode, the input is isolated from the connected battery.
This feature prevents draining the battery during the absence of VIN. When VIN < V(BAT) + VSLP, the device turns
the battery discharge FET on, sends a 128-µs pulse on the INT output, and the FAULT bits of the register are
update over I2C. Once VIN > V(BAT) + VSLP, the device initiates a new charge cycle. The FAULT bits are not
cleared until they are read over I2C and the sleep condition no longer exists. It is not recommended to do a
battery connection or plug in when VUVLO< VIN < VBAT + VSLP as it may cause higher quiescent current to be
drained form the battery.
8.3.6 Input Voltage Based Dynamic Power Management (VIN(DPM))
During the normal charging process, if the input power source is not able to support the programmed or default
charging current and System load, the supply voltage decreases. Once the supply approaches VIN(DPM), the input
DPM current and voltage loops will reduce the input current through the blocking FETs, to prevent the further
drop of the supply. The VIN(DPM) threshold is programmable through the I2C register from 4.2 V to 4.9 V in 100mV steps. It can be disabled completely as well. When the device enters this mode, the charge current may be
lower than the set value and the VINDPM_STAT bit is set. If the 2X timer is set, the safety timer is extended
while VIN(DPM) is active. Additionally, termination is disabled. Note that in a condition where the battery is
connected while VUVLO<VIN < VIN(DPM), the VINDPM loop will prevent the battery from being charged and PMID
will be powered from BAT.
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8.3.7 Input Overvoltage Protection and Undervoltage Status Indication
The input overvoltage protection protects the device and downstream components connected to PMID, SYS, and
BAT against damage from overvoltage on the input supply. When VIN > VOVP an OVP fault is determined to exist.
During the OVP fault, the device turns the battery discharge FET on, sends a single 128-µs pulse on INT, and
the FAULT bits are updated over I2C. Once the OVP fault is removed, after the deglitch time, tDGL_OVP, STAT and
FAULT bits are cleared and the device returns to normal operation. The FAULT bits are not cleared until they are
read in from I2C after the OVP condition no longer exists. The OVP threshold for the device is set to operate from
standard USB sources.
The input under-voltage status indication is used to notify the host or other device when the input voltage falls
below a desired threshold. When VIN < VUVLO, after the deglitch time tDGL_UVLO, a UVLO fault is determined to
exist. During the VIN UVLO fault, the device sends a single 128-µs pulse on INT, and the STAT and FAULT bits
are updated over I2C. The FAULT bits are not cleared until they are read in from I2C after the UVLO condition no
longer exists.
8.3.8 Battery Charging Process and Charge Profile
When a valid input source is connected (VIN > VUVLO and V(BAT) + VSLP < VIN < VOVP and VIN > VIN(DPM)), the CE
bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input
source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on
the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input
can be used to enable and disable charge.
The device supports multiple battery chemistries for single-cell applications. Charging is done through the
internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC),
constant voltage loop (CV), input current limit, VDPPM, and VIN(DPM). During the charging process, all loops are
enabled and the one that is dominant takes control.
The charge current is regulated to ICHARGE until the voltage between BAT and GND reaches the regulation
voltage. The voltage between BAT and GND is regulated to VBATREG (CV Mode) while the charge current
naturally tapers down. When termination is enabled, the device monitors the charging current during the CV
mode, and once the charge current tapers down to the termination threshold, ITERM, and the battery voltage is
above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination
is disabled when any loop is active other than CV.
8.3.9 Dynamic Power Path Management Mode
With a valid input source connected, the power-path management circuitry monitors the input voltage and current
continuously. The current into IN is shared at PMID between charging the battery and powering the system load
at PMID, SYS, and LS/LDO. If the sum of the charging and load currents exceeds the current that the VIN can
support, the input DPM loop(VINDPM) reduces the current going into PMID through the input blocking FETs.
This will cause a drop on the PMID voltage if the system demands more current. If PMID drops below the DPPM
voltage threshold(VDPPM), the charging current is reduced by the DPPM loop through the BATFET in order to
stabilize PMID. If PMID continues to drop after BATFET charging current is reduced to zero, the part enters
supplement mode when PMID falls below the supplement mode threshold. Battery termination is disabled while
in DPPM mode. In order to charge the battery, the voltage at PMID has to be greater than VBATREG + VDPPM
threshold..
8.3.10 Battery Supplement Mode
While in DPPM mode, if the charging current falls to zero and the system load current increases beyond the
programmed input current limit, the voltage at PMID reduces further. When the PMID voltage drops below the
battery voltage by V(BSUP1), the battery supplements the system load. The battery stops supplementing the
system load when the voltage on the PMID pin rises above the battery voltage by V(BSUP2). During supplement
mode, the battery supplement current is not regulated, however, the short-circuit protection circuit is active.
Battery termination is disabled while in supplement mode.
22
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8.3.11 Default Mode
The default mode is used when there is no host, or I2C communication is not available. If the externally
programmable pins, ILIM, ISET, and ITERM have resistors connected, that is considered the default mode. If any
one of these resistors is tied to GND, the default register settings are used. The default mode can be entered by
connecting a valid power source to VIN or the RESET bit is written. Default mode is exited by writing to the I2C
interface.
8.3.12 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
The termination current threshold is user programmable through an external resistor or through registers over
I2C. Set the termination current using the IPRETERM pin by connecting a resistor from IPRETERM to GND. The
termination can be set between 5% and 20% of the programmed output current set by ISET, using Table 3 for
guidance:
Table 3. IPRETERM Resistor Settings
IPRE_CHARGE and ITERM
MIN
TYP
(% of ISET)
RIPRETERM
(STANDARD 1%
VALUES)
KKIPRETERM
MAX
MIN
TYP
MAX
RECOMMENDED
RIPRETERM
UNIT
5
180
200
220
15000
Ω
10
180
200
220
4990
Ω
15
180
200
220
1650
Ω
20
180
200
220
549
Ω
Using the I2C register, the termination current can be programmed with a minimum of 500 µA and a maximum of
37 mA.
The pre-charge current is not independently programmable through the external resistor, and is set at the
termination current. The pre-charge and termination currents are programmable using the IPRETERM registers.
If no IPRETERM resistor is connected and the pin is tied to GND, the default values in the IPRETERM registers
are used. The external value can be used in host mode by configuring the IPRETERM registers. If the external
ICHG setting will be used after being in Host mode, the IPRETERM registers should be set to match the desired
external threshold for the highest ICHG accuracy.
Termination is disabled when any loop other than CV is active.
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8.3.13 Input Current Limit Programming by External Components (ILIM)
The input current limit threshold is user programmable through an external resistor or through registers over I2C.
Set the input current limit using the ILIM pin by connecting a resistor from ILIM to GND using Table 4 for
guidance. If no ILIM resistor is connected and the pin is tied to GND, the default ILIM register value is used. The
external value is not valid once the device enters host mode.
Table 4. ILIM Resistor Settings
MIN
ILIM
TYP
MAX
MIN
TYP
KILIM
MAX
RILIM
(STANDARD 1%
VALUES)
UNIT
0.048469388
0.051020408
0.053571429
190
200
210
3920
Ω
0.09047619
0.095238095
0.1
190
200
210
2100
Ω
0.146153846
0.153846154
0.161538462
190
200
210
1300
Ω
0.19
0.2
0.21
190
200
210
1000
Ω
0.285714286
0.30075188
0.315789474
190
200
210
665
Ω
0.380761523
0.400801603
0.420841683
190
200
210
499
Ω
The device has register programmable input current limits from 50 mA to 400 mA in 50-mA steps. The device is
USB-IF compliant for inrush current testing, assuming that the input capacitance to the device is selected to be
small enough to prevent a violation (<10 µF), as this current is not limited.
8.3.14 Charge Current Programming by External Components (ISET)
The fast charge current is user programmable through an external resistor or through registers over I2C. Set the
fast charge current by connecting a resistor from ISET to GND. If no ISET resistor is connected and the pin is
tied to GND, the default ISET register value is used. While charging, if the charge current is using the externally
programmed value, the voltage at ISET reflects the actual charging current and can be used to monitor charge
current. The current out of ISET is 1/100 (±10%) of the charge current. The charge current can be calculated by
using Table 5 for guidance:
Table 5. ISET Resistor Settings
ISET
24
KISET
RISET
(STANDARD 1%
VALUES)
UNIT
210
665
Ω
210
1000
Ω
200
210
1500
Ω
190
200
210
2000
Ω
0.071428571
190
200
210
2940
Ω
0.051020408
0.053571429
190
200
210
3920
Ω
0.038076152
0.04008016
0.042084168
190
200
210
4990
Ω
0.031456954
0.033112583
0.034768212
190
200
210
6040
Ω
0.025956284
0.027322404
0.028688525
190
200
210
7320
Ω
0.019
0.02
0.021
190
200
210
10000
Ω
0.012666667
0.013333333
0.014
190
200
210
15000
Ω
0.0095
0.01
0.0105
190
200
210
20000
Ω
0.006462585
0.006802721
0.007142857
190
200
210
29400
Ω
0.004846939
0.005102041
0.005357143
190
200
210
39200
Ω
MIN
TYP
MAX
MIN
TYP
MAX
0.285714286
0.30075188
0.315789474
190
200
0.19
0.2
0.21
190
200
0.126666667
0.133333333
0.14
190
0.095
0.1
0.105
0.06462585
0.068027211
0.048469388
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8.3.15 Safety Timer
At the beginning of the charge cycle, the device starts the safety timer. If charging has not terminated before the
programmed safety time, tMAXCHG, expires, the device enters idle mode and charging is disabled. The pre-charge
safety time, tPRECHG, is 10% of tMAXCHG. When a safety timer fault occurs, a single 128 µs pulse is sent on the INT
pin and the STAT and FAULT bits of the status registers are updated over I2C. The CD pin or power must be
toggled in order to clear the safety timer fault. The safety timer duration is programmable using the TMR bits.
When the safety timer is active, changing the safety timer duration resets the safety timer. The device also
contains a 2X_TIMER bit that enables the 2X timer function to prevent premature safety timer expiration when
the charge current is reduced by a load on PMID, SYS, LS/LDO or a NTC condition. When t2X_TIMER function is
enabled, the timer is allowed to run at half speed when any loop is active other than CC or CV.
8.3.16 External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the device provides a flexible voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging.
To satisfy the JEITA requirements, four temperature thresholds are monitored: the cold battery threshold, the
cool battery threshold, the warm battery threshold, and the hot battery threshold. These temperatures correspond
to the V(COLD), V(COOL), V(WARM), and V(HOT) threshold in the Electrical Characteristics. Charging and timers are
suspended when V(TS) < V(HOT) or > V(COLD). When V(COOL) < V(TS) < V(COLD), the charging current is reduced to
half of the programmed charge current. When V(HOT) < V(TS) < V(WARM), the battery regulation voltage is reduced
by 140 mV (minimum VBATREG under this condition is 3.6V).
The TS function is voltage based for maximum flexibility. Connect a resistor divider from VIN to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 18. The resistor values are
calculated using Equation 1 and Equation 2. To disable the TS function, pull TS above TSOFF threshold.
DISABLE
VBATREG
– 140 mV
1 x Charge/
0.5 x Charge
VDRV
TS COLD
TS COOL
+
+
TS WARM
+
VDRV
TS HOT
RHI
+
TS
TEMP
PACK+
BQ25121A
RLO
PACK–
Figure 18. TS Circuit
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æ
ö
1
1
÷
VIN x R(COLD) x R(HOT) x ç
ç V(COLD) V(HOT) ÷
è
ø
R(LO) =
æ V
ö
æ V
ö
IN - 1÷ - R
IN
R(HOT) x ç
- 1÷
(COLD) x çç
ç V(HOT)
÷
÷
V
è
ø
è (COLD)
ø
R(HI) =
(1)
æ V
ö
IN
ç
- 1÷
ç V(COLD)
÷
è
ø
æ 1
ö
1
ç
÷
+
ç R(LO)
R(COLD) ÷ø
è
(2)
Where
• R(HOT) = the NTC resistance at the hot temperature
• R(COLD) = the NTC resistance at the cold temperature
The warm and cool thresholds are not independently programmable. The cool and warm NTC resistances for a
selected resistor divider are calculated using Equation 3 and Equation 4.
R(COOL) =
R(LO) x R(HI) x VCOOL %
R(LO) - R(LO) x VCOOL % - R(HI) x VCOOL %
R(LO) x R(HI) x VWARM %
R(WARM) =
R(LO)
26
(R(LO) x VWARM%
(3)
- R(HI) x VWARM %
)
(4)
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8.3.17 Thermal Protection
During the charging process, to prevent overheating in the device, the junction temperature of the die, TJ, is
monitored. When TJ reaches T(SHUTDOWN) the device stops charging, disables the PMID output, disables the SYS
output, and disables the LS/LDO output. During the time that T(SHUTDOWN) is exceeded, the safety timer is reset.
The charge cycle resumes when TJ falls below T(SHUTDOWN) by T(HYS).
To avoid reaching thermal shutdown, ensure that the system power dissipation is under the limits of the device.
The power dissipated by the device can be calculated using Equation 5.
PDISS = P(BLOCK) + P(SYS) + P(LS/LDO) + P(BAT)
(5)
Where
• P(BLOCK) = (VIN – V(PMID)) x IIN
• P(SYS) = ISYS2 x RDS(ON_HS)
• P(LS/LDO) = (V(INLS) – V(LS/LDO)) x I(LS/LDO)
• P(BAT) = (V(PMID) – V(BAT)) x I(BAT)
8.3.18 Typical Application Power Dissipation
The die junction temperature, TJ, can be estimated based on the expected board performance using Equation 6.
TJ = TA + θJA x PDISS
(6)
The θJA is largely driven by the board layout. For more information about traditional and new thermal metrics, see
the IC Package Thermal Metrics application report SPRA953. Under typical conditions, the time spent in this
state is short.
8.3.19 Status Indicators (PG and INT)
The device contains two open-drain outputs that signal its status and are valid only after the device has
completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output
signals when a valid input source is connected. PG pulls to GND when VIN > VUVLO, VIN> VBAT+VSLP and VIN <
VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic
voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is highimpedance when the MR input is not low, and PG pulls to GND when the MR input is below VOL(TH_MRS). Connect
PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When
EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is
high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128
µs pulse (interrupt) is sent on INT to notify the host.
8.3.20 Chip Disable (CD)
The device contains a CD input that is used to disable the device and place it into a high impedance mode when
only battery is present. In this case, when CD is low, PMID and SYS remain active, and the battery discharge
FET is turned on. If the LS/LDO output has been enabled prior to pulling CD low, it will stay on. The LSCTRL pin
can also enable/disable the LS/LDO output when the CD pin is pulled low. The CD pin has an internal pull-down.
If VIN is present and the CD input is pulled low, charge is enabled and all other functions remain active. If VIN is
present and the CD input is pulled high, charge is disabled.
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8.3.21 Buck (PWM) Output
The device integrates a low quiescent current switching regulator with DCS control allowing high efficiency down
to 10-µA load currents. DCS control combines the advantages of hysteretic and voltage mode control. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors. During PWM mode, it operates in continuous conduction mode, with a frequency up to
2 MHz. If the load current decreases, the converter enters a power save mode to maintain high efficiency down
to light loads. In this mode, the device generates a single switching pulse to ramp up the inductor current and
recharge the output capacitor, followed by a sleep period where most of the internal circuits are shut down to
achieve a low quiescent current. The duration of the sleep period depends on the load current and the inductor
peak current. For optimal operation and maximum power delivery allow VPMID > VSYS + 0.7V.
The output voltage is programmable using the SYS_SEL and SYS_VOUT bits in the SYS VOUT control register.
The SW output is enabled using the EN_SYS_OUT bit in the register. This bit is for testing and debug only and
not intended to be used in the final system. When the device is enabled, the internal reference is powered up
and the device enters softstart, starts switching, and ramps up the output voltage. When SW is disabled, the
output is in shutdown mode in a low quiescent state. The device provides automatic output voltage discharge so
the output voltage will ramp up from zero once the device in enabled again. Once SYS has been disabled, either
VIN needs to be connected or the MR button must be held low for the tRESET duration to re-enable SYS.
The output is optimized for operation with a 2.2-µH inductor and 10-µF output capacitor. Table 6 shows the
recommended LC output filter combinations.
Table 6. Recommended Output Filter
INDUCTOR VALUE (µH)
2.2
OUTPUT CAPACITOR VALUE (µF)
4.7
10
22
Possible
Recommended
Possible
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point where the part
enters and exits Pulse Frequency Modulation to lower the power consumed at low loads, the output voltage
ripple and the efficiency. The selected inductor must be selected for its DC resistance and saturation current. The
inductor ripple current (ΔIL) can be estimated according to Equation 7.
ΔIL = VSYS x (1-(VSYS/VPMID))/(L x f)
(7)
Use Equation 8 to calculate the maximum inductor current under static load conditions. The saturation current of
the inductor should be rated higher than the maximum inductor current. As the size of the inductor decreases,
the saturation “knee” must be carefully considered to ensure that the inductance does not decrease during higher
load condition or transient. This is recommended because during a heavy load transient the inductor current rises
above the calculated value. A more conservative way is to select the inductor saturation current above the highside MOSFET switch current.
IL(max) = ISYS(max) + ΔIL / 2
(8)
Where
• F = Switching Frequency
• L = Inductor Value
• ΔIL = Peak to Peak inductor ripple current
• IL(max) = Maximum Inductor current
In DC/DC converter applications, the efficiency is affected by the inductor AC resistance and by the inductor
DCR value.
Table 7 shows recommended inductor series from different suppliers.
Table 7. Inductor Series
DIMENSIONS
(mm3)
INDUCTOR TYPE
0.300
1.6 x 0.8 x 0.8
MDT1608CH2R2N
TOKO
Smallest size, 75mA max
0.170
1 .6 x 0.8 x 0.8
GLFR1608T2R2M
TDK
Smallest size, 150mA max
INDUCTANCE (µH)
DCR (Ω)
2.2
2.2
(1)
See Third-party Products Disclaimer
28
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(1)
COMMENT
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Table 7. Inductor Series (continued)
INDUCTANCE (µH)
DCR (Ω)
DIMENSIONS
(mm3)
INDUCTOR TYPE
2.2
0.245
2.0 x 1.2 x 1.0
MDT2012CH2R2N
TOKO
2.2
0.23
2.0 x 1.2 x 1.0
MIPSZ2012 2R2
TDK
2.2
0.225
2.0 x 1.6 x 1.0
74438343022
Wurth
2.2
0.12
2.5 x 2.0 x 1.2
MIPSA2520 2R2
TDK
2.2
0.145
3.3 x 3.3 x 1.4
LPS3314
Coicraft
SUPPLIER
(1)
COMMENT
Small size, high efficiency
The PWM allows the use of small ceramic capacitors. Ceramic capacitors with low ESR values have the lowest
output voltage ripple and are recommended. The output capacitor requires either an X7R or X5R dielectric. At
light load currents, the converter operates in Power Save Mode and the output voltage ripple is dependent on the
output capacitor value and the PFM peak inductor current. Because the PWM converter has a pulsating input
current, a low ESR input capacitor is required on PMID for the best voltage filtering to ensure proper function of
the device and to minimize input voltage spikes. For most applications a 10-µF capacitor value is sufficient. The
PMID capacitor can be increased to 22 µF for better input voltage filtering.
Table 8 shows the recommended input/output capacitors.
Table 8. Capacitors
(1)
CAPACITANCE (µF)
SIZE
CAPACITOR TYPE
SUPPLIER (1)
COMMENT
10
0603
GRM188R60J106ME84
Murata
Recommended
10
0402
CL05A106MP5NUNC
Samsung EMA
Smallest size
See Third-party Products Disclaimer
8.3.22 Load Switch / LDO Output and Control
The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can
be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as
there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low
voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to
VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times
larger than the output capacitor on LS/LDO.
The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated
using Equation 9.
LS/LDO = 0.8 V + LS_LDOCODE x 100 mV
(9)
If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS V(DROPOUT). Table 9 summarizes the control of the LS/LDO output based on the I2C or LSCTRL pin setting:
Table 9. LS/LDO Output Control
2
I C LS_LDO_EN
PIN LSCTRL
I2C VLDO > 3.3
LS/LDO Output
0
0
0
Pulldown
0
0
1
Pulldown
0
1
0
VLDO
0
1
1
LSW
1
0
0
VLDO
1
0
1
LSW
1
1
0
VLDO
1
1
1
LSW
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If the output of the LDO is less than the programmed V(SYS) voltage, connect VINLS to SYS. If the output of the
LDO is greater than the programmed VSYS voltage, connect VINLS to PMID.
The current capability of the LDO depends on the VINLS input voltage and the programmed output voltage. The
full 100-mA output current for 0.8-V output voltage can be achieved when V(VINLS) > 3.25 V. The full 100-mA
output current for 3.3-V output voltage can be achieved when V(VINLS) > 3.6 V.
When the LSLDO output is disabled with LSCTRL or through the register, an internal pull-down discharges the
output.
8.3.23 Manual Reset Timer and Reset Output (MR and RESET)
The MR input has an internal pull-up to BAT, and MR is functional only when BAT is present or when VIN is
valid, stable, and charge is enabled. If MR input is asserted during a transient condition while VIN ramps up the
IC may incorrectly turn off the SYS buck output, therefore MR should not be asserted during this condition in
order to avoid unwanted shutdown of SYS output rail.The input conditions can be adjusted by using MRWAKE
bits for the wake conditions and MRRESET bits for the reset conditions. When a wake condition is met, a 128-µs
pulse is sent on INT to notify the host, and the WAKE1 and/or WAKE2 bits are updated on I2C. The MR_WAKE
bits and RESET FAULT bits are not cleared until the Push-button Control Register is read from I2C.
When a MR reset condition is met, a 128-µs pulse is sent on INT to notify the host and a RESET signal is
asserted. A reset pulse occurs with duration of tRESET_D only one time after each valid MRRESET condition. The
MR pin must be released (go high) and then driven low for the MRWAKE period before RESET asserts again.
After RESET is asserted with battery only present, the device enters either Ship mode or Hi-Z mode depending
on MRREC register settings. For details on how to properly enter Ship Mode through MR, see Ship Mode Entry
and Exit section. After RESET is asserted with a valid VIN present, the device resumes operation prior to the MR
button press. If SYS was disabled prior to RESET, the SYS output is re-enabled if recovering into Hi-Z or Active
Battery.
The MRRESET_VIN register can be configured to have RESET asserted by a button press only, or by a button
press and VIN present (VUVLO + VSLP < VIN < VOVP).
30
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8.4 Device Functional Modes
Table 10. Modes and Functions
FUNCTION
READY (PRIOR
TO I2C) AND
AFTER RESET
HOST MODE
READY (AFTER
I2C)
CHARGE
SHIP MODE
HIGH_Z
ACTIVE
BATTERY
VOVP
Yes
Yes
Yes
No
No
No
VUVLO
Yes
Yes
Yes
Yes
Yes
Yes
VBATUVLO
Yes
Yes
Yes
No
Yes
Yes
VINDPM
Default or
registers
Default or
registers
If enabled
No
No
No
SYS
Default or
registers
Default or
registers
If enabled
No
If enabled
If enabled
LS/LDO
Default or
registers
Default or
registers
If enabled
No
If enabled
If enabled
BATFET
Yes
Yes
Yes
No
Yes
Yes
TS
Yes (VIN Valid)
Yes (VIN Valid)
Yes
No
No
No
IPRETERM
External
Default, registers,
or external
Default, registers,
or external
No
No
No
ISET
External
Default, registers,
or external
Default, registers,
or external
No
No
No
ILIM
External
Default, registers,
or external
Default, registers,
or external
No
No
No
MR input
Yes
Yes
Yes
Yes
Yes
Yes
LSCTRL input
Yes
Yes
Yes
No
Yes
Yes
RESET output
Yes
Yes
Yes
No
Yes
Yes
INT output
Yes
Yes
Yes
No
No
Yes
I2C interface
Yes
Yes
Yes
No
No
Yes
CD input
Yes
Yes
Yes
No
Yes
Yes
PG output
Yes
Yes
Yes
No
No
If enabled
VBMON
No
Yes
No
No
No
Yes
Table 11. Fault and Status Condition Responses
FAULT or STATUS
ACTIONS
CHARGER
BEHAVIOR
SYS BEHAVIOR
LS/LDO
BEHAVIOR
TS BEHAVIOR
VIN_OV
Update VIN_OV status, Update
STAT to fault, interrupt on INT,
PG shown not good
Disabled
Enabled through
BAT
Enabled through
BAT
Disabled
VIN_UV
Update VIN_UV status, Update
STAT to fault, interrupt on INT,
PG shown not good
Disabled
Enabled through
BAT
Enabled through
BAT
Disabled
VIN_ILIM
Update charge in progress
status, interrupt on INT, input
current is limited
Enabled, input
current limited
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
OVER_TEMP
Disabled
Disabled
Disabled
Disabled
Pre-charge
Enabled (if
enabled) and VIN
Valid
Enabled (if
enabled) and VIN
Valid
Enabled if VIN
Valid
SW_SYS_SHORT
Enabled
Current Limit
Enabled (if
enabled)
Enabled
LS_LDO_OCP
Enabled
Enabled (if
enabled)
Current Limit
Enabled
Disabled
Enabled (if
enabled)
Enabled (if
enabled)
Disabled
BAT_UVLO
TIMER fault
Update BAT_UVLO status,
Update STAT to fault, interrupt
on INT
Update TIMER, Update STAT
to fault, interrupt on INT
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Table 11. Fault and Status Condition Responses (continued)
FAULT or STATUS
ACTIONS
CHARGER
BEHAVIOR
SYS BEHAVIOR
LS/LDO
BEHAVIOR
TS BEHAVIOR
VINDPM
Update VINDPM_STAT,
Update STAT to fault, interrupt
on INT
Enabled, input
current reduced
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
TS_FAULT COLD
or HOT
Update TS_FAULT to COLD
OR HOT, Update STAT to
fault, interrupt on INT
Disabled
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
TS_FAULT COOL
Update TS_FAULT to COOL,
Update STAT to fault, interrupt
on INT
Reduce ICHG to ½
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
TS_FAULT WARM
Update TS_FAULT to WARM,
Update STAT to fault, interrupt
on INT
Reduce VBATREG
by 140 mV
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
Charge Done
Update STAT to Charge Done,
interrupt on INT
Disabled, monitor
for VBAT falling
below VRCHG
Enabled (if
enabled)
Enabled (if
enabled)
Enabled
/CE
RESET
yVIN_OV
yVIN_UV
yOVER_TEMP
yBAT_SHORT
yBAT_OVP
yVBAT>VBAT_UVLO
yVIN<VBAT+VSLP
yCD9
HZ_MODE
yCD;|VIN>VUVLO
FAULT
A failure occurred. The fault event
must be cleared before going to the
previous state.
READY STATE
After Reset, all default OTP settings
are used in this state.
HIGH_Z
Lowest quiescent current state. SYS
is powered by BAT, MR input is active,
and the LSCTRL input is active.
!FAULT|/CE
yTIMER
yVIN_OV
yOVER_TEMP
yTS_FAULT (HOT OR COLD)
/CE
yBAT_OVP
yVIN_OV
yTS_FAULT (HOT OR COLD)
!/CE
HZ_MODE
yCD9
!FAULT|!/CE & DONE
yCD;|VIN<VUVLO
yVBAT>VBAT_UVLO
yVIN<VBAT+VSLP
!FAULT|!/CE
CHARGING
The system charges the battery using
the programmed register settings,
default OTP settings, or the externally
programmed settings. Safety timers
are active in this state, unless disabled
in OTP or register settings.
yCHARGING DONE|TE
DONE
The termination requirements have
been met. VBAT is monitored and
Charging resumes when conditions
are met.
ACTIVE BATTERY
The device is powered from BAT, all
outputs and interfaces are active.
yVIN>VUVLO
yVIN>VBAT+VSLP
yVBAT;
!TE
Comments about naming convention:
^/ ^ }Π^HZ_DK ^ -> Register name: event caused by user / configuration
^!^ -> Not
^y^ -> Event caused by external influence
^Event|condition^ -> describes the event with a specific condition
Figure 19. State Diagram
32
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ILIM
VINDPM
TS_FAULT
PRE_CHARGE
2X TIMER MODE
VALID CHARGE INPUTS
RESET
CC MODE
CV MODE
DEFAULT MODE CHARGE
No HOST or I2C is not available, ILIM,
ISET, and ITERM have resistors
populated .
Default OTP charge settings are used if
no resistors are populated
Register settings used if changed in
I2C
ICHRG+ISW+ILDO>ILIM
ICHG”0
PMID<VBAT-VBSUP1
ICHRG+ISW+ILDO<ILIM
DYNAMIC POWER PATH MODE
Charging current is reduced to supply
the load to SW/OUT and LSLDO
Battery Termination is disabled
BAT SUPPLEMENT MODE
BAT supplements the load at
SW/OUT and LSLDO
ICHG>0
PMID<VBAT-VBSUP2
TS_FAULT (COOL)
VBAT>VBATSHORT
VBAT<VBATUVLO
VBAT<VBATSHORT
VBAT>VBATUVLO + 150 mV
PRE-CHARGE MODE
Charge current is reduced
to the Pre-charge current
level to slowly bring up the
VBAT voltage
!TS_FAULT
TS_FAULT (WARM)
!TS_FAULT
½ CHARGE MODE
Charging current is reduced to half the
programmed or default current
VIN>VIN_DPM
VIN ” VIN_DPM
BAT-SHORT MODE
Charge current is reduced to
the Bat-Short current level to
slowly bring up the VBAT
voltage
VINDPM MODE
Charge current is reduced , 2X TIMER
mode is active (if enabled ) and
termination is disabled
VBATREG ± 140mV MODE
VBATREG is reduced by 140mV from
the programmed or default VBATREG
Comments about naming convention:
^/ ^ }Π^HZ_DK ^ -> Register name: event caused by user / configuration
^!^ -> Not
^y^ -> Event caused by external influence
^Event|condition^ -> describes the event with a specific condition
Figure 20. Change State Diagram
8.5 Programming
8.5.1 Serial Interface Description
The device uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial
interface developed by NXP. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures.
When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C
bus through open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C BUS
Specification: standard mode (100 kbps) and fast mode (400kbps). The interface adds flexibility to the battery
management solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. The I2C circuitry is powered from the battery in active battery mode. The battery
voltage must stay above V(BATUVLO) when no VIN is present to maintain proper operation. The host must also wait
for SYS to come up before starting communication with the part.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 6A (8-bit
shifted address is D4).
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Programming (continued)
To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the SDA line is held low longer than
tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START and
repeated START conditions and stops when a valid STOP condition is sent.
8.5.2 F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 21. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 21. Start Stop Condition
The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on
the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the
SDA line to be stable during the entire high period of the clock pulse (see Figure 22). All devices recognize the
address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates and acknowledge (see Figure 23) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 22. Bit Transfer on the Serial Interface
34
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Programming (continued)
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
9
8
Clock Pulse for
Acknowledgement
START
Condition
Figure 23. Acknowledge on the I2C Bus
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the
slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An
acknowledge signal can either be generated by the master or by the slave, depending on which on is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 24). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the STOP condition. Upon the receipt of
a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a
matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to
prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses
not listed in this section results in 0xFFh being read out.
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgement
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Figure 24. Bus Protocol
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8.6 Register Maps
8.6.1 Status and Ship Mode Control Register
Memory location 0x00h, Reset State: xx0x xxx1 (BQ25121A)
Figure 25. Status and Ship Mode Control Register
7 (MSB)
x
R
6
x
R
5
0
Write Only
4
x
R
3
x
R
2
x
R
1
x
R
0 (LSB)
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Status and Ship Mode Control Register
Field
Type
Reset
Description
B7 (MSB)
Bit
STAT_1
R
x
B6
STAT_0
R
x
00 - Ready
01 - Charge in Progress
10 - Charge done
11 - Fault
Status is current status only.
B5
EN_SHIPMODE
Write
Only
0
0 – Normal Operation
1 – Ship Mode Enabled
B4
RESET_FAULT
R
x
1 – RESET fault. Indicates when the device meets the RESET
conditions, and is cleared after I2C read.
B3
TIMER
R
x
1 – Safety timer fault. Continues to show fault after an I2C read
unless the CD pin or power have been toggled.
B2
VINDPM_STAT
R
x
0 – VIN_DPM is not active
1 – VIN_DPM is active
B1
CD_STAT
R
x
0 – CD low, IC enabled
1 – CD high, IC disabled
SYS_EN_STAT
R
x
1 – SW enabled
0 – SW disabled
B0 (LSB)
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8.6.2 Faults and Faults Mask Register
Memory location 0x01h, Reset State: xxxx 0000 (BQ25121A)
Figure 26. Faults and Faults Mask Register
7 (MSB)
x
R
6
x
R
5
x
R
4
x
R
3
0
R/W
2
0
R/W
1
0
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Faults and Faults Mask Register
Field
Type
Reset
Description
B7 (MSB)
Bit
VIN_OV
R
x
1 - VIN overvoltage fault. VIN_OV continues to show fault after
an I2C read as long as OV exists
B6
VIN_UV
R
x
1 - VIN undervoltage fault. VIN_UV is set when the input falls
below VSLP. VIN_UV fault shows only one time. Once read,
VIN_UV clears until the the UVLO event occurs.
B5
BAT_UVLO
R
x
1 – BAT_UVLO fault. BAT_UVLO continues to show fault after
an I2C read as long as BAT_UVLO conditions exist.
B4
BAT_OCP
R
x
1 – BAT_OCP fault. BAT_OCP is cleared after I2C read.
B3
VIN_OV_M
R/W
0
1 – Mask VIN overvoltage fault
B2
VIN_UV_M
R/W
0
1 – Mask VIN undervoltage fault
B1
BAT_UVLO_M
R/W
0
1 – Mask BAT UVLO fault
B0 (LSB)
BAT_OCP_M
R/W
0
1 – Mask BAT_OCP fault
If a fault is read on the status register and it is neither of any of the faults in this register or subsequent registers, it indicates an ILIM fault.
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8.6.3 TS Control and Faults Masks Register
Memory location 0x02h, Reset State: 1xxx 1000 (BQ25121A)
Figure 27. TS Control and Faults Masks Register (02)
7 (MSB)
1
R/W
6
x
R
5
x
R
4
x
R
3
1
R/W
2
0
R/W
1
0
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. TS Control and Faults Masks Register, Memory Location 0010
Bit
Field
Type
Reset
Description
TS_EN
R/W
1
0 – TS function disabled
1 – TS function enabled
B6
TS_FAULT1
R
x
B5
TS_FAULT0
R
x
TS Fault mode:
00 – Normal, No TS fault
01 – TS temp < TCOLD or TS temp > THOT (Charging suspended)
10 – TCOOL > TS temp > TCOLD (Charging current reduced by
half)
11 – TWARM < TS temp < THOT (Charging voltage reduced by
140 mV)
B4
Reserved
R
x
Reserved
B3
EN_INT
R/W
1
0 – Disable INT function (INT only shows faults and does not
show charge status)
1 – Enable INT function (INT shows faults and charge status)
B2
WAKE_M
R/W
0
1 – Mask interrupt from Wake Condition from MR
B1
RESET_M
R/W
0
1 – Mask RESET interrupt from MR . The RESET output is not
masked by this bit.
B0 (LSB)
TIMER_M
R/W
0
1 – Mask Timer fault interrupt (safety)
B7 (MSB)
To save power, the device will shut off the clock that counts the deglitch time for the faults in the Hi-Z mode. For any of the fault conditions
that contain a deglitch time as specified in the Electrical Characteristics, the device will have to be in Active BAT with an I2C transaction or
VIN present to count against the deglitch to clear the fault on the register.
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8.6.4 Fast Charge Control Register
Memory location 0x03h, Reset State: 0001 0100 (BQ25121A)
Figure 28. Fast Charge Control Register
7 (MSB)
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. Fast Charge Control Register
Bit
Field
Type
Reset
Description
ICHRG_RANGE
R/W
0
0 – to select charge range from 5 mA to 35 mA, ICHRG bits are
1-mA steps
1 – to select charge range from 40 mA to 300 mA, ICHRG bits
are 10-mA steps
B6
ICHRG_4
R/W
0
Charge current 16 mA or 160 mA
B5
ICHRG_3
R/W
0
Charge current 8 mA or 80 mA
B4
ICHRG_2
R/W
1
Charge current 4 mA or 40 mA
B3
ICHRG_1
R/W
0
Charge current 2 mA or 20 mA
B2
ICHRG_0
R/W
1
Charge current 1 mA or 10 mA
B1
CE
R/W
0
0 – Charger enabled
1 – Charger is disabled
HZ_MODE
R/W
0
0 – Not high impedance mode
1 – High impedance mode
B7 (MSB)
B0 (LSB)
ICHRG_RANGE and ICHRG bits are used to set the charge current. The ICHRG is calculated using the following equation: If
ICHRG_RANGE is 0, then ICHRG = 5 mA + ICHRGCODE x 1 mA. If ICHRG_RANGE is 1, then ICHRG = 40 mA + ICHRGCODE x 10 mA. If a
value greater than 35 mA (ICHRG_RANGE = 0) or 300 mA (ICHRG_RANGE = 1) is written, the setting goes to 35 mA or 300 mA
respectively except if the ICHRG bits are all 1 (that is, 11111), then the externally programmed value is used. The PRETERM bits must also
be set prior to writing all 1s to ensure the external ISET current is used as well as the proper termination and pre-charge values are used.
For IPRETERM = 5%, set the IPRETERM bits to 000001, for IPRETERM = 10%, set the IPRETERM bits to 000010, for IPRETERM = 15%,
set the IPRETERM bits to 000100, and for IPRETERM = 20%, set the iPRETERM bits to 001000. The default may be overridden by the
external resistor on ISET.
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8.6.5 Termination/Pre-Charge and I2C Address Register
Memory location 0x04h, Reset State: 0000 1110 (BQ25121A)
Figure 29. Termination/Pre-Charge and I2C Address Register
7 (MSB)
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. Termination/Pre-Charge and I2C Address Register
Bit
Field
Type
Reset
Description
IPRETERM_RANGE
R/W
0
0 – to select termination range from 500 µA to 5 mA,
IPRETERM bits are 500-µA steps
1 – to select charge range from 6 mA to 37 mA, IPRETERM bits
are 1-mA steps
B6
IPRETERM_4
R/W
0
Termination current 8 mA or 16 mA
B5
IPRETERM_3
R/W
0
Termination current 4 mA or 8 mA
B4
IPRETERM_2
R/W
0
Termination current 2 mA or 4 mA
B3
IPRETERM_1
R/W
1
Termination current 1 mA or 2 mA
B2
IPRETERM_0
R/W
1
Termination current 500 µA or 1 mA
B1
TE
R/W
1
0 – Disable charge current termination
1 – Enable charge current termination
R/W
0
B7 (MSB)
B0 (LSB)
IPRETERM_RANGE and IPRETERM bits are used to set the termination and pre-charge current. The ITERM is calculated using the
following equation: If IPRETERM_RANGE is 0, then ITERM = 500 µA + ITERMCODE x 500 µA. If IPRETERM_RANGE is 1, then ITERM = 6
mA + ITERMCODE x 1 mA. If a value greater than 5 mA (IPRETERM_RANGE = 0) is written, the setting goes to 5 mA. Termination is
disabled if any loop other than CC or DV in control, such as VINDPM, and TS/Cool. The default may be overridden by the external resistor
on IPRETERM.
8.6.6 Battery Voltage Control Register
Memory location 0x05h, Reset State: 0111 1000 (BQ25121A)
Figure 30. Battery Voltage Control Register
7 (MSB)
0
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. Battery Voltage Control Register
Field
Type
Reset
Description
B7 (MSB)
Bit
VBREG_6
R/W
0
Battery Regulation Voltage: 640 mV
B6
VBREG_5
R/W
1
Battery Regulation Voltage: 320 mV
B5
VBREG_4
R/W
1
Battery Regulation Voltage: 160 mV
B4
VBREG_3
R/W
1
Battery Regulation Voltage: 80 mV
B3
VBREG_2
R/W
1
Battery Regulation Voltage: 40 mV
B2
VBREG_1
R/W
0
Battery Regulation Voltage: 20 mV
B1
VBREG_0
R/W
0
Battery Regulation Voltage: 10 mV
R/W
0
B0 (LSB)
VBREG Bits: Use VBREG bits to set the battery regulation threshold. The VBATREG is calculated using the following equation: VBATREG = 3.6
V + VBREGCODE x 10 mV. The charge voltage range is from 3.6 V to 4.65 V. If a value greater than 4.65 V is written, the setting goes to
4.65 V.
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8.6.7 SYS VOUT Control Register
Memory location 0x06h, Reset State: 1011 1000 (BQ25121A)
Figure 31. SYS VOUT Control Register
7 (MSB)
1
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. SYS VOUT Control Register
Bit
Field
Type
Reset
Description
EN_SYS_OUT
R/W
1
0 – Disable SW
1 – Enable SW
(When disabled, output is pulled low)
B6
SYS_SEL1
R/W
0
B5
SYS_SEL0
R/W
1
00 –
01 –
10 –
11 –
B4
SYS_VOUT_3
R/W
1
OUT Voltage: 800 mV step if SYS_SEL is 01 or 11
B3
SYS_VOUT_2
R/W
1
OUT Voltage: 400 mV step if SYS_SEL is 01 or 11
B2
SYS_VOUT_1
R/W
0
OUT Voltage: 200 mV step if SYS_SEL is 01 or 11
B1
SYS_VOUT_0
R/W
0
OUT Voltage: 100 mV step if SYS_SEL is 01 or 11
B7 (MSB)
B0 (LSB)
1.1 V and 1.2 V selection
1.3 V through 2.8 V selection
1.5V through 2.75 V selection
1.8 V through 3.3 V selection
0
SW_VOUT Bits: Use SYS_SEL and SYS_VOUT bits to set the output on SYS. The SYS voltage is calculated using the following equation:
See table below for all VOUT values that can be programmed through SYS_SEL and SYS_VOUT.
If SYS_SEL = 01, then SYS = 1.30 V + SYS_VOUTCODE x 100 mV.
If SYS_SEL = 11, then SYS = 1.80 V + SYS_VOUTCODE x 100 mV.
Table 19. SYS_SEL Codes
SYS_SEL
SYS_VOUT
TYP
UNIT
00
0000
1.1
V
00
0001
1.2
V
00
0010
1.25
V
00
0011
1.333
V
00
0100
1.417
V
00
0101
1.5
V
00
0110
1.583
V
00
0111
1.667
V
00
1000
1.75
V
00
1001
1.833
V
00
1010
1.917
V
00
1011
2
V
00
1100
2.083
V
00
1101
2.167
V
00
1110
2.25
V
00
1111
2.333
V
01
0000
1.3
V
01
0001
1.4
V
01
0010
1.5
V
01
0011
1.6
V
01
0100
1.7
V
01
0101
1.8
V
01
0110
1.9
V
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Table 19. SYS_SEL Codes (continued)
42
SYS_SEL
SYS_VOUT
TYP
UNIT
01
0111
2
V
01
1000
2.1
V
01
1001
2.2
V
01
1010
2.3
V
01
1011
2.4
V
01
1100
2.5
V
01
1101
2.6
V
01
1110
2.7
V
01
1111
2.8
V
10
0000
1.5
V
10
0001
1.583
V
10
0010
1.667
V
10
0011
1.75
V
10
0100
1.833
V
10
0101
1.917
V
10
0110
2
V
10
0111
2.083
V
10
1000
2.167
V
10
1001
2.25
V
10
1010
2.333
V
10
1011
2.417
V
10
1100
2.5
V
10
1101
2.583
V
10
1110
2.667
V
10
1111
2.75
V
11
0000
1.8
V
11
0001
1.9
V
11
0010
2
V
11
0011
2.1
V
11
0100
2.2
V
11
0101
2.3
V
11
0110
2.4
V
11
0111
2.5
V
11
1000
2.6
V
11
1001
2.7
V
11
1010
2.8
V
11
1011
2.9
V
11
1100
3
V
11
1101
3.1
V
11
1110
3.2
V
11
1111
3.3
V
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8.6.8 Load Switch and LDO Control Register
Memory location 0x07h, Reset State: 0111 110x (BQ25121A)
Figure 32. Load Switch and LDO Control Register
7 (MSB)
6
1
R/W
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R
0 (LSB)
x
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. Load Switch and LDO Control Register
Bit
Field
Type
Reset
Description
EN_LS_LDO
R/W
0
0 – Disable LS/LDO
1 – Enable LS/LDO
B6
LS_LDO_4
R/W
1
LS/LDO Voltage: 1600 mV
B5
LS_LDO_3
R/W
1
LS/LDO Voltage: 800 mV
B4
LS_LDO_2
R/W
1
LS/LDO Voltage: 400 mV
B3
LS_LDO_1
R/W
1
LS/LDO Voltage: 200 mV
B2
LS_LDO_0
R/W
1
LS/LDO Voltage: 100 mV
B7 (MSB)
B1
B0 (LSB)
0
MRRESET_VIN
R/W
x
0 – Reset sent when MR Reset time is met
1 – Reset sent when MR Reset time is met and VUVLO + VSLP <
VIN < VOVP
LS_LDO Bits: Use LS_LDO bits to set the LS/LDO output. The LS/LDO voltage is calculated using the following equation: LS/LDO = 0.8 V
+ LS_LDOCODE x 100 mV. If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS VDROPOUT. The LS_LDO output can only be changed when the EN_LS_LDO and LSCTRL pin has disabled the output.
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8.6.9 Push-button Control Register
Memory location 0x08h, Reset State: 0110 10xx (BQ25121A)
Figure 33. Push-button Control Register
7 (MSB)
0
R/W
6
1
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
x
R
0 (LSB)
x
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. Push-button Control Register
Field
Type
Reset
Description
B7 (MSB)
Bit
MRWAKE1
R/W
0
MR Timer adjustment for WAKE1:
0 – 80 ms < MR
1 – 600 ms < MR
B6
MRWAKE2
R/W
1
MR Timer adjustment for WAKE2:
0 –1000 ms < MR
1 – 1500 ms < MR
B5
MRREC
R/W
1
0 – After Reset, device enters Ship mode
1 – After Reset, device enters Hi-Z Mode
B4
MRRESET_1
R/W
0
B3
MRRESET_0
R/W
1
MR Timer adjustment for reset:
00 – 5 s ± 20%
01 - 9 s ± 20%
10 - 11 s ± 20%
11 - 15 s ± 20%
B2
PGB_MR
R/W
0
0 – Output functions as PG
1 – Output functions as voltage shifted push-button (MR) input
B1
WAKE1
R
x
1 – WAKE1 status. Indicates when the device meets the WAKE1
conditions, and is cleared after I2C read.
B0 (LSB)
WAKE2
R
x
1 – WAKE2 status. Indicates when the device meets the WAKE2
conditions, and is cleared after I2C read.
44
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8.6.10 ILIM and Battery UVLO Control Register
Memory location 0x09h, Reset State: 0000 1010 (BQ25121A)
Figure 34. ILIM and Battery UVLO Control Register
7 (MSB)
0
Write
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. ILIM and Battery UVLO Control Register, Memory Location 1001
Bit
B7 (MSB)
Field
Type
Reset
Description
RESET
Write
only
0
Write:
1- Reset all registers to default values
0 – No effect
Read: Always get 0
B6
R/W
0
N/A
B5
INLIM_2
R/W
0
Input Current Limit: 200 mA
B4
INLIM_1
R/W
0
Input Current Limit: 100 mA
B3
INLIM_0
R/W
1
Input Current Limit: 50 mA
B2
BUVLO_2
R/W
0
B1
BUVLO_1
R/W
1
B0 (LSB)
BUVLO_0
R/W
0
000,
010:
011:
100:
101:
110:
111:
001: RESERVED
BUVLO = 3.0 V
BUVLO = 2.8 V
BUVLO = 2.6 V
BULVO = 2.4 V
BUVLO = 2.2 V
BUVLO = 2.2V
INLIM Bits: Use INLIM bits to set the input current limit. The I(INLIM) is calculated using the following equation: I(INLIM) = 50 mA +
I(INLIM)CODE x 50 mA. The default may be overridden by the external resistor on ILIM.
8.6.11 Voltage Based Battery Monitor Register
Memory location 0x0Ah, Reset State: 0xxx xxxx (BQ25121A)
Figure 35. Voltage Based Battery Monitor Register
7 (MSB)
0
R/W
6
x
R
5
x
R
4
x
R
3
x
R
2
x
R
1
x
R
0 (LSB)
x
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. Voltage Based Battery Monitor Register, Memory Location 1010
Bit
Field
Type
Reset
Description
VBMON_READ
R/W
0
Write 1 to initiate a new VBATREG reading. Read always 0.
B6
VBMON_RANGE_1
R
x
B5
VBMON_RANGE_0
R
x
11 –
10 –
01 –
00 –
B4
VBMON_TH_2
R
x
B3
VBMON_TH_1
R
x
B2
VBMON_TH_0
R
x
B1
R
x
N/A
B0 (LSB)
R
x
N/A
B7 (MSB)
90%
80%
70%
60%
to 100% of VBATREG
to 90% of VBATREG
to 80% of VBATREG
to 70% of VBATREG
111 – Above 8%
110 – Above 6%
011 – Above 4%
010 – Above 2%
001 – Above 0%
of VBMON_RANGE
of VBMON_RANGE
of VBMON_RANGE
of VBMON_RANGE
of VBMON_RANGE
The VBMON registers are used to determine the battery voltage. Before entering a low power state, the device will determine the voltage
level by starting at VBMON_RANGE 11 (90% to 100%), and if VBMON_TH of 000 is read, then it will move to VBMON_RANGE 10 (80% to
90%) and continue until a non 000 value of VBMON_TH is found. If this does not happen, then VBMON_RANGE and VBMON_TH will be
written with 00 000. The VBMON_READ bit can be used to initiate a new reading by writing a 1 to it. Example: A reading of 10 011
indicated a VBAT voltage of between 84% and 86% of the VBATREG setting.
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8.6.12 VIN_DPM and Timers Register
Memory location 0x0Bh, Reset State: 0100 1010 (BQ25121A)
Figure 36. VIN_DPM and Timers Register
7 (MSB)
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0 (LSB)
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. VIN_DPM and Timers Register
Bit
Field
Type
Reset
Description
VINDPM_ON
R/W
0
0 - enable VINDPM
1 - disable VINDPM
B6
VINDPM_2
R/W
1
Input V(IN_DPM) voltage: 400 mV
B5
VINDPM_1
R/W
0
Input V(IN_DPM) voltage: 200 mV
B4
VINDPM_0
R/W
0
Input V(IN_DPM) voltage: 100 mV
B3
2XTMR_EN
R/W
1
0 – Timer is not slowed at any time
1 – Timer is slowed by 2x when in any control other than CC or
CV
B2
TMR_1
R/W
0
B1
TMR_0
R/W
1
Safety Timer Time Limit
00 – 30 minute fast charge
01 – 3 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers
B7 (MSB)
B0 (LSB)
0
The VINDPM threshold is set using the following equation: VINDPM = 4.2 + VINDPM_CODE x 100 mV
46
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
A typical design is shown in Figure 37. This design uses the BQ25121A with external resistors for ILIM,
IPRETERM, and ISET. These are not needed if these values are set with a host controller through I2C
commands. This design also shows the TS resistors, which is also optional.
When powering up in default mode the battery voltage is the default for the part (4.2 V), the SYS output is the
default (2.5 V). External resistors set the charge current to 40 mA, the termination current to 10% (4 mA), and
the input current limit to 100 mA. If the I2C interface is used the part goes to the internal default settings until
changed by the host.
9.2 Typical Application
`
PG
Unregulated
Load
PMID
4.7 µF
IN
1 µF
VINLS
GND
SYS
2.2 µH
CD
MCU /
SYSTEM
SW
10 µF
SDA
SCL
HOST
LS / LDO
INT
1 µF
RESET
<100mA
Load
LSCTRL
BAT
MR
IPRETERM
ISET
1 µF
+
14.3 kŸ
NTC
-
TS
ILIM
14 kŸ
4.99 kŸ
499 Ÿ
BQ25121A
IN
4 kŸ
Figure 37. Typical Application Circuit
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Typical Application (continued)
9.2.1 Design Requirements
This application is for a low power system that has varying loads from less than 10 mA up to 300 mA. It must
work with a valid adaptor or USB power input. Below are some of the key components that are needed in normal
operation. For this example, the fast charge current is 50 mA, input current limit is 400 mA and the pre-charge
and termination current is 10% of the fast charge current.
• Supply voltage = 3.4 V to 20 V
• Fast charge current is default to 10 mA with ISET pin shorted to ground. To program the fast charge current,
connect an external resistor from ISET to ground.
• Input current limit is default to 100 mA with ILIM pin shorted to ground. To program the input current limit,
connect an external resistor from ILIM to ground.
• Termination current threshold is default to 2 mA with IPRETERM pin shorted to ground. To program the input
current limit, connect an external resistor from IPRETERM to ground.
• A 2.2-µH inductor is needed between SW pin and SYS pin for PWM output.
• TS- Battery temperature sense needs a NTC connected on TS pin.
9.2.2 Detailed Design Procedure
See Figure 37 for an example of the application diagram.
9.2.2.1 Default Settings
•
•
•
•
•
•
•
•
Connect ISET, ILIM and IPRETERM pins to ground to program fast charge current to 10 mA, input current
limit to 100 mA and pre-charge/termination current to 2 mA.
BAT_UVLO = 3 V.
VSYS = 2.5 V
LS/LDO is LS
VBREG = 4.2 V
VIN_DPM is enabled and VIN_DPM Threshold = 4.6 V.
Safety Timer = 3 hr
If the function is not needed, connect TS to the center tab of the resistor divider between VIN and the ground.
(pull up resistor = 14 kΩ, pull down resistor = 14.3 kΩ)
9.2.2.2 Choose the Correct Inductance and Capacitance
Refer to the Buck (PWM) Output section for the detailed procedure to determine the optimal inductance and
capacitance for the buck output.
9.2.2.3 Calculations
9.2.2.3.1 Program the Fast Charge Current (ISET)
RISET = KISET/ICHG
(10)
KISET = 200 AΩ from the Specifications table
RISET = 200 AΩ / 0.05 A = 4 kΩ
(11)
Select the closest standard value, which in this case is 4.99 kΩ. Connect this resistor between ISET pin and
GND.
9.2.2.3.2 Program the Input Current Limit (ILIM)
RILIM = KILIM/II_MAX
(12)
KILIM = 200 AΩ from the Specifications table
RILIM = 200 AΩ / 0.4 A = 500 Ω
(13)
Select the closest standard value, which in this case is 499 Ω. Connect this resistor between ILIM pin and GND.
48
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Typical Application (continued)
9.2.2.3.3 Program the Pre-charge/termination Threshold (IPRETERM)
According to Table 3, the RIPRETERM is 4990 Ω for 10% termination threshold. Therefore, connect a 4.99-kΩ
resistor between IPRETERM pin and GND.
9.2.2.3.4 TS Resistors (TS)
The voltage at TS is monitored to determine that the battery is at a safe temperature during charging. This device
uses JEITA temperature profile which has four temperature thresholds. Refer to Specifications for the detailed
thresholds number.
The TS circuit is shown in Figure 18. The resistor values can be calculated using Equation 1 and Equation 2.
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Typical Application (continued)
9.2.3 Application Performance Curves
5 V/div
5 V/div
10 mA/div
500 mV/div
1 V/div
5 V/div
5 V/div
5 V/div
9.2.3.1 Charger Curves
Time 100 ms/div
Time 4 ms/div
Figure 39. Power Supply Connected to VIN
2 V/div
500 mV/div
10 mA/div
100 mA/div
500 mV/div
100 mA/div
2 V/div
500 mV/div
Figure 38. Battery Connected to V(BAT)
Time 4 ms/div
Time 4 ms/div
Figure 41. Exiting DPPM Mode
2 V/div
500 mV/div
20 mA/div
100 mA/div
20 mA/div
100 mA/div
2 V/div
500 mV/div
Figure 40. Entering DPPM Mode
Time 4 ms/div
Time 4 ms/div
Figure 42. Entering Battery Supplement Mode
50
Figure 43. Exiting Battery Supplement Mode
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2 V/div
500 mV/div
10 mA/div
20 mA/div
10 mA/div
100 mA/div
2 V/div
500 mV/div
Typical Application (continued)
Time 4 ms/div
Time 2 ms/div
Figure 44. Charger On/Off Using CD
Figure 45. OVP Fault
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Typical Application (continued)
100%
100%
90%
90%
80%
80%
Efficiency (%)
Efficiency (%)
9.2.3.2 SYS Output Curves
70%
60%
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
50%
40%
1E-6
1E-5
TA = 25°C
0.0001
0.001
0.01
Load Current (A)
70%
60%
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
50%
40%
1E-6
0.10.2 0.5
VSYS = 1.2 V
TA = 25°C
100%
100%
90%
90%
80%
80%
70%
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
50%
40%
1E-6
1E-5
TA = 25°C
0.0001
0.001
0.01
Load Current (A)
D004
VSYS = 1.5 V
60%
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
50%
40%
1E-6
0.10.2 0.5
1E-5
D007
VSYS = 1.8 V
TA = 25°C
0.0001
0.001
0.01
Load Current (A)
0.10.2 0.5
D010
VSYS = 2.5 V
Figure 49. 2.5 VSYS System Efficiency
100%
1.238
1.228
SYS Output Voltage (V)
90%
Efficiency (%)
0.10.2 0.5
70%
Figure 48. 1.8 VSYS System Efficiency
80%
70%
60%
3.6 V BAT
3.8 V BAT
4.2 V BAT
50%
40%
1E-6
1E-5
TA = 25°C
0.0001
0.001
0.01
Load Current (A)
1.218
1.208
1.198
1.188
2.7 V
3V
3.6 V
3.8 V
4.2 V
1.178
1.168
0.10.2 0.5
1.158
1E-6
1E-5
D013
VSYS = 3.3 V
TA = 25°C
Figure 50. 3.3 VSYS System Efficiency
52
0.0001
0.001
0.01
Load Current (A)
Figure 47. 1.5 VSYS System Efficiency
Efficiency (%)
Efficiency (%)
Figure 46. 1.2 VSYS System Efficiency
60%
1E-5
D001
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0.0001
0.001
0.01
Load Current (A)
0.1
0.5
D003
VSYS = 1.2 V
Figure 51. 1.2 VSYS Load Regulation
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Typical Application (continued)
1.5475
1.857
1.837
SYS Output Voltage (V)
SYS Output Voltage (V)
1.5275
1.5075
1.4875
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
1.4675
1.4475
1E-6
1E-5
1.817
1.797
1.777
2.7 V BAT
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
1.757
0.0001
0.001
0.01
Load Current (A)
TA = 25°C
0.1
1.737
1E-6
0.5
1E-5
D006
VSYS = 1.5 V
0.0001
0.001
0.01
Load Current (A)
TA = 25°C
Figure 52. 1.5 VSYS Load Regulation
0.1
0.5
D009
VSYS = 1.8 V
Figure 53. 1.8 VSYS Load Regulation
3.3845
2.5725
SYS Output Voltage (V)
SYS Output Voltage (V)
2.5525
2.5325
2.5125
2.4925
2.4725
2.4525
3.0 V BAT
3.6 V BAT
3.8 V BAT
4.2 V BAT
2.4325
2.4125
1E-6
1E-5
3.3345
3.2845
3.2345
3.8 V BAT
4.2 V BAT
0.0001
0.001
0.01
Load Current (A)
TA = 25°C
0.1
3.1845
1E-6
0.5
VSYS = 2.5 V
0.0001
0.001
0.01
Load Current (A)
TA = 25°C
Figure 54. 2.5 VSYS Load Regulation
0.1
0.5
D015
VSYS = 3.3 V
Figure 55. 3.3 VSYS Load Regulation
1.238
1.5475
1 PA
10 PA
100 PA
1.228
1 mA
10 mA
100 mA
1 PA
10 PA
100 PA
1.5275
Vsys Voltage (V)
1.218
Vsys Voltage (V)
1E-5
D012
1.208
1.198
1.188
1 mA
10 mA
100 mA
1.5075
1.4875
1.178
1.4675
1.168
1.158
1.4475
3
3.2
TA = 25°C
3.4
3.6
3.8
VBAT Voltage (V)
4
4.2
3
3.2
D002
VSYS = 1.2 V
TA = 25°C
Figure 56. 1.2 VSYS Line Regulation
3.4
3.6
3.8
VBAT Voltage (V)
4
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D005
VSYS = 1.5 V
Figure 57. 1.5 VSYS Line Regulation
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Typical Application (continued)
1.857
2.5725
2.5525
Vsys Voltage (V)
Vsys Votage (V)
1.837
1.817
1.797
1.777
2.5325
2.5125
2.4925
2.4725
2.4525
1.757
1 PA
10 PA
100 PA
1 mA
10 mA
100 mA
1 PA
10 PA
100 PA
2.4325
300ma
1.737
1 mA
10 mA
100 mA
2.4125
3
3.2
TA = 25°C
3.4
3.6
3.8
VBAT Voltage (V)
4
4.2
3
3.2
D008
VSYS = 1.8 V
TA = 25°C
Figure 58. 1.8 VSYS Line Regulation
3.4
3.6
3.8
VBAT Voltage (V)
4
4.2
D011
VSYS = 2.1 V
Figure 59. 2.1 VSYS Line Regulation
3.3845
1400
1200
Frequency, FSW (kHz)
3.2845
3.2345
1 PA
10 PA
100 PA
800
600
400
1 mA
10 mA
100 mA
200
5 V VBAT
4.2 V VBAT
4
VBAT Voltage (V)
0
4.2
50
D014
2.5 V VBAT
100
150
200
Load Current (mA)
250
300
D023
VSYS = 3.3 V
Figure 61. 1.8 VSYS Switching Frequency vs Load Current
500 mA/div
10 mA/div
SW
2 V/div
2 V/div
SW
500 mA/div
Figure 60. 3.3 VSYS Line Regulation
5 V/div
TA = 25°C
Time 40 ms/div
Time 40 ms/div
ILOAD = 10 µA
ILOAD = 100 mA
Figure 62. Light Load Operation Showing SW
54
3.6 V VBAT
3 V VBAT
0
3.1845
3.8
5 V/div
1000
10 mA/div
Vsys Votage(V)
3.3345
Figure 63. Light Load Operation Showing SW
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5 V/div
2 V/div
500 mA/div
500 mA/div
SW
10 mA/div
2 V/div
SW
10 mA/div
5 V/div
Typical Application (continued)
Time 40 ms/div
Time 2 ms/div
ILOAD = 1 mA
ILOAD = 10 mA
2 V/div
SW
500 mA/div
200 mA/div
2 V/div
500 mA/div
5 V/div
Figure 65. Light Load Operation Showing SW
SW
100 mA/div
5 V/div
Figure 64. Light Load Operation Showing SW
Time 400 ns/div
Time 400 ns/div
ILOAD = 100 mA
ILOAD = 200 mA
50 mV/div
SW
500 mA/div
50 mV/div
2 V/div
500 mA/div
5 V/div
Figure 67. Light Load Operation Showing SW
SW
200 mA/div
5 V/div
Figure 66. Light Load Operation Showing SW
Time 4 ms/div
Time 400 ns/div
ILOAD = 300 mA
VSYS = 1.2 V
Figure 68. Light Load Operation Showing SW
Figure 69. 1.2 VSYS Load Transient, 0 to 50 mA
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50 mV/div
5 V/div
500 mA/div
500 mA/div
SW
50 mV/div
50 mV/div
SW
50 mV/div
5 V/div
Typical Application (continued)
Time 4 ms/div
Time 4 ms/div
VSYS = 1.8 V
VSYS = 2.1 V
500 mA/div
500 mA/div
SW
50 mV/div
5 V/div
Figure 71. 2.1 VSYS Load Transient, 0 to 50 mA
50 mV/div
50 mV/div
SW
50 mV/div
5 V/div
Figure 70. 1.8 VSYS Load Transient, 0 to 50 mA
Time 4 ms/div
Time 4 ms/div
VSYS = 2.5 V
VSYS = 3.3 V
500 mA/div
500 mA/div
SW
50 mV/div
5 V/div
Figure 73. 3.3 VSYS Load Transient, 0 to 50 mA
200 mV/div
50 mV/div
SW
200 mV/div
5 V/div
Figure 72. 2.5 VSYS Load Transient, 0 to 50 mA
Time 4 ms/div
Time 4 ms/div
VSYS = 1.2 V
VSYS = 1.8 V
Figure 74. 1.2 VSYS Load Transient, 0 to 200 mA
56
Figure 75. 1.8 VSYS Load Transient, 0 to 200 mA
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50 mV/div
5 V/div
500 mA/div
500 mA/div
SW
200 mV/div
50 mV/div
SW
200 mV/div
5 V/div
Typical Application (continued)
Time 4 ms/div
Time 4 ms/div
VSYS = 2.1 V
VSYS = 2.5 V
5 V/div
Figure 77. 2.5 VSYS Load Transient, 0 to 200 mA
1 V/div
500 mA/div
2 V/div
50 mV/div
SW
200 mV/div
5 V/div
Figure 76. 2.1 VSYS Load Transient, 0 to 200 mA
Time 4 ms/div
Time 1 ms/div
VSYS = 3.3 V
Figure 79. Startup Showing SS on SYS in PWM Mode
500 mA/div
2 V/div
2 V/div
5 V/div
Figure 78. 3.3 VSYS Load Transient, 0 to 200 mA
Time 20 ms/div
Figure 80. Short Circuit and Recovery for SYS
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Typical Application (continued)
20 mA/div
50 mA/div
2 V/div
2 V/div
2 V/div
2 V/div
9.2.3.3 Load Switch and LDO Curves
Time 20 ms/div
Time 400 ms/div
Figure 81. Short Circuit and Recovery for LS
50 mV/div
5 V/div
20 mV/div
20 mV/div
50 mV/div
5 V/div
Figure 82. Startup Showing SS on LS/LDO Output
Time 4 ms/div
Time 4 ms/div
VSLSDO = 0.8 V
VSLSDO = 1.2 V
50 mV/div
5 V/div
Figure 84. 1.2 VLSLDO Load Transient, 0 to 10 mA
20 mV/div
20 mV/div
50 mV/div
5 V/div
Figure 83. 0.8 VLSLDO Load Transient, 0 to 10 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 1.8 V
VSLSDO = 2.5 V
Figure 85. 1.8 VLSLDO Load Transient, 0 to 10 mA
58
Figure 86. 2.5 VLSLDO Load Transient, 0 to 10 mA
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50 mV/div
100 mV/div
20 mV/div
50 mV/div
5 V/div
5 V/div
Typical Application (continued)
Time 4 ms/div
Time 4 ms/div
VSLSDO = 3.3 V
VSLSDO = 0.8 V
Figure 87. 3.3 VLSLDO Load Transient, 0 to 10 mA
50 mV/div
100 mV/div
100 mV/div
50 mV/div
5 V/div
5 V/div
Figure 88. 0.8 VLSLDO Load Transient, 0 to 100 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 1.8 V
VSLSDO = 1.2 V
Figure 90. 1.8 VLSLDO Load Transient, 0 to 100 mA
50 mV/div
100 mV/div
100 mV/div
50 mV/div
5 V/div
5 V/div
Figure 89. 1.2 VLSLDO Load Transient, 0 to 100 mA
Time 4 ms/div
Time 4 ms/div
VSLSDO = 2.5 V
VSLSDO = 3.3 V
Figure 91. 2.5 VLSLDO Load Transient, 0 to 100 mA
Figure 92. 3.3 VLSLDO Load Transient, 0 to 100 mA
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Typical Application (continued)
200 mA/div
2 V/div
20 mA/div
2 V/div
2 V/div
2 V/div
9.2.3.4 LS/LDO Output Curves
Time 400 ms/div
Time 20 ms/div
Figure 93. Startup Showing SS on LS/LDO in LDO Mode
60
Figure 94. Short Circuit and Recovery for LDO
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Typical Application (continued)
2 V/div
500 mV/div
500 mV/div
2 V/div
500 mV/div
2 V/div
2 V/div
500 mV/div
9.2.3.5 Timing Waveforms Curves
Time 10 ms/div
Time 2 ms/div
500 mV/div
2 V/div
Figure 96. Show PG and INT Timing (VIN Removal)
5 V/div
2 V/div
5 V/div
2 V/div
500 mV/div
2 V/div
Figure 95. Show PG and INT Timing (VIN Insertion)
Time 400 ms/div
Time 400 ms/div
Time 200 ms/div
Wake1 = 500 ms
Wake2 = 1 s
2 V/div
2 V/div
Figure 98. PG Functions as Shifted MR Output
2 V/div
500 mV/div
2 V/div
500 mV/div
2 V/div
2 V/div
Figure 97. PG Functions as Shifted MR Output
Time 200 ms/div
Wake1 = 50 ms
Figure 99. Show MR Timing
Wake2 = 1.5 s
Figure 100. Show MR Timing
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2 V/div
2 V/div
2 V/div
500 mV/div
2 V/div
500 mV/div
2 V/div
2 V/div
Typical Application (continued)
Time 1 s/div
Time 1 s/div
RESET = 4 s
RESET = 8 s
Figure 102. RESET Timing
2 V/div
2 V/div
500 mV/div
2 V/div
500 mV/div
2 V/div
2 V/div
2 V/div
Figure 101. RESET Timing
Time 2 s/div
Time 2 s/div
RESET = 14 s
Figure 103. RESET Timing
Figure 104. RESET Timing and Enter Ship Mode
10 Power Supply Recommendations
It is recommended to use a power supply that is capable of delivering 5 V at the input current limit set by the
BQ25121A.
62
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11 Layout
11.1 Layout Guidelines
•
•
•
•
Keep the core components of the system close to each other and the device.
Keep the PMID, IN, and SYS caps as close to their respective pins as possible. Place the bypass caps for
PMID, SYS, and LSLDO close to the pins.
Place the GNDs of the PMID and IN caps close to each other.
Don’t route so the power planes are interrupted.
11.2 Layout Example
Figure 105. BQ25121A Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
DCS-Control, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
64
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ25121AYFPR
ACTIVE
DSBGA
YFP
25
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25121A
BQ25121AYFPT
ACTIVE
DSBGA
YFP
25
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
BQ25121A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-May-2018
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
BQ25121AYFPR
DSBGA
YFP
25
3000
180.0
8.4
BQ25121AYFPT
DSBGA
YFP
25
250
180.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.65
2.65
0.69
4.0
8.0
Q1
2.65
2.65
0.69
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ25121AYFPR
DSBGA
YFP
25
3000
182.0
182.0
20.0
BQ25121AYFPT
DSBGA
YFP
25
250
182.0
182.0
20.0
Pack Materials-Page 2
D: Max = 2.56 mm, Min = 2.5 mm
E: Max = 2.498 mm, Min =2.438 mm
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