Siemens HYB3165405TL-50 16m x 4-bit dynamic ram Datasheet

16M x 4-Bit Dynamic RAM
(4k & 8k Refresh, EDO-version)
HYB 3164405J/T(L) -50/-60
HYB 3165405J/T(L) -50/-60
Preliminary Information
•
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•
•
•
•
•
•
•
•
•
16 777 216 words by 4-bit organization
0 to 70 ˚C operating temperature
Fast access and cycle time
RAS access time:
50 ns (-50 version)
60 ns (-60 version)
Cycle time:
84 ns (-50 version)
104 ns (-60 version)
CAS access time:
13 ns ( -50 version)
15 ns ( -60 version)
Hyper page mode (EDO) cycle time
20 ns (-50 version)
25 ns (-60 version)
Single + 3.3 V (± 0.3V) power supply
Low power dissipation
max. 396 active mW ( HYB 3164405J/T(L)-50)
max. 360 active mW ( HYB 3164405J/T(L)-60)
max. 504 active mW ( HYB 3165405J/T(L)-50)
max. 432 active mW ( HYB 3165405J/T(L)-60)
7.2 mW standby (TTL)
720 W standby (MOS)
14.4 mW Self Refresh (L-version only)
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh modes
Hyper page mode (EDO) capability
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164405J/T(L))
4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165405J/T(L))
Plastic Package:
P-SOJ-34-1
500 mil
HYB 3164(5)400J
P-TSOPII-34-1 500 mil
HYB 3164(5)400T
Semiconductor Group
89
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
This HYB3164(5)405 is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is
fabricated in SIEMENS/IBM most advanced first generation 64Mbit CMOS silicon gate process
technology. The circuit and process design allow this device to achieve high performance and low
power dissipation. The HYB3164(5)405 operates with a single 3.3 +/-0.3V power supply and
interfaces with either LVTTL or LVCMOS levels. Multiplexed address inputs permit the HYB
3164(5)400J/T to be packaged in a 500mil wide SOJ-34 or TSOP-34 plastic package. These
packages provide high system bit densities and are compatible with commonly used automatic
testing and insertion equipment.The HYB3164(5)405TL parts have a very low power „sleep mode“
supported by Self Refresh.
Ordering Information
Type
Ordering
Code
Package
HYB 3164405J-50
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
HYB 3164405J-60
on request
P-SOJ-34-1
500 mil DRAM (access time 60 ns)
HYB 3164405T-50
on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3164405T-60
on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
HYB 3164405TL-50 on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3164405TL-60 on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
HYB 3165405J-50
on request
P-SOJ-34-1
500 mil DRAM (access time 50 ns)
HYB 3165405J-60
on request
P-SOJ-34-1
500 mil DRAM (access time 60 ns)
HYB 3165405T-50
on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3165405T-60
on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
HYB 3165405TL-50 on request
P-TSOPII-34-1
500 mil DRAM (access time 50 ns)
HYB 3165405TL-60 on request
P-TSOPII-34-1
500 mil DRAM (access time 60 ns)
Pin Names
A0-A12
Address Inputs for HYB 3164405J/T(L)
A0-A11
Address Inputs for HYB 3165405J/T(L)
RAS
Row Address Strobe
OE
Output Enable
I/O1-I/O4
Data Input/Output
CAS
Column Address Strobe
WRITE
Read/Write Input
Vcc
Power Supply ( + 3.3V)
Vss
Ground
Semiconductor Group
90
Descriptions
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
P-SOJ-34-1 (500 mil)
P-TSOPII-34-1 (500 mil)
Pin Configuration
Semiconductor Group
91
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
RAS
CAS
WRITE
OE
ROW
ADDR
COL
ADDR
I/O1I/O4
Standby
H
H-X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L
L
H-L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H-L
L-H
ROW
COL
Data Out, Data In
Hyper Page Mode Read 1st Cycle
L
H-L
H
L
ROW
COL
Data Out
2nd Cycle
L
H-L
H
L
n/a
COL
Data Out
Hyper Page Mode Write 1st Cycle
L
H-L
L
X
ROW
COL
Data In
2nd Cycle
L
H-L
L
X
n/a
COL
Data In
Hyper Page Mode RMW 1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data Out, Data In
2st Cycle
L
H-L
H-L
L-H
n/a
COL
Data Out, Data In
L
H
X
X
ROW
n/a
High Impedance
CAS-before-RAS refresh
H-L
L
H
X
X
n/a
High Impedance
Test Mode Entry
H-L
L
L
X
X
n/a
High Impedance
READ
L-H-L
L
H
L
ROW
COL
Data Out
WRITE
L-H-L
L
L
X
ROW
COL
Data In
H-L
L
H
X
X
X
High Impedance
RAS only refresh
Hidden Refresh
Self Refresh
(L-version only)
Semiconductor Group
92
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3164405J/T(L)
Semiconductor Group
93
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Block Diagram for HYB 3165405J/T(L)
Semiconductor Group
94
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Absolute Maximum Ratings
Operating temperature range..............................................................................................0 to 70 ˚C
Storage temperature range.........................................................................................– 55 to 150 ˚C
Input/output voltage..................................................................................-0.5 to min (Vcc+0.5,4.6) V
Power supply voltage....................................................................................................-0.5V to 4.6 V
Power dissipation......................................................................................................................1.0 W
Data out current (short circuit)..................................................................................................50 mA
Note
Stresses above those listed under „Absolute Maximum Ratings“ may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may effect device
reliability.
DC Characteristics
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
min.
max.
Unit Note
Input high voltage
VIH
2.0
Vcc+0.3
V
1)
Input low voltage
VIL
– 0.3
0.8
V
1)
Output high voltage (LVTTL)
Output „H“ level voltage (Iout = -2mA)
VOH
2.4
–
V
Output low voltage (LVTTL)
Output „L“level voltage (Iout = +2mA)
VOL
–
0.4
V
Output high voltage (LVCMOS)
Output „H“ level voltage (Iout = -100uA)
VOH
Vcc-0.2 -
V
Ouput low voltage (LVCMOS)
Output „L“ level voltage (Iout = +100uA)
VOL
-
0.2
V
Input leakage current,any input
II(L)
–2
2
µA
IO(L)
–2
2
µA
–
–
110 (140) mA
100 (120) mA
2) 3) 4)
–
2
–
(0 V < Vin < Vcc , all other pins = 0 V
Output leakage current
(DO is disabled, 0 V < Vout < Vcc )
ICC1
Average Vcc supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby Vcc supply current
ICC2
(RAS=CAS= Vih)
Semiconductor Group
95
mA
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
DC Characteristics (cont’d)
TA = 0 to 70 ˚C, VSS = 0 V, VCC = 3.3 V ± 0.3 V, (values in brackets for HYB 3165405J/T)
Parameter
Symbol
Limit Values
Unit Note
min.
max.
–
–
110 (140) mA
100 (120) mA
2) 4)
–
–
115 (150) mA
100 (120) mA
2) 3) 4)
ICC5
–
200
–
Average Vcc supply current, during CAS-before- ICC6
RAS refresh mode:
-50 ns version
-60 ns version
–
–
110 (140) mA
100 (120) mA
–
400
Average Vcc supply current, during RAS-only
ICC3
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling: CAS = VIH: tRC = tRC min.)
Average Vcc supply current, during
hyperpage mode (EDO):
ICC4
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling: tHPC=tHPC min.)
Standby Vcc supply current
A
(RAS=CAS= Vcc-0.2V)
2) 4)
(RAS, CAS cycling: tRC = tRC min.)
ICC7
Self Refresh Current (L-version only)
A
Average Power Supply Current during Self Refresh.
(CBR cycle with tRAS>TRASSmin, CAS held low,
WE = Vcc-0.2V, Address and Din=Vcc-0.2V or 0.2V)
Capacitance
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A11,A12)
CI1
–
5
pF
Input capacitance (RAS, CAS, WRITE, OE)
CI2
–
7
pF
I/O capacitance (I/O1-I/O4)
CIO
–
7
pF
Semiconductor Group
96
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
AC Characteristics 5)6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
tRC
84
–
104
–
ns
RAS precharge time
tRP
30
–
40
–
ns
RAS pulse width
tRAS
50
100k
60
100k
ns
CAS pulse width
tCAS
8
10k
10
10k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
8
–
10
–
ns
RAS to CAS delay time
tRCD
12
37
14
45
ns
RAS to column address delay time
tRAD
10
25
12
30
ns
RAS hold time
tRSH
8
10
–
ns
CAS hold time
tCSH
45
50
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
Refresh period for HYB3164405
tREF
–
128
–
128
ms
Refresh period for HYB3165405
tREF
–
64
–
64
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
25
–
30
ns
8,10
OE access time
tOEA
–
13
–
15
ns
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to tRRH
RAS
0
–
0
–
ns
11
7
Read Cycle
Semiconductor Group
97
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
ns
12
Output buffer turn-off delay from OE
tOEZ
0
13
0
15
ns
12
Data to CAS low delay
tDZC
0
–
0
–
ns
13
Data to OE low delay
tDZO
0
–
0
–
ns
13
CAS high to data delay
tCDD
13
–
15
–
ns
14
OE high to data delay
tODD
13
–
15
–
ns
14
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
7
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
8
–
10
–
ns
Write command to CAS lead time
tCWL
8
–
10
–
ns
Data setup time
tDS
0
–
0
–
ns
16
Data hold time
tDH
7
–
10
–
ns
16
Read-write cycle time
tRWC
111
–
135
–
ns
RAS to WE delay time
tRWD
67
–
79
–
ns
15
CAS to WE delay time
tCWD
30
–
34
–
ns
15
Column address to WE delay time
tAWD
42
–
49
–
ns
15
OE command hold time
tOEH
7
–
10
–
ns
Hyper page mode (EDO) cycle time
tHPC
20
–
25
–
ns
CAS precharge time
tCP
8
–
10
–
ns
Access time from CAS precharge
tCPA
–
27
–
35
ns
Output data hold time
tCOH
5
–
5
–
ns
RAS pulse width in hyper page mode
tRAS
50
200k
60
200k
ns
Write Cycle
15
Read-modify-Write Cycle
Hyper Page Mode (EDO) Cycle
Semiconductor Group
98
7
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
CAS precharge to RAS Delay
tRHCP
27
–
35
–
ns
OE pulse width
tOEP
7
–
10
–
ns
OE hold time from CAS high
tOEHC
7
–
10
–
ns
WE pulse width to output disable at CAS tWPZ
high
7
–
10
–
ns
Output buffer turn-off delay from WE
tWPZ
0
10
0
10
ns
Hyper page mode (EDO) read-write
cycle time
tPRWC
51
–
66
–
ns
CAS precharge to WE
tCPWD
41
–
49
–
ns
CAS setup time
tCSR
5
–
5
–
ns
CAS hold time
tCHR
8
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
8
–
10
–
ns
Write hold time referenced to RAS
tWRH
8
–
10
–
ns
tCPT
35
–
40
–
ns
tRASS
100k
_
100k
_
ns
17
RAS precharge time during self refresh tRPS
84
_
104
_
ns
17
CAS hold time during self refresh
-50
_
-50
_
ns
17
Hyper Page Mode (EDO) Readmodify-Write Cycle
CAS before RAS refresh cycle
CAS-before-RAS counter test cycle
CAS precharge time (CAS-before-RAS
counter test cycle)
Self Refresh Cycle
RAS pulse width during self refresh
Semiconductor Group
tCHS
99
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 ˚C,VCC = 3.3 V ± 0.3V , tT = 2 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
Test Mode
Write command setup time
tWTS
10
–
10
–
ns
18)
Write command hold time
tWTH
10
–
10
–
ns
18)
Semiconductor Group
100
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Notes:
1) All voltages are referenced to VSS.
Vih may overshoot to VV + 0.2V for pulse widths of < 4ns with 3.3V. Vil may undershoot to -2.0V for pulse width
< 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
2) ICC1, ICC3, ICC4 and ICC6 and ICC7 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = Vil.In the case of ICC4 it can be changed once or less
during a hyper page mode cycle ( thpc).
5) An initial pause of 100 s is required after power-up followed by 8 RAS-only-refresh cycles, before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS
initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Also, transition times are
measured between VIH and VIL.
8) Measured with the specified current load and 100 pF at Voh = 2.0 V and Vol = 0.8 V.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11) Either tRCH or tRRH must be satisfied for a read cycle.
12) tOFF (max.) and tOEZ (max.) define the time at which the outputs achieve the open-circuit condition and are
not referenced to output voltage levels.
13) Either tDZC or tDZO must be satisfied.
14) Either tCDD or tODD must be satisfied.
15) tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin
will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD
(min.), tAWD > tAWD (min.) and tCPWD > tCPWD (min.) , the cycle is a read-write cycle and I/O pins will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition
of the I/O pins (at access time) is indeterminate.
16) These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in
Read-Modify-Write cycles.
17) When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
operation:
If row addresses are being refresh in an evenly distributed manner over the refresh interval using CBR refresh
cycles, then only one CBR cycle must be performed immediatly after exit from Self Refresh.
If row addresses are being refresh in any other manner (ROR - Distributed/Burst or CBR-Burst) over the
refresh interval, then a full set of row refreshed must be performed immediately before entry to and immediatey
after exit from Self Refresh
18) In a Test Mode Read Cycle, the value of trac, taa, tcac and tcpa are delayed by 5 ns from the specified value.
These parameters must be adjusted in Test Mode cycles by adding 5ns to the specified value. Associated
timings must be adjusted by 5 ns.
Semiconductor Group
101
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
V
IH
VIL
tRAD
tASR
Address
V
IH
VIL
OE
I/O
(Inputs)
tRAL
tCAH
tASC
tASR
Column
Row
Row
tRCH
tRAH
WE
tCRP
tRSH
tCAS
tRCD
CAS
tRP
tRCS
tRRH
V
IH
VIL
tAA
tOEA
V
IH
VIL
tCDD
tDZC
tODD
tDZO
V
IH
tCAC
VIL
tCLZ
V
OH
I/O
(Outputs) V
Hi Z
tOFF
tOEZ
Valid Data Out
Hi Z
OL
tRAC
WL1
“H” or “L”
Read Cycle
Semiconductor Group
102
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
tRCD
tRSH
tCAS
V
IH
CAS
VIL
tRAD
tASR
Address
V
IH
OE
Row
tCAH
tASR
tCWL
tWCS
V
IH
.
Row
Column
VIL
t WP
VIL
tWCH
tRWL
V
IH
VIL
tDS
I/O
(Inputs)
tCRP
tRAL
tASC
tRAH
WE
tRP
tDH
V
IH
Valid Data In
VIL
V
OH
I/O
(Outputs) V
Hi Z
OL
WL2
“H” or “L”
Write Cycle (Early Write)
Semiconductor Group
103
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
RAS
V
IH
VIL
tCSH
tRCD
VIL
tRAD
tASR
V
IH
Address V
IL
tCAH
tASC
Row
tRAL
tASR
tCWL
tRWL
tWP
V
IH
VIL
tOEH
OE
V
IH
tODD
tDS
tOEZ
VIL
tDZO
tDZC
I/O
(Inputs)
tDH
V
IH
Valid Data
VIL
tCLZ
tOEA
V
OH
I/O
(Outputs) V
Hi-Z
Hi-Z
OL
“H” or “L”
WL3
Write Cycle (OE Controlled Write)
Semiconductor Group
104
.
Row
Column
tRAH
WE
tCRP
tRSH
tCAS
V
IH
CAS
tRP
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRWC
tRAS
RAS
V
IH
tCSH
VIL
tRSH
tCAS
tRCD
V
IH
CAS
tCAH
V
IH
VIL
tASR
tASC
tASR
Row
Column
Row
tCWL
tRWL
tAWD
tRAD
tCWD
tRWD
tWP
V
IH
WE
tCRP
VIL
tRAH
Address
tRP
VIL
tAA
tRCS
tOEH
tOEA
V
IH
OE
VIL
tDS
tDZO
tDZC
I/O
(Inputs)
tDH
V
IH
Valid
Data in
VIL
tCLZ
tODD
tCAC
tOEZ
V
OH
I/O
(Outputs) VOL
Data
Out
tRAC
“H” or “L”
WL4
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
105
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
RAS
V
IH
tRHCP
tRCD
VIL
tRSH
tHPC
tCRP
tCAS
tCP
tCAS
tCRP
tCAS
V
IH
CAS
VIL
tCSH
tASR
Address
tRAH tASC
tRAL
tCAH
V
IH
VIL
Row
Column 1
tASC tCAH
tASC tCAH
Column 2
Column N
tRAD
tRRH
tRCH
tRCS
WE
VIH
VIL
tAA
tCPA
tOES
OE
tAA
tCPA
tOFF
tOEA
V
OH
V
tCAC
tCAC
OL
tRAC
tAA
tCAC
tOEZ
tCOH
tCLZ
V
I/O
IH
(Output) V
IL
Data Out
1
Data Out
2
Data Out
N
WL5
“H” or “L”
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
tCOH
106
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
IH
RAS
tRHCP
tRCD
VIL
tRSH
tHPC
tCRP
tCAS
tCAS
tCP
tCRP
tCAS
V
IH
CAS
VIL
tCSH
tASR
Address
tRAH tASC
tRAL
tCAH
V
IH
VIL
Row
Column 1
tASC tCAH
tASC tCAH
Column 2
Column N
tRAD
tRRH
tRCH
tRCS
WE
VIH
tCAC
tAA
VIL
tOES
OE
tOEA
V
OH
V
OL
tRAC
tAA
tCAC
tCAC
tAA
tCPA
tOEHC
tOEP
tCPA
tOFF
tOEHC
tOEA
tOEP tOEA
tOEZ
tOEZ
tOEZ
tCLZ
V
I/O
IH
(Output) V
IL
Data Out
1
Data Out
2
Data Out
N
WL6
“H” or “L”
Hyper Page Mode (EDO) Read Cycle (OE Control)
Semiconductor Group
107
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
IH
RAS
tRHCP
tRCD
VIL
tRSH
tHPC
tCRP
tCAS
tCAS
tCP
tCRP
tCAS
V
IH
CAS
VIL
tCSH
tASR
Address
tRAH tASC
tRAL
tCAH
V
IH
VIL
Row
Column 1
tASC tCAH
tASC tCAH
Column 2
Column N
tRAD
tRCS
WE
tAA
tRCH
tRCS
tRRH
tRCH
tRCH
tRCS
VIH
VIL
tWPZ
tOES
OE
tAA
tCPA
tWPZ
tCAC
tOFF
tCPA
tOEA
V
OH
V
tCAC
OL
tRAC
tAA
tCAC
tOEZ
tWHZ
tWHZ
tCLZ
V
I/O
IH
(Output) V
IL
Data Out
1
Data Out
2
Data Out
N
WL7
“H” or “L”
Hyper Page Mode (EDO) Read Cycle (WE Control)
Semiconductor Group
108
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
IH
RAS
tRHCP
tRCD
VIL
tRSH
tHPC
tCRP
tCAS
tCAS
tCP
tCRP
tCAS
V
IH
CAS
VIL
tASR
Address
tRAL
tCSH
V
IH
VIL
tRAH tASC
Row
Addr
tCAH
tASC tCAH
tASC tCAH
Column 2
Column N
Column 1
tRAD
tWCS
tCWL
tCWL
tWCH tWCS
tWCH
tWP
tWP
WE
OE
VIH
tRWL
tCWL
tWCS
tWCH
tWP
VIL
V
OH
V
OL
tDS
tDH
tDS
tDH
tDS
tDH
V
IH
I/O (Input) V
IL
Data In 1
Data In 2
“H” or “L”
WL8
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
Data In N
109
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
V
IH
RAS
tRCD
VIL
tRSH
tHPC
tCRP
tCAS
tCP
tCAS
tCP
tCRP
tCAS
V
IH
CAS
VIL
tCSH
tASR
Address
tRAH tASC
tRAL
tCAH
V
IH
VIL
Row
Column 1
tRAD
tASC tCAH
tASC tCAH
Column 2
Column N
tCWL
tCWL
tCWL
tRWL
tRCS
tRCS
WE
OE
tRCS
VIH
VIL
tWP
tWP
tWP
tOEH
tOEH
tOEH
V
OH
V
OL
tODD
tDS
tDH
tODD
tDS tDH
tDS
tDH
tODD
I/O
(Input)
V
IH
Data In
2
Data In
1
VIL
Data In
N
WL16
“H” or “L”
Hyper Page Mode (EDO) Late Write Cycle
Semiconductor Group
110
Semiconductor Group
Hyper Page Mode (EDO) Read-Modify-Write Cycle
111
IH
IH
IH
IH
V
IH
V IL
V
V IL
V
V IL
V
V IL
V
V IL
IH
OL
OH
I/O
(Outputs) V
V
I/O
(Inputs) V IL
OE
WE
Address
CAS
RAS
V
tASR
Row
tRAH
tRAD
tRAC
tCAS
tAA
tOEA
tCAC
Data In
tDS
tOEH
tCLZ
tOEZ
tWP
tDS
tDH
Data In
tODD
Data
Out
tOEA
tAWD
tCPA
tAA
tDZC
tCAS
tPRWC
tCPWD
tCWD
tCAH
Column
tASC
tCP
tCWL
tWP
tOEZ tDH
tODD
Data
Out
tAWD
tRWD
tCWD
Column
tASC
tCAH
tDZC
tCLZ
tDZO
tRCS
tRCD
tCSH
tRASP
tOEH
tDZC
tCWL
tAWD
tCAC
tAA
tCLZ
tCPA
tRAL
Data
Out
tDS
tDH
tOEH
tRWL
tCWL
tWP
Data In
tODD
tCPWD
tCWD
tOEA
Column
tASC
tCAH
tCAS
tRSH
tCRP
Row
tASR
tRP
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
WL17
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRAS
RAS
tRP
V
IH
VIL
tCRP
tRPC
V
IH
CAS
VIL
tRAH
tASR
tASR
Address
V
IH
Row
VIL
Row
V
OH
I/O
(Outputs) V
HI-Z
OL
“H” or “L”
WL9
RAS Only Refresh Cycle
Semiconductor Group
112
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRP
RAS
tRAS
V
IH
VIL
tRPC
tCSR
tCRP
tCP
CAS
tRP
tRPC
tCHR
V
IH
VIL
tWRP
tWRH
WE
V
IH
VIL
tOEZ
OE
V
IH
VIL
tCDD
I/O
(Inputs)
V
IH
VIL
tODD
V
OH
I/O
(Outputs)VOL
HI-Z
tOFF
“H” or “L”
WL10
CAS-before-RAS Refresh Cycle
Semiconductor Group
113
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRC
RAS
tRP
tRAS
V
IH
tRP
tRAS
VIL
tRSH
tRCD
tCRP
tCHR
CAS
V
IH
tRAD
VIL
tWRP
tASC
tASR
Address
tRAH
V
IH
VIL
Column
Row
Row
tRRH
tRCS
WE
tASR
tWRH
tCAH
V
IH
VIL
tAA
tOEA
OE
V
IH
VIL
tDZC
tCDD
tDZO
I/O
(Inputs)
tODD
V
IH
VIL
tCAC
tOFF
tCLZ
tOEZ
tRAC
V
OH
I/O
(Outputs) V
Valid Data Out
HI-Z
OL
“H” or “L”
WL11
Hidden Refresh Read Cycle
Semiconductor Group
114
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRC
tRP
RAS
tRAS
V
IH
WE
tRSH
VIL
tCRP
tRAD
tRAH
tASC
tCAH
V
IH
VIL
Row
tASR
Row
Column
tWCS
tWRP
tWCH
tWRH
tWP
V
IH
VIL
tDS
I/O
(Input)
tCHR
V
IH
tASR
Address
tRP
VIL
tRCD
CAS
tRAS
V
IH
tDH
Valid Data
V
IL
V
OH
I/O
(Output) V
OL
HI-Z
“H” or “L”
WL12
Hidden Refresh Early Write Cycle
Semiconductor Group
115
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRASS
tRP
RAS
tRPS
V
IH
VIL
tRPC
CAS
V
IH
tCRP
tCHS
tCSR
tCP
VIL
tWRP
tWRH
WE
OE
V
IH
VIL
V
IH
VIL
tCDD
I/O
(Inputs)
V
IH
VIL
tODD
tOEZ
V
OH
I/O
(Outputs) V
OL
HI-Z
tOFF
“H” or “L”
WL13
Self Refresh (Sleep Mode)
Semiconductor Group
116
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRC
tRP
RAS
VIL
tRP
tRPC
tCP
CAS
tRAS
V
IH
tCSR
tCHR
tRPC
tCRP
V
IH
VIL
tASR tRAH
V
Address IH
Row
VIL
tWTS
WE
OE
tWTH
V
IH
VIL
V
IH
VIL
tODD
V
IH
I/O
(Inputs) V
IL
HI-Z
tCDD
tOEZ
V
OH
I/O
(Outputs) V
HI-Z
OL
tOFF
“H” or “L”
WL15
Test Mode Entry Cycle
Semiconductor Group
117
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
tRP
tRAS
Read Cycle:
RAS
V IH
V IL
tRSH
tCAS
tCP
tCHR
tCSR
CAS
V IH
V IL
tRAL
tASC
Address
V IH
Column
V IL
tWRP
WE
OE
I/O
(Inputs)
I/O
(Outputs)
V IL
tWRH
tRRH
tOEA
tRCS
V IH
V IL
tDZC
V IH
V IL
tODD
tDZO
tCLZ
VOH
VOL
V IH
V IL
OE
V IH
V IL
I/O
(Inputs)
V IH
tWCS
tWRH
tDH
Data In
V IL
HI-Z
CAS-before-RAS Refresh Counter Test Cycle
Semiconductor Group
tRWL
tCWL
tWCH
tDS
V
IH
V
IL
tOEZ
Data Out
Write Cycle:
I/O
(Outputs)
Row
tAA
tCAC
V IH
tWRP
WE
tASR
tCAH
118
tCDD
tOFF
tRCH
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
Package Outlines
P-SOJ-34-1 (500 mil)
(Plastic Small Outline J-leaded Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
119
Dimensions in mm
HYB3164(5)405J/T(L)-50/-60
16M x 4-DRAM
P-TSOPII-34-1 (500 mil)
(Plastic Thin Small Outline Package Type II
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
120
Dimensions in mm
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