STMicroelectronics M48TV-70PM1 3.3v-5v 1 mbit 128kb x8 timekeeper sram Datasheet

M48T128Y
M48T128V*
5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48T128Y: VCC = 4.5 to 5.5V
4.1V ≤ VPFD ≤ 4.5V
– M48T128V*: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER
SELF-CONTAINED BATTERY AND
CRYSTAL IN THE DIP PACKAGE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact local ST sales office for availability of 3.3V version.
February 2005
1/22
M48T128Y, M48T128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2.
Table 1.
Figure 3.
Figure 4.
Logic Diagram . .
Signal Names . .
DIP Connections
Block Diagram . .
...................
...................
...................
...................
.......
.......
.......
.......
......
......
......
......
.......
.......
.......
.......
......
......
......
......
......
......
......
......
.....4
.....4
.....4
.....5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M48T128Y, M48T128V*
SUMMARY DESCRIPTION
The M48T128Y/V TIMEKEEPER® RAM is a
128Kb x 8 non-volatile static RAM and real time
clock. The special DIP package provides a fully integrated battery back-up memory and real time
clock solution. The M48T128Y/V directly replaces
industry standard 128Kb x 8 SRAM.
It also provides the non-volatility of Flash without
any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 32-pin, 600mil DIP Hybrid houses a
controller chip, SRAM, quartz crystal, and a long
life lithium button cell in a single package.
Figure 2. Logic Diagram
Table 1. Signal Names
VCC
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
WRITE Enable
E
VCC
Supply Voltage
G
VSS
Ground
NC
Not Connected Internally
17
8
A0-A16
W
DQ0-DQ7
M48T128Y
M48T128V
VSS
AI02244
Figure 3. DIP Connections
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
32
2
31
3
30
4
29
28
5
27
6
7
26
8 M48T128Y 25
9 M48T128V 24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
AI02245
4/22
VCC
A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
M48T128Y, M48T128V*
Figure 4. Block Diagram
8x8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
A0-A16
POWER
131,064 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
W
VPFD
G
VSS
AI01804
5/22
M48T128Y, M48T128V*
OPERATION MODES
Figure 4., page 5 illustrates the static memory array and the quartz controlled clock oscillator. The
clock locations contain the year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - valid until 2100),
30, and 31 day months are made automatically.
Byte 1FFF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual
clock counters, they are memory locations consisting of BiPORT™ READ/WRITE memory cells
within the static RAM array. The M48T128Y/V includes a clock control circuit which updates the
clock bytes with current information once per sec-
ond. The information can be accessed by the user
in the same manner as any other location in the
static memory array. The M48T128Y/V also has its
own Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When VCC is out of tolerance, the circuit write protects the TIMEKEEPER ®
Register data and external SRAM, providing data
security in the midst of unpredictable system operation. As VCC falls below the Battery Back-up
Switchover Voltage (VSO), the control circuitry automatically switches to the battery, maintaining
data and clock operation until valid power is restored.
Table 2. Operating Modes
Mode
VCC
Deselect
WRITE
READ
4.5 to 5.5V
or
3.0 to 3.6V
READ
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 11., page 18 for details.
6/22
M48T128Y, M48T128V*
READ Mode
The M48T128Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Address Inputs defines which one of the 131,072
bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within tAVQV (Address Access Time) after the last
address input signal is stable, providing the E and
G access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
able after the latter of the Chip Enable Access
Times (tELQV) or Output Enable Access Time
(tGLQV). The state of the eight three-state Data I/O
signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain
active, output data will remain valid for tAXQX (Output Data Hold Time) but will go indeterminate until
the next Address Access.
Figure 5. READ Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Note: WE = High.
Table 3. READ Mode AC Characteristics
Symbol
M48T128Y
M48T128V
–70
–85
Parameter(1)
Min
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
85
ns
tELQV
Chip Enable Low to Output Valid
70
85
ns
tGLQV
Output Enable Low to Output Valid
40
55
ns
70
85
ns
tELQX(2)
Chip Enable Low to Output Transition
5
5
ns
tGLQX(2)
Output Enable Low to Output Transition
5
5
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
25
30
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
25
30
ns
tAXQX
Address Transition to Output Transition
10
5
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
7/22
M48T128Y, M48T128V*
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E
or W must return high for a minimum of tEHAX from
Chip Enable or tWHAX from WRITE Enable prior to
the initiation of another READ or WRITE cycle.
Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
disable the outputs tWLQZ after W falls.
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
VALID
A0-A16
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
VALID
A0-A16
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02383
8/22
M48T128Y, M48T128V*
Table 4. WRITE Mode AC Characteristics
Symbol
M48T128Y
M48T128V
–70
–85
(1)
Parameter
Min
tAVAV
WRITE Cycle Time
tAVWL
Max
Min
Unit
Max
70
85
ns
Address Valid to WRITE Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
WRITE Enable Pulse Width
50
60
ns
tELEH
Chip Enable Low to Chip Enable 1 High
55
65
ns
tWHAX
WRITE Enable High to Address Transition
5
5
ns
tEHAX
Chip Enable High to Address Transition
10
15
ns
tDVWH
Input Valid to WRITE Enable High
30
35
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tWHDX
WRITE Enable High to Input Transition
5
5
ns
tEHDX
Chip Enable High to Input Transition
10
15
ns
tWLQZ(2,3)
WRITE Enable Low to Output Hi-Z
25
30
ns
tAVWH
Address Valid to WRITE Enable High
60
70
ns
tAVEH
Address Valid to Chip Enable High
60
70
ns
5
5
ns
tWHQX(2,3)
WRITE Enable High to Output Transition
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
9/22
M48T128Y, M48T128V*
Data Retention Mode
With valid VCC applied, the M48T128Y/V operates
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD
(min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be
assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48T128Y/V may respond to transient noise
10/22
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T128Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max).
M48T128Y, M48T128V*
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER® registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so
updating the registers can be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD
format (see Table 5., page 11). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers 1FFFFh-1FFF9h to the actual TIMEKEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur one second later.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. The M48T128Y/V is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T128Y/
V oscillator starts after one second.
Table 5. Register Map
Data
Address
D7
1FFFFh
D6
D5
D4
D3
10 Years
10 M
D1
D0
Function/Range
BCD Format
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Day
01-07
Hours
Hours
00-23
1FFFEh
0
0
1FFFDh
0
0
1FFFCh
0
FT
1FFFBh
0
0
1FFFAh
0
10 Minutes
Minutes
Minutes
00-59
1FFF9h
ST
10 Seconds
Seconds
Seconds
00-59
1FFF8h
W
R
0
D2
10 Date
0
0
10 Hours
S
0
Day
Calibration
Control
Keys: S = SIGN Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
11/22
M48T128Y, M48T128V*
Calibrating the Clock
The M48T128Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than +1/–2 ppm at 25°C. The oscillation rate of
crystals changes with temperature (see Figure
8., page 13). The M48T128Y/V design employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 128 stage, as shown in Figure 9., page 13.
The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration bits found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration
bits occupy the five lower order bits (D4-D0) in the
Control Register 1FFF8h. These bits can be set to
represent any value between 0 and 31 in binary
form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64
minute cycle will be modified; if a binary 6 is load-
12/22
ed, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding
512 or subtracting 256 oscillator cycles for every
125, 829, 120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
One method is available for ascertaining how
much calibration a given M48T128Y/V may require. This involves setting the clock, letting it run
for a month and comparing it to a known accurate
reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be found
in the STMicroelectronics Application Note,
“TIMEKEEPER CALIBRATION.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment requires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte. For example, a deviation of 21
seconds slow over a period of 30 days would indicate a –8 ppm oscillator frequency error, requiring
a +2(WR100010) to be loaded into the Calibration
Byte for correction.
M48T128Y, M48T128V*
Figure 8. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
-60
T0 = 25 °C
-80
-100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
°C
AI02124
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/22
M48T128Y, M48T128V*
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
14/22
Figure 10. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
M48T128Y, M48T128V*
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 6. Absolute Maximum Ratings
Symbol
TA
TSTG
TSLD(1)
Parameter
Value
Unit
0 to 70
°C
–40 to 85
°C
260
°C
–0.3 to 7
V
M48T128Y
–0.3 to 7
V
M48T128V
–0.3 to 4.6
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
No preheat above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
15/22
M48T128Y, M48T128V*
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter
M48T128Y
M48T128V
Unit
4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC Testing Load Circuit
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF(1)
CL includes JIG capacitance
1.75V
AI03630
Note: 50pF for M48T128V.
Table 8. Capacitance
Parameter(1,2)
Symbol
CIN
CIO(3)
Min
Max
Unit
Input Capacitance
20
pF
Input / Output Capacitance
20
pF
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/22
M48T128Y, M48T128V*
Table 9. DC Characteristics
Symbol
Parameter
Test Condition
M48T128Y
M48T128V
–70
–85
(1)
Min
ILI
ILO(2)
Input Leakage Current
Output Leakage Current
Max
Min
Unit
Max
0V ≤ VIN ≤ VCC
±2
±2
µA
0V ≤ VOUT ≤ VCC
±2
±2
µA
Outputs open
95
50
mA
ICC
Supply Current
ICC1
Supply Current (Standby)
TTL
E = VIH
8
4
mA
ICC2
Supply Current (Standby)
CMOS
E = VCC – 0.2V
4
3
mA
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.4
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.4
2.4
2.2
V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
17/22
M48T128Y, M48T128V*
Figure 12. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSS
tDR
tF
tREC
tRB
tFB
INPUTS
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
AI03612
Table 10. Power Down/Up AC Characteristics
Symbol
Parameter(1)
Min
Max
Unit
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
tFB(3)
VPFD (min) to VSS VCC Fall Time
10
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
0
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tREC
VPFD (max) to Inputs Recognized
40
200
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol
Parameter(1,2)
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
Min
Typ
Max
Unit
M48T128Y
4.1
4.35
4.5
V
M48T128V
2.7
2.9
3.0
V
M48T128Y
3.0
V
M48T128V
VPFD –100mV
V
10
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
3. At 25°C; VCC = 0V.
18/22
YEARS
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION
Figure 13. PMDIP32 – 32-pin Plastic Module DIP, Package Outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note: Drawing is not to scale.
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
34.29
41.91
1.350
1.650
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
19/22
M48T128Y, M48T128V*
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M48T
128Y
–70
PM
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
128Y = VCC = 4.5 to 5.5V; VPFD = 4.1 to 4.5V
128V(1) = VCC = 3.0 to 3.6V; VPFD = 2.7 to 3.0V
Speed
–70 = 70ns (128Y)
–85 = 85ns (128V)
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. Contact local ST sales office for availability of 3.3V version.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
20/22
M48T128Y, M48T128V*
REVISION HISTORY
Table 14. Document Revision History
Date
Version
Revision Details
June 1998
1.0
First Issue
01/31/00
1.1
Calibrating The Clock Paragraph changed
03/30/00
1.2
Storage Temperature changed (Table 6)
07/20/01
2.0
Reformatted; temperature information added to tables (Table 8, 9, 3, 4, 10, 11)
09/21/01
2.1
Corrected speed grade in ordering information
05/23/02
2.2
Add countries to disclaimer; add marketing status
08/07/02
2.3
Refine marketing status text
28-Mar-03
3.0
v2.2 template applied; test condition updated (Table 11)
06-Aug-04
4.0
Reformatted; updated Register Map (Table 5)
22-Feb-05
5.0
IR reflow update (Table 6)
21/22
M48T128Y, M48T128V*
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
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22/22
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