ON FAN53601AUC105X 6 mhz, 600ma / 1 a synchronous buck regulator Datasheet

Features
 600 mA or 1 A Output Current Capability
 24 µA Typical Quiescent Current
 6 MHz Fixed-Frequency Operation
 Best-in-Class Load Transient Response
 Best-in-Class Efficiency
 2.3 V to 5.5 V Input Voltage Range
 Low Ripple Light-Load PFM Mode
 Forced PWM and External Clock Synchronization
 Internal Soft-Start
 Input Under-Voltage Lockout (UVLO)
 Thermal Shutdow n and Overload Protection
 Optional Output Discharge
 6-Bump WLCSP, 0.4 mm Pitch
Applications
 3G, 4G, WiFi®, WiMAX™, and WiBro® Data Cards
 Tablets
 DSC, DVC
 Netbooks ®, Ultra-Mobile PCs
Description
The FAN53601/11 is a 6 MHz, step-dow n sw itching voltage
regulator, available in 600 mA or 1 A options, that delivers a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a propr ietary architecture w ith synchronous
rectification, the FA N53601/11 is capable of delivering a
peak efficiency of 92%, w hile maintaining efficiency over
80% at load currents as low as 1 mA.
The regulator operates at a nominal fixed frequency of
6 MHz, w hich reduces the value of the external components
to as low as 470 nH for the output inductor and 4.7 µF for the
output capacitor. In addition, the Pulse Width Modulation
(PWM) modulator can be synchronized to an external
frequency source.
At moderate and light loads, Pulse Frequency Modulation
(PFM) is used to operate the device in Pow er-Save Mode
w ith a typical quiescent current of 24 µA. Even w ith such a
low quiescent current, the part exhibits excellent transient
response during large load sw ings. At higher loads, the
system automatically sw itches to fixed-frequency control,
operating at 6 MHz. In Shutdow n Mode, the supply current
drops below 1 µA, reducing pow er consumption. For
applications that require minimum ripple or fixed frequency,
PFM Mode can be disabled using the MODE pin.
The FA N53601/11 is available in 6-bump, 0.4 mm pitch,
Wafer-Level Chip-Scale Package (WLCSP).
MODE
All trademarks are the property of their respective owners.
L1
SW
A1
A2
B1
B2
C1
C2
VIN
CIN
2.2µF
EN
470nH
FB
4.7µF
COUT
Figure 1.
© 2010 Semiconductor Components Industries, LLC.
December-2017, Rev. 2
GND
Typical Application
Publication Order Number:
FAN53611/D
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
FAN53601 / FAN53611
6 MHz, 600 mA / 1 A Synchronous Buck Regulator
Part Number
Output
Voltage (1)
FAN53601AUC10X
FAN53601AUC105X
FAN53611AUC11X
FAN53611AUC115X
FAN53611AUC13X
FAN53611AUC135X
FAN53611UC123X
FAN53601UC182X
FAN53611AUC205X
FAN53611AUC123X
FAN53611AUC12X
FAN53611AUC18X
1.000
1.050
1.100
1.150
1.300
1.350
1.233
1.820
2.050
1.233
1.200
1.800
V
V
V
V
V
V
V
V
V
V
V
V
Max. Output
Active
Max.
Current
Discharge (2) VIN
600 mA
600 mA
1A
1A
1A
1A
1A
600 mA
1A
1A
1A
1A
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
5.5 V
Package
WLCSP-6,
0.4 mm Pitch
Temperature
Packing
Range
-40 to +85°C
Tape and
Reel
Notes:
1. Other voltage options available on request. Contact a ON Semiconductor representative.
2. All voltage and output current options are available w ith or w ithout active discharge. Contact a ON Semiconductor
representative.
Pin Configurations
MODE
A1
A2
VIN
VIN
A2
A1
MODE
SW
B1
B2
EN
EN
B2
B1
SW
FB
C1
C2
GND
GND
C2
C1
FB
Figure 2.
Bum ps Facing Dow n
Figure 3.
Bum ps Facing Up
Pin Definitions
Pin #
Name
Description
A1
MODE
B1
SW
MODE. Logic 1 on this pin forces the IC to stay in PWM Mode. A logic 0 allow s the IC to
automatically sw itch to PFM during light loads. The regulator also synchronizes its sw itching
frequency to four times the frequency provided on this pin. Do not leave this pin floating.
Sw itching Node. Connect to output inductor.
C1
FB
Feedback / V OUT. Connect to output voltage.
C2
GND
B2
EN
A2
VIN
Ground. Pow er and IC ground. All signals are referenced to this pin.
Enable. The device is in Shutdow n Mode w hen voltage to this pin is < 0.4 V and enabled w hen
> 1.2 V. Do not leave this pin floating.
Input Voltage. Connect to input pow er source.
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2
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Ordering Information
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol
Parameter
Min.
V IN
Input Voltage
-0.3
V SW
Voltage on SW Pin
-0.3
V CTRL
EN and MODE Pin Voltage
-0.3
Other Pins
ESD
-0.3
Electrostatic Discharge
Protection Level
Max.
Units
7.0
V
(3)
V
(3)
V
(3)
V
V IN + 0.3
V IN + 0.3
V IN + 0.3
Human Body Model per JESD22-A114
2.0
Charged Device Model per JESD22-C101
1.5
kV
TJ
Junction Temperature
-40
+150
°C
TSTG
Storage Temperature
-65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 7 V or V IN+0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specif ied to ensure optimal performance to the datasheet specifications. ON Semiconductor does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
V CC
IOUT
L
CIN
COUT
Parameter
Min.
Supply Voltage Range
Typ.
Max.
Units
2.3
5.5
V
Output Current for FAN53601
0
600
mA
Output Current for FAN53611
0
1
A
Inductor
470
nH
Input Capacitor
2.2
µF
Output Capacitor
1.6
TA
Operating Ambient Temperature
TJ
Operating Junction Temperature
4.7
12.0
µF
-40
+85
°C
-40
+125
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured w ith four-layer 2s2p
boards in accordance to JEDEC standard JESD51. Special attention must be paid to not exceed junction temperature TJ(max) at a
given ambient temperature TA.
Symbol
θJA
Parameter
Junction-to-Ambient Thermal Resistance
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3
Typical
Unit
125
°C/W
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Absolute Maximum Ratings
Minimum and maximum values are at V IN = V EN = 2.3 V to 5.5 V, V MODE = 0 V (AUTO Mode), TA = -40°C to +85°C; circuit of
Figure 1 , unless otherw ise noted. Typical values are at TA = 25°C, V IN = V EN = 3.6 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
No Load, Not Sw itching
24
50
PWM Mode
8
Units
Pow er Supplies
IQ
I(SD)
V UVLO
Quiescent Current
µA
mA
Shutdow n Supply Current
EN = GND, V IN = 3.6 V
0.25
1.00
µA
Under-Voltage Lockout Threshold
Rising V IN
2.15
2.27
V
V UVHYST Under-Voltage Lockout Hysteresis
200
mV
Logic Inputs: EN and MODE Pins
V IH
Enable HIGH-Level Input Voltage
V IL
Enable LOW-Level Input Voltage
V LHYST
Logic Input Hysteresis Voltage
IIN
Enable Input Leakage Current
1.2
V
0.4
100
Pin to V IN or GND
V
mV
0.01
1.00
µA
Sw itching and Synchronization
f SW
f SYNC
Sw itching Frequency
(4)
(4)
MODE Synchronization Range
V IN = 3.6 V, TA = 25°C, PWM
Mode, ILOAD = 10 mA
5.4
6.0
6.6
MHz
Square Wave at MODE Input
1.3
1.5
1.7
MHz
ILOAD = 0 to 600 mA
0.953
1.000
1.048
PWM Mode
0.967
1.000
1.034
ILOAD = 0 to 1 A
1.298
1.350
1.402
Regulation
1.000 V
1.35 V
1.233 V
1.820 V
1.100 V
VO
Output Voltage
Accuracy
1.300 V
1.150 V
1.050 V
2.050 V
1.200 V
1.800 V
tSS
Soft-Start
PWM mode
1.309
1.350
1.391
ILOAD = 0 to 1 A
1.185
1.233
1.281
PWM Mode
1.192
1.233
1.274
ILOAD = 0 to 600 mA
1.755
1.820
1.885
PWM Mode
1.781
1.820
1.859
ILOAD = 0 to 1 A
1.054
1.100
1.147
PWM Mode
1.061
1.100
1.140
ILOAD = 0 to 1 A
1.250
1.300
1.350
PWM Mode
1.259
1.300
1.341
ILOAD = 0 to 1 A
1.104
1.150
1.196
PWM Mode
1.110
1.150
1.190
ILOAD = 0 to 600 mA
1.003
1.050
1.097
PWM Mode
1.016
1.050
1.084
ILOAD = 0 to 1 A, V IN = 2.7 V to
5.5 V
1.973
2.050
2.127
PWM Mode, V IN = 2.7 V to 5.5 V
2.004
2.050
2.096
ILOAD = 0 to 1 A
1.152
1.200
1.248
PWM Mode
1.160
1.200
1.240
ILOAD = 0 to 1 A
1.732
1.800
1.868
PWM Mode
1.756
1.800
1.844
180
300
V IN = 4.5 V, From EN Rising Edge
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4
V
µs
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Electrical Characteristics
Minimum and maximum values are at V IN = V EN = 2.3 V to 5.5 V, V MODE = 0 V (AUTO Mode), TA = -40°C to +85°C; circuit of
Figure 1 , unless otherw ise noted. Typical values are at TA = 25°C, V IN = V EN = 3.6 V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Driver
RDS(on)
ILIM(OL)
RDIS
TTSD
THYS
Notes:
4.
5.
PMOS On Resistance
V IN = V GS = 3.6 V
175
mΩ
NMOS On Resistance
V IN = V GS = 3.6 V
165
mΩ
PMOS Peak Current Limit
Output Discharge Resistance
Open-Loop for FAN53601,
V IN = 3.6 V, TA = 25°C
900
1100
1250
mA
Open-Loop for FAN53611,
V IN = 3.6 V, TA = 25°C
1500
1750
2000
mA
EN = GND
230
Ω
Thermal Shutdow n
150
°C
Thermal Shutdow n Hysteresis
15
°C
Limited by the effect of tOFF minimum (see Operation Description section).
The Electrical Characteristics table reflects open-loop data. Refer to the Operation Description and Typical Characteristics Sections for
closed-loop data.
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FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Electrical Characteristics (Continued)
Unless otherw ise noted, V IN = V EN = 3.6 V, V MODE = 0 V (AUTO Mode), V OUT = 1.82 V, and TA = 25°C.
95%
92%
90%
88%
86%
84%
82%
80%
78%
76%
74%
72%
70%
68%
66%
64%
62%
60%
Efficiency
Efficiency
90%
85%
80%
75%
2.7
3.6
4.2
5.0
70%
0
200
400
600
800
VIN
VIN
VIN
VIN
1000
- 40C, AUTO
+25C, AUTO
+85C, AUTO
- 40C, PWM
+25C, PWM
+85C, PWM
0
200
400
Load Current (mA)
1000
Figure 5. Efficiency vs. Load Current
and Tem perature, Auto Mode, Dotted for FPWM
90%
90%
88%
88%
86%
86%
84%
84%
82%
82%
80%
80%
Efficiency
Efficiency
800
Load Current (mA)
Figure 4. Efficiency vs. Load Current and
Input Voltage, Auto Mode, Dotted for Decreasing Load
78%
76%
74%
78%
76%
74%
72%
70%
72%
- 40C, AUTO
+25C, AUTO
+85C, AUTO
- 40C, PWM
+25C, PWM
+85C, PWM
68%
70%
2.7
3.6
4.2
5.0
68%
66%
64%
0
200
400
600
800
66%
VIN
VIN
VIN
VIN
64%
62%
60%
1000
0
200
Load Current (mA)
400
600
800
1000
Load Current (mA)
Figure 7. Efficiency vs. Load Current
and Tem perature, V OUT = 1.23 V, Auto Mode,
Dotted for FPWM
Figure 6. Efficiency vs. Load Current and
Input Voltage, V OUT = 1.23 V, Auto Mode, Dotted
for Decreasing Load
3
90%
2.7VIN, AUTO
88%
3.6VIN, AUTO
4.2VIN, AUTO
5.0VIN, AUTO
2.7VIN, PWM
2
86%
84%
82%
3.6VIN, PWM
1
Efficiency
Output Regulation (%)
600
4.2VIN, PWM
5.0VIN, PWM
0
80%
78%
76%
74%
72%
70%
-1
2.7 VIN
3.6 VIN
4.2 VIN
5.0 VIN
68%
66%
-2
64%
0
100
200
300
400
500
600
0
Load Current (mA)
100
200
300
400
500
600
Load Current (mA)
Figure 8. Output Regulation vs. Load Current,
V OUT = 1.00 V, Dotted for Auto Mode
Figure 9.
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6
Efficiency vs. Load Current, V OUT = 1.00 V,
Dotted for Decreasing Load
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
(Continued)
Unless otherw ise noted, V IN = V EN = 3.6 V, V MODE = 0 V (AUTO Mode), V OUT = 1.82 V, and TA = 25°C.
3
3
Output Regulation (%)
2
1
0
2.7VIN, AUTO
3.6VIN, AUTO
4.2VIN, AUTO
5.0VIN, AUTO
2.7VIN, PWM
3.6VIN, PWM
4.2VIN, PWM
5.0VIN, PWM
2
Output Regulation (%)
2.7VIN, AUTO
3.6VIN, AUTO
4.2VIN, AUTO
5.0VIN, AUTO
2.7VIN, PWM
3.6VIN, PWM
4.2VIN, PWM
5.0VIN, PWM
1
0
-1
-1
-2
-2
0
200
400
600
800
0
1000
200
600
Figure 10. ∆V OUT (%) vs. Load Current and Input
Voltage, Norm alized to 3.6 V IN, 500 m A Load, FPWM,
Dotted for Auto Mode
Figure 11. ∆V OUT (%) vs. Load Current and Input
Voltage, V OUT = 1.23 V, Norm alized to 3.6 V IN, 500 m A
Load, FPWM, Dotted for Auto Mode
350
300
300
Load Current (mA)
350
250
200
150
100
250
200
150
100
PWM
PWM
PFM
PFM
50
50
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
Input Voltage (V)
35
4.0
4.5
5.0
5.5
Figure 13. PFM / PWM Boundary vs. Input Voltage,
V OUT = 1.23 V
15
- 40C, EN=VIN
+25C, EN=VIN
+85C, EN=VIN
- 40C, EN=1.8V
+25C, EN=1.8V
+85C, EN=1.8V
- 40C
+25C
+85C
12
Input Current (mA)
30
3.5
Input Voltage (V)
Figure 12. PFM / PWM Boundary vs. Input Voltage
Input Current (µA)
1000
800
Load Current (mA)
Load Current (mA)
Load Current (mA)
400
25
9
6
20
3
15
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
Input Voltage (V)
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage (V)
Figure 14. Quiescent Current vs. Input Voltage and
Tem perature, Auto Mode; EN = V IN Solid, Dotted for
o
o
o
EN=1.8 V (-40 C, +25 C, +85 C)
Figure 15. Quiescent Current vs. Input Voltage and
Tem perature, Mode = EN = V IN (FPWM)
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FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
(Continued)
Unless otherw ise noted, V IN = V EN = 3.6 V, V MODE = 0 V (AUTO Mode), V OUT = 1.82 V, and TA = 25°C.
25
Switching Frequency (KHz)
20
Output Ripple (mVpp)
7,500
2.7VIN, AUTO
3.6VIN, AUTO
5.0VIN, AUTO
2.7VIN, PWM
3.6VIN, PWM
5.0VIN, PWM
15
10
5
6,000
4,500
3,000
2.7VIN, AUTO
3.6VIN, AUTO
5.0VIN, AUTO
1,500
2.7VIN, PWM
3.6VIN, PWM
5.0VIN, PWM
0
0
0
200
400
600
800
0
1000
200
400
600
800
1000
Load Current (mA)
Load Current (mA)
Figure 16. Output Ripple vs. Load Current and
Input Voltage, FPWM, Dotted for Auto Mode
Figure 17. Frequency vs. Load Current and
Input Voltage, Auto Mode, Dotted for FPWM
Figure 18. Load Transient, 10-200-10 m A, 100 ns Edge
Figure 19. Load Transient, 200-800-200 m A,
100 ns Edge
Figure 20. Line Transient, 3.3-3.9-3.3 V IN, 10 µs Edge,
36 m A Load
Figure 21. Line Transient, 3.3-3.9-3.3 V IN, 10 µs Edge,
600 m A Load
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FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
(Continued)
Unless otherw ise noted, V IN = V EN = 3.6 V, V MODE = 0 V (AUTO Mode), V OUT = 1.82 V, and TA = 25°C.
Figure 22. Com bined Line / Load Transient, 3.9-3.3 V IN, Figure 23. Com bined Line / Load Transient, 3.3-3.9 V IN,
10 µs Edge, 36-400 m A Load, 100 ns Edge
10 µs Edge, 400-36 m A Load, 100 ns Edge
Figure 24. Startup, 50 Ω Load
Figure 25. Startup, 3 Ω Load
Figure 26. Shutdow n, 10k Ω Load, No Output Discharge
Figure 27. Shutdow n, No Load, Output Discharge
Enabled
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FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
(Continued)
Unless otherw ise noted, V IN = V EN = 3.6 V, V MODE = 0 V (AUTO Mode), V OUT = 1.82 V, and TA = 25°C.
Figure 28. Over-Current, Load Increasing Past
Current Lim it, FAN53601
Figure 29. 250 m Ω Fault, Rapid Fault,
Hiccup, FAN53601
Figure 30. Over-Current, Load Increasing Past
Current Lim it, FAN53611
Figure 31. 250 m Ω Fault, Rapid Fault,
Hiccup, FAN53611
70
70
36mA Load
24mA Load
600mA Load
500mA Load
60
50
PSRR (dB)
PSRR (dB)
60
40
30
50
40
30
20
20
0.1
1
10
100
1000
0.1
Frequency (KHz)
Figure 32. PSRR, 50 Ω and 3 Ω Load
1
10
100
1000
Frequency (KHz)
Figure 33. PSRR, 50 Ω and 3 Ω Load, V OUT = 1.23 V
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FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Typical Performance Characteristics
The FAN53601/11 is a 6 MHz, step-dow n sw itching voltage
regulator available in 600 mA or 1 A options that delivers a
fixed output from an input voltage supply of 2.3 V to 5.5 V.
Using a proprietary architecture w ith synchronous
rectification, the FA N53601/11 is capable of delivering a
peak efficiency of 92%, w hile maintaining efficiency over
80% at load currents as low as 1 mA.
The regulator operates at a nominal fixed frequency of
6 MHz, w hich reduces the value of the external components
to as low as 470 nH for the output inductor and 4.7 µF for the
output capacitor. In addition, the PWM modulator can be
synchronized to an external frequency source.
IDISP = C OUT •
w here
dV
dt
(1)
dV
refers to the soft-start slew rate.
dt
To prevent shut dow n during soft-start, the follow ing condition
must be met:
IDISP + ILOAD < IMAX(DC)
(2)
where IMAX(DC) is the maximum load current the IC is
guaranteed to support.
Control Scheme
Startup into Large COUT
The FAN53601/11 uses a proprietary, non-linear, fixedfrequency PWM modulator to deliver a fast load transient
response, while maintaining a constant sw itching frequency
over a w ide range of operating conditions. The regulator
performance is independent of the output capacitor ESR,
allow ing for the use of ceramic output capacitors. Although
this type of operation nor mally results in a sw itching frequency
that varies w ith input voltage and load current, an internal
frequency loop holds the sw itching frequency constant over a
large range of input voltages and load currents.
Multiple soft-start cycles are required for no-load startup if
COUT is greater than 15 µF. Large COUT requires light initial
load to ensure the FA N53601/11 starts appropr iately. The IC
shuts dow n for 1.3 ms w hen IDISP exceeds ILIMIT for more
than 200 µs of current limit. The IC then begins a new softstart cycle. Since COUT retains its charge w hen the IC is off,
the IC reaches regulation after multiple soft-start attempts.
For very light loads, the FAN53601/11 operates in
Discontinuous Current Mode ( DCM) s ingle-pulse PFM Mode,
which produces low output ripple compared w ith other PFM
architectures. Transition betw een PWM and PFM is
seamless, allow ing for a smooth transition betw een DCM
and CCM.
Combined
w ith
exceptional
transient
response
characteristics, the very low quiescent current of the
controller maintains high efficiency; even at very light loads;
while preserving fast transient response for applications
requiring tight output regulation.
Enable and Soft-Start
When EN is LOW, all circuits are off and the IC draw s
~250 nA of current. When EN is HIGH and V IN is above its
UVLO threshold, the regulator begins a soft-start cycle. The
output ramp during soft-start is a fixed slew rate of 50 mV/µs
from Vout = 0 to 1 V, then 12.5 mV/µs until the output reaches
its setpoint. Regardless of the state of the MODE pin, PFM
Mode is enabled to prevent current from being discharged
from COUT if soft-start begins w hen COUT is charged.
In addition, all voltage options can be ordered w ith a feature
that actively discharges FB to ground through a 230 Ω path
when EN is LOW. Raising EN above its threshold voltage
activates the part and starts the soft-start cycle. During softstart, the internal reference is ramped using an exponential
RC shape to prevent overshoot of the output voltage. Current
limiting minimizes inrush during soft-start.
The current-limit fault response protects the IC in the event
of an over-current condition present dur ing soft-start. As a
result, the IC may fail to start if heavy load is applied during
startup and/or if excessive COUT is used.
The current required to charge COUT during soft-start
commonly referred to as “displacement current” is given as:
MODE Pin
Logic 1 on this pin forces the IC to stay in PWM Mode. A
logic 0 allow s the IC to automatically sw itch to PFM during
light loads. If the MODE pin is toggled w ith a frequency
betw een 1.3 MHz and 1.7 MHz, the converter synchronizes
its sw itching frequency to four times the frequency on the
MODE pin.
The MODE pin is internally buffered w ith a Schmitt trigger,
which allows the MODE pin to be driven w ith slow rise and
fall times. An asy mmetric duty cycle for frequency
synchronization is also per mitted as long as the minimum
time below V IL(MAX) or above V IH(MAX) is 100 ns.
Current Limit, Fault Shutdown, and Restart
A heavy load or short circuit on the output causes the current
in the inductor to increase until a maximum current threshold
is reached in the high-side sw itch. Upon reaching this point,
the high-side sw itch turns off, preventing high currents from
causing damage. The regulator continues to limit the current
cycle-by-cycle. After 16 cycles of current limit, the regulator
triggers an over-current fault, causing the regulator to shut
dow n for about 1.3 ms before attempting a restart.
If the fault is caused by short circuit, the soft-start circuit
attempts to restart and produces an over-current fault after
about 200 µs, w hich results in a duty cycle of less than 15%,
limiting pow er dissipation.
The closed- loop peak-current limit is not the same as the
open-loop tested current limit, ILIM(OL) , in the Electrical
Characteristics table. This is primar ily due to the effect of
propagation delays of the IC current limit comparator.
Under-Voltage Lockout (UVLO)
When EN is HIGH, the under-voltage lockout keeps the part
from operating until the input supply voltage r ises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
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11
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Operation Description
When the die temperature increases, due to a high load
condition and/or a high ambient temperature; the output
sw itching is disabled until the die temperature falls suffic iently.
The junction temperature at w hich the thermal shutdow n
activates is nominally 150°C w ith a 15°C hysteresis.


1
, 6MHz 
fSW = min 
 tSW ( MAX )



w here:

VOUT + IOUT • ROFF
tSW ( MAX ) = 40ns • 1 +
V
IN − IOUT • RON − VOUT

w here:
Minimum Off-Time Effect on Switching
Frequency
tOFF(MIN) is 40 ns. This imposes constraints on the maximum
VOUT
that the FA N53601/11 can provide or the maximum
VIN
output voltage it can provide at low V IN w hile maintaining a
fixed sw itching frequency in PWM Mode.
When V IN is LOW, fixed sw itching is maintained as long as:
VOUT
≤ 1 − t OFF ( MIN ) • fSW ≈ 0.7 .
VIN
The sw itching frequency drops when the regulator cannot
provide sufficient duty cycle at 6 MHz to maintain regulation.
This occurs when V OUT is 1.82 V and V IN is below 2.7 V at
high load currents (see Figure 34).
Switching Frequency (KHz)
7,500
6,000
4,500
2.7VIN, AUTO
2.3VIN, AUTO
2.7VIN, PWM
2.3VIN, PWM
3,000
1,500
0
0
200
400
600
800
(3)
1000
Load Current (mA)
Figure 34. Frequency vs. Load Current to
Dem onstrate t OFFMIN Effect, V IN = 2.3 V and 2.7 V,
V OUT = 1.82 V, Auto Mode, FPWM Dotted
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12
ROFF = RDSON _ N + DCRL
RON = RDSON _ P + DCRL




(4)
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
The calculation for sw itching frequency is given by:
Thermal Shutdown (TSD)
Selecting the Inductor
The output inductor must meet both the required inductance
and the energy-handling capability of the application. The
inductor value affects average current limit, the PWM-toPFM transition point, output voltage ripple, and efficiency.
The ripple current (∆I) of the regulator is:
 V − VOUT 
V

(5)
∆I ≈ OUT •  IN

VIN
 L • fSW 
The maximum average load current, IMAX(LOAD), is related to
the peak current limit, ILIM(PK) , by the ripple current, given by:
IMAX(LOAD ) = ILIM(PK ) −
∆I
2
(6)
The transition betw een PFM and PWM operation is
deter mined by the point at w hich the inductor valley current
crosses zero. The regulator DC current w hen the inductor
current crosses zero, IDCM , is:
IDCM =
∆I
2
(7)
The FA N53601/11 is optimized for operation w ith L = 470 nH,
but is stable w ith inductances up to 1 µH (nominal). The
inductor should be rated to maintain at least 80% of its value
at ILIM(PK) .
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical size
typically decreases the DCR; but because ∆I increases, the
RMS current increases, as do the core and skin effect losses.
IRMS =
2
IOUT(DC) +
The increased RMS current produces higher losses through
the RDS(ON) of the IC MOSFETs, as w ell as the inductor DCR.
Increasing the inductor value produces low er RMS currents,
but degrades transient response. For a given physical
inductor size, increased inductance usually results in an
inductor w ith low er saturation current and higher DCR.
Table 1 shows the effects of inductance higher or low er than
the recommended 1 µH on regulator performance.
Output Capacitor
Table 2 suggests 0402 capacitors. 0603 capacitors may
further improve performance in that the effective capacitance
is higher. This improves transient response and output ripple.
Increasing COUT has no effect on loop stability and can
therefore be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆V OUT, is:
f

⋅C
⋅ ESR 2
1
+
∆VOUT = ∆IL  SW OUT

(
)
⋅
⋅
−
⋅
⋅
8
f
C
2
D
1
D
SW
OUT 

(9)
Input Capacitor
The 2.2 µF ceramic input capacitor should be placed as
close as possible betw een the V IN pin and GND to minimize
the paras itic inductance. If a long w ire is used to bring pow er
to the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed betw een CIN and the pow er
source lead to reduce the ringing that can occur betw een the
inductance of the pow er source leads and CIN.
The effective capacitance value decreases as V IN increases
due to DC bias effects.
∆I
12
2
(8)
Table 1. Effects of Changes in Inductor Value (from 470 nH Recom m ended Value) on Regulator Perform ance
Inductor Value
IMAX(LOAD)
∆VOUT
Transient Response
Increase
Increase
Decrease
Degraded
Decrease
Decrease
Increase
Improved
Table 2. Recom m ended Passive Com ponents and their Variation Due to DC Bias
Component
Description
Vendor
Min.
Typ.
Max.
L1
470 nH,
2012,90 mΩ,
1.1 A
Murata LQM21PNR47MC0
Murata LQM21PNR54MG0
Hitachi Metals HLSI 201210R47
300 nH
470 nH
520 nH
CIN
2.2 µF, 6.3 V,
X5R, 0402
Murata or Equivalent GRM155R60J225ME15
GRM188R60J225KE19D
1.0 µF
2.2 µF
COUT
4.7 µF, X5R,
0402
Murata or Equivalent GRM155R60G475M
GRM155R60E475ME760
1.6 µF
4.7 µF
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13
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
Applications Information
There are only three external components: the inductor and
the input and output capacitors. For any buck sw itcher IC,
including the FAN53601/11, it is important to place a low -ESR
input capacitor very close to the IC, as show n in Figure 35.
The input capacitor ensures good input decoupling, w hich
helps reduce noise appearing at the output terminals and
ensures that the control sections of the IC do not behave
erratically due to excessive noise. This reduces switching
cycle jitter and ensures good overall performance. It is
important to place the common GND of CIN and COUT as close
as possible to the C2 terminal. There is some flexibility in
moving the inductor further aw ay from the IC; in that case,
V OUT should be considered at the COUT terminal.
Figure 35. PCB Layout Guidance
The following information applies to the WLCSP package dimensions on the next page:
Product-Specific Dimensions
D
E
X
Y
1.160 ±0.030
0.860 ±0.030
0.230
0.180
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14
FAN53601 / FAN53611 — 6 MHz 600 mA / 1 A Synchronous Buck Regulator
PCB Layout Guidelines
F
0.03 C
E
2X
A
0.40
B
A1
BALL A1
INDEX AREA
D
(Ø0.20)
Cu Pad
0.40
F
(Ø0.30)
Solder Mask
Opening
0.03 C
2X
TOP VIEW
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
0.06 C
0.625
0.547
0.05 C
0.378±0.018
0.208±0.021
E
SEATING PLANE
C
D
SIDE VIEWS
Ø0.260±0.010
6X
0.40
0.005
A. NO JEDEC REGISTRATION APPLIES.
C A B
B. DIMENSIONS ARE IN MILLIMETERS.
C
B
0.40
NOTES:
(Y) +/-0.018
A
F
1 2
(X) +/-0.018
BOTTOM VIEW
C. DIMENSIONS AND TOLERANCES PER
ASMEY14.5M, 1994.
D. DATUM C, THE SEATING PLANE IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
E. PACKAGE TYPICAL HEIGHT IS 586 MICRONS
±39 MICRONS (547-625 MICRONS).
F. FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILENAME: UC006ACrev4.
Figure 36. 6-Bum p WLCSP, 0.4 m m Pitch
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15
FAN53601 / FAN53611 — 6 MHz, 600 mA / 1 A Synchronous Buck Regulator
Physical Dimensions
FAN53601 / FAN53611 — 6 MHz, 600 mA / 1 A Synchronous Buck Regulator
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