ACPL-32JT Automotive 2.5 Amp Gate Drive Optocoupler with Integrated Flyback Controller for Isolated DC-DC Converter, Integrated IGBT Desat Overcurrent Sensing, Miller Current Clamping and UVLO Feedback Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features Avago's Automotive 2.5 Amp Gate Drive Optocoupler features integrated flyback controller for isolated DC-DC converter, IGBT desaturation sensing and fault feedback, Under-Voltage LockOut (UVLO) with soft-shutdown and fault feedback and active Miller current clamping. The fast propagation delay with excellent timing skew performance enables excellent timing control and efficiency. This full feature optocoupler comes in a compact, surfacemountable SO-16 package for space-savings, is suitable for traction power train inverter, power converter, battery charger, air-conditioner and oil pump motor drives in HEV and EV applications. • Qualified to AEC-Q100 Grade 1 Test Guidelines • Automotive temperature range: -40 °C to +125 °C • Integrated flyback controller for isolated DC-DC converter • Regulated Output Voltage: 20 V • Peak output current: 2.5 A max. • Miller Clamp Sinking Current: 1.7 A max. • Wide Input Voltage Range: 8 V to 18 V • Common-Mode Rejection (CMR): > 30 kV/ms at VCM = 1500 V • Propagation delay: 250 ns max. • Integrated fail-safe IGBT protection – Desat sensing, “Soft” IGBT turn-off and Fault Feedback – Under Voltage Lock-Out (UVLO) protection with Feedback • High Noise Immunity – Miller Current Clamping – Direct LED input with low input impedance and low noise sensitivity – Negative Gate Bias • SO-16 package with 8 mm clearance and creepage • Regulatory approvals: – UL 1577, CSA – IEC/EN/DIN EN 60747-5-5 Avago R2Coupler isolation products provide reinforced insulation and reliability that delivers safe signal isolation critical in automotive and high temperature industrial applications. Functional Diagram SW VEE2 VCC2 OSC Logic Control R S LED2+ VCC1 COMP /UVLO UVLO VE DESAT Input Driver /FAULT Output Driver Over Current VEE1 VO AN SSD Control Miller Control CA SSD/ CLAMP VEE2 Figure 1. ACPL-32JT Functional Diagram Applications • • • • • Automotive Isolated IGBT/MOSFET Inverter gate drive Automotive DC-DC Converter AC and brushless DC motor drives Hybrid and Plug-in hybrid powertrain inverter Uninterruptible Power Supplies (UPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation, which may be induced by ESD. Ordering Information Option (RoHS Compliant) Package ACPL-32JT -000E SO-16 ACPL-32JT -500E Part Number IEC/EN/DIN EN 60747-5-5 Surface Mount Tape & Reel X X X Quantity X 45 per tube X 850 per reel To order, choose a part number from the Part Number column and combine with the desired option from the Option column to form an order entry. Example: ACPL-32JT-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-5 Safety Approval that is RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawing (16-Lead Surface Mount) 0.457 typ. (0.018) 1.270 BSC (0.050) RECOMMENDED LAND PATTERN PART NUMBER DATE CODE RoHS COMPLIANCE INDICATOR • A 32JT YYWW EE +0.254 10.363 –0.127 (0.408 +0.010) –0.005) +0.254 +0.010) (0.295 –0.005) Extended Datecode for lot tracking ) 4 9°(× 3.505± 0.127 (0.138± 0.005) Dimensions in millimeters (inches) 11.634 (0.458) 7.493 –0.127 0.203± 0.102 (0.008± 0.004) STANDOFF Note: Lead coplanarity = 0.10 mm (0.004 inches) Floating lead protrusion = 0.25 mm (0.010 inches) Max. Mold Flash on each side = 0.127 mm (0.005 inches) Max. 2.160 (0.085) 0.635 (0.025) 1.270 (0.050) 8.763± 0.254 (0.345± 0.010) 9°(× 4) (0 - 8°) 0.635 min. (0.025) 10.363± 0.254 (0.408± 0.010) Recommended Lead-free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-halide flux should be used. 2 0.254 typ. (0.010) Product Overview Description The ACPL-32JT (shown in Figure 1) is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit. It features a flyback controller for isolated DC-DC converter, a high current gate driver, Miller current clamping, IGBT desaturation, Under-Voltage Lock-Out (UVLO) protection, and feedback in a SO-16 package. Direct LED input allows flexible logic configuration and differential current mode driving with low input impedance, greatly increases its noise immunity. Package Pin Out 1 VEE1 VEE2 16 2 SW LED2+ 15 3 VCC1 DESAT 14 4 COMP VE 13 5 /UVLO VCC2 12 6 /FAULT VO 11 7 AN SSD/CLAMP 10 8 CA VEE2 9 Figure 2. Pinout of ACPL-32JT Pin Description Pin Name Function Pin Name Function VEE1 Input IC common VEE2 Output IC common and negative power supply reference to IGBT Emitter SW Switch Output to Primary Winding LED2+ No connection, for testing only VCC1 Input power supply DESAT Desat overcurrent sensing COMP Compensation network for Flyback Controller VE IGBT emitter reference /UVLO VCC2 under voltage lock out feedback VCC2 Positive power supply /FAULT Overcurrent fault feedback VO Driver output to IGBT gate AN Input LED anode SSD/CLAMP Soft shutdown sensing/Miller current clamping output. (For proper functionality, this pin must be connected to the gate of the IGBT directly or through a current buffer.) CA Input LED cathode VEE2 Negative power supply 3 Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three-phase inverter is susceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase or rail supply short circuits due to user misconnect or bad wiring; control signal failures due to noise or computational errors; overload conditions induced by the load; and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches the saturation current of the device, and the collector-to-emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn off the overcurrent during a fault condition. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-32JT limits the power dissipation in the IGBT, even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not needed to protect the IGBT. A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components, board space consumed, cost, and complexity have until now limited its use to high performance drives. The features that this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. The recommended application circuit shown in Figure 3 illustrates a typical gate drive implementation using the ACPL-32JT. The ACPL-32JT satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shutdown, and optically isolated fault and UVLO status feedback signal into a single 16-pin surface mount package. The fault detection method, which the ACPL-32JT has adopted, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off-state of the IGBT, the fault detect circuitry is simply disabled to prevent false ‘fault’ signals. 4 Recommended Application Circuit The ACPL-32JT has non-inverting gate control inputs, an open collector fault, and UVLO outputs suitable for wired ‘OR’ applications. The two supply bypass capacitors (1.0 µF or larger) provide the large transient currents necessary during a switching transition. The Desat diode and 220 pF blanking capacitor are the necessary external components for the fault detection circuitry. The gate resistor (10 Ω) serves to limit gate charge current and indirectly controls the IGBT collector voltage rise and fall times. The open collector fault and UVLO outputs have a passive 10 kΩ pull-up resistor and a 330 pF filtering capacitor. Vin = 8V - 18V, 220nF Lp 2kΩ Ls 10uF 10uF + 5V 1uF 470kΩ 330pF 22nF 10kΩ 10kΩ uC IF 330pF 130Ω 330pF 130Ω VEE1 VEE2 SW LED2+ VCC1 DESAT COMP VE /UVLO VCC2 /FAULT VO AN SSD/CLAMP CA VEE2 1kΩ 1kΩ 220pF C 10uF 10Ω 1uF 10uF VGATE G E ACPL-32JT Figure 3. Typical gate drive circuits with Desat current sensing using ACPL-32JT Note. Component value subject to change with varying application requirements Operation of Integrated Flyback Controller Reference DC/DC circuit The primary control block implements direct duty cycle control logics for line and load regulation. Primary winding currents are sensed and limited to prevent transformer short circuit failure from damaging the primary switch. Secondary output voltage VCC2 is also sensed and fed back to the primary control circuits. VCC2 over voltage can be detected and the primary switch is turned off to protect secondary overvoltage failure. The maximum PWM duty cycle is designed to be around 55% to ensure discontinuous operation mode under a high load condition. For a complete isolated DC-DC converter, connect a discrete transformer to ACPL-32JT, as in Figure 3. Keep the LED off when you are powering up VCC1. To ensure proper operation of the DC-DC converter, a fast VCC1 rise time (≤ 5 ms) is preferred for a soft start function to control the inrush current. Figure 3 shows a reference circuit for DC/DC flyback conversion including the compensation network at pin 4, COMP. The average PWM switching frequency of the primary switch (SW) is dithered typically in a range of ±6%. This frequency dithering feature helps to achieve better EMI performance by spreading the switching and its harmonics over a wider band. 5 This compensation network is referenced to a nominal transformer of Lp = 60 µH, Ls=260 µH. For VCC1 = 8 V to 18 V, this circuit will nominally support a secondary-side load of up to 60 mA (including ICC2) at the regulated VCC2 voltage. For VCC1 = 6 V to 8V, the supported load will be up to 40 mA. Users must further characterize the DC/DC flyback conversion across their target operating conditions and chosen components to ensure that the required load can be supported. DESAT Fault Detection Blanking Time After the IGBT is turned on, the DESAT fault detection circuitry must remain disabled for a short time period to allow the collector voltage to fall below the DESAT threshold. This time period, called the total DESAT blanking time, is controlled by the both internal DESAT blanking time tDESAT(BLANKING) and external blanking time, determined by the internal charge current, the DESAT voltage threshold, and the external DESAT capacitor. The total blanking time is calculated in terms of internal blanking time (tDESAT(BLANKING)), external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG) as tBLANK = tDESAT(BLANKING) + CBLANK × VDESAT / ICHG Description of Gate Driver and Miller Clamping The gate driver is directly controlled by the LED current. When the LED current is driven high, ACPL-32JT can then deliver a 2.5 A sourcing current to drive the IGBT’s gate. When the LED is switched off, the gate driver can provide a 2.5 A sinking current to quickly switch off the gate. The additional Miller clamping pull-down transistor is activated when the output voltage reaches about 2 V with respect to VEE2 to provide a low impedance path to the Miller current, as shown in Figure 6. IF VO V GATE Figure 4. Gate Drive Signal Behavior Description of Under Voltage Lock Out Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage due to high heat dissipation. ACPL-32JT monitors the output power supply constantly. When output power supply is lower than under voltage lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias. During power up, the UVLO feature forces the ACPL‑32JT’s output low to prevent an unwanted turn-on at lower voltage. V CC1 V CC2 V CC1_TH V UVLO - V UVLO+ LED I F t UVLO_OFF t UVLO_ON VO /FAULT /UVLO t PHL_UVLO t PLH_UVLO Figure 5. Circuit Behaviors at Power-up and Power down Description of Over-Voltage Protection If VCC2 is greater than the specified VCC2 OverVoltage Protection Threshold, then the transistor at the SW pin on the primary side will shut down and the DC/DC flyback conversion will stop. 6 During a Short Circuit: 1. DESAT terminal monitors IGBT’s VCE voltage. 2. When the voltage on the DESAT terminal exceeds 7 V, the IGBT gate voltage (VGATE) is slowly lowered by soft shutdown pin SSD. Output driver Vo enters into high impedance state. 3. Output driver Vo ignores all PWM commands during mute time tDESAT(MUTE). 4. FAULT output goes Low, notifying the microcontroller of the fault condition. 5. Microcontroller takes appropriate action. 6. When tDESAT(MUTE) expires, the LED input needs to be kept Low for tDESAT(RESET) before fault condition can be cleared. FAULT status will return to High. 7. Output starts to respond to LED input after fault condition is cleared. t DESAT (RESET) IF Hi-Z V O state SSD/Clamp State Hi-Z SSD Clamp Hi-Z t DESAT (90%) VGATE VDESAT_TH VDESAT t DESAT (BLANKING) V /FAULT t DESAT (MUTE) t DESAT (/FAULT) Figure 6. Circuit Behaviors During Desaturation Event 7 Clamp Hi-Z Clamp Regulatory Information The ACPL-32JT is approved by the following organizations: UL CSA Approved under UL 1577, component Approved under CSA Component Acrecognition program up to VISO = 5000 ceptance Notice #5, File CA 88324. VRMS expected before product release. IEC/EN/DIN EN 60747-5-5 Approved under: IEC 60747-5-5: EN 60747-5-5: DIN EN 60747-5-5: IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Description Symbol Units Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000 Vrms I – IV I – IV I - IV I - III Climatic Classification 40/125/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 1230 VPEAK Input-to-Output Test Voltage, Method b VIORM × 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC VPR 2306 VPEAK Input-to-Output Test Voltage, Method a VIORM × 1.6 = VPR, Type and Sample Test with tm = 10 sec, Partial discharge < 5 pC VPR 1968 VPEAK Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 8000 VPEAK Safety-limiting values – maximum values allowed in the event of a failure, (also see Figure 7) Case Temperature Input Power Output Power Ts PS,INPUT PS,OUTPUT 175 400 1200 °C mW mW Insulation Resistance at TS, VIO = 500 V RS > 109 W Notes: 1. Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in the application. Surface mount classification is Class A in accordance with CECCOO802. 2. Refer to the Optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulation section IEC/EN/ DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles. 8 Insulation and Safety Related Specifications Parameter Symbol Value Unit Conditions Minimum External Air Gap (External Clearance) L(101) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.5 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. > 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI IIIa Material Group (DIN VDE 0110) Absolute Maximum Ratings Unless otherwise specified, all voltages at input IC reference to VEE1, all voltages at output IC reference to VEE2. Parameter Symbol Min. Max. Units Storage Temperature TS -55 150 °C Operating Temperature TA -40 125 °C IC Junction Temperature TJ 150 °C Average Input Current IF(AVG) 20 mA Peak Transient Input Current (< 1 µs pulse width, 300 pps) IF(TRAN) 1 A Reverse Input Voltage (VCA-VAN) VR 6 V Primary Switch Voltage VSW 36 V Input Supply Voltage VCC1 -0.5 26 V /UVLO Pin Voltage V/UVLO -0.5 6 V /Fault Pin Voltage V/FAULT -0.5 6 V /Fault Output Current (Sinking) I/FAULT 10 mA /UVLO Output Current (Sinking) I/UVLO 10 mA Output Supply Voltage VCC2 - VEE2 -0.5 25 V Negative Output Supply Voltage VEE2 - VE -10 0.5 V Positive Output Supply Voltage VCC2 - VE -0.5 25 V Gate Drive Output Voltage Vo(peak) - VEE2 -0.5 VCC2+0.5 V Miller Clamping Pin Voltage VCLAMP - VEE2 -0.5 VCC2+0.5 V Desat Voltage VDESAT - VE – 0.5 10 V 3 Peak Output Current |IO(peak)| 2.5 A 4 Output IC Power Dissipation PO 580 mW 1 Input IC Power Dissipation PI 180 mW 9 Note 1 33 2 Recommended Operating Conditions Parameter Symbol Min. Max. Units Operating Temperature TA -40 125 °C Input IC Supply Voltage VCC1 8 18 V 5 Total Output IC Supply Voltage VCC2 – VEE2 18 22 V 6 Positive Output IC Supply Voltage VCC2 – VE 15 25 7 Negative Output IC Supply Voltage VEE2-VE -8 0 7 Input LED Turn on Current IF(ON) 10 16 mA Input LED Turn off Voltage (VAN-VCA) VF(OFF) -5.5 0.8 V PWM Duty Cycle DMAX 50 % Peak SW current ISW_PK 1.3 A Input pulse width tON(LED) 500 Notes ns Electrical Specifications Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25 °C, VCC1 = 12 V, VCC2-VEE2 = 20 V, VE-VEE2 = 0 V. Parameter Symbol Min Typ Max Units Test Conditions Fig. PWM Switching Frequency fPWM 40 60 80 kHz Maximum PWM Duty Cycle D VCC1 Turn-on Threshold VCC1_TH SW turn-on Resistance RON_SW Regulated VCC2 Voltage VCC2 SW Overcurrent Protection Threshold ISW_TH 2 A VCC2 OverVoltage Protection Threshold VOV_TH 24 V Input Supply Current ICC1 4.0 6.1 mA Output Low Supply Current ICC2L 10.5 13.2 mA IF = 0 mA VCC2 = 20 V 12 Output High Supply Current ICC2H 10.6 13.6 mA IF = 10 mA VCC2 = 20 V 12 1.55 1.85 V IF = 10 mA 13 V IF = -10 µA DCDC Flyback Converter 56 % 6 0.9 19 20 21.5 8 V Ω ISW = 1.3 A 9 V ICOMP = 0 A 10 IC Supply Current 11 Logic Input and Output LED Forward Voltage (VAN – VCA) VF 1.25 LED Reverse Breakdown Voltage (VCA – VAN) VBR 6 LED Input Capacitance CIN 90 LED Turn-on Current Threshold Low-to-High ITH+ 2.4 6.6 mA VO = 5 V 14 LED Turn-on Current Threshold High-to-Low ITH- 1.8 6.4 mA VO = 5 V 14 LED Turn-on Current Hysteresis ITH_HYS 0.6 mA FAULT Logic Low Output Current IFAULT_L 9.0 mA V/FAULT = 0.4 V FAULT Logic High Output Current IFAULT_H µA V/FAULT = 5 V UVLO Logic Low Output Current IUVLO_L mA V/UVLO = 0.4 V UVLO Logic High Output Current IUVLO_H µA V/UVLO = 5 V Continued on next page... 10 4.0 pF 20 4.0 9.0 20 Note Electrical Specifications (continued) Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25 °C, VCC1 = 12 V, VCC2-VEE2 = 20 V, VE-VEE2 = 0 V. Parameter Symbol Min Typ Max Units Test Conditions Fig. Note -1.9 -0.75 A VO = VCC2 - 3 V 15 4 16 4 Gate Driver High Level Output Current IOH Low Level Output Current IOL 1.0 2.3 A VO = VEE2 + 2.5 V High Level Output Voltage VOH VCC2–0.5 VCC2–0.15 V IO = -100 mA Low Level Output Voltage VOL Vsource to High Level Output Propagation Delay Time tPLH Vsource to Low Level Output Propagation Delay Time 8,9,10 0.1 0.5 V IO = 100 mA 50 120 250 ns tPHL 50 160 250 ns Pulse Width Distortion PWD -40 40 140 ns Vsource = 5 V 17,22 Rf = 260 Ω, Rg = 10 Ω Cload = 10 nF 17,22 f = 10 kHz Duty Cycle = 50% Dead Time Distortion (tPLH-tPHL) DTD -160 -40 60 ns 10% to 90% Rise Time tR 70 ns 90% to 10% Fall Time tF 35 ns Output High Level Common Mode Transient Immunity |CMH| 30 >50 kV/μs TA=25 °C, IF = 10 mA, VCM =1500 V 23 16 Output Low Level Common Mode |CML| Transient Immunity 30 >50 kV/μs TA = 25 °C, IF = 0 mA, VCM=1500 V 24 17 22 35 55 mA VSSD – VEE2 = 14 V 18 2.0 3.0 V 11 12 13,14 14,15 Active Miller Clamp and Soft Shutdown Low Level Soft Shutdown Current During Fault Condition ISSD Clamp Threshold Voltage V TH_CLAMP Clamp Low Level Sinking Current ICLAMP 0.5 2.0 A VCLAMP = VEE2 + 2.5 V VCC2 UVLO Protection (UVLO voltage VUVLO reference to VE) VCC2 UVLO Threshold Low to High VUVLO+ 10.9 12.5 13.8 V VO > 5 V 10,18 VCC2 UVLO Threshold High to Low VUVLO- 10.0 11.3 12.8 V VO < 5 V 10,19 VCC2 UVLO Hysteresis VUVLO_HYS 1.2 V 10 VCC2 to UVLO High Delay tPLH_UVLO 15 µs 20 VCC2 to UVLO Low Delay tPHL_UVLO 10.7 µs 21 VCC2 UVLO to VOUT High Delay tUVLO_ON 5.3 µs 22 VCC2 UVLO to VOUT Low Delay tUVLO_OFF 1.1 µs 23 Continued on next page... 11 Electrical Specifications (continued) Unless otherwise specified, all Minimum/Maximum specifications are at recommended operating conditions, all voltages at input IC are referenced to VEE1, all voltages at output IC referenced to VEE2. All typical values at TA = 25 °C, VCC1 = 12 V, VCC2-VEE2 = 20 V, VE-VEE2 = 0 V. Parameter Symbol Min Typ Max Units Test Conditions Fig. Note 19 10 Desaturation Protection (Desat voltage VDESAT reference to VE) Desat Sensing Threshold VDESAT 6.2 7.0 7.8 V Desat Charging Current ICHG -1.1 -0.9 -0.65 mA VDESAT = 2 V 20 Desat Discharging Current IDSCHG 20 53 mA VDESAT = 8 V 21 VCC2 during fault condition VCC2(FAULT) 19 V ICC2 during fault condition ICC2(FAULT) Internal Desat Blanking Time tDESAT(BLANKING) Desat Sense to 90% SSD Delay tDESAT(90%) 0.6 µs 25 Desat Sense to 10% SSD Delay tDESAT(10%) 6.0 µs 26 Desat to Low Level /FAULT Signal Delay tDESAT(/FAULT) µs 27 11.6 0.3 0.6 1.1 7.0 mA VCC2 = 20 V µs CSSD=10 nF 24 Output Mute Time due to Desat tDESAT(MUTE) 2.3 3.2 ms 28 Time for Input Kept Low Before Fault Reset to High tDESAT(RESET) 2.3 3.2 ms 29 Parameter Symbol Min. Typ. Input-Output Momentary Withstand Voltage VISO 5000 Resistance (Input-Output) RI-O Capacitance (Input-Output) Thermal coefficient between LED and input IC Package Characteristics Units Test Conditions Note VRMS RH < 50%, t = 1 min. TA = 25 °C 30, 31, 32 1014 Ω VI-O = 500 VDC 32 CI-O 1.3 pF f = 1 MHz 32 AEI 35.4 °C/W Thermal coefficient between LED and output IC AEO 33.1 °C/W Thermal coefficient between input IC and output IC AIO 25.6 °C/W Thermal coefficient between LED and Ambient AEA 176.1 °C/W Thermal coefficient between input IC and Ambient AIA 92 °C/W Thermal coefficient between output IC and Ambient AOA 76.7 °C/W 12 Max. Notes: 1. Output IC power dissipation is derated linearly above 100 °C from 580 mW to 260 mW at 125 °C. 2. This supply is optional. Required only when negative gate drive is implemented. 3. Maximum 500 ns pulse width if peak VDESAT > 10 V. 4. Maximum pulse width = 1 μs, maximum duty cycle = 1%. 5. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that input remains low until VCC1 reaches the proper operating voltage to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down. 6. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 13.5 V. 7. If DC-DC controller is not used for powering output IC. 8. For High Level Output Voltage testing, VOH is measured with a DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero. 9. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 10. Once VOUT of the ACPL-32JT is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-32JT will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VCC2 exceeds VUVLO+ threshold, DESAT will remain functional until VCC2 is below VUVLO- threshold. Thus, the DESAT detection and UVLO features of the ACPL-32JT work in conjunction to ensure constant IGBT protection. 11. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output. 12. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output. 13. Pulse Width Distortion (PWD) is defined as (tPHL – tPLH) of any given unit. 14. As measured from IF to VO. 15. Dead Time Distortion (DTD) is defined as (tPLH - tPHL) between any two ACPL-32JT parts under the same test conditions. 16. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection mode. 17. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection mode. 18. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE. 19. This is the “decreasing” (i.e. turn-off or “negative going” direction) of VCC2 - VE. 20. The delay time when VCC2 exceeds UVLO+ threshold to UVLO positive-going edge. 21. The delay time when VCC2 falls below UVLO- threshold to UVLO negative-going edge. 22. The delay time when VCC2 exceeds UVLO+ threshold to 50% of High level output. 23. The delay time when VCC2 falls below UVLO- threshold to 50% of Low level output. 24. The delay time for ACPL-32JT to respond to a DESAT fault condition without any external DESAT capacitor. 25. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions. 26. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions. 27. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage. 28. The amount of time when DESAT threshold is exceeded, Output is mute to LED input. 29. The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High. 30. In accordance with UL1577, each optocoupler is proof-tested by applying an insulation test voltage ≥ 6000 VRMS for 1 second. 31. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table. 32. Device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 33. Max 34V, 10 pulses, 400ms pulse width, 60s intervals. Thermal Characteristics are based on the ground planes layout of the evaluation PCB. 60 mm 60 mm VEE1 VEE1 40 mm 40 mm VEE2 VEE2 PCB top side Figure 7. PCB Layout of evaluation board used for thermal characterization 13 VEE1 PCB bottom side Notes on Thermal Calculation Application and environmental design for ACPL-32JT needs to ensure that the junction temperature of the internal ICs and LED within the gate driver optocoupler does not exceed 150 °C. The following equations are to calculate the maximum power dissipation and the corresponding effect on junction temperatures. LED Junction Temperature = AEA*PE + AEI*PI + AEO*PO + TA Input IC Junction Temperature = AEI*PE + AIA*PI + AIO*PO + TA Output IC Junction Temperature = AEO*PE + AIO*PI + AOA*PO + TA PE - LED Power Dissipation PI - Input IC Power Dissipation PO - Output IC Power Dissipation Calculation of LED Power Dissipation LED Power Dissipation, PE = IF(LED) (Recommended Max) * VF(LED) (125 °C) * Duty Cycle Example: PE = 16 mA * 1.25 * 50% duty cycle = 10 mW Calculation of Input IC Power Dissipation Input IC Power Dissipation, PI = PI(Static) + PI(SW) PI(Static) - static power dissipated by the input IC PI(SW) - power dissipated in the SW pin due to switching current of primary winding of transformer. It is calculated based on averaging switching current and turn-on resistance of SW. where PI(Static) = Icc1 * Vcc1 PI(SW) = Isw(avg)2 * Ron_sw(125 °C) = (ISW_PK/2 * Dmax * Vin_min/Vin)2 * Ron_sw(125 °C) The highest input power dissipation is at minimum Vin, where the average current of SW pin is highest, Vin = VCC1= VIN(min) = 8 V. PI(Static) = 6 mA * 8 V = 48 mW PI(SW) = (1.3 A/2 * 50% * 8V/8V )2 * 0.9 Ω = 95 mW PI = PI(Static) + PI(SW) = 48 mW + 95 mW =143 mW Calculation of Output IC Power Dissipation Output IC Power Dissipation, PO = VCC2 (Recommended Max) * ICC2 (Max) + PHS + PLS PHS - High Side Switching Power Dissipation PLS - Low Side Switching Power Dissipation PHS = (VCC2 * QG * fPWM) * ROH(MAX)/(ROH(MAX) + RGH)/2 PLS = (VCC2 * QG * fPWM) * ROL(MAX)/(ROL(MAX) + RGL)/2 QG – IGBT Gate Charge at Supply Voltage fPWM - LED Switching Frequency ROH(MAX) – Maximum High Side Output Impedance - VOH(MIN)/IOH(MIN) RGH - Gate Charging Resistance ROL(MAX) – Maximum Low Side Output Impedance - VOL(MIN)/IOL(MIN) RGL - Gate Discharging Resistance 14 Example: ROH(MAX) = (VCC2-VOH(MIN))/IOH(MIN) = 3.0 V / 0.75 A = 4.0 Ω ROL(MAX) = VOL(MIN)/IOL(MIN) = 2.5 V / 1 A = 2.5 Ω PHS =(20 V * 1 µC * 10 kHz) * 4.0 Ω / (4.0 Ω + 10 Ω) / 2 = 28.5 mW PLS =(20 V * 1 µC * 10 kHz) * 2.5 Ω / (2.5 Ω + 10 Ω) / 2 = 20 mW PO = 20 V * 13.6 mA + 25 mW + 20 mW = 320.5 mW Calculation of Junction Temperature LED Junction Temperature = 176.1 °C/W * 10 mW + 35.4 °C/W * 143 mW + 33.1 °C/W * 320.5 mW + TA = 17.4 °C + TA Input IC Junction Temperature = 35.4 °C/W * 10 mW + 92 °C/W * 143 mW + 25.6 °C/W * 320.5 mW + TA = 21.7 °C + TA Output IC Junction Temperature = 33.1 °C/W * 10 mW + 25.6 °C/W * 143 mW + 76.7 °C/W * 320.5 mW + TA = 28.5 °C + TA 15 60 RON_SW - SW TURN-ON RESISTANCE - Ω 1.6 D - PWM DUTY CYCLE - % 50 40 30 20 10 0 0 1 2 3 VCOMP - COMPENSATION VOLTAGE - V 4 Figure 8. PWM Duty Cycle vs. VCOMP ICC1 - INPUT SUPPLY CURRENT - mA ICOMP - COMPENSATION CURRENT - µA 5 0 -5 -15 10 15 20 VCC - SUPPLY VOLTAGE - V 0.8 0.6 0.4 0.2 0 - 50 - 25 0 25 50 75 TA - TEMPERATURE - °C 100 125 100 125 IF - FORWARD CURRENT - mA 10.8 10.7 10.6 10.5 Figure 12. ICC2 vs. temperature 25 50 75 TA - TEMPERATURE - °C 2 1 - 25 0 25 50 75 TA - TEMPERATURE - °C Ta = 25 °C 10.9 0 3 100.00 ICC2H ICC2L - 25 4 Figure 11. ICC1 vs. temperature 11.1 11 5 0 - 50 25 Figure 10. ICOMP vs. Supply Voltage ICC2 - OUTPUT SUPPLY CURRENT - mA 1 6 -40 °C 25 °C 125 °C -10 16 1.2 Figure 9. RON_SW vs. temperature 10 10.4 - 50 1.4 100 125 10.00 1.00 0.10 0.01 1.2 Figure 13. IF vs. VF 1.3 1.4 1.5 VF - FORWARD VOLTAGE - V 1.6 20 ITH+ ITH- 3.5 VOH - OUTPUT HIGH VOLTAGE - V ITH - LED CURRENT THRESHOLD - mA 4 3 2.5 2 1.5 1 - 50 - 25 0 25 50 75 TA - TEMPERATURE - °C 100 Figure 14. ITH vs. temperature 6 5 4 3 2 1 0 0.00 1.00 2.00 3.00 IOL - OUTPUT LOW CURRENT - A 4.00 4 5 TPLH TPHL 100 50 0 -50 VDESAT - DESAT SENSING THRESHOLD - V ISSD - SOFT SHUTDOWN CURRENT - mA 2 3 IOH - OUTPUT HIGH CURRENT - A - 25 0 25 50 75 TA - TEMPERATURE - °C 100 125 25 50 75 TA - TEMPERATURE - °C 100 125 Figure 17. tP vs. temperature 40 35 30 25 -40 °C 25 °C 125 °C 20 5 Figure 18. ISSD vs. VSSD 17 1 150 45 0 0 200 5.00 Figure 16. VOL vs. IOL 15 14 250 -40 °C 25 °C 125 °C 7 16 Figure 15. VOH vs. IOH TP - PROPAGATION DELAY - ns VOL - OUTPUT LOW VOLTAGE - V 8 18 12 125 - 40 °C 25 °C 125 °C 10 15 VSSD - CLAMP VOLTAGE - V 20 25 7.5 7.4 7.3 7.2 7.1 7 6.9 6.8 6.7 6.6 6.5 - 50 - 25 0 Figure 19. VDESAT Threshold vs. temperature IDSHG - DESAT DISCHARGING CURRENT - mA -0.75 -0.8 -0.85 -0.9 -0.95 -1 - 50 - 25 0 25 50 75 TA - TEMPERATURE - °C 100 125 Figure 20. ICHG vs. temperature Signal Source 5V Vsource 0V 0 25 50 75 TA - TEMPERATURE - °C 100 125 VEE2 SW LED2+ VCC1 DESAT COMP VE /UVLO VCC2 /FAULT Rf - 25 Figure 21. IDCHG vs. temperature VEE1 260 Ω 70 65 60 55 50 45 40 35 30 25 20 - 50 Vsource 0.1 µF 10 Ω VO AN SSD/CLAMP CA VEE2 Vo Rg Cload 10 nF _ + ICHG - DESAT CHARGING CURRENT - mA -0.7 20 V tPLH tPHL 50% VO Figure 22. Propagation Delay Test Circuit VEE1 SW + - 130R 5V 130R VEE2 LED2+ VCC1 DESAT COMP VE /UVLO VCC2 /FAULT VO AN SSD/CLAMP CA VEE2 + VEE2 VEE1 0.1 µF _ + 20 V Scope 130R 10R 10 nF 130R - For product information and a complete list of distributors, please go to our web site: LED2+ VCC1 DESAT COMP VE /UVLO VCC2 AN SSD/CLAMP CA VEE2 + Figure 24. CMR Vo Low Test Circuit www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-4256EN - March 23, 2015 0.1 µF _ + 20 V Scope VO /FAULT - High Voltage Pulse V CM = 1500 V High Voltage Pulse V CM = 1500 V Figure 23. CMR Vo High Test Circuit SW 10R 10 nF