LM96511 LM96511 Ultrasound Receive Analog Front End (AFE) Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SNAS476H May 2010 – Revised May 2013 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Contents 1 INTRODUCTION 1.1 1.2 1.3 2 3 4 5 6 2 .................................................................................................................. 6 FEATURES .................................................................................................................. 6 APPLICATIONS ............................................................................................................. 6 DESCRIPTION .............................................................................................................. 6 ........................................................................................................ 7 2.1 KEY SPECIFICATIONS .................................................................................................... 7 2.2 Simplified LM96511 Block Diagram ...................................................................................... 8 2.3 Typical Application .......................................................................................................... 8 2.4 Connection Diagrams ...................................................................................................... 9 ELECTRICAL SPECIFICATIONS .......................................................................................... 15 3.1 Absolute Maximum Ratings .............................................................................................. 15 3.2 Operating Ratings ......................................................................................................... 15 3.3 AFE Electrical Characteristics (B-Mode) ............................................................................... 16 3.4 CW Doppler Electrical Characteristics .................................................................................. 18 3.5 LNA Electrical Characteristics ........................................................................................... 19 3.6 DVGA Electrical Characteristics ......................................................................................... 20 3.7 ADC Electrical Characteristics ........................................................................................... 21 3.8 Digital Input and Output Characteristics ................................................................................ 22 GENERAL DIAGRAMS ........................................................................................................ 24 4.1 TIMING DIAGRAMS ...................................................................................................... 24 TYPICAL PERFORMANCE CHARACTERISTICS ..................................................................... 27 5.1 General Typical Performance Characteristics ......................................................................... 27 5.2 CW Doppler Plots ......................................................................................................... 30 OVERVIEW ....................................................................................................................... 32 6.1 LNA INPUT AMPLITUDE RANGE ...................................................................................... 32 6.2 TYPICAL INPUT CONFIGURATION ................................................................................... 33 6.3 PROGRAMMABLE INPUT IMPEDANCE & LNA GAIN SELECTION .............................................. 34 6.4 OFFSET SOFT-TRIM ..................................................................................................... 35 6.5 DYNAMIC RANGE ........................................................................................................ 36 6.6 DVGA OPERATION ....................................................................................................... 36 6.6.1 DVGA Half Step Mode ......................................................................................... 40 6.6.2 DVGA CLK Pin .................................................................................................. 40 6.6.3 CW/DVGA RST Pin ............................................................................................ 41 6.6.4 DVGA UP Pin: .................................................................................................. 41 6.6.5 DVGA Accelerated Gain Adjustment: ........................................................................ 41 6.7 THE LM96511 ADC ....................................................................................................... 42 6.8 ADC OUTPUT INTERFACE ............................................................................................. 43 6.9 12–BIT SIGMA DELTA (ΣΔ) ADC CORE .............................................................................. 43 6.10 INSTANT OVERLOAD RECOVERY .................................................................................... 44 6.11 USING IOR ON MODE ................................................................................................... 44 6.11.1 Standard Use of IOR On Mode ............................................................................... 44 6.11.2 Advanced Use of IOR On Mode .............................................................................. 44 6.12 INTEGRATED PRECISION LC PLL ADVANTAGES ................................................................. 45 6.13 DIGITAL DECIMATION FILTER AND EQUALIZER .................................................................. 45 6.14 OUTPUT CLOCK SYNCHRONIZATION ACROSS MULTIPLE CHIPS ............................................ 46 6.15 CAPACITOR SELECTION ............................................................................................... 46 6.16 ADC OUTPUT CONSIDERATIONS .................................................................................... 47 6.16.1 Output Driving Voltage, ADC IO DVDD ...................................................................... 47 6.16.1.1 Output Modes and Output Common Mode ..................................................... 47 6.16.1.2 Termination ......................................................................................... 47 6.16.1.3 LVDS Output Training Sequences ............................................................... 48 DEVICE INFORMATION Contents Copyright © 2010–2013, Texas Instruments Incorporated LM96511 www.ti.com 6.17 6.18 6.19 6.20 6.21 6.22 SNAS476H – MAY 2010 – REVISED MAY 2013 The Voltage Reference ................................................................................................... CW Doppler Section Theory of Operation ............................................................................. 6.18.1 CW DOPPLER NOISE ANALYSIS ........................................................................... 6.18.2 CW DOPPLER 16x LO SOURCE IMPLEMENTATION ................................................... LM96511 Power Management ........................................................................................... 6.19.1 POWER-UP SEQUENCING .................................................................................. SPI™ Interface ............................................................................................................. 6.20.1 THE SERIAL PERIPHERAL INTERFACE .................................................................. 6.20.2 ACCESS TO THE SERIAL PERIPHERAL INTERFACE .................................................. 6.20.3 CONNECTING MULTIPLE LM96511 DEVICES TOGETHER ........................................... 6.20.4 SERIAL PERIPHERAL INTERFACE READ AND WRITE SPEED ...................................... SPI™ Register Map ....................................................................................................... SPI™ Register Map Notes ............................................................................................... Revision History 48 49 52 53 54 55 56 56 56 57 58 58 61 ......................................................................................................................... 70 Copyright © 2010–2013, Texas Instruments Incorporated Contents 3 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com List of Figures 2-1 Simplified LM96511 Block Diagram ............................................................................................. 8 2-2 8-Channel Transmit/Receive Chipset ........................................................................................... 9 2-3 376–Pin NFBGA Package (18 Rows by 32 Columns) See Package Number NZJ0376A .............................................................................................. 10 2-4 376–Pin NFBGA Package (18 Rows by 32 Columns) See Package Number NZJ0376A .............................................................................................. 10 4-1 B-Mode ADC Data Output Timing.............................................................................................. 24 4-2 B-Mode ADC Data Output Level Definitions .................................................................................. 25 4-3 CW CLK Level Definitions....................................................................................................... 25 4-4 SPI™ Write Timing ............................................................................................................... 25 4-5 SPI™ Read Timing............................................................................................................... 26 4-6 CW/DVGA RST Timing (CW Doppler Mode) ................................................................................. 26 6-1 Ultra-Sound System Block Diagram ........................................................................................... 32 6-2 Signal Path (B-Mode) Single Channel Including Input Clamp and Diode Bridge ...................................................................................... 33 6-3 Standard Input Termination ..................................................................................................... 34 6-4 Active Termination Schematic .................................................................................................. 35 6-5 Offset Distribution Histogram including Soft-Trim Improvement ........................................................... 35 6-6 LM96511 in Typical TGC Operation at 5MHz ................................................................................ 36 6-7 Periodic TGC Ramp: Example 1 (Half-Step Disable bit = 1) ............................................................... 37 6-8 DVGA UP bit Change (Half-Step Disable bit = 1) ............................................................................ 38 6-9 Periodic TGC Ramp: Example 2 (Half Step Disable bit = 1) ............................................................... 38 6-10 Basic Gain Adjustment (Half Step Disable Bit = 1) .......................................................................... 39 6-11 Accelerated Gain Adjustment (Half Step Disable bit = 1) ................................................................... 39 6-12 Gain Reset with DVGA UP bit = 0 ............................................................................................. 40 6-13 DVGA Gain control “Micro Illustration” of the Gain Stair Case ............................................................. 40 6-14 LM96511 ADC Block Diagram .................................................................................................. 42 6-15 ADC WCLK 6-16 6-17 6-18 6-19 6-20 6-21 6-22 6-23 6-24 6-25 6-26 6-27 6-28 6-29 6-30 4 ....................................................................................................................... PLL Phase Noise Transfer Function: ADC CLK = 40 MHz ................................................................. Digital Filter Transfer Function ................................................................................................. DAC LPF Capacitor .............................................................................................................. LVDS Training Sequence ....................................................................................................... Reference Sharing ............................................................................................................... Signal Path (CW Doppler) Single Channel ................................................................................... I-V with Integrated 2–Pole LFP ................................................................................................. CW Doppler LPF Gain/Phase Characteristics ................................................................................ CW Doppler Output (I or Q) Implementation (64 Receive Channels) ..................................................... CW Doppler Low-Phase Noise Clock Source Design ....................................................................... LM3881 Power Sequencer Can be Used for Proper LM96511 Power-Up ............................................... SPI™ Bus Master Slave Connection .......................................................................................... SPI™ Compatible Read/Write Timing Diagram .............................................................................. SPI™ Compatible Interconnect for Multiple LM96511's (Open Drain Mode) ............................................. CW Doppler Shadow Register Representation............................................................................... List of Figures 43 45 46 47 48 49 50 50 51 53 54 56 56 57 58 67 Copyright © 2010–2013, Texas Instruments Incorporated LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 List of Tables ................................................................................................................. 2-1 Pin Descriptions 6-1 ADC Output Mode Summary ................................................................................................... 47 6-2 LM96511 Power Consumption for Various Conditions ...................................................................... 54 6-3 Recommended Operating Conditions ......................................................................................... 56 6-4 DVGA Initial Attenuation Truth Table .......................................................................................... 68 6-5 DVGA Notation ................................................................................................................... 68 6-6 Offset Trim “Write” Truth Table ................................................................................................. 69 6-7 Offset Trim “Write” and “Read” Example ...................................................................................... 69 Copyright © 2010–2013, Texas Instruments Incorporated List of Tables 11 5 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com LM96511 Ultrasound Receive Analog Front End (AFE) Check for Samples: LM96511 1 INTRODUCTION 1.1 FEATURES 12 • 8-Channel LNA, DVGA, and 12-bit Continuous Time ΣΔ ADC • Programmable Active Termination LNA • 8-channel, Integrated CW Doppler Beamforer • Low-Power Consumption 1.2 • • • • • • • • Embedded ADC Digital Filter ADC Instant Overload Recovery Embedded ADC “Clock-Cleaning” PLL 11 mm x 17 mm RoHS NFBGA Package APPLICATIONS Ultrasound Imaging Communications Portable Instrumentation Sonar 1.3 DESCRIPTION The LM96511 is an 8-channel integrated analog front end (AFE) module for multi-channel applications, particularly medical ultrasound. Each of the 8 signal paths consists of a low noise amplifier (LNA), a digitally programmable variable gain amplifier (DVGA) and a 12-bit, 40 Mega Samples Per Second (MSPS) analog-to-digital converter (ADC) with Instant Overload Recovery (IOR). The architecture of the DVGA is a digitally-controlled linear-in-dB step attenuator driving a fixed-gain post-amplifier (PA). The ADC uses a Continuous-Time-Sigma-Delta (CTΣΔ) architecture with digital decimation filtering to maximize dynamic performance and provide an alias free input bandwidth to ADC CLK / 2. The ADC digital outputs are serialized and provided on differential LVDS outputs. The ADC includes an on-chip clock cleaner PLL. In addition, for baseband CW Doppler Beamformer applications, an 8-channel demodulator with 16 discrete phase rotation angles is included. Selective power reduction is included to minimize consumption of idle sections during interleaved imaging modes. An SPI™ compatible serial interface allows dynamic digital programming and control. Texas Instruments offers a full development package for sale which includes acquisition analysis hardware and software with user friendly GUI for device programming and control. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010–2013, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. LM96511 www.ti.com 2 DEVICE INFORMATION 2.1 KEY SPECIFICATIONS SNAS476H – MAY 2010 – REVISED MAY 2013 VALUE UNIT (Full path unless noted) B-Mode: Total Input Voltage Noise (RTI) 0.9 nV/vHz Max AFE Gain 58 Single-Ended Input Swing 500mVpp Programmable Maximum DVGA Attenuation 38, 36, 34, 32 dB Programmable Post Amp Gain 31 or 38 dB Attenuator Step Resolution 0.05 or 0.1 dB ADC Resolution 12 bits Conversion Rate (ADC CLK) 40 MSPS ADC Digital Filter stop band attenuation 72 dB ADC Digital Filter Passband Ripple ± 0.01 dB ADC Instant Overload Recovery 1 ADC Clock Period Power Consumption (per channel) 110 mW dB CW Doppler Mode: Phase Rotation Resolution 22.5 degrees Phase Noise (Per Channel, Offset = 5KHz) -144 dBc/Hz Dynamic Range -161 dB/Hz Amplitude Quadrature Error (I to Q) ± 0.04 Phase Quadrature Error (I to Q) ± 0.10° Power Consumption (Per Channel) 208 mW dB Common Specifications: LNA Input Voltage Noise 0.82 nV/vHz Operating temp. Range 0 to +70°C DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 7 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 2.2 www.ti.com Simplified LM96511 Block Diagram DVGA LNA IN CH0+ Attenuator Attenuator LNA LNA ADC DOUT CH0+ 6' CT6' CT ADC ADC Post Post AmpAmp - LNA IN CH0- 12b 12 Serializer Serializer 1b 1b LVDS LVDS SLVS SLVS ADC DOUT CH0- B - Mode Mode CW Doppler (D - Mode) XX CW I CH0 XX CW Q CH0 Channel 0 Channel Channel Channel 7 22 22 00°° 90 ° 90° Divide by 16 & Phase Shift To ToRegisters Registers Reference Reference & Bias SPI SPI ADC WCLK+ PLL && CMU PLL CMU ADC WCLKADC BCLK+ ADC CLK- ADC CLK+ ADC SPI CS* SPI DIO AMS SPI CS* SPI CLK CW/DVGA RST DVGA CLK DVGA UP CW CLK- CW CLK+ ADC BCLK- Figure 2-1. Simplified LM96511 Block Diagram 2.3 Typical Application Figure 2-2. 8-Channel Transmit/Receive Chipset 8 DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com 2.4 SNAS476H – MAY 2010 – REVISED MAY 2013 Connection Diagrams Top View Figure 2-3. 376–Pin NFBGA Package (18 Rows by 32 Columns) See Package Number NZJ0376A DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 9 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Top View Figure 2-4. 376–Pin NFBGA Package (18 Rows by 32 Columns) See Package Number NZJ0376A 10 DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Table 2-1. Pin Descriptions Ball Id. (Row_Column) Pin Name Function Description Amplifier Signals U1 LNA IN CH0+ R1 LNA IN CH1+ N1 LNA IN CH2+ L1 LNA IN CH3+ J1 LNA IN CH4+ G1 LNA IN CH5+ E1 LNA IN CH6+ D2 LNA IN CH7+ V1 LNA IN CH0- T2 LNA IN CH1- P2 LNA IN CH2- M2 LNA IN CH3- K2 LNA IN CH4- H2 LNA IN CH5- F2 LNA IN CH6- D1 LNA IN CH7- V2 LNA OUT CH0- T1 LNA OUT CH1- P1 LNA OUT CH2- M1 LNA OUT CH3- K1 LNA OUT CH4- H1 LNA OUT CH5 - F1 LNA OUT CH6- D4 LNA OUT CH7- V8 DVGA BYP CH0 T17 DVGA BYP CH1 R16 DVGA BYP CH2 L15 DVGA BYP CH3 J17 DVGA BYP CH4 D16 DVGA BYP CH5 C15 DVGA BYP CH6 B9 DVGA BYP CH7 J14 J15 CW CLK+ CW CLK- V10 CW I CH0 V14 CW I CH1 P15 CW I CH2 M16 CW I CH3 G16 CW I CH4 E15 CW I CH5 B16 CW I CH6 A11 CW I CH7 LNA Non-Inverting Input Input LNA Inverting Input Output LNA Inverting Output Bypass Decoupling Capacitor to Analog Ground Input CW DOPPLER Differential Input Clock + CW DOPPLER Differential Input Clock - Output CW DOPPLER In-Phase output current DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 11 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Table 2-1. Pin Descriptions (continued) Ball Id. (Row_Column) Pin Name Function Description U10 CW Q CH0 V17 CW Q CH1 P17 CW Q CH2 N14 CW Q CH3 G14 CW Q CH4 F14 CW Q CH5 A17 CW Q CH6 B11 CW Q CH7 K14 DVGA CLK DVGA GAIN Clock L17 DVGA UP 1 = Increment DVGA gain 0 = Decrement DVGA gain A6 DVGA INIT MSB B5 DVGA INIT LSB Output CW DOPPLER Quadrature-Phase output current Amplifier Controls K15 CW/DVGA RST K16 AMP CW/DVGA DVGA Initial Gain Control. Sets the initial DVGA gain. See Section 6. Input 1 = CW DOPPLER Phase and DVGA Gain Reset 0 = B-mode 1 = CW DOPPLER mode A1 LNA PD A2 DVGA PD 1 = LNA Power-down 1 = DVGA Power-down A3 AMP RST 1 = Reset all Amplifier SPI™ Registers B1 DVGA PA HI Post Amplifier Gain: 1= 38 dB 0= 31 dB ADC Signals B22 A22 ADC CLK+ ADC CLK- V31 ADC DOUT CH0+ U32 ADC DOUT CH1+ P32 ADC DOUT CH2+ L32 ADC DOUT CH3+ J32 ADC DOUT CH4+ G32 ADC DOUT CH5+ E32 ADC DOUT CH6+ C32 ADC DOUT CH7+ V32 ADC DOUT CH0- T32 ADC DOUT CH1- N32 ADC DOUT CH2- K32 ADC DOUT CH3- H32 ADC DOUT CH4- F32 ADC DOUT CH5- D32 ADC DOUT CH6- B32 ADC DOUT CH7- 12 Input Differential Input Clock. The input clock must lie in the range of 40 to 40.5 MHz. It is used by the PLL to generate the internal sampling clocks. Output Differential Serial Outputs for channels 0 to 7. Each pair of outputs provides the serial output for the specific channel. The default output is LVDS format, but programming the appropriate control registers, the output format can be changed to SLVS . By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100Ω resistors. DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Table 2-1. Pin Descriptions (continued) Ball Id. (Row_Column) A30 A29 Pin Name Function ADC WCLK+ ADC WCLK- Output A32 A31 ADC BCLK+ ADC BCLK- Description Word Clock. Differential output frame clock used to indicate the bit boundary of each data sample. Information on timing can be seen in Electrical Characteristics. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100Ω resistors. Bit clock. Differential output clock used for sampling the serial outputs. Information on timing can be seen in Electrical Characteristics. By programming TX_term (bit 4) in the LVDS Control register, it is possible to internally terminate these outputs with 100Ω resistors. ADC Controls This pin is an active low reset for the entire ADC, both analog and digital components. The pin must be held low for 500 ns then returned to high in order to ensure that the chip is reset correctly. U25 _______ ADC RST V26 ADC CW/DVGA V22 ADC VREF V21 ADC VREF GND U23 ADC RREF Output External 10k ±1% resistor to ADC Analog GND. Used to set internal bias currents. Required regardless of the type of reference used. V23 ADC LPF BYP Bypass Capacitor required by the Modulator DAC's LP Filter. Must be at least 100 nF to ADC Analog GND. Can be increased to 10 µF to minimize close-in phase noise. Input 0 = B-mode 1 = CW DOPPLER mode, PLL and References are still active to minimize recovery time. Input ADC Optional External Reference Voltage; Improves channel-tochannel and converter-to-converter matching. If Internal Reference is used, connect to AGND. SPI™ Compatible Interface B3 SPI™ CLK Input B4 SPI™ DIO Input/Output A5 __________ ADC SPI™ CS A4 __________ AMP SPI™ CS SPI™ clock SPI™ Data Input/Output 0 = ADC SPI™ Chip Select Input 0 = Amplifier SPI™ Chip Select. Power and Ground A10, B8, C16, C17, D14, D15, D17, E4, E14, G3, J3, J16, K17, L3, L16, M4, N4, R3, R14, R15, T4, T14, T15, U4, U7, U8, U13, V4, V6, V13 AMP AVCC A B10, B14, B15, C14, E16, E17, H15, G15, M14, M15, P16, R17, T16, U9, U16, V9, B2, C2, E2, F4, G4, H4, J4, K4, L4, N2, P4, T3 CW AVCC V5, A7, B7, H16, H17, U14, U15 AMP DVDD B6, L14 Amplifier Analog Power Nominally +3.3V. CW DOPPLER Analog Power Nominally +5.0V. Power DVGA Digital Power. Nominally +3.3V. AMP IO DVDD Amplifier IO Digital Power. Connect to ADC IO DVDD. Nominally +1.2V. B30, G31, H31, U31 ADC IO DVDD ADC IO Digital Power. Nominally +1.2V. A19, C18, F18, J18, M19, R19, U19, U24, U26, U28, V27, V29 ADC AVDD ADC Analog Power. Nominally +1.2V. A26, B25, B26, U27, V28 ADC DVDD ADC Digital Power. Nominally +1.2V . DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 13 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Table 2-1. Pin Descriptions (continued) Ball Id. (Row_Column) Pin Name A9, A12, A13, A16, A23, A24, A25, B17, B19, B20, B21, B23, B24, B29, B31, C3, C19, C31, D3, D18, D19, F3, F17, F19, F31, G17, G18, G19, H3, J19, J31, K3, K19, K31, L18, L31, M3, M17, M18, M32, N17, N18, P3, P14, P18, P31, R4, R18, R31, T18, T19, U3, U6, U12, U21, U22, U30, V3, V11, V12, V15, V19, V24, V25 AGND F7, F8, F9, F10, F11, G7, G8, G9, G10, G11, H7, H8, H9, H10, H11, J7, J8, J9, J10, J11, K7, K8, K9, K10, K11, L7, L8, L9, L10, L11, M7, M8, M9, M10, M11, N7, N8, N9, N10, N11 AMP THRM GND F23, F24, F25, F26, F27, G23, G24, G25, G26, G27, H23, H24, H25, H26, H27, J23, J24, J25, J26, J27, K23, K24, K25, K26, K27, L23, L24, L25, L26, L27. M23, M24, M25, M26, M27, N23, N24, N25, N26, N27 Description Analog Ground Ground Thermal Ground (Connect to AGND) ADC THRM GND A14, A15, B12, B13, F15, F16, N15, N16, U11, V16 CW DGND A8, H14, U5, U17 AMP DGND A27, A28, B27, B28, D31, E31, M31, N31, U29, V30 Function Digital Ground ADC IO DGND No Connect Important: “NC” pins should be left unconnected. Any connection to these pins could affect performance and functionality. A18, A20, A21, B18, C1, E3, E18, E19, G2, H18, H19, J2, K18, L2, L19, N3, N19, P19, R2, U2, U18, U20, V18, V20, R32, T31, V7, C4 14 NC Do Not Connect DEVICE INFORMATION Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 3 ELECTRICAL SPECIFICATIONS 3.1 Absolute Maximum Ratings (1) (2) Supply Voltage (CW AVCC) -0.3V and +6V Supply Voltage (AMP AVCC A, AMP DVDD) -0.3V and +3.63V Supply Voltage (ADC AVDD, ADC DVDD) -0.3V and +1.44V IO Supply Voltage (AMP IO DVDD, ADC IO DVDD) -0.3V and +2.0V Voltage at Analog Inputs -0.3V and +2.0V Voltage at SPI™ Compatible inputs (SPI™ CLK, SPI™ DIO, AMP SPI™ CS, ADC SPI™ CS) -0.3V and +2.0V Input Current at any pin other than a Supply Voltage and LNA Inputs LNA Inputs (1) (2) 3.2 25 mA 2.6 Vpp & ±10 mA Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. Operating Ratings indicate conditions for which the device is specified to be functional, but do not specify specific performance limits. Specifications and test conditions are specified in the Electrical Characteristics sections below. Operations of the device beyond the Operating Ratings is not recommended as it may degrade the lifetime of the device. All voltages are measured with respect to GND = AGND = DNGD = 0V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Operating Ratings (1) Operation Temperature Range 0°C to + 70°C Supply Voltage (CW AVCC) +4.75V to +5.25V Supply Voltage (AMP AVCC A, AMP DVDD) +3.13V to 3.47V Supply Voltage (ADC AVDD, ADC DVDD) +1.14V to +1.26V IO Supply Voltage (AMP IO DVDD, ADC io DVD) +1.14V to +1.89V SPI™ Compatible Inputs (SPI™ CLK, SPI™ DIO, AMP SPI™ CS, ADC SPI™ CS) +1.14V to +1.89V ADC CLK Input Frequency 40 MHz ADC CLK Duty Cycle 30 to 70% DVGA CLK Frequency < 100 MHz Ground Difference |AGND - DGND| ESD Tolerance (2): (1) (2) 50 mV Human Body Model 1500V Machine Model 100V Charge Device Model 750V Absolute maximum ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the device should be operated at these limits. Operating Ratings indicate conditions for which the device is specified to be functional, but do not specify specific performance limits. Specifications and test conditions are specified in the Electrical Characteristics sections below. Operations of the device beyond the Operating Ratings is not recommended as it may degrade the lifetime of the device. All voltages are measured with respect to GND = AGND = DNGD = 0V, unless otherwise specified. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 15 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 3.3 www.ti.com AFE Electrical Characteristics (B-Mode) Unless otherwise noted, specified limits apply for AMP AVCC A = 3.3V, CW AVCC = 5V, AMP IO DVDD = ADC IO DVDD = 1.2V, ADC AVDD = ADC DVDD = 1.2V, Full Scale ADC Output with RF Input at 5 MHz, DVGA PA HI = LO; AMP CW/DVGA pin = ADC CW/DVGA pin = LO, FCLK = 40 MSPS; Clock duty cycle stabilization enabled; IOR On Mode. All 8 channels powered. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Conditions Min Typ Max Units Total Input (RTI) Voltage Noise See , No Active Feedback, Input AC shorted to ground 0.9 nV/√Hz Noise Figure Equivalent 50Ω termination using Active Feedback (RFB = 301Ω) 3.7 dB Single-Ended LNA Input Swing 1 dB SNR Loss (TGC in Operation). (1) (2) Externally Programmable Input Resistance Range (overall) Offset Related Full Scale Amplitude Loss 380 50 Max DVGA Gain. 1δ (3) Max DVGA Gain, IOR Off Mode. 1δ, mVPP Ω 2k -0.23 (3) dB -0.15 Offset Tempco -0.22 LSB/ ºC Max DVGA Gain, Error < ±1% 1/fCLK seconds Max DVGA Gain, Error < ±1% 1/fCLK Ch-Ch Gain Match Worst case across DVGA Gain Range ± 0.06 ±0.2 dB Ch-Ch Phase Match Worst case across DVGA Gain Range ±0.35 ±0.75 ºC ±0.20 ±0.80 ns Overload Recovery Ch-Ch Group Delay Match Ch-Ch Crosstalk Bandwidth Min DVGA Gain. (4) -61 Min DVGA Gain. (4) -62 Min DVGA Gain. (4) dBc -62 -3 dB, Small Signal Mid DVGA gain, -6dB FS, DVGA PA HI pin= LO seconds fCLK/2 60 MHz 63 Mid DVGA gain, -1dB FS, DVGA PA HI pin= LO 62 Mid DVGA gain, -6dB FS, DVGA PA HI pin= HI 57 Mid DVGA gain, -1dB FS, DVGA PA HI pin= HI 56 fin = 5 MHz, -6dBFS, Mid DVGA Gain -72 fin = 5 MHz, -1dBFS, Mid DVGA Gain -68 fin = 5 MHz, -6dBFS, Mid DVGA Gain -52 fin = 5 MHz, -1dBFS, Mid DVGA Gain -43 DVGA Clock Feedthrough DVGA CLK frequency = 7.5MHz -95 dBFS Spurious Noise near fin, fin ± (3/8 x fin) fin = 2 to 20 MHz -84 dBFS -83 dBFS fin = 5 MHz, -6 dBFS, Mid DVGA Gain 88 dBFS fin = 5 MHz, -1 dBFS, Mid DVGA Gain 82 Active Mode, IO DVDD = 1.2V 880 Active Mode, IO DVDD = 1.8V 905 Power Down 50 SNR HD2 HD3 Spurious Noise near 2fin, 2 x fin ± (3/4 x fin) SFDR Power Consumption (1) (2) (3) 16 -60 dBFS dBFS 910 mW The LNA non-inverting input is always driven single-ended. The inverting input is always AC grounded. See Section 6 for typical connection diagrams in Figure 6-2. Please take note of the LNA Input Amplitude Range information described in the Section 6.1 Maximum expected full scale amplitude loss due to DC offset (minimum DVGA attenuation): = 20 x log (4) dBFS §212 - |Offset (LSB)| · ¸ ¨ 12 2 ¹ © For Further information, refer to Section 6.4. One channel with active input and the worst of the other 7 channels measured. ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 AFE Electrical Characteristics (B-Mode) (continued) Unless otherwise noted, specified limits apply for AMP AVCC A = 3.3V, CW AVCC = 5V, AMP IO DVDD = ADC IO DVDD = 1.2V, ADC AVDD = ADC DVDD = 1.2V, Full Scale ADC Output with RF Input at 5 MHz, DVGA PA HI = LO; AMP CW/DVGA pin = ADC CW/DVGA pin = LO, FCLK = 40 MSPS; Clock duty cycle stabilization enabled; IOR On Mode. All 8 channels powered. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Power Supply Current Wake-up Time (5) Conditions Min Typ AMP AVCC = 3.3V 155 AMP DVDD = 3.3V 1.6 CW AVCC = 5.0V 3.2 ADC AVDD = 1.2V 147 ADC DVDD = 1.2V 104 IO DVDD = 1.2V 35 From Stand-By (From CW DOPPLER to B Mode when AMP CW/DVGA pin is switched from HI to LO). See (5) 15 Max Units mA mA 20 µs “Wake up” time defined as the time it takes the output (or its digital representation) to reach within 10% of expected. ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 17 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 3.4 www.ti.com CW Doppler Electrical Characteristics Unless otherwise noted, specified limits apply for AMP AVCC A = 3.3V, CW AVCC = 5V, AMP IO DVDD = ADC IO DVDD = 1.2V, ADC AVDD = ADC DVDD = 1.2V; Full Scale ADC Output with RF Input at 5 MHz; CW CLK = 80 MHz (LVPECL levels), AMP CW/DVGA pin = ADC CW/DVGA = HI. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Conditions Min Typ Max Units Phase Noise fOFFSET = 5kHz with LNA Input = 240 mVPP @ 5 MHz. See (1) -144 Dynamic Range (DNR) IP1dB referred to RTI Noise -161 dB/Hz 1.2 nV/√Hz RTI Noise dBc/Hz Single-Ended LNA Input Swing 1dB Compression (CW Doppler Mode). (IP1dB). (2) & (3) 500 mVPP Phase Rotation Resolution 16 dynamically selectable angles 22.5 degrees Phase Temperature Coefficient I or Q. See ±20 milli°C Phase Quadrature Accuracy I to Q. ±6δ. See ± 0.10 ºC (4) (4) (5) Phase Match I to I or Q to Q. See Amplitude Match I to Q. See (6) Amplitude Temperature Coefficient I or Q. See (4) (6) (5) (5) & (7) CW CLK Input Freq Range See RF Input Freq Range CW CLK = 16 x RF Input frequency. See (7) ±0.35 ºC ±0.04 dB ±11 mdB/°C 12 240 MHz 0.7 15 MHz Equal tones (f1 = 10 KHz offset, f2 = 15 KHz offset). See (8) -72 Unequal tones. (f1 = 10 KHz offset, f2 = 15 KHz offset). See (8) -50 Channel-to-Channel Crosstalk “I” or “Q” output of undriven channel relative to driven channel -95 Output Signal Current I or Q, Per Channel, LNA Input = 380mVPP Output Noise Current Density fOFFSET = 5KHz with no LNA Input Third order IMD (IMD3) ±3.9 (1) (2) (3) (4) (5) (6) (7) (8) dBc ±4.2 ±4.5 53 Output Compliance Range Output Impedance dBc DC to 50 kHz mA pA/√Hz 2.1 to 3.6 V 100k Ω Per 1 Hz BW, offset 1 kHz from a 5 MHz, FS input. Output Phase noise, expressed in - dBc/Hz, follows both RF input and CW CLK phase noise. To meet the demodulated Output specification, integrated phase noise of both the RF Input signal and CW CLK must be better than -160 dBc/Hz at 1 kHz offset. The LNA non-inverting input is always driven single-ended. The inverting input is always AC grounded. See Section 6 for typical connection diagrams in Figure 6-2. Please take note of the LNA Input Amplitude Range information described in the Section 6.1 Within one channel Ensured by characterization for all phases. Channel-to-Channel This parameter is specified by design and/or characterization and is not tested in production. Intermodulation Distortion with unequal tones performed using (ΔP = 25 dB). 80.00 MHz Wenzel Attenuator +3.3V Minicircuits 2.1k ADT1-1 1.2k 0.1 PF 0.1 PF ?P 50 2.1k +3.3V TeK AFG3252 Attenuator1 (dB) 0 25 Attenuator2Attenuator1 (dB) 0 25 fIN1 TeK AFG3252 Attenuator2 fIN2 IMD3 CW CLK- CW CLK+ CW I Chx or CW Q Chx CI_V RI_V LM96511 ?f f1 - ?f f1 f2 f2 + ?f 330 Splitter/ Combiner 5.015 MHz 18 100 2.2 nF 310 CFB RFB 5.010 MHz 'P 1.2k + - 100 nF LNA + Audio Precision AP2700 100 nF ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 CW Doppler Electrical Characteristics (continued) Unless otherwise noted, specified limits apply for AMP AVCC A = 3.3V, CW AVCC = 5V, AMP IO DVDD = ADC IO DVDD = 1.2V, ADC AVDD = ADC DVDD = 1.2V; Full Scale ADC Output with RF Input at 5 MHz; CW CLK = 80 MHz (LVPECL levels), AMP CW/DVGA pin = ADC CW/DVGA = HI. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Power Consumption 3.5 Typ Max Active Mode (ADC CW/DVGA pin = HI) Conditions Min 1.66 1.70 Power Down 0.05 Units W LNA Electrical Characteristics Parameter Conditions Min Typ (1) Max Input Voltage Noise See Input Current Noise RS=50Ω, f=1Mhz, No Active Termination, See (1) 5 Input Capacitance Each Input to ground 17 pF 500 mV p-p 3 Vp-p Single-Ended Input Swing 0.82 Units 1 dB Compression. See pA/√Hz (1) (2) Max Differential Output Swing HD2 HD3 fin = 5MHz, -6dBFS out, Minimum DVGA Gain -55 1.65 LNA Gain Single-ended In to Differential Out Power Consumption Total, 8 channels Active Power Up Time From Power-Down mode (2) dBc -52 Output VCM (1) nV/√Hz 19 20 V 21 280 10 dB mW µs The LNA non-inverting input is always driven single-ended. The inverting input is always AC grounded. See Section 6 for typical connection diagrams in Figure 6-2. Please take note of the LNA Input Amplitude Range information described in the Section 6.1 ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 19 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 3.6 www.ti.com DVGA Electrical Characteristics Unless otherwise noted, specified limits apply for AMP AVCC A = AMP DVDD = 3.3V; “half-step” enabled (SPI™ Register 1Ah[3] = 1), fin = 5MHz. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Post Amp Gain Selectable DVGA Initial Attenuation (See Table 6-4) Attenuation Steps Attenuation error from nominal Min Typ Max DVGA PA HI = HI Conditions 36.0 38.0 40.0 DVGA PA HI = LO 28.4 31 32.4 DVGA UP pin = HI CW/DVGA RST pin = HI DVGA INIT MSB pin = LO DVGA INIT LSB pin= LO 36.0 38.0 40.0 DVGA UP pin = HI CW/DVGA RST pin = HI DVGA INIT MSB pin = LO DVGA INIT LSB pin= HI 34.0 36.0 38.0 DVGA UP pin = HI CW/DVGA RST pin = HI DVGA INIT MSB pin = HI DVGA INIT LSB pin= LO 32.0 34.0 36.0 DVGA UP pin = HI CW/DVGA RST pin = HI DVGA INIT MSB pin = HI DVGA INIT LSB pin= HI 30.0 32.0 34.0 DVGA UP pin = LO CW/DVGA RST pin = HI DVGA INIT MSB pin = X DVGA INIT LSB pin= X -1.6 0 2.4 SPI™ Register 1Ah[3] = 0 0.05 SPI™ Register 1Ah[3] = 1 0.1 See (1) Attenuator step error from 0.05dB PA Input Noise Power-Up Time (1) 20 From Power-Down mode Units dB dB dB ±0.15 dB ±20 mdB 3.6 nV/√Hz 0.1 µs “Nominal” attenuation defined as straight line connecting minimum attenuation (0dB) to maximum attenuation (38dB). ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com 3.7 SNAS476H – MAY 2010 – REVISED MAY 2013 ADC Electrical Characteristics Unless otherwise noted, specified limits apply for ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = 1.2V; FCLK = 40 MSPS; Clock duty cycle stabilization enabled; IOR On Mode. AMP CW/DVGA pin = ADC CW/DVGA pin = LO. Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Conditions Min Typ (1) Resolution No missing codes. See Sampling Rate ADC CLK 40 Conversion Latency Equalizer On 19 Input Range (Differential) IOR On Mode 3.12 IOR Off Mode 4.6 ADC CLK Duty Cycle 20 19 50 RMS Clock Jitter Generated by PLL. Integrated from 0MHz to BWLoop 300 PLL Loop Filter Bandwidth (BWLoop) Low Bandwidth (ADC CLK = 40MHz) 415 High Bandwidth (ADC CLK = 40MHz) Over-sampling Frequency Signal-to-Noise Ratio (SNR) Single-Tone SFDR 67.6 4.4MHz Input, IOR Off Mode 69.1 4.4MHz Input Digital Filter Passband Ripple < ± 0.01dB ADC CLK = 40MHz, Ripple < ± 0.01dB Digital Filter -3 dB Frequency Digital Filter Stop Band Attenuation bits 40.5 MSPS 19 Samples VPP 80 KHz MHz dBFS 76 dBFS 67 dBFS 22 MHz 17.6 25 MHz 20 fin ≥ 34.5 MHz 72 dB 19 samples Digital Filter Group Delay Ripple (peak to peak) fin< 22 Mhz with Equalizer On. See Instant Overload Recovery (IOR) ≤ 5dB above Full Scale (dBFS) (1) 0.05 1 All 8 channels Active (PD = 0) at 40 MSPS (Group Delay Equalizer OFF) 350 All 8 channels Active (PD = 0) at 40MSPS (Group Delay Equalizer ON) 383 (2) Power Consumption (Sleep) Sleep mode, all 8 channels. See Power Consumption (Power Down) Power-Down mode, all 8 channels Recovery Time from CW Doppler Mode Power-up Time (1) (2) MHz ADC CLK = 40MHz Digital filter Group Delay Power Consumption (Active) % fsecond 800 4.4MHz Input, IOR On Mode Units 12 1.5 640 Signal-To-Noise-and-Distortion (SINAD) Max samples Sample Clock cycle mW 40 mW 5 mW ADC CW/DVGA pin switch from Hi to LO 170 µs From single channel Power Down (SPI™ register 01h) 6 From Power Down mode (SPI™ register 00h[0] = HI) 20 µs ms This parameter is specified by design and/or characterization and is not tested in production. Sleep mode keeps the PLL, Reference and Bias networks active to allow fast recovery and interleaved imaging modes. ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 21 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 3.8 www.ti.com Digital Input and Output Characteristics Unless otherwise noted, specified limits apply ADC AVDD = ADC DVDD = 1.2V; ADC CLK = 40 MHz, ADC IO DVDD = AMP IO DVDD = 1.2V, ADC data out RL=100Ω, SPI™ DIO capacitance = 5pF; Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter Conditions Min Typ Max Units Single Ended I/O: SPI™ CLK, SPI™ DIO, ADC SPI™ CS, AMP SPI™ CS, DVGA CLK, DVGA UP, DVGA INIT MSB, DVGA INIT LSB, CW/DVGA RST, AMP CW/DVGA, ADC CW/DVGA, LNA PD, DVGA PD, AMP RST, DVGA PA HI: Levels & Generic Specifications: Logical Input “HI” Voltage 900 mV Logical Input “LO” Voltage 300 mV Logical Input Current ±1 µA SPI™ DIO Logical Output “HI” Voltage Test run at 1MHz SPI™ DIO Logical Output “LO” Voltage Test run at 1MHz 950 IO DVDD 0 mV 250 mV Timing: CW/DVGA RST Setup Time Falling edge must precede CW CLK+ rising transition by (tCWS). See Figure 4-6 CW/DVGA RST Hold Time Falling edge must follow CW CLK+ rising transition by (tCWH). See Figure 4-6 CW/DVGA RST Pulse Width CW/DVGA RST Removal time CW Doppler Mode. See Figure 4-6 (1) See (2) ns 0 ns 200 20 ns DVGA CLK pin Freq DVGA CLK pin Rise and Fall Time ns 2 B-Mode See 2 DVGA CLK pin Pulse Width 100 MHz 7 ns 4 ns AMP SPI™ CS or ADC SPI™ CS Setup Time (tSSELS) See Figure 4-4 15 ns AMP SPI™ CS or ADC SPI™ CSHold Time (tSSELH) See Figure 4-4 3 ns AMP SPI™ CS or ADC SPI™ CSHI Time (TSSELH) Read / Write Transactions. See Figure 4-5 SPI™ DIO Setup Time (tWS) Write Transaction. See Figure 4-4 SPI™ DIO Hold Time (tWH) SPI™ CLK Write Period (tSCLK) SPI™ Read Propagation Delay (tOD) Read Transaction Propagation Delay. See Figure 4-5 SPI™ Master Hi-Z End (tHiZ-E) Read Transaction End of SPI™ Master HiZ. See Figure 4-5 SPI™ Read Valid Time (tVALD) Read Transaction. See Figure 4-5 SPI™ CLK Read Period (tSCLKRD) Read Clock Period. See Figure 4-5 250 ns 110 40 Write Transaction. See Figure 4-4 24 40 ns Write Clock Period. See Figure 4-4 0.2 1 µs SPI™ CLK Duty Cycle (tSCKL / tSCLKH) See Figure 4-4 SPI™ CLK Rise / Fall Time (tSCLKR / tSCLKF) See Figure 4-4 ns 120 ns 100 ns tSCLKRD tOD ns 0.2 µs 45 % of SPI™ CLK Period 55 50 ns Differential Input: Levels & Generic Specifications: LVDS, Common Voltage. See CW CLK Level (See Figure 4-3) (2) LVPECL, Common Voltage. See LVDS, Differential Voltage. See 1.2 (2) (2) LVPECL, Differential Voltage. See CW CLK Input Impedance (1) (2) 22 (2) 2.0 240 400 600 800 Differential 10 V mV kΩ “Removal time” refers to the time CW/DVGA RST must be low prior to the rising edge of DVGA CLK. This parameter is specified by design and/or characterization and is not tested in production. ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Digital Input and Output Characteristics (continued) Unless otherwise noted, specified limits apply ADC AVDD = ADC DVDD = 1.2V; ADC CLK = 40 MHz, ADC IO DVDD = AMP IO DVDD = 1.2V, ADC data out RL=100Ω, SPI™ DIO capacitance = 5pF; Boldface limits apply for TA = TMIN to TMAX; All other limits apply for TA = +25°C. Parameter ADC CLK Level Conditions Min Typ Max Units 0.4 to ADC AVDD Common Mode (AC Coupled within LM96511). See (3) V Differential Mode Drive (peak-to-peak) or Single Ended. See (3) 200 400 ADC AVDD ADC IO DVDD = 1.2V Reduced CM LVDS, RL = 100Ω, OCM = 0. See (2) 318 370 428 ADC IO DVDD = 1.8V LVDS, RL = 100Ω, OCM= 1. See 280 350 417 262 330 393 ADC IO DVDD = 1.2V Reduced CM LVDS, RL = 100Ω, OCM = 0. See (2) 895 945 1000 ADC IO DVDD = 1.8V LVDS, RL = 100Ω, OCM= 1. See 1200 1265 1340 185 225 270 4 4.5 mA -10 ±1 10 µA mV Differential Output: Levels & Generic Specifications: Output Differential Voltage (VOD) ADC IO DVDD = 1.2V SLVS, RL = 100Ω. See Output Common Mode Voltage (VOCM) ADC IO DVDD = 1.2V SLVS, RL = 100Ω. See Output Short Circuit Current (IOS) Shorted to GND. High Impedance Output Current (IOZ) Tri-stated (opened) (2) (2) (2) (2) mV mV Timing: ADC BCLK (Bit Clock) Period (tBCLK) ADC CLK= 40 MHz. See Figure 4-1 Bit Clock (ADC BCLK) Jitter (RMS) See ADC WCLK (Word Clock) Period (tWCLK) ADC CLK= 40 MHz. See Figure 4-1 Output Data Edge to Output Clock Edge Setup Time (tS) ADC CLK= 40 MHz. See Figure 4-1 Output Data Edge to Output Clock Edge Hold Time (tH) ADC CLK= 40 MHz. See Figure 4-1 Output Data Valid Window (tDV) ADC CLK= 40 MHz. See 4.16 (4) ns 2 (4) Figure 4-1 ps 25 ns 480 900 ps 770 1150 ps 1410 1820 ps Rise/ Fall Time 320 See Figure 4-1 ADC Input Clock to Word Clock Delay (tprop) ADC CLK = 40 MHz. Upon applying RST signal or a proper power reset. 5.4 ns Upon applying RST signal or a proper power reset. 5.1 ns (3) (4) -720 -295 ps Data Edge to Word Edge Skew (tDWS) 220 ps ADC CLK input(s) minimum swing should never extend more negative than ground because of ESD protection diode(s) to ground. This parameter is specified by design and/or characterization and is not tested in production. ELECTRICAL SPECIFICATIONS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 23 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 4 GENERAL DIAGRAMS 4.1 TIMING DIAGRAMS tprop ADC CLK- ADC CLK ADC CLK+ tBCLK ADC BCLK+ ADC Bit Clock ADC BCLKtR tDWS tF tDWS tWCLK ADC WCLKADC Word Clock ADC WCLK+ tDV tH ADC DOn+ ADC Output data D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 ADC DOntS Sample n+1 Sample n Figure 4-1. B-Mode ADC Data Output Timing ADC IO DVDD VOCM + VOD/2 Differential output signal VOCM VOCM - VOD/2 0 Figure 4-2. B-Mode ADC Data Output Level Definitions 24 GENERAL DIAGRAMS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 AMP DVDD VOCM + VOD/2 CW CLK Levels VOCM VOCM - VOD/2 0 Figure 4-3. CW CLK Level Definitions tSCLK tSSELS tSCLKL tSSELH tSCLKF tSCLKR tWH tWS tSCLKH SPI CLK SPI DIO 90% 10% 10% D7 R/W A7 90% D0 ADC SPI CS or AMP SPI CS Figure 4-4. SPI™ Write Timing tOD tSCLKRD tVALD tHIzE SPI CLK SPI DIO A7 R/W D7 D0 tSSELHI ADC SPI CS or AMP SPI CS Figure 4-5. SPI™ Read Timing GENERAL DIAGRAMS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 25 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Phase Reset Initiated CW CLKCW CLK CW CLK+ tCW tCWS CW/DVGA RST tCWH Figure 4-6. CW/DVGA RST Timing (CW Doppler Mode) 26 GENERAL DIAGRAMS Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 5 TYPICAL PERFORMANCE CHARACTERISTICS 5.1 General Typical Performance Characteristics Unless otherwise noted, AMP AVCC A = AMP DVDD= 3.3V, CW AVCC = 5V; ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = AMP IO DVDD = 1.2V, Full Scale RF Input at 5 MHz; CW CLK = 80 MHz; FCLK = 40 MSPS, TA =+25°C. AFE Gain vs. Steps (DVGA PA HI = HI) Attenuation Error from Nominal Attenuation Error from Nominal (dB) 0.02 Nominal Gain = Straight Line from Min to Max Attenuation 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 0 10 20 30 DVGA Attenuation (dB) 40 Figure 5-2. Attenuation Step Error from 0.1 dB Attenuation Step Error from 0.05 dB ATTENUATION STEP ERROR FROM 0.05 dB (dB) Figure 5-1. Attenuation Step Error from 0.1dB (dB) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 0 10 20 30 DVGA Attenuation (dB) 40 0.020 0.015 0.020 0.010 0.015 0.010 0.005 0.005 0 0 -0.005 -0.010 -0.005 -0.015 -0.010 -0.020 -0.015 -0.020 0 10 20 30 DVGA ATTENUATION (dB) Figure 5-3. Figure 5-4. Gain Variation from Nominal vs Supply Voltage Gain Variation from Nominal vs Temperature 0.250 40 0.4 70°C 0.3 SUPPLY -5% DELTA GAIN (dB) DELTA GAIN (dB) 0.125 0.000 0.1 0.0 0°C SUPPLY +5% -0.125 -0.2 -0.250 -40 Delta Gain Referenced to AMP AVCC A pin = 3.3V Condition -30 -20 -10 DVGA GAIN (dB) Figure 5-5. Copyright © 2010–2013, Texas Instruments Incorporated 0 Delta Gain Referenced to 25°C Condition -0.3 -40 -30 -20 -10 0 DVGA GAIN (dB) Figure 5-6. TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links: LM96511 27 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Unless otherwise noted, AMP AVCC A = AMP DVDD= 3.3V, CW AVCC = 5V; ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = AMP IO DVDD = 1.2V, Full Scale RF Input at 5 MHz; CW CLK = 80 MHz; FCLK = 40 MSPS, TA =+25°C. LNA S11 vs. Frequency 0 0.9 -50 0.8 Phase 1.0 0.9 0.7 0.8 RFB = 310Ö (RIN = 50Ö) 0.7 0.6 0.6 CFB = 2.2 nF 0.5 0.5 0.4 0.3 0.4 0.2 Magnitude 0.1 0.3 0.0 0.2 -100 0 -50 -150 -100 -150 -200 -200 -250 -250 -300 -350 -300 -400 -450 -350 -500 -400 0.1 -450 0.0 0.1 1 10 100 1000 PHASE (o) MAGNITUDE (dB) 1.0 AFE Offset Distribution IOR On Mode, Minimum DVGA attenuation, DVGA PA HI pin = LO) -500 10,000 F (MHz) Figure 5-7. Figure 5-8. HD vs. LNA Input Swing (PA HI pin = LO) HD vs. LNA Input Swing (PA HI pin = HI) 0.02 0.02 DVGA Attenuation = 38 dB 0.01 (Gain Parked) ADC Swing DVGA PA HI pin = LO 0 IOR Off Mode DVGA Attenuation = 38 dB 0.01 (Gain Parked) DVGA PA HI pin = HI ADC Swing 0 IOR Off Mode -0.01 HD (dBc) HD (dBc) -0.01 -0.02 -0.03 HD3 -0.04 -0.05 -0.03 HD3 -0.04 -0.05 HD2 -0.06 -0.07 0 -0.02 HD2 -0.06 10 20 30 -0.07 0 40 10 LNA Input Swing (mVpp) 30 40 Figure 5-9. Figure 5-10. RTI Noise vs. Frequency (DVGA Attenuation = 0dB) RTI Noise vs. Frequency (DVGA Attenuation = 32dB) 1.4 1.2 20 DVGA Attenuation = 0 dB RFB = Open RS = 0: DVGA PA HI pin = Lo 15 RTI Noise (nV Hz) 1.6 RTI Noise (nV/ Hz) 20 LNA Input Swing (mVpp) 1.0 0.8 0.6 DVGA PA HI pin= Hi DVGA attenuation = 32 dB RFB = Open DVGA PA HI pin = LO RS =0: 10 0.4 DVGA PA HI pin = HI 5 0.2 0.0 0 5M 10M 15M 20M f (Hz) Figure 5-11. 28 TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links: LM96511 0 0 5M 10M 15M 20M f (Hz) Figure 5-12. Copyright © 2010–2013, Texas Instruments Incorporated LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Unless otherwise noted, AMP AVCC A = AMP DVDD= 3.3V, CW AVCC = 5V; ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = AMP IO DVDD = 1.2V, Full Scale RF Input at 5 MHz; CW CLK = 80 MHz; FCLK = 40 MSPS, TA =+25°C. Far-Field Overload Recovery @ Post Amp Output (No User Access) AFE (B-Mode) Overload Recovery 1V/Div 100 ns/Div Figure 5-13. Figure 5-14. Spectral Response @ fIN=10 MHz, ADC CLK = 400 mHz, IOR On Close-In Spectral Response @ fIN=1.9 MHz, TGC Running, Cosine 6 Term Window Figure 5-15. Figure 5-16. ADC INL ADC DNL Figure 5-17. Figure 5-18. Copyright © 2010–2013, Texas Instruments Incorporated TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links: LM96511 29 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Unless otherwise noted, AMP AVCC A = AMP DVDD= 3.3V, CW AVCC = 5V; ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = AMP IO DVDD = 1.2V, Full Scale RF Input at 5 MHz; CW CLK = 80 MHz; FCLK = 40 MSPS, TA =+25°C. 5.2 CW Doppler Plots CW Doppler IMD3, Unequal Tones See Electrical Characteristics (5), 10kHz & 15kHz Offset, 25 dB Separation Figure 5-19. CW Doppler Output Noise (CWDIFF CLK = 80.0MHz) -120 80 CW Doppler Phase Noise, See Electrical Characteristics LNA Input = 240 mVpp @ 5.00 MHz Single Channel (I or Q Output) 70 Phase Noise (dBc/Hz) Output Noise Density (pA/RtHz) Singe Channel (I or Q Output) 60 50 -130 -140 40 30 100 1,000 f (Hz) 10,000 -150 100 Figure 5-20. (5) (6) 30 (6) 1k 10k f (Hz) Figure 5-21. “Removal time” refers to the time CW/DVGA RST must be low prior to the rising edge of DVGA CLK. Per 1 Hz BW, offset 1 kHz from a 5 MHz, FS input. Output Phase noise, expressed in - dBc/Hz, follows both RF input and CW CLK phase noise. To meet the demodulated Output specification, integrated phase noise of both the RF Input signal and CW CLK must be better than -160 dBc/Hz at 1 kHz offset. TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links: LM96511 Copyright © 2010–2013, Texas Instruments Incorporated LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 I-Q Quadrature Phase Error (Within Channel) 0.02 I-Q Output Amplitude Match (Within Channel) 0.01 Ch6 0.01 0.02 |Amplitude Mismatch (%)| Phase Error (degrees) Unless otherwise noted, AMP AVCC A = AMP DVDD= 3.3V, CW AVCC = 5V; ADC AVDD = ADC DVDD = 1.2V, ADC IO DVDD = AMP IO DVDD = 1.2V, Full Scale RF Input at 5 MHz; CW CLK = 80 MHz; FCLK = 40 MSPS, TA =+25°C. 0 Ch1 -0.01 Ch5 Ch0 -0.02 -0.03 Ch4 Ch2 -0.04 -0.05 Ch3 Ch7 0 -0.02 Ch4 -0.04 -0.07 0 Figure 5-22. Copyright © 2010–2013, Texas Instruments Incorporated Ch5 -0.05 -0.07 0 40 Ch3 Ch1 -0.03 -0.06 20 30 SPI Phase Data (#) Ch0 -0.01 -0.06 10 Ch2 Ch6 Ch7 10 20 30 SPI Phase Data (#) 40 Figure 5-23. TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links: LM96511 31 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 6 www.ti.com OVERVIEW The LM96511 is an eight-channel, fully integrated entire subsystem intended for ultrasound receive applications. LM96511 consolidates many receiver functions currently residing in multiple IC’s, thereby achieving lower cost, higher board density, higher performance, lower system integration cost, and lower power consumption. The LM96511 has two distinct signal paths: one for B-mode (Brightness) and the other for CW-mode (CW Doppler). The LM96511 consists of the following blocks / functions for each of its 8 channels: 1. Low-Noise Amplifier (LNA) with programmable input impedance for improved ultrasound probe matching characteristics 2. Digital Variable Gain Amplifier (DVGA) with capability to increase or decrease gain (linear in dB) using digital input for rate of change control 3. 12-Bit ADC with on board PLL for superior jitter reduction 4. CW Doppler output (I and Q) with 16 user selectable phase rotation 5. SPI™ compatible interface for user programming and control FPGA / DSP Block TXBeamformer HV Pulser Beamformer Control Timing HV Mux/ Demux HV Protection T/ R switch DVGA Control LM96511 8 - Channel Analog Front End RX Beamformer LNA +DVGA+ADC + CW Doppler I/Q Demod Cable Transducer Summing Amps Power ADC ADC CW- Doppler Processing B-Mode and Color Doppler Processing Temp Sensor . Display and Post Processor Figure 6-1. Ultra-Sound System Block Diagram 6.1 LNA INPUT AMPLITUDE RANGE The input amplitude range of the LM96511’s Low Noise Amplifier is well suited for ultrasound applications in both CW and B-Mode operation. However, T/R switch leakage and strong echoes from near-field or acoustically dense material is unavoidable. Because of such large transient signal amplitudes and increasing DVGA gain during TGC, overload at the LNA input impairs signal integrity in ultrasound applications. Thus, it is very important to prevent the LM96511 inputs from being overloaded by: 1. Limiting the input signal amplitude (see further explanation in Section 6.2) 2. Gating the transmit signal path before it reaches the T/R switch 3. Clamping the input signal with a pair of back-to-back signal diodes as additional protection against overload at the LNA input 32 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Furthermore, in B-Mode TGC operation, when the LNA functions in series with the DVGA and PostAmplifier, the maximum input signal swing is subject to the LNA’s output slew rate limitation. Because the LNA has a maximum differential output slew rate of 100V/μs, or 50V/μs at its inverting output, the input signal should be adjusted such that the inverting output of the LNA does not exceed this 50V/μs limit. In addition to limiting the input signal slew rate, to avoid further overload effects induced by surges in input bias current associated with the maximum slew rate limitation, the signal swing at the LNA input should be limited to 200mVPP for optimal performance across typical signal frequencies above 5MHz. Ultimately, it is most important to ensure that the input signal is within the LNA’s slew rate limitation. Thus, as shown and explained further in the next section, the input circuit to the LM96511 should have the current source for the T/R switch diode bridge carefully selected to limit the input current to the LNA (~1mA) and include a capacitor (~100pF) and resistor (~100Ω) to ground. 6.2 TYPICAL INPUT CONFIGURATION The schematic in Figure 6-2 shows a typical B-Mode input configuration circuit for the LM96511. The input is typically AC coupled through a T/R switch diode bridge configuration which blocks the transmit (Tx) high voltage pulses from the receive (Rx) low voltage inputs. +5V 5 k: I_source Tx S1 Diode Bridge C1 100 pF Signal Source R1 100: I_source 5 k: Max gain = 51 dB or 58 dB Schottky CIN Clamp 1 nF RS LNA 20 dB Attenuator 0 dB to -38 dB Post Amp 31 dB or 38 dB CT6' ADC 12 b Serial LVDS/ SLVS output 1 nF To CW_Doppler Path -5V Digital gain control PA GAIN Figure 6-2. Signal Path (B-Mode) Single Channel Including Input Clamp and Diode Bridge It is recommended to use Texas Instrument's LM96530 T/R switch with the LM96511 AFE for optimal operation and performance. Alternatively, the discrete 4-diode bridge T/R switch shown in Figure 6-2 may be used. In such designs, diode characteristics are not ideal, and thus the LM96511 inputs should be protected from the resulting leakage transients, as well as strong reflections. Thus, the transmit signal path should be gated off with switch S1. During Ultrasound Rx, switch S1 is open and, with no input signal, “I_source” flowing from the top current source, through the 4 diodes, to the bottom current source. The Input signal crosses the diode bridge to the LM96511 input as long as the current through CIN is less than “I_source” (~1mA). Larger input signal amplitudes which require excess CIN current beyond I_source's value will thus be limited by the diode bridge action. During the Tx cycle, switch S1 is shorted so that the Diode Bridge is current starved and any leakage from the T/R switch (not shown) will be strongly attenuated. This ensures effective isolation for maximum protection in the presence of any Tx leakage. In addition to gating the transmit path with switch S1, capacitor C1 and termination resistor R1 must be included to improve overload recovery time and reduce reflection. C1 acts as a filter to suppress high voltage transient spikes, while R1 acts to divide the signal amplitude down to a favorable level for the LM96511 input, e.g., 200mVPP. This provides adequate protection for the LNA input. C1 (~100pF) also acts to band-limit the input signal to ensure that it is within the LNA's slew rate limitation. Although R1 may increase the noise figure and the input impedance seen by the ultrasound transducer, it still provides good harmonic distortion and low offset. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 33 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Finally, the Schottky clamp diodes provide an additional level of overload protection where the LM96511 input swing is limited to ~ ± 0.35V regardless of the LM96511’s input impedance. 6.3 PROGRAMMABLE INPUT IMPEDANCE & LNA GAIN SELECTION The LM96511 input termination can be configured in either of two ways: 1. Standard Termination is illustrated in Figure 6-3, where the receive (Rx) probe (through the T/R switch) is terminated with RT for proper cable termination, and AC coupled to the LNA's non-inverting input. The inverting input is returned to ground through a capacitor. +5V 1 nF + VOUTLNA VOUT+ - RT 1 nF Figure 6-3. Standard Input Termination 2. Active feedback termination is illustrated in Figure 6-4, where no termination resistor is used and feedback (RFB + CFB) sets the effective input impedance to provide proper cable termination. This termination scheme is employed for improved harmonic distortion and noise performance. With no physical termination resistor, there is no resistor thermal noise degradation of the LNA noise, and thus increased SNR compared to standard termination. However, as with any amplifier with active feedback termination, abrupt increases in input amplitude may diminish the active termination and may even result in total loss of termination, which will then further overload the LM96511 inputs. It is important to be mindful that with active feedback termination, the LNA is: 1. Even more susceptible to overload effects associated with the maximum slew rate limitation mentioned above 2. Subject to gain reduction at higher output amplitudes Thus, in achieving better harmonic distortion and noise performance, active feedback termination may be employed, but as long as the input signal is limited to an amplitude of 200mVPP and slew-rate limited such that the LNA inverting output slew rate is less than 50V/μs. RFB CFB +5V C1 + VOUTLNA - VOUT+ Figure 6-4. Active Termination Schematic 34 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Active impedance termination is achieved through an external shunt feedback resistor from LNA IN+ to LNA OUT-. The input resistance RIN is given by the equation below, where A is the LNA single-ended gain (=10V/V ÷ 2 = 5V/V) and 5kΩ is the un-terminated input impedance of the LM96511 LNA. CFB is required in series with RFB, since the DC levels at LNA IN+ and LNA OUT- are unequal. RFB RIN = 6.4 1+ A || 5 k: RIN (Ω) RFB (Ω) 50 301 7 453 100 619 200 1.24k 1k 7.5k 3k 45.3k OFFSET SOFT-TRIM To minimize offset, the LM96511 is laser trimmed during manufacturing. To improve accuracy and to allow periodic calibration, if needed, the LM96511’s LNA and Post-Amplifier (PA) include provisions for offset trim using the SPI™ compatible interface after chip power-up (volatile). In B-mode, LNA offset trim improves gain-dependant offset shift, while PA offset trim reduces fixed offset to maximize the LM96511 ADC’s Full-Scale swing for maximum dynamic range. SPI™ offset trim should be performed with a software algorithm (Soft-Trim) that looks at the ADC code, at various DVGA attenuation settings, and then invokes a binary search for the best value that centers the ADC code. A couple of iterations are usually adequate to “zero-in” on the best Soft-Trim setting for each channel. Texas Instruments provides such software algorithms to its customers for use “as-is” or for modification to meet individual requirements. Figure 6-5 shows the LM96511 B-mode offset, measured through the ADC. As can be seen, Soft-trim allows extremely accurate offset adjustment (typically within 1LSB) and allows significant tightening of the distribution. Figure 6-5. Offset Distribution Histogram including Soft-Trim Improvement Maximum expected full scale amplitude loss due to DC offset is: = 20 x log §212 - |Offset (LSB)| · ¸ ¨ 12 2 ¹ © (1) OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 35 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 6.5 www.ti.com DYNAMIC RANGE Figure 6-5 shows the LM96511 B-mode TGC in action. In this diagram, a 5MHz ultrasound signal enters the LNA with 350mVPP single ended Near Field (NF) amplitude and the signal path headroom runs into clipping. 3.5VPP differential NF amplitude appears at the LNA output (Differential gain = 20dB) where the DVGA TGC will equalize the signal so that the ADC FS range of 3.12VPP (with IOR On or 4.4VPP with IOR off) can be transversed to maximize the data acquisition resolution. Note that the LM96511’s B-mode ADC operates off a 1.2V supply and yet can accommodate 3.12VPP_FS with IOR on or 4.4VPP_FS with IOR off. This is because of the coupling resistor ladder built into the ADC in spite of ADC input noise level performance which does not impact ENOB. IOR-Level 350 mV Differential 3.5V Differential 3.12V TGC Differential 3.5V ADC Dynamic Range IOR-Level 31 dB & 38 dB DVGA -32 dB - 20 dB 6' ADC Figure 6-6. LM96511 in Typical TGC Operation at 5MHz 6.6 DVGA OPERATION The LM96511 features a linear-in-dB, digital variable gain amplifier which consists of a digitally variable attenuator and post amplifier. The attenuator has a variable range of 0 to -38dB (or -36, -34, or -32dB depending on settings) in increments of either 0.05dB or 0.1dB per LSB step (depending on the “Half Step” mode setting). The variable gain operation is essentially achieved with a “Clock and Reset” scheme. There are three digital control signals for the attenuator: DVGA CLK, CW/DVGA RST, and DVGA UP. The heart of the variable gain control lies in the DVGA CLK and CW/DVGA RST logic input signals, as illustrated in Figure 6-7. The positive edge of every CLK pulse will increment or decrement each gain step for as long as the CW/DVGA RST logic pulse is LOW. For a periodic gain ramp-up sequence, the negative edge of every CW/DVGA RST pulse begins a ramp upwards, and the positive edge of every RESET pulse ends the ramp, resetting the gain back to its DVGA Initial Attenuation. The number of DVGA CLK pulses during each LOW interval of the CW/DVGA RST pulse, determines the duration of the gain ramp, while the frequency of the DVGA CLK pulses determines the slope of the gain ramp. 36 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 The DVGA UP input determines whether gain is incremented or decremented. Depending on the logic level of this input, the DVGA can begin at the bottom of the gain ramp (maximum attenuation setting) and proceed to ramp up, or at the top of the gain ramp (minimum attenuation setting) and proceed to ramp down. Figure 6-8 illustrates how this logic level can also be dynamically changed midway through a ramp up or ramp down operation, which can allow the sonographer to flatten the image’s grey background or to reduce the level of a bright reflector. DVGA UP | CW/DVGA RST | DVGA CLK Max Gain | | GAIN (dB) Initial Gain Figure 6-7. Periodic TGC Ramp: Example 1 (Half-Step Disable bit = 1) Must be 8 1 DVGA CLK Period | | Must be 8 1 DVGA CLK Period | DVGA UP | CW/DVGA RST DVGACLK | Ramp polarity change occurs on the 2nd rising DVGA CLK edge | GAIN (dB) MIN GAIN Figure 6-8. DVGA UP bit Change (Half-Step Disable bit = 1) OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 37 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com DVGA UP | CW/DVGA RST | DVGA CLK Max Gain | | GAIN (dB) Initial Gain Figure 6-9. Periodic TGC Ramp: Example 2 (Half Step Disable bit = 1) DVGA UP | CW\DVGA RST DVGA CLK | | Min Removal Time (20 ns) GAIN (dB) Initial Gain Figure 6-10. Basic Gain Adjustment (Half Step Disable Bit = 1) 38 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 DVGA UP | CW/DVGA RST | DVGA CLK 100 MHz 10 MHz 10 MHz | GAIN (dB) Initial Gain Figure 6-11. Accelerated Gain Adjustment (Half Step Disable bit = 1) DVGA UP | CW/DVGA RST | DVGA CLK 100 MHz 10 MHz | Max Gain Ramp polarity change occurs on the 1st rising DVGA CLK edge GAIN (dB) Initial Gain Figure 6-12. Gain Reset with DVGA UP bit = 0 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 39 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Half step disabled, 0.1 dB DVGA UP pin DVGA Gain DVGA CLK pin Half step enabled, 0.05 dB DVGA UP pin DVGA Gain DVGA CLK pin Figure 6-13. DVGA Gain control “Micro Illustration” of the Gain Stair Case 6.6.1 DVGA Half Step Mode Another feature of the DVGA which makes it ideal for TGC (Time Gain Control) Applications is its ultra-fine gain step resolution. In its default startup state, the step attenuator is controlled with the clock and reset scheme described above, where each DVGA CLK rising edge changes attenuation by 1/2 step (0.05 dB typical), and the following DVGA CLK falling edge changes attenuation by another 1/2 step (0.05 dB typical). In other words one complete DVGA CLK cycle changes attenuation by 0.1dB. Alternatively, the Half Step mode may be disabled so that a gain step of 0.1dB will occur on the positive edge of the DVGA CLK and no gain change will occur on the negative edge of the DVGA CLK. The Half Step mode is controlled via SPI™ compatible interface register 0x1Ah, bit 3 (0x1A[3] = “1”, Half Step Disabled, 0.1dB step). 6.6.2 DVGA CLK Pin The DVGA clock frequency determines the rate of change of attenuation (i.e. DVGA gain). The DVGA will increment or decrement gain by one step (0.05dB or 0.1dB) with each DVGA CLK cycle when CW/DVGA RST pin is low. The Maximum DVGA clock frequency is 100MHz which sets the maximum gain change rate at 10dB/μs. The minimum DVGA CLK pulse duration (either high or low state) is 4ns. To take advantage of Half Step DVGA clocking, it is recommended to keep DVGA CLK duty cycle close to 50%. 40 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com 6.6.3 SNAS476H – MAY 2010 – REVISED MAY 2013 CW/DVGA RST Pin When CW/DVGA RST is LOW, the step attenuator will increment or decrement attenuation with each DVGA CLK pulse. In the absence of DVGA CLK, the step attenuator will remain at its current attenuation until either CW/DVGA RST is pulled HIGH or a DVGA CLK pulse is applied. For example, assume DVGA UP is held HIGH while CW/DVGA RST is LOW and 74 clock cycles are applied. The attenuation is reduced by 74 steps or 7.4 dB. If CW/DVGA RST is still held LOW and 10 additional clock pulses are applied, the attenuation is further reduced by 1dB. If CW/DVGA RST is pulled HIGH, the attenuation will return to the DVGA Initial Attenuation (as shown in Table 6-4). The first positive CLK edge following a HIGH to LOW DVGA RST transition is valid and will increment or decrement gain depending on whether DVGA UP is HIGH or LOW respectively. 6.6.4 DVGA UP Pin: DVGA UP pin determines the DVGA Initial Attenuation point and whether attenuation is decremented or incremented (i.e. DVGA gain increment or decrement respectively). If DVGA UP is HIGH, the DVGA gain will increment upwards, towards the Minimum Attenuation (Maximum Gain) limit of 0dB. If DVGA UP is LOW, the DVGA gain will decrement downwards, towards the minimum gain limit (38 dB of full attenuation assuming the “attenuation range setting” is at 38dB). DVGA UP can be dynamically switched during an increment or decrement operation. After DVGA UP is switched from LOW to HIGH (or HIGH to LOW), the first positive edge of DVGA CLK synchronizes the new state with the DVGA CLK. The second positive edge of DVGA CLK will decrement (or increment) the DVGA Gain. 6.6.5 DVGA Accelerated Gain Adjustment: With the LM96511’s clock and reset scheme and the ability for a high frequency DVGA clock (max = 100MHz), it is possible to get to the desired TGC starting point quickly. Assuming a DVGA “attenuation range setting” of 32dB selected, the fastest way to achieve DVGA attenuations of 16-32 dB is to apply a CW/DVGA RST pulse with DVGA UP HIGH (to get to 32dB attenuation) followed by a succession of DVGA CLK pulses sufficient to get to the attenuation level desired. For attenuations from 0-15.9 dB, it is faster to apply a CW/DVGA RST pulse with DVGA UP LOW (to get to 0dB attenuation) and followed by a succession of fast DVGA CLK pulses. Figure 6-11 and Figure 6-12 illustrate examples of this feature in order to explain the accelerated gain adjustment sequence more clearly. In certain instances, an important parameter may be the time required for this operation (i.e., “T_attenuation”). Starting from the rising edge of the CW/DVGA RST pulse, the total time is the sum of the CW/DVGA RST minimum pulse width (“T_RST_width” = 200ns), the minimum time required to start the DVGA CLK from the CW/DVGA RST’s LOW state (i.e.,“ DVGA RST removal time” which is listed in Electrical Characteristics as, “T_RST_rem” = 20 ns), and the time required to clock the DVGA to achieve the desired attenuation (“Attenuation” in dB): • T_attenuation = T_RST_wdith + T_RST_mem + 10ns/ step x (Attenuation / 0.1dB/ step) – For 0 ≤ Attenuation ≤ 15.9 dB (DVGA UP = 0 during clocking) • T_attenuation = T_RST_wdith + T_RST_mem + 10ns/ step x ((32 – Attenuation) / 0.1dB/ step) – For 16 ≤ Attenuation ≤ 32 dB (DVGA UP = 1 during clocking) For example, with a 32 dB DVGA attenuation range, to achieve 20 dB DVGA attenuation, the time required is: • T_attenuation = T_RST_wdith + T_RST_mem + 10n s/ step x ((32 – Attenuation) / 0.1 B/ step) • T_attenuation = 200 ns + 20 ns + 10 ns/ step x ((32 – 20) / 0.1 dB/ step) = 1.42 μs OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 41 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 6.7 www.ti.com THE LM96511 ADC The LM96511 ADC employs a number of unique strategies to provide a high performance multi-channel AFE that offers a significant power consumption reduction when compared to competing architectures, as well as easing system level design. The ultra-low power performance of the LM96511 ADC is derived from the implementation of a fast continuous time sigma delta (CTΣΔ) modulator. Other features of this technology are: • Intrinsic anti-alias filter: The digital decimating filter provides an intrinsic anti-alias filter, eliminating external analog filter components, and simplifying multi-channel designs. • Instant overload recovery (IOR) system ensures extremely fast recovery from overload (< one clock cycle), and no settling errors on return from overload. • Ultra-low inter-channel crosstalk. • Digital Equalizer provides low group delay and hence minimizes signal path delay variation. CMOS IN ADC CLK+ (SE) PLL LVDS Input ADC CLK- Output LVDS SLVS ADC BCLK+ Output LVDS SLVS ADC WCLK+ LC VCO ADC CONTROL ADC SLEEP ADC RST ADC AVDD Register 1.2V Register AGND 1.2V to 1.8V ADC DVDD 1.2V ADC BCLK- ADC WCLKADC IO DVDD ADC IO DGND Input+ (from PA) Clipping Control 12 bit 3 bit 1.3 kÖ Serializer 1 bit CTÐ' Digital Decimation Filter Modulator Input(from PA) Output LVDS SLVS 1.3 kÖ Register Register Register Register ADC DOUT CHn+ ADC DOUT CHn- Register ADC LPF BYP 8 times Reference and Bias ADC RREF IRef SPI Control To Registers 0.5V DC Register SPI DIO SPI CLK ADC SPI CS Figure 6-14. LM96511 ADC Block Diagram The major components of the LM96511 ADC, shown in Figure 6-14, are: clipping control; CTΣΔ modulator; digital decimation filter; 12-bit serializer; and finally the LVDS/SLVS outputs. The PLL is critical to the operation of the LM96511 ADC, and the PLL also provides the bit and word clock outputs. The SPI™ Compatible Control Interface gives uncomplicated user access to the ADC registers. 42 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com 6.8 SNAS476H – MAY 2010 – REVISED MAY 2013 ADC OUTPUT INTERFACE The ADC outputs provide a sampling clock and data information. The output sampling or bit clock is a differential high speed bit clock that is 6 times the input clock and 90° out of phase with respect to the output data information. This clock is automatically synchronized to the input ADC clock within the LM96511. However, this bit clock is not phase aligned with the input ADC clock. The output data information consists of two components: the serialized ADC output data and the output word or frame clock. Each serialized data word or frame is 12-bits wide. The word clock output provides framing information necessary for deserialization of the data by identifying the bit boundary of each data word sample. The word clock is a lower frequency clock that is phase aligned (within a very small skew, tDWS) with the data and is primarily used as a strobe to capture and align data words in a parallel register within the deserializer. The rising edge of the word clock is aligned (within a very small skew) with the LSB of a data word output from the ADC. The word clock signal is sampled on the positive and negative edges of the bit clock output. Thus, a rising edge of the word clock indicates that a full data word is available to load into a deserializer’s parallel register and that a new data word begins. This word clock is not phase aligned with the input ADC clock. tBCLK ADC BCLK+ ADC Bit Clock ADC BCLKtDWS tDWS tWCLK ADC WCLKADC Word Clock ADC WCLK+ ADC DOn+ ADC Output data D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 ADC DOn- Sample n Sample n+1 Figure 6-15. ADC WCLK 6.9 12–BIT SIGMA DELTA (ΣΔ) ADC CORE The LM96511 ADC comprises eight analog ADC channels using a CTΣΔ architecture, which provides very high dynamic performance with ultra-low power, while operating from a minimal 1.2V supply. The CTΣΔ ADC architecture uses a third order sigma delta modulator operating at a nominal 16 times over-sampling rate in combination with a 3-bit quantizer. The modulator output is coupled to a power efficient digital decimation filter that decimates the high rate modulator output (640 MHz) to provide output data at a sample rate of 40 MSPS. A benefit of the CTΣΔ design is that the ADC requires no external antialias filters for most applications. This benefit is derived from a combination of the design of the analog sigma delta modulator and digital decimation filter. The digital filter achieves a steep transition band, and provides 72 dB of attenuation in the stop band. Using the digital equalizer, the signal transfer characteristics including phase performance can be optimized so as to minimize group delay variation. In applications where it is not required, the digital equalizer can be disabled to further save power. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 43 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 6.10 INSTANT OVERLOAD RECOVERY The LM96511 features an overload handling system which provides instantaneous recovery from signals driving the ADC inputs beyond the full-scale input range. The ADC can operate in two different modes. In the default ADC mode (IOR Off mode) a full-scale input range of 4.2 VPP is supported, here the ADC operates with some inherent overload recovery time, similar to a conventional ADC. In the IOR On mode, the ADC has a reduced 3.2 VPP full scale input range, but provides a significant benefit in that the ADC can now be driven by input voltages as high as 5 dB beyond the nominal full-scale (fIN < 12 MHz), that is 5.7 VPP, and will recover instantaneously. In a number of applications this feature can help simplify input stage design and manufacturing set-up and calibration. The LM96511 recovers immediately from overload with no missing codes and no settling time. The proprietary strategy used within the LM96511 ADC uses high speed patented clamp techniques to limit the input signal and keep it within the stable input range of the ADC. This process happens at a speed equivalent to the on-chip over-sampling rate of 640 MHz. The advantage of this system is that it responds immediately to out of range signals. While the inputs are over-range the ADC outputs a full scale result. As the over-range input is removed the ADC adjusts to the input signal level and is able to provide sampled data instantaneously. The LM96511’s behavior on emerging from overload is repeatable and independent of whether the input signal was positive or negative going at the point of overload. 6.11 USING IOR ON MODE As discussed earlier, IOR On mode provides instantaneous recovery from overload conditions, with no ringing and correct data output as soon as the input returns in range. 6.11.1 Standard Use of IOR On Mode The recommended way to enable IOR On mode is by setting bit 4 (IOR) of the Modulator Overload Control register (02h). Setting this bit will enable IOR mode with the default settings for Digital Gain Factor (DGF) in the Decimator Clipping Control register (0Ah) and OL in the Modulator Overload Control register (02h). Setting the IOR mode bit to 0 will restore DGF and OL to their default values, hence putting the LM96511 back into IOR Off mode. As can be seen in Electrical Characteristics, using IOR On mode gives a slight reduction in SNR performance, and also a reduction of the full scale input range to 3.2VPP differential. 6.11.2 Advanced Use of IOR On Mode The registers described above allow the user to customize IOR On mode. In order to correctly set the DGF and OL values, it is necessary to understand how the IOR On mode functions. The implementation of IOR On mode in the LM96511’s ADC consists of analog and digital parts working in tandem. The analog clipping circuitry, controlled by OL, is designed to protect the sigma delta modulator from large signal inputs. Using an analog clamp, signals are soft-limited to the less than the 4.2VPP full scale range of the modulator. OL gives the value at which the circuit will begin to clamp. The digital filter of the ADC12EU050 is where the full scale input range is selected and the hard limiting of the signal takes place. DGF selects the gain of the digital filter, and hence the new full scale input range of the ADC. In order to set a custom value for DGF, Custom Gain Setting (CGS), bit 7 of the Decimator Clipping Control register (0Ah), must be set. The DGF can then be set, based on the application requirements. OL should then be set to a value approximately half-way between the new full scale input range (which was just selected by DGF) and the default full scale input range of 4.2VPP. OL must be set to a value higher than DGF, otherwise the signal will be limited by the analog clipping circuitry, rather than the digital circuitry, and overload recovery will be impacted. 44 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 6.12 INTEGRATED PRECISION LC PLL ADVANTAGES The LM96511 ADC includes an integrated high performance “clean up” phase locked loop (PLL), simplifying the need for a low jitter external clock for ADC CLK pin(s). The PLL serves three important functions; it generates a highly accurate internal sampling clock source of up to 640 MHz; a clock for the LVDS serializers at 600 MHz; and it provides a low jitter clock for other internal components. With its jitter clean-up capability this PLL allows lower performance system clocks to be used. The ADC CLK pin(s) are AC coupled within the LM96511 so that the common mode voltage is not critical. The clock can be single ended or differential (unused ADC CLK input can be grounded). A single ended clock input should be connected to ADC CLK+ (B22) pin, and ADC CLK- (A22) pin should be grounded. Furthermore, the ADC CLK source can be a sine or square wave for maximum flexibility. Datasheet parameter testing is done with a “clean”, differential square wave clock source routed as 100Ω differential pairs, and terminated with a 100Ω resistor close to LM96511 clock inputs. The benefit of having an on chip PLL is that in most applications a high precision clock source is not required. The impact of aperture jitter on the ADC’s performance is reduced dramatically by the jitter clean-up properties of the PLL, which ensures that any RMS jitter outside of the PLL bandwidth is attenuated. The PLL also significantly relaxes the input clock duty cycle requirements, accepting input clock duty cycles of 20% to 80%. The PLL offers two choices of bandwidth, selectable by SPI™ register 03h[1] (SHBW). For the majority of systems, the default bandwidth of 415 KHz is suitable. If the system already contains a high performance clock, with excellent RMS jitter performance up to a 1.5 MHz bandwidth, then the PLL’s high bandwidth mode may be used. 40 20 GAIN (dB) 0 -20 -40 -60 Loop Bandwidth at 0.415 MHz Loop Bandwidth at 1.50 MHz -80 1 10 10 2 10 3 10 4 10 5 10 6 10 7 8 10 OFFSET (Hz) Figure 6-16. PLL Phase Noise Transfer Function: ADC CLK = 40 MHz On the input clock, excessive RMS jitter within the PLL bandwidth will be seen in the output spectrum as sidebands, or close in phase noise, around the fundamental signal. 6.13 DIGITAL DECIMATION FILTER AND EQUALIZER The digital decimation filter is an integral part of the sigma delta architecture. It decimates the oversampled data from the modulator down to the sample rate, and its extremely sharp low pass characteristic combined with the modulator’s broad band response provides the intrinsic anti-alias filter. The digital low pass filter exhibits 72 dB of attenuation in the stop band. Figure 6-17 shows the digital filter transfer function at 40 MSPS, compared to a third order Butterworth transfer function. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 45 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Figure 6-17. Digital Filter Transfer Function Due to the digital implementation of the filter, the filter parameters automatically scale with the ADC sampling frequency. Such steep digital filters introduce group delay problems, but the LM96511 ADC includes a digital equalizer, which reduces group delay ripple variation to less than 0.05 samples. In applications where group delay is not of concern, the equalizer can be turned off through the SPI™ interface (register address 0Bh) in order to save power. 6.14 OUTPUT CLOCK SYNCHRONIZATION ACROSS MULTIPLE CHIPS In systems containing more than one LM96511, it is often required that the timing of output samples is synchronized across the multiple chips. The PLL in the LM96511 ADC takes care of this automatically by frequency-locking the output clocks with the input clock for each LM96511 device. However, the user must still ensure, using correct board layout and clock buffering techniques, that the input clock to each LM96511 ADC (ADC CLK) is synchronized to each other. If this is the case, then the output bit clocks from each LM96511 ADC will also be synchronized. This means that output samples are aligned with each other. 6.15 CAPACITOR SELECTION The ADC LPF BYP pin provides the capacitance for the low pass filter between the DAC bias block and the DAC in the sigma-delta modulator. The filter blocks noise from the DAC Bias block from entering the DAC. Any noise which passes through this filter will be seen in the spectrum as side skirts around the carrier. The filter circuit, which is a first order RC filter, is shown in Figure 6-18 LM96511 ADC 6' Modulator RDCAP DAC Bias DAC 1.5 k5 ADC LPF BYP CDCAP AGND Figure 6-18. DAC LPF Capacitor 46 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 The ADC LPF BYP pin must be connected to AGND through a low leakage, minimum 100 nF capacitor. If the application is especially sensitive to close to the carrier phase noise, then it is recommended to increase CDCAP, up to a maximum of 10 μF. For other applications where close to the carrier phase noise is not important, the capacitor can be kept small in order to reduce costs and minimize board space. The corner frequency of this filter is determined by the equation: ´ ¶ = 1 2SRDCAPCDCAP (2) 6.16 ADC OUTPUT CONSIDERATIONS The LM96511 offers a variety of output settings in order to cater for different system design and integration needs 6.16.1 Output Driving Voltage, ADC IO DVDD The ADC output driver voltage, ADC IO DVDD, can be set between 1.2V and 1.8V. An ADC IO DVDD of 1.2V will offer the lowest power consumption. Because ADC IO DVDD can be varied, the LM96511 provides, via the SPI™ registers, the ability to adjust the output common mode voltage. 6.16.1.1 Output Modes and Output Common Mode Three different output modes are also supported: SLVS, LVDS and reduced common mode LVDS. SLVS and LVDS modes output data according to their respective specifications. Reduced common mode LVDS must be used when the output driver voltage, ADC IO DVDD, is 1.2V. The standard LVDS common mode voltage is 1.2V, which is obviously not feasible if ADC IO DVDD is 1.2V. Therefore, the output common mode voltage must be set to 1.0V by setting the bit OCM in the LVDS Control Register to 0. When ADC IO DVDD is 1.8V, the standard LVDS common mode voltage of 1.25V must be used, by setting OCM (SPI™ Register 0Ch) equal to 1. Table 6-1 summarizes these different output modes: Table 6-1. ADC Output Mode Summary Output Mode ADC IO DVDD (V) SPI™ Register 0Ch[1] (OCM) SPI™ Register 0Ch[0] (SLVS) Reduced CM LVDS 1.2 0 0 Output Common Mode (V) 1.0 LVDS 1.8 1 0 1.25 SLVS 1.2 X 1 0.175 SLVS mode offers the lowest power consumption followed by reduced common mode LVDS and then the standard LVDS. As well as the different output modes, the output drive current can also be controlled via the LVDS Control Register. The default output drive current is 2.5 mA, but this can be increased to 3.5 mA or 5 mA, depending on output trace routing and receiver requirements. Power consumption of the LM96511 will increase slightly as the output driver current is increased. 6.16.1.2 Termination The final control feature available in the LVDS Control Register is the choice between internal and external 100Ω termination. Although the termination is recommended to be as close to the receiver as possible, in some cases it may be necessary or desirable to perform this termination at the transmitter. Internal 100Ω termination at the transmitter (the LM96511) is enabled by setting the SPI™ register bit TX_term to 1. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 47 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 6.16.1.3 LVDS Output Training Sequences Often it is necessary to calibrate the LVDS receiver, for example an FPGA or DSP, so that skew between the eight ADC output channels is minimized. In order to simplify this process, the LM96511 provides three LVDS training modes, where a pre-defined or custom pattern is output on all eight channels simultaneously. While a training mode is active, the word and bit clocks are output as usual. In order to select a training mode, the TSEL bits of the Decimator Control Register (0Bh) must be programmed via the SPI™ compatible interface. There are two pre-defined training patterns, or a custom pattern can be loaded via the SPI™ compatible interface into the Serializer Custom Pattern 0 and 1 Registers (08h and 09h). In order to return to normal ADC operation after skew calibration, the TSEL bits should be returned to their default value of 00. ADC Outputs CH0 Decimator Output Training Sequence 1: 000000111111 CH0 Serializer DO0+ DO0- CH7 Serializer DO7+ DO7- Training Sequence 2: 101010101010 Training Sequence 3: Custom Pattern Serializer Custom Pattern Registers 10h and 11h TSEL[0] TSEL[1] CH7 Decimator Output From Decimator Control Register 16h Figure 6-19. LVDS Training Sequence 6.17 The Voltage Reference The LM96511 ADC provides an on chip, ±5% tolerance voltage reference (ADC RREF), together with all necessary biasing circuits and current sources. A 10kΩ (±1%) resistor (RREF) must be connected between ADC RREF and AGND in order to establish the biasing current of the ADC. If a tighter tolerance reference is required for improved thermal stability, an external voltage reference can be connected between the ADC VREF and AGND pins. This external reference must be able to support a 20kΩ internal load tied to the internal voltage reference (500 mV nominal). The RREF resistor must be connected even when using an external reference. When using the internal reference, ADC VREF should be connected to AGND through a 100 nF capacitor. Chip-to-chip gain matching between several LM96511 ADCs can be improved by connecting the ADC VREF pins of the ADCs. This is shown in Figure 6-20: 48 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 10 k5 (±1%) RREF 10 k5 (±1%) RREF AGND ADC VREF ADC RREF LM96511 n AGND ADC VREF ADC RREF LM96511 2 AGND ADC VREF ADC RREF LM96511 1 10 k5 (±1%) RREF AGND plane Figure 6-20. Reference Sharing 6.18 CW Doppler Section Theory of Operation As illustrated in Figure 6-21 below, the LM96511 includes a CW Doppler demodulator for analog beamforming in ultrasound applications. Eight single-ended in-phase (CW I Chx) and quadrature (CW Q Chx) output pin currents (16 total pins for 8 channels) are summed together using an external summing amplifier (one each for I and Q outputs) as shown. Each channel’s phase can be controlled in 22.5° increments using a 4 bit phase code with an SPI™ compatible interface register. With a common RF input applied to all channels and the same phase code programmed, all 8 channels’ outputs will be nominally in phase (I to I and Q to Q). If, for example, Channel 5’s phase code is changed from the default value of 0000 to 0101, the Channel 5 output will lead any Channel with phase code 0000 by 112.5° (= 5 x 22.5°). With N-phase-aligned channels summed together, the SNR increases by √N or 3 dB every time N doubles, since the CW Doppler signal increases by N but uncorrelated noise increases by √N. Similarly, the LNAs and demodulators do not share any references or internal functions in order to keep their noise contributions uncorrelated. The CW Doppler section requires a differential 16x Local Oscillator (LO) input. The clock source used must have high fidelity and low phase noise to maintain low Doppler phase noise. The typical LO common mode (CM) level is 1.2V with a 0.4Vpp differential swing (100Ω differential source). Internally, the LO input is divided by 16 and fed to doubly-balanced demodulators. The LO duty cycle should be close to 50%. A Doppler Reset pin is provided (CW/DVGA RST) which resets all the LO dividers to allow synchronization by placing the divider's individual counters in a known state. This allows several LM96511’s to be used with additional channels. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 49 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com LNA IN CH 0+ B - mode path Sleep Mode LNA LNA IN CH 0 - I OUT Other I Channels Summing Amplifier X CW I CH 0 CW Q CH 0 X Q OUT Other Q Channels 0° CW CLK + Summing Amplifier 90 ° Divide by 16 CW CLK - Phase Control (individual phase adjust for each channel) ) LM96511 Figure 6-21. Signal Path (CW Doppler) Single Channel Individual I and individual Q outputs are summed together using a single-supply summing amplifier which observes the LM96511 Doppler output compliance range (2.1V to 3.6V). Figure 6-22 shows one such implementation employed on the LM96511 Reference Board (available for purchase from Texas Instruments): R3 82 C2 47 nF R2 200 R1 82 C1 330 nF ++ +2.5V I1 5V -U1 ½ LMP7732 I-V Converter Figure 6-22. I-V with Integrated 2–Pole LFP It is important to be mindful of noise, especially 1/f noise in the power supplies, particularly the “+2.5V” supply tied to the non-inverting input of the summing Op Amp. 50 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 A low noise Op Amp (LMP7732) is selected for this application to minimize the noise impact. The “I1” current source represents a single output current from the CW Doppler section of the LM96511. Other outputs can be paralleled together. The I-V converter output is then AC coupled to a 24-bit ADC (AsahiKasei (AKM) Part # AK5386VT) input for acquisition and processing. The use of a high bit count (or proaudio grade) ADC is essential in keeping the noise floor low to maximize SNR. The I-V converter of Figure 6-22 is biased for single supply (VCC=5V) operation with its non-inverting input tied to a low noise +2.5V reference. The Feedback action ensures low CW DOPPLER output compliance. The 2nd order Butterworth LPF in Figure 6-22 has a passband gain of ~38 dB.Ω (=R3=82 V/Amp). Figure 6-23 shows the I-V converter’s transfer function: 20 35 Gain 0 30 -20 25 -40 20 15 -60 Phase -80 10 -100 5 -120 0 -140 -5 -160 -10 1.0e2 1.0e3 1.0e4 TRANSIMPEDANCE PHASE (°) TRANSIMPEDANCE GAIN (dB. ) 40 -180 1.0e5 f (Hz) Figure 6-23. CW Doppler LPF Gain/Phase Characteristics With a typical ±4.2 mA from each CW DOPPLER output and 4 channels summed together, the Op Amp output voltage is ±1.38V (= ±4.2 mA x 4 x 82 ohm) from VCC/2, which can be supported with a single 5V supply and the op amp’s Rail-to-Rail output. The LMP7732 has approximately 17 mA (± 4.2 mA x 4) output current capability required when its output is at least 0.4V away from either rail, which is the present case. The LPF in Figure 6-22 has a -3dB bandwidth of 10 KHz, suitable for CW Doppler blood flow applications. The Doppler shift expression below shows the shift in frequency as a function of target speed: '´ ¶D = ± where • • • • 2'Q cos T O ΔfD = Change in frequency (CW Doppler output tone frequency) (Hz) Δν = Speed difference between target and ultra source (m/s) λ = Wavelength of ultra-sound signal (m/cycle) θ = Angle between incident wave and the velocity vector of the moving target (3) With a typical ultrasound propagation speed of 1540 m/s and 5MHz repetition rate, the wavelength, λ, is 308 μm/cycle. Assuming a 0° incidence angle, blood flowing at around 15 cm/s will produce a frequency shift of 974 Hz: 2 x 0.15(m/s) x cos(0) 308(Pm/s) (4) OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 51 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 6.18.1 CW DOPPLER NOISE ANALYSIS The combination I-V converter & LPF of Figure 6-22, slightly degrades the LM96511 Doppler output noise. From the Section 3.4, with 53 pA/√Hz typical RMS noise from each of the four LM96511 outputs summed, one can expect 8.7 nV/√Hz (= 53 pA/√Hz x 82Ω x √4) of typical RMS noise voltage density at the I-V converter output, assuming a noiseless I-V converter. The I-V converter noise contribution is dominated by the LMP7732's voltage noise (= 2.9nV/√Hz) and its noise gain (≊ (1+R3/R1)= 2V/V passband approximation) resulting in 5.8nV/√Hz typical rms noise at the output. Resistor (R1-R3) thermal noise accounts for another 3.9nV/√Hz for a total RSS noise of 7nV/√Hz at the I-V converter output. The impact on the LM96511 related noise is 2.3 dB : 20 x log (7.0 nV/RtHz) 2 + (8.7 nV/RtHz ) 2 8.7 nV/RtHz (5) With a 10 kHz LPF and the LM96511's typical ±3mA current from each output, and assuming a sinusoidal peak-to-RMS ratio of √2, one can expect a SNR of 119 dB: 20 x log 3 mA x 8 x 82: x 1/ 2 (7 nV) 2 + (8.7 nV) 2 x 10 kHz (6) Note that the LMP7732's low 1/f noise corner frequency (= 3Hz) helps in keeping the 1/f noise inconsequential thus maintaining high SNR. Figure 6-24 shows an implementation of 64 CW Doppler receive channels for either “I” or “Q” outputs. Each LM96511 CW Doppler output is represented by a current source symbol. In this implementation, each primary I-V converter (U1) handles 4 channels while U2 sums the outputs of all I-V converters. R4, R5, C3, and C4 form a combination high-pass and low-pass filter that strips the DC component and attenuates the signals beyond ~50 KHz. Analog switch S1 is used to selectively shutdown channels; Often, a 128 channel ultrasound system operates with 64 receive channels. Switches S2 and S3 are used to set the overall gain. This is commonly done to optimize dynamic range depending on the target Doppler echo. The U2 gain is set for FS output (3VPP in this case) with offset frequency signal amplitudes typically 20 dB down from the FS CW Doppler output, or about ±0.42 mA from each LM96511 output. 52 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 R3 82 R2 200 - R4 1k U1 ½ LMP7732 C1 330 nF + C3 0.68 PF S1 R5 1k R7 C4 3.9 nF I-V_Converter +2.5V R1 82 C6 5V C5 S3 LM96511 (4 Outputs) C2 47 nF - R4 1k U1 ½ LMP7732 C1 330 nF + C3 0.68 PF S1 5V - R5 1k U2 ½ LMP7732 + C4 3.9 nF I-V_Converter +2.5V R1 82 C2 47 nF 5V +2.5V LM96511 (4 Outputs) S2 R6 R3 82 R2 200 To ADC Input 3Vpp Out Full Scale Repeated as needed (64 Receive Channels Total) R3 82 R2 200 LM96511 (4 Outputs) - R4 1k 5V U1 ½ LMP7732 C1 330 nF + +2.5V R1 82 C2 47 nF I-V_Converter C3 0.68 PF S1 R5 1k C4 3.9 nF Figure 6-24. CW Doppler Output (I or Q) Implementation (64 Receive Channels) 6.18.2 CW DOPPLER 16x LO SOURCE IMPLEMENTATION In order to achieve the phase noise performance specified in Electrical Characteristics, the CW_Doppler 16x LO source (CW CLK input pins) should have low jitter (low phase noise). The performance specifications reflected in this datasheet were obtained with highly accurate 80 MHz (for 5MHz CW_Doppler signal) sources made by Wenzel Associates, Inc. Their oscillators exhibit ~ -165 dBc/ Hz @ 10 KHz phase noise. The 16xLO implemented in the LM96511 Reference design, uses a lower cost oscillator from Vectron International, which exhibits acceptable phase noise performance (-145 dBc/Hz @ 10 KHz) in conjunction with Texas Instrument's LMK01000 low phase-noise clock buffer-divider chip. By dividing down from a higher frequency source, one can achieve 6dB of improvement in phase noise for every divide-by-two. The block diagram below shows this in more detail: OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 53 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 5V Vectron 320 MHz 150 LMK01000 240 1 nF CLKout3 LVPECL CLKout3* CLKIn0 C1310A10103-320MHz 150 100 CLKout0 CLKIn0* CLKout0* LVDS 1 nF 240 100 LEuWire CW CLK+ CW CLK- DATAuWire CLKuWire LMK01000 MICROWIRE Programming Pins ADC CLK+ 100 40 MHz LM96511 ADC CLK- Figure 6-25. CW Doppler Low-Phase Noise Clock Source Design In Figure 6-25, a low phase noise 320 MHz source is divided by 4 (MICROWIRE programmable) in an LMK01000 to provide an 80.0 MHz CW CLK for a 5.0 MHz ultrasound signal. Other LMK01000 outputs are available for auxiliary functions like the 40 MHz B-mode ADC clock. Keep in mind however that the low-phase noise of this approach is not required by the B-mode ADC CLK because of its integrated PLL. The faster edges and lower signal swing of the LMK01000's LVPECL outputs (CLKout3-7) provide better phase noise performance (lower jitter) than the LVDS outputs (CLKout0-2). 6.19 LM96511 Power Management Table 6-2. LM96511 Power Consumption for Various Conditions AMP CW/DVGA & ADC CW/DVGA Pins Operating Condition LNA DVGA B-Mode ON (LNA PD=LO) 280 mW ON (DVGA PD=LO) 230 mW — POWER DOWN (LNA PD=HI) 12 mW POWER DOWN (DVGA PD=HI) 14 mW CW Doppler Mode ON (LNA PD=LO) 280 mW — POWER DOWN (LNA PD=HI) 12 mW 0 1 (1) 54 Doppler Demod. ADC Total Power Consumption ON 350 mW 884 mW SLEEP MODE (1) 40 mW N/A OFF 24 mW 1.63W POWER DOWN 14mW ON 1.3W 40 mW N/A ADC in Sleep Mode using SPI™ compatible register 00h[1]. See Section 6.21. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 The ADC within the LM96511 operates normally at ultra-low power levels. In addition, several power management modes are provided: • Power Down (Accessible through PD bit of Top Control Register, 00h[0], or through individual channel power down, 01h[0-7]. See Section 6.21) • Sleep (Accessible through SLEEP bit of Top Control Register 00h[1]. See Section 6.21) Power Down is the lowest power consumption mode, but with a longer wake-up time than Sleep mode. In power down mode, all circuits in the ADC chip are turned off, including the PLL, reference and bias circuits. The LM96511 ADC Power consumption in Sleep mode is higher than in Power Down mode, but pin access (ADC CW/DVGA pin) and fast wake-up enables duty cycle powering of the ADC. The LM96511 ADC also allows channel by channel Power Down through the ADC/ LVDS Channel Power Down register (SPI™ register 01h[0-7]). When a single channel is in Power Down, the ΣΔ modulator, digital decimating filter and LVDS outputs for that channel will be shut off, with the corresponding single channel reduction in power consumption. 6.19.1 POWER-UP SEQUENCING The ADC within the LM96511 should be powered-up prior to the amplifier section. The ADC contains a power-on reset circuit, connected to ADC AVDD. To ensure correct reset operation, the power supplies should be provided in the following order (10 ms minimum delay between each supply): 1. ADC IO DVDD (connected to AMP IO DVDD) (1.2V) 2. ADC DVDD (1.2V) 3. ADC AVDD (1.2V) 4. The remaining supplies simultaneously or in any order: AMP AVCC A (3.3V), CW AVCC (5V), AMP DVDD (3.3V) Additionally, it is required that the rise time for ADC DVDD and ADC AVDD each is longer than 40 μs. If the ADC power-up sequence order above (steps 1-3) is not followed, then , prior to amplifier power-up (step 4), the user should apply a 10ms duration reset via the reset pin (ADC RST), and wait another 10ms before applying the amplifier power (step 4). One method of power sequencing is to use the LM3881, or equivalent, Power Sequencer IC. When used with on-board regulators with shutdown capability (e.g. LP3878), the LM3881 can provide a simple, costeffective way of controlling the sequence of 3 supplies. Input Supply (2.7V ± 5.5V) LM3881 VCC EN INV FLAG1 Flag1 Æ ADC DVDD Regulator FLAG2 Flag2 Æ ADC AVDD Regulator FLAG3 Flag3 Æ AMP AVCC, CW AVCC, & AMP DVDD Regulators TADJ CADJ GND Figure 6-26. LM3881 Power Sequencer Can be Used for Proper LM96511 Power-Up OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 55 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com LM3881’s “Flag1” output is the first to come-up and “Flag3” is the last. For the LM96511, the ADC IO DVDD regulator will be the first to come-up and thus need not be controlled by the LM3881. ADC DVDD will be controlled by the LM3881 “Flag1” output, ADC AVDD by “Flag2” output, and “Flag3” powers-up the rest of the supplies simultaneously. To power down, turn off the voltages in the exact reverse order. Table 6-3. Recommended Operating Conditions IOR On (SPI™ Register 02h[4]= 1) ADC Sampling Rate 40/40.5 MSPS (SPI™ Register 00h[4]=1) DVGA Initial Attenuation (See Table 6-5) 32dB (DVGA INIT MSB = HI, DVGA INIT LSB = HI) DVGA PA HI LO ADC Data Out LVDS Equalizer Off (SPI™ Register 0Bh[4]=0) (Default) CGS Auto Gain (SPI™ Register 0Ah[7]= 0) (Default) SHBW (PLL Bandwdith) Low Bandwidth (SPI™ Register 03h[1]= 0) (Default) DVGA Half-Step Disable 0 (SPI™ Register 1Ah[3]= 0) (Default) All Other Conditions Default 6.20 SPI™ Interface 6.20.1 THE SERIAL PERIPHERAL INTERFACE The LM96511 provides several user controlled functions which are accessed through a standard SPI™ compatible, Serial Interface. Figure 6-27 illustrates a method to convert a “four wire” SPI™ compatible controller (Data Out, Data In, Clock, and Chip Select) to the “three-wire” (bi-directional Data In / Out) SPI™ compatible interface required by LM96511. The Serial Interface offers users with a range of supply voltages from 1.2V to 1.8V. The Level Translator shown allows the SPI™ Controller to Write to or Read from the LM96511 even if it uses a different supply voltage than LM96511. TRI-STATE® or Hi-Z Buffer output_enable SPI Controller (Master) e.g. DSP, Microcontroller, FPGA serial_out Note: ADC SPI CS* and AMP SPI CS* should never be enabled (low) at the same time serial_in SPI DIO clock SPI CLK LM96511 ADC SPI CS chip_select_b chip_select_a AMP SPI CS Figure 6-27. SPI™ Bus Master Slave Connection 6.20.2 ACCESS TO THE SERIAL PERIPHERAL INTERFACE The SPI™ compatible interface is accessed through the use of four pins: ADC SPI™ CS, AMP SPI™ CS, SPI™ DIO, and SPI™ CLK. The SPI™ DIO is the data input/ output bidirectional port. The SPI™ DIO voltage levels are between the SPI™ supply voltage and ground. The SPI™ CLK acts as the SPI™ compatible clock input. Two chip selects are used to access the two functional parts of the device, ADC SPI™ CS for the ADC segment and AMP SPI™ CS for the amplifier segment. The generic timing diagram in Figure 6-28 shows the relative timing of the signals used to access the Serial Interface. Figure 4-4 and Figure 4-5 are included to give timing specifics for write mode and read mode respectively. Values for these specific parameters can be found in Section 3.8. 56 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 The initial conditions for the SPI™ compatible signals are the beginning of an access sequence as follows: SPI™ CLK will start low, both AMP SPI™ CS and ADC SPI™ CS will start high, and SPI™ DIO will be undriven. To start an SPI™ access, either AMP SPI™ CS or ADC SPI™ CS (never both at the same time) will be brought low. At the same time, SPI™ DIO should be driven to the MSB of the address to be accessed. The SPI™ CLK will then start and rise in the center of the address bits from MSB to LSB. Each address is represented with 7 bits, A[7:1], the first 7 bits of the sequence on SPI™ DIO . The eighth bit in the SPI™ DIO sequence, A[0] denotes a read or write access command, R/W. If the access is a read access, R/W = 1, then the user must disable the master line driven on the next falling edge of SPI™ CLK. At this point, the line will be driven by the SPI™ compatible interface of the LM96511 (slave). As the SPI™ CLK continues to toggle, the SPI™ slave will drive out the bits associated with the address input to the part D[7:0]. After the eight bits have been shifted out, the chip select can be returned high. If the access is a write access, R/W = 0, the user must drive the 8 bits associated with the address given, D[7:0], on the next eight SPI™ compatible clock cycles. After these 8 bits are shifted in, the chip select can return to the high state ending the transaction. If multiple transactions are done on a single SPI™, the associated chip select must be returned high between successive commands. During a write command, if the chip select signal is pulled high prior to the appropriate time, the write access will not be completed and the internal SPI™ compatible interface may not properly clear. At this point, a hard reset may be necessary to overcome a bad state, and writing may need to recommence. Two reset pins are also available on the LM96511, AMP RST (active HI) and ADC RST (active LO). These reset pins will asynchronously clear the AMP SPI™ and ADC SPI™ respectively. SPI CLK AMP/ADC SPI CS SPI DIO A7 A6 A5 A4 A3 A2 A1 SPI DIO is driven from externally R/W D7 D6 D5 D4 D3 D2 D1 D0 If R/W = 1 (read), the SPI drives SPI DIO. If R/W = 0 (write), SPI DIO is driven externally. Figure 6-28. SPI™ Compatible Read/Write Timing Diagram 6.20.3 CONNECTING MULTIPLE LM96511 DEVICES TOGETHER In certain applications, more than one LM96511 may need to be accessed by the same SPI™ compatible master controller. In this case, separate chip selects will be required for each AMP SPI™ CS pin in the system. This is due to the fact that each amplifier path will have path specific information which will need to be relayed to the paths individually. The ADC SPI™ CS can typically be shared as the ADC channels have very few channel specific programming requirements. An exception may be made in the case of a user who would choose to power down certain ADC’s in the system (done through ADC SPI™ register), in which case separate lines would be needed for each . A shared ADC SPI™ CS system is shown in Figure 6-29. The user must realize that connecting the chip selects of numerous chips in any system will negate the use of read mode for the affected SPI™ slaves. This is due to bus contention issues as each slave will attempt to drive its value at that address. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 57 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Tri-state or Hi-Z Buffer output_enable SPI Master SDATA_OUT SDATA SPI DIO SDATA_IN LM96511 SCLK e.g. DSP, Microcontroller, FPGA SPI CLK SCLK chip_select_b_1 ADC Chip Select to multiple ADCs ADC SPI CS chip_select_a_1 AMP SPI CS 1-N chip_select_a_N SPI DIO LM96511 SPI CLK ADC SPI CS AMP SPI CS Figure 6-29. SPI™ Compatible Interconnect for Multiple LM96511's (Open Drain Mode) 6.20.4 SERIAL PERIPHERAL INTERFACE READ AND WRITE SPEED SPI™ CLK controls the speed of interaction with the LM96511. See Section 3.8 for the timing information. The following table shows the complete set of user accessible SPI™ compatible registers, with descriptions of the functionality of each bit in the following section. 6.21 SPI™ Register Map • • • The “Address” column corresponds to A7-A1 (MSB –LSB). A0, which is the R/W bit, is not considered as part of the address. “RSV” = Reserved (See notes if applicable.) Register Index — ADC Section (Enabled with ADC SPI™ CS): Addr b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] Default CBR 40/40.5 SRES 0 SLEEP PD 00h PD5 PD4 PD3 PD2 PD1 PD0 00h 0 0 IOR 0 0 0 0 00h 0 0 0 0 0 SHBW STCAL 00h 0 INVCLK 100HYS 50HYS 20HYS 10HYSOFF HYSOFF 00h ADC Top Control Register (Note 1) 00h 0 0 ADC / LVDS Channel Power Down Register ( 01h PD7 PD6 (1) ) Modulator Overload Control Register ( (2)) 02h 0 PLL Control Register ( 03h (3) ) 0 LVDS Input Clock Hysteresis ( (4)) 05h (1) (2) (3) (4) 58 0 The LNA non-inverting input is always driven single-ended. The inverting input is always AC grounded. See Section 6 for typical connection diagrams in Figure 6-2. Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument’s Average Outgoing Quality Level (AOQL). Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Sleep mode keeps the PLL, Reference and Bias networks active to allow fast recovery and interleaved imaging modes. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Register Index — ADC Section (Enabled with ADC SPI™ CS): Addr b[7] b[6] Serializer Custom Pattern 0 Register ( 08h Custom Pattern[7] b[5] b[4] b[3] b[2] b[1] b[0] Default Custom Pattern[5] Custom Pattern[4] Custom Pattern[ 3] Custom Pattern[2] Custom Pattern[1] Custom Pattern[0] 00h 0 0 Custom Custom Pattern[ Pattern[10 11] ] Custom Pattern[9] Custom Pattern[8] 00h (5) ) Custom Pattern[6] Serializer Custom Pattern 1 Register ( (5)) 09h 0 0 Decimator Clipping Control Register ( (6)) DGFa 0Ah CGS Decimator Control Register ( 0Bh 0 DGFb 0 a[2] a[1] a[0] b[2] b[1] b[0] 00h 0 0 EQON DFS MSB TSEL[1] TSEL[0] 00h 0 0 TX_term I_drive[ 1] I_drive[0] OCM SLVS 00h RSV RSV RSV RSV RSV RSV RSV N/A (7) ) LVDS Control Register ( (8)) 0Ch ADC Die ID (Read Only) 0Fh (5) (6) (7) (8) Per 1 Hz BW, offset 1 kHz from a 5 MHz, FS input. Output Phase noise, expressed in - dBc/Hz, follows both RF input and CW CLK phase noise. To meet the demodulated Output specification, integrated phase noise of both the RF Input signal and CW CLK must be better than -160 dBc/Hz at 1 kHz offset. Within one channel Channel-to-Channel One channel with active input and the worst of the other 7 channels measured. Register Index— Amplifier Section (Enabled with AMP SPI™ CS): Doppler Controls ( (1)) 11h 0 0 0 0 CH0 PH[3] CH0 PH[2] CH0 PH[1] CH0 PH[0] 00h 12h 0 0 0 0 CH1 PH[3] CH1 PH[2] CH1 PH[1] CH1 PH[0] 00h 13h 0 0 0 0 CH2 PH[3] CH2 PH[2] CH2 PH[1] CH2 PH[0] 00h 14h 0 0 0 0 CH3 PH[3] CH3 PH[2] CH3 PH[1] CH3 PH[0] 00h 15h 0 0 0 0 CH4 PH[3] CH4 PH[2] CH4 PH[1] CH4 PH[0] 00h 16h 0 0 0 0 CH5 PH[3] CH5 PH[2] CH5 PH[1] CH5 PH[0] 00h 17h 0 0 0 0 CH6 PH[3] CH6 PH[2] CH6 PH[1] CH6 PH[0] 00h 18h 0 0 0 0 CH7 PH[3] CH7 PH[2] CH7 PH[1] CH7 PH[0] 00h CS5 CS4 CS3 CS2 CS1 CS0 00h 0 0 Half Step Disable (0=0.05 db; 1=0.1d b R_EN R1 R0 00h Individual CW Doppler Channel Phase Update Register ( (2)) 19h CS7 CS6 DVGA Attenuation Control Register ( (3)) 1Ah (1) (2) (3) 0 0 “Nominal” attenuation defined as straight line connecting minimum attenuation (0dB) to maximum attenuation (38dB). This parameter is specified by design and/or characterization and is not tested in production. Ensured by characterization for all phases. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 59 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Register Index— Amplifier Section (Enabled with AMP SPI™ CS): LNA Offset Trim ( (4)) 1Bh LNA Ch0 Polarity LNA Ch0 D6 (MSB) LNA Ch0 D5 LNA Ch0 D4 LNA Ch0 D3 LNA Ch0 D2 LNA Ch0 D1 LNA Ch0 D0 (LSB) Factory Set 1Ch LNA Ch1 Polarity LNA Ch1 D6 (MSB) LNA Ch1 D5 LNA Ch1 D4 LNA Ch1 D3 LNA Ch1 D2 LNA Ch1 D1 LNA Ch1 D0 (LSB) Factory Set 1Dh LNA Ch2 Polarity LNA Ch2 D6 (MSB) LNA Ch2 D5 LNA Ch2 D4 LNA Ch2 D3 LNA Ch2 D2 LNA Ch2 D1 LNA Ch2 D0 (LSB) Factory Set 1Eh LNA Ch3 Polarity LNA Ch3 D6 (MSB) LNA Ch3 D5 LNA Ch3 D4 LNA Ch3 D3 LNA Ch3 D2 LNA Ch3 D1 LNA Ch3 D0 (LSB) Factory Set 1Fh LNA Ch4 Polarity LNA Ch4 D6 (MSB) LNA Ch4 D5 LNA Ch4 D4 LNA Ch4 D3 LNA Ch4 D2 LNA Ch4 D1 LNA Ch4 D0 (LSB) Factory Set 20h LNA Ch5 Polarity LNA Ch5 D6 (MSB) LNA Ch5 D5 LNA Ch5 D4 LNA Ch5 D3 LNA Ch5 D2 LNA Ch5 D1 LNA Ch5 D0 (LSB) Factory Set 21h LNA Ch6 Polarity LNA Ch6 D6 (MSB) LNA Ch6 D5 LNA Ch6 D4 LNA Ch6 D3 LNA Ch6 D2 LNA Ch6 D1 LNA Ch6 D0 (LSB) Factory Set 22h LNA Ch7 Polarity LNA Ch7 D6 (MSB) LNA Ch7 D5 LNA Ch7 D4 LNA Ch7 D3 LNA Ch7 D2 LNA Ch7 D1 LNA Ch7 D0 (LSB) Factory Set Post Amp (PA) Offset Trim ( (5)) 23h 0 0 0 PA Ch0 Polarity PA Ch0 D3 (MSB) PA Ch0 D2 PA Ch0 D1 PA Ch0 D3 (LSB) Factory Set 24h 0 0 0 PA Ch1 Polarity PA Ch1 D3 (MSB) PA Ch1 D2 PA Ch1 D1 PA Ch1 D3 (LSB) Factory Set 25h 0 0 0 PA Ch2 Polarity PA Ch20 D3 (MSB) PA Ch2 D2 PA Ch2 D1 PA Ch2 D3 (LSB) Factory Set 26h 0 0 0 PA Ch3 Polarity PA Ch3 D3 (MSB) PA Ch3 D2 PA Ch3 D1 PA Ch3 D3 (LSB) Factory Set 27h 0 0 0 PA Ch4 Polarity PA Ch4 D3 (MSB) PA Ch4 D2 PA Ch4 D1 PA Ch4 D3 (LSB) Factory Set 28h 0 0 0 PA Ch5 Polarity PA Ch5 D3 (MSB) PA Ch5 D2 PA Ch5 D1 PA Ch5 D3 (LSB) Factory Set 29h 0 0 0 PA Ch6 Polarity PA Ch6 D3 (MSB) PA Ch6 D2 PA Ch6 D1 PA Ch6 D3 (LSB) Factory Set 2Ah 0 0 0 PA Ch70 Polarity PA Ch7 D3 (MSB) PA Ch7 D2 PA Ch7 D1 PA Ch7 D3 (LSB) Factory Set Reserved Registers (RSV) 2Bh RSV RSV RSV RSV RSV RSV RSV RSV N/A 2Ch RSV RSV RSV RSV RSV RSV RSV RSV N/A 2Dh RSV RSV RSV RSV RSV RSV RSV RSV N/A 2Eh RSV RSV RSV RSV RSV RSV RSV RSV N/A 2Fh RSV RSV RSV RSV RSV RSV RSV RSV N/A Id[6] Id[5] Id[4] Id[3] Id[2] Id[1] Id[0] N/A Chip ID (Read Only) 30h (4) (5) 60 Id[7] “Removal time” refers to the time CW/DVGA RST must be low prior to the rising edge of DVGA CLK. “Removal time” refers to the time CW/DVGA RST must be low prior to the rising edge of DVGA CLK. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 6.22 SPI™ Register Map Notes 1. ADC Top Control Register The Top Control Register is the basic initialization and control register for the LM96511 ADC. Bit Description 7:6 Write 0 5 CBR: Control Bus Read. When asserted register 00h (this register) can be read, but no other registers. When de-asserted all other registers can be read, but not register 00h. 0: Register 00h cannot be read using SPI™ Read. All other registers can be read back. 1: Register 00h can be read using SPI™ Read. All other registers cannot be read back. 4 40/40.5 Selects the ADC sample rate. This bit should be set according to the applied input clock to obtain optimal performance. 1: 40-40.5 MSPS 3 SRES: Software Reset. When asserted the software reset will reset the LM96511 ADC device. SRES performs the same function as the hardware reset (ADC RST pin). The SRES is self clearing in approximately 2 µs. 0: Software Reset Inactive 1: Software Reset Active 2 0 1 SLEEP: Sleep Mode. Powers down the device with the exception of the PLL and the reference blocks. The time to wake-up from sleep mode is < 10 µs. 0: Sleep Mode Inactive 1:Sleep Mode Active 0 PD: Power Down Mode. Completely powers down the device. The power up time is approximately 20 ms. 0: PD Mode Inactive, device operates normally 1: PD Mode Active, device powered down 2. ADC/LVDS Channel Power Down Register The ADC/ LVDS Channel Power Down Mode Register provides the capability to independently put each ADC channel in Power Down mode. Bit Description 7 PD7: Channel 7 Power Down 0: Channel Active 1: Channel Power Down 6 PD6: Channel 6 Power Down 0: Channel Active 1: Channel Power Down 5 PD5: Channel 5 Power Down 0: Channel Active 1: Channel Power Down 4 PD4: Channel 4 Power Down 0: Channel Active 1: Channel Power Down 3 PD3: Channel 3 Power Down 0: Channel Active 1: Channel Power Down OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 61 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Bit Description 2 PD2: Channel 2 Power Down 0: Channel Active 1: Channel Power Down 1 PD1: Channel 1Power Down 0: Channel Active 1: Channel Power Down 0 PD0: Channel 0 Power Down 0: Channel Active 1: Channel Power Down 3. Modulator Overload Control Register Bit 7:5 4 3:0 Description Write 0 IOR: Enable IOR On Mode (Instand Overload Recovery) This bit can be used to quickly enable IOR mode with the default IOR settings for DGF (see register 0Ah). 0: IOR Mode Disabled 1: IOF Mode Enabled Write 0 4. PLL Control Register Bit 7:2 Description Write 0 4 SHBW: Set PLL to High Bandwidth. The selection of the PLL bandwidth permits to set the sensitivity of the PLL to input clock jitter. Less bandwidth decreases the sensitivity to input clock jitter. The PLL Bandwidth is related to the sampling frequency, the exact values of which can be found in Section 3.3. The PLL will pass any input clock jitter up to the PLL bandwidth, while jitter above the PLL bandwidth will be attenuated. Low bandwidth mode should be used for high jitter input clocks, while high bandwidth mode can be used for high-quality, low jitter input clocks. 0: PLL bandwidth is set to Low Bandwidth (400 kHz). 1: PLL bandwidth is set to High Bandwidth (1.4 MHz). 0 STCAL: Start VCO calibration. The calibration can be manually started in order to assure that the frequency tuning margin is maximum, for example, in case of large temperature change during operation it can be useful to restart the calibration. 0: The VCO calibration starts automatically if a Loss of Lock is detected. 1: The VCO calibration is restarted. 5. LVDS Input Clock - Hysteresis Affects ADC CLK input hysteresis level. Bit 7:6 5 62 Description Write 0 INVCLK: Invert Input Reference Clock. This bit is used to invert the input clock. 0: Reference input clock not inverted. 1: Reference input clock inverted. OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Bit Description 4 100HYS: Enable 100 mV hysteresis. This bit enables 100 mV hysteresis. It should be used for a CMOS input clock only. 0: Normal operation (10 mV hysteresis). 1: 100 mV hysteresis (CMOS input clock only) 3 50HYS: Enable 50 mV hysteresis. This bit enables 50 mV hysteresis. It should be used for a CMOS input clock only. 0: Normal operation (10 mV hysteresis). 1: 50 mV hysteresis (CMOS input clock only) 2 20HYS: Enable 50 mV hysteresis. This bit enables 20 mV hysteresis. It should be used for a CMOS input clock only. 0: Normal operation (10 mV hysteresis). 1: 20 mV hysteresis (CMOS input clock only) 1 10HYSOFF: Disable 10 mV hysteresis. 10 mV hysteresis is the default setting. This bit is used to disable 10 mV hysteresis, in the case where another hysteresis setting is desired, for example when using a CMOS input clock. 0: 10 mV hysteresis. (LVDS Input clock only). 1: 10 mV hysteresis disabled. 0 HYSOFF: Disable all hysteresis settings This bit is used to disable all hysteresis settings. 0: Normal operation (10 mV hysteresis). 1: All hysteresis settings disabled. 6. Serializer Custom Pattern 0 and 1 Registers Address: 08h (pattern 0): This register in conjunction with register 09h provides storage for the custom de-skew pattern. See register 0Bh for a description of how this training sequence is used. Bit 7:0 Description Custom Pattern [7:0]. This pattern forms the lower byte of Custom Pattern [11:0] which is output by the serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register are set to select Training sequence 3. 7. Address: 09h (pattern 1): This register in conjunction with User Register 08h provides storage for the custom de-skew pattern. See register 0Bh for a description of how this training sequence is used. Bit Description 7:4 Write 0 3:0 Custom Pattern [11:8]. This pattern forms the upper 4 bits of Custom Pattern [11:0] which is output by the serializer when the Training Sequence Select bits (bits 1:0) of the Decimator Control Register are set to select Training sequence 3. 8. Decimator Clipping Control Register Bit Description 7 CGS: Custom Gain Setting. This bit is used to override the automatic gain settings for ADC and IOR modes. If the user wishes to write a custom digital gain coefficient using a[2:0] and b[2:0] of this register, then the CGS bit must be set. 0: Normal operation Automatic gain settings used 1: Custom Gain Setting Gain setting from a[2:0] and b[2:0] used OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 63 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Bit Description 6 Write 0 5:3 a[2:0]: Digital Gain Coefficient. In IOR on mode, the input range of an ADC channel is limited to 3.12 Vpp. In IOR off mode the input range is 4.20 Vpp. The output of the digital filter has to be scaled according to the selected mode (the filter data has to be mapped in to the 12bit output data), the difference between 3.12 Vpp and 4.20 Vpp is -2.6 dB, hence the digital filter gain has to be set to 2.6 dB when in IOR on mode and to 0dB when in IOR off mode (default mode). This is performed by setting a Digital Gain Factor (DGF) which is calculated DGF = 32 + 4 x DGFa + DGFb 26 using the following formula: The mapping of the coefficient values for a[2:0] is as follows: 011 = Not used. Defaults to 2 010 = 2 001 = 1 000 = 0 111 = −1 110 = −2 101 = Not used. Defaults to −2 100 = Not used. Defaults to −2 The mapping of the coefficient values for b[2:0] is shown below. shows the available Digital Gain Coefficient settings. 2:0 The mapping of the coefficient values for b[2:0] is as follows: 011 = Not used. Defaults to 2 010 = 2 001 = 1 000 = 0 111 = −1 110 = −2 101 = Not used. Defaults to −2 100 = Not used. Defaults to −2 9. DGF To Digital Gain Look-Up Table 64 Coefficient a[2:0] Coefficient b[2:0] Digital Gain (dB) Equivalent ADC Full Scale Input Range (Vpp) 010 010 4.16 2.60 010 001 3.95 2.66 010 000 3.74 2.74 010 111 3.52 2.80 010 110 3.29 2.88 001 001 3.06 2.96 001 000 2.82 3.04 001 111 2.58 3.12 OVERVIEW IOR ON Mode Default Setting Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Coefficient a[2:0] Coefficient b[2:0] Digital Gain (dB) Equivalent ADC Full Scale Input Range (Vpp) 001 110 2.33 3.22 000 001 2.07 3.3 000 000 1.80 3.42 000 111 1.53 3.52 000 110 1.24 3.64 111 001 0.95 3.96 111 000 0.64 3.90 111 111 0.33 4.04 111 110 0 4.20 110 001 -0.34 4.32 110 000 -0.70 4.56 110 111 -1.07 4.76 110 110 -1.45 4.96 IOR Off Mode Default Setting 10. Decimator Control Register Bit 7:5 Description Write 0 4 EQON: Equalizer Enable. This bit is used to enable or disable the digital equalizer. The equalizer can be switched on in order to reduce the group delay of the output data, at the cost of increased power. 0: Equalizer Disabled 1: Equalizer Enabled 3 DFS: Data Format Select. Selects the format, either Offset Binary or Twos Complement of the output data. 0: 2s Complement 1: Offset Binary 2 MSB: Select the bit order of the LVDS output data stream. 0: LSB first 1: MSB first 1:0 TSEL[1:0]: Training Sequence Select. These bits select the LVDS output data. The default mode of operation is where the filter output data is serialized. In the remaining modes the selected training sequence is repeatedly output from the serializer this allows the receiving data capture circuitry to perform the de-skewing process. One of three known words can be selected, the first two words are hard-coded in the block, the third one, the custom pattern, is written into Registers 08h and 09h Serializer Custom Pattern Registers. Note: The outputs bit-clock and word-clock are not affected by the value of the Training Sequence Select bits. 00 ADC data[11:0] 01 Training Sequence 1: 000000111111 10 Training Sequence 2: 101010101010 11 Training Sequence 3: Custom Pattern OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 65 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com 11. LVDS Control Register Bit 7:5 4 3:2 Description Write 0 TX_term: Enable Internal 100Ω termination for data outputs. 0: Internal 100Ω termination disabled. 1: Internal 100Ω termination enabled. I_drive[1:0]: Controls the current drive of the data outputs. 00: 2.5 mA 01: 3.5 mA 10: Reserved 11: 5mA 1 OCM: Output Common mode. Allows the output common mode to be shifted depending on the setting of ADC IO DVDD. If bit 0 of this register, SLVS, is set to 1 then changing OCM will have no impact on the output common mode. The output common mode in SLVS mode is fixed, as described in Electrical Characteristics. For ADC IO DVDD = 1.2V, OCM must be set to 0. For ADC IO DVDD = 1.8V, OCM must be set to 1. 0: Output Common Mode, VOCM = 1.0V 1: Output Common Mode, VOCM = 1.25V 0 SLVS: Select the format for output data, either LVDS or SLVS. The differences in timing and electrical specifications between the two modes can be seen in Electrical Characteristics. If this bit is set to 1 (SLVS mode), OCM has no effect and the output common mode will be set for SLVS as described in Electrical Characteristics. When LVDS mode is selected, the output common mode must be selected using the OCM bit of this register. 0: LVDS Mode 1: SLVS Mode 12. Doppler Controls: Bit Description 7:4 Write 0 3:0 Chx[3:0]: CW Doppler Channel “x” (0-7) phase angle in binary format from 0° (0000) to 360° (1111) in 22.5° increments. 13. Individual CW Doppler Channel Phase Update The SPI™ compatible registers for the Doppler function (i.e. 11h-18h) are shadow registers that will only be loaded into an active working register on CW CLK+ rising edge after a CW/DVGA RST (pin K15) pulse (see Figure 4-6). This load action will also reset all counters in the CW Doppler mixer. Upon initial chip power-up, CW Doppler register load and mixer counter reset occurs (see Section 6.21 for default values). SPI™ Read operation reads the value of the Shadow register (not the Active register). However, Shadow and Active register values should be the same assuming no Write operation after the pervious CW/DVGA RST high state. 66 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Figure 6-30. CW Doppler Shadow Register Representation In addition to being able to load all CW Doppler channels 0-7 phase angles simultaneously, it is also possible to load each channel’s phase angle individually using SPI™ address 19h. For example, to update phase angle for channel 5 and channel 6 only, the following data is written to 19h: 01100000. This way, Channel 5 and 6 Active register is updated with data in 16h and 17h but Active registers for the other 6 channels are left intact. Bit Description 7 CS7: This bit allows CW Doppler channel 7 phase angle to be updated to the value in shadow register 18h. 0: Active register for channel 7 left intact 1: Load active register for channel 7 with 18h data when CW/DVGA RST is pulled HI 6 CS6: This bit allows CW Doppler channel 6 phase angle to be updated to the value in shadow register 17h. 0: Active register for channel 6 left intact 1: Load active register for channel 6 with 17h data when CW/DVGA RST is pulled HI 5 CS5: This bit allows CW Doppler channel 5 phase angle to be updated to the value in shadow register 16h. 0: Active register for channel 5 left intact 1: Load active register for channel 5 with 16h data when CW/DVGA RST is pulled HI 4 CS4: This bit allows CW Doppler channel 4 phase angle to be updated to the value in shadow register 15h. 0: Active register for channel 4 left intact 1: Load active register for channel 4 with 15h data when CW/DVGA RST is pulled HI 3 CS3: This bit allows CW Doppler channel 3 phase angle to be updated to the value in shadow register 14h. 0: Active register for channel 3 left intact 1: Load active register for channel 3 with 14h data when CW/DVGA RST is pulled HI 2 CS2: This bit allows CW Doppler channel 2 phase angle to be updated to the value in shadow register 13h. 0: Active register for channel 2 left intact 1: Load active register for channel 2 with 13h data when CW/DVGA RST is pulled HI OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 67 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Bit Description 1 CS1: This bit allows CW Doppler channel 1 phase angle to be updated to the value in shadow register 12h. 0: Active register for channel 1 left intact 1: Load active register for channel 1 with 12h data when CW/DVGA RST is pulled HI 0 CS0: This bit allows CW Doppler channel 0 phase angle to be updated to the value in shadow register 11h. 0: Active register for channel 0 left intact 1: Load active register for channel 0 with 11h data when CW/DVGA RST is pulled HI 14. DVGA Attentuation Control: When the CW/DVGA RST pin is HIGH, the step attenuator block in the DVGA can be reset to one of five discrete selectable DVGA Initial Attenuations: 38, 36, 34, 32, or 0 dB. This DVGA Initial Attenuation can be set by either the SPI™ compatible register or by physically applying logic level voltages to ball pin A6 (DVGA INIT MSB), B5 (DVGA INIT LSB), and L17 (DVGA UP). See Table 6-4. SPI™ address 1Ah[2:0] are the register bits used. Normal attenuator gain clocking can be resumed only after CW/DVGA RST pin is returned to 0. Table 6-4. DVGA Initial Attenuation Truth Table DVGA UP E_EN R1 R0 DVGA INIT MSB DVGA INIT LSB Attenuation with CW/DVGA RST pin High (dB) L17 pin 1Ah[2] 1Ah[1] 1Ah[0] A6 pin B5 pin 1 1 0 0 X X 38 1 1 0 1 X X 36 1 1 1 0 X X 34 1 1 1 1 X X 32 1 0 X X 0 0 38 1 0 X X 0 1 36 1 0 X X 1 0 34 1 0 X X 1 1 32 0 X X X X X 0 15. The following short-hand notation for the DVGA gain has been used: Table 6-5. DVGA Notation DVGA Gain (dB) DVGA Attenuation (dB) Short-hand Name 0 0 Max DVGA Gain -19 19 Mid DVGA Gain -38 38 Min DVGA Gain 16. LNA and PA Offset Trim Control Register: There are 7 bits dedicated to LNA offset trim, plus the polarity bit. The maximum positive offset is 1111,1111 and the maximum negative offset is 0111,1111 with X000,0000 for minimum trim. There are 4 bits dedicated to PA offset trim, plus the polarity bit. The maximum positive offset is 1,1111 and the maximum negative offset is 0,1111 with X,0000 for minimum trim. The SPI™ compatible trim data operates through the same die fuses that are used for factory laser trim. The data written into a particular bit is influenced by whether the fuse related to that bit is blown at the factory or not. Here is what should be written to the SPI™ compatible bits for a particular “intended data”: 68 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 LM96511 www.ti.com SNAS476H – MAY 2010 – REVISED MAY 2013 Table 6-6. Offset Trim “Write” Truth Table Write Data Intended Data Factory Blown Fuse Factory Un-Blown Fuse 0 1 0 1 0 1 To know whether a fuse is blown at the factory or not, the register should be read-back at power up (or after AMP RST pulse); a “1” indicates a blown fuse. Here is an example, related to LNA offset trim, for easier understanding: Table 6-7. Offset Trim “Write” and “Read” Example SPI™ Read Back at Power-up or after AMP RST 0000 1100 Intended Data 0000 1010 SPI™ Write Data 0000 0110 SPI™ Read Data (after Write) 0000 1010 OVERVIEW Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 69 LM96511 SNAS476H – MAY 2010 – REVISED MAY 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision G (May 2013) to Revision H • 70 Changed layout of National Data Sheet to TI format Page .......................................................................... OVERVIEW 69 Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM96511 PACKAGE OPTION ADDENDUM www.ti.com 8-May-2015 PACKAGING INFORMATION Orderable Device Status (1) LM96511CCSM/NOPB ACTIVE Package Type Package Pins Package Drawing Qty NFBGA NZJ 376 132 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) SNPB Level-4-260C-72 HR Op Temp (°C) Device Marking (4/5) 0 to 70 LM96511 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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