1/21
STRUCTURE
PRODUCT SERIES
Silicon Monolithic Integrated Circuit
7-Channel Switching Regulator Controller for Digital Camera
ＢＤ９７４５ＥＫＮ
TYPE
PACKAGE
Fig. 1 (Plastic mold) HQFN-48U package
PIN ASSIGNMENT
Fig. 2
BLOCK DIAGRAM
Fig. 3
APPLICATION CIRCUIT
Fig. 4
● 1.5V Minimum input operating.
FEATURES
● Controls up to 7 switching regulators. Step up converter (1channel), Step-down converter
(1channel), Configurable for Step-up or Step-down conversion (3channels),
Positive to negative converter (1channel), Step-up converter for LED (1channel).
● Synchronous rectifying action mode (4channel), Built-in FET Transistor.
● Step-up converter for CCD,Built-in FET Transistor.
● Internal compensation.
● Operating frequency 1.2MHz(CH1～4), 600kHz(CH5～7).
● Short Circuit Protection(SCP) for Over load condition.
● Built-in load switch with soft-start for Step-up converter(CH6,7).
● Back gate control synchronous rectified DC/DC for Step-up(CH1,2,4).
● Thermally enhanced QFN48 package. ( 7mmX 7mm，0.4mm pitch )
Absolute maximum ratings（Ta＝25℃）
Parameter
Power
Power
Supply
Input
O u t p u t
P o w e r
Vo l ta g e
Voltage
C u r r e n t
D i s s i p a t i o n
O p e r a t i n g Te m p e r a t u r e
S t o r a g e Te m p e r a t u r e
J u n c t i o n Te m p e r a t u r e
Symbol
Limits
Units
VBAT, VCC, PVCC
－0.3～7
V
PVCC5, HS6H, HS7H
－0.3～7
V
VHx1～4
－0.3～7
V
VLx1～4
VLx6
IomaxLx1
IomaxLx2～4
－0.3～7
－0.3～18
±1.8
±1.5
0.65(*1)
1.50(*2)
－25～+85
－55～+150
+150
V
V
A
A
W
W
℃
℃
℃
Pd
Topr
Tstg
Tjmax
(*1) Without external heat sink, the power dissipation reduces by 5.2mW/℃ over25℃.
(*2) Reduced by 12mW/℃ over 25℃, when mounted on a PCB (70.0mm×70.0mm×1.6mm).
Recommended operating conditions
Parameter
Power Supply Voltage
Symbol
Spec.
Units
VBAT
1.5 ～ 5.5
V
VCC, PVCC
2.5 ～ 5.5
V
REV. D
2/21
○ Recommended operating conditions
Standard value
Parameter
Symbol
MIN
TYP
MAX
Units
VREF Pin Connect Capacitor
CVREF
0.47
1.0
4.7
μF
VREGA Pin Connect Capacitor
CVREGA
0.47
1.0
4.7
μF
Cscp
-
-
0.47
μF
Oscillator Frequency
fosc
0.6
1.2
1.5
MHz
OSC Timing Resistor
RT
47
62
120
kΩ
P-channel Drain Current(CH1～4)
Idpl
-
-
1.5
A
N-channel Drain Current(CH1～4)
Idnl
-
-
1.5
A
N-channel Drain Current (CH6)
Idnh
-
-
1.0
A
P-channel Drain Current
(Load SW of CH6～7)
-
-
Idpr
1.5
A
500
mA
SCP Pin Connect Capacitor
【Oscillator】
【Driver】
Driver Peak Current (CH5, 7)
Idpeak
-
-
REV. D
Conditions
3/21
○Electrical characteristics（Ta=25℃，VBAT=3V, VCC=5V, RT=62kohm, STB1～7=3V）
Spec.
Parameter
Symbol
Units
Conditions.
Min.
Typ.
Max
【 Reference Voltage for CH5 】
Reference Voltage
Vref5
0.99
1.00
1.01
V
STB5=3V
Line Regulation
DVLi
4.0
12.5
mV Vcc=2.8V～5.5V
Load Regulation
DVLo
1.0
7.5
mV Iref=10μA～100μA
Short Circuit Output Current
Ios
0.2
1
mA Vref=0V
【 Internal Regulator 】
REGA Output Voltage
VREGA
2.4
2.5
2.6
V
Ireg=5mA
【 Low Voltage Input Prevented Operation Faults Circuit 】
Threshold Voltage 2
Vstd2
2.3
2.4
2.5
V
VCC monitor
Hysteresis width 2
ΔVst2
100
200
300
mV
Threshold Voltage 3
Vstd3
1.6
2.0
2.3
V
VREGA monitor
Hysteresis width 3
ΔVst3
100
200
300
mV
【 Start up Circuit 】
Oscillator Frequency
Fstart
150
300
600
kHz
Minimum VBAT Voltage
Vst1
1.5
-
-
V
Soft-start time
Tss1
2.6
4.2
7.4
msec
【 Soft-Start 】
Soft-start time
(CH2～4,CH6,7)
Soft-start time CH5
Tss4
6.8
8.5
10.2
msec
Tss3
5.8
7.7
9.6
msec
2.1
2.2
2.3
V
0.56
0.64
0.72
V
2
0.9
22
4
1.0
170
6
1.1
mV
μA
V
VSCP=0.1V
1.0
1.2
1.4
MHz
RT=62kohm
500
600
700
kHz
RT=62kohm
-5
0.79
-12
380
0
0.80
0
400
5
0.81
12
420
μA
V
mV
mV
INV1~4,6,7,7I,NON5=7.0V
86
77
92
85
97
93
%
%
【 Protection Circuit 】
Timer Start Threshold
Vtcfb
Voltage
Timer Start Threshold
Vtcinv
Voltage
SCP Standby Voltage
Vssc
SCP Output Current
Iscp
SCP Threshold Voltage
Vscp
【 Triangular wave oscillator 】
Oscillator Frequency
ｆosc1
CH1～4
Oscillator Frequency
ｆosc2
CH5～7
【 Error Amp 】
Iinv
Input Bias Current
VINV
INV Threshold
VINV5
NON5 Threshold
VINV7I
INV7I Threshold
【 PWM Comparator 】
MAX DUTY1, 2,3,4
MAX DUTY5, 6,7
Dmax2
Dmax4
VREF5monitor
Error Amp Output monitor
CH1,5～7
INV monitor
CH2～4
CH1～4,CH6,7V
CH5
CH7I
◎This product is not designed for normal operation within a radioactive environment.
REV. D
Test
Circuit
4/21
○Electrical characteristics（Ta=25℃，VBAT=3V, VCC=5V, RT=62kohm, STB1～7=3V）
Spec.
Parameter
Symbol
Units
Conditions
Min
Typ.
Max.
【 Output Circuit 】
CH1,2,3,4 Pch FET
Ronlp
250
350
mΩ Hx=5V
ON Resistor
CH1 Nch FET ON Resistor
Ron1n
-
80
120
mΩ PVCC=5V
CH2,3,4 Nch FET
ON Resistor
Ron2n
-
130
200
mΩ PVCC=5V
CH6,7 Load SW ON Resistor
Ronl
-
250
350
mΩ HS6, 7H=5V
CH6 Nch FET ON Resistor
Ronh
-
450
700
mΩ PVCC=5V
VOUT5H
PVCC5
-1.0
PVCC5
-0.5
-
V
PVCC5=5V,IOUT5=50mA
NON5=0.2V
VOUT5H
-
0.5
1.0
V
PVCC5=5V,IOUT5= - 50mA
NON5=-0.2V
VOUT7H
PVCC
-1.0
PVCC
-0.5
-
V
PVCC=5V,IOUT7=50mA
INV7I=0V,INV7=0.4V
VOUT7H
-
0.5
1.0
V
PVCC=5V,IOUT7= - 50mA
INV7I=0.6V,INV7=1.2V
VUDDO
VBAT×
0.7
-
VBAT
V
VUDUP
0
-
VBAT
×0.3
V
ON
VSTBH1
1.5
-
5.5
V
OFF
VSTBL1
-0.3
-
0.3
V
RSTB1
250
400
700
KΩ
VBAT
ISTB1
-
-
5
μA
VCC, PVCC
ISTB2
-
-
5
μA
Hx
ISTB3
-
-
5
μA
Step-down
UDSEL1, 2,4=VBAT
Lx
ISTB4
-
-
5
μA
Step-up
UDSEL1, 2,4=0V
Start up Current
(VBAT Sink Current)
IST
-
300
1000
μA VBAT=1.5V
Circuit Current on Driving 1
(VBAT Sink Current)
Icc1
-
200
400
μA VBAT=3.0V
Circuit Current on Driving 2
（VCC,PVCC Sink Current）
Icc2
-
4.8
8.5
mA
OUT5 High-level
Output Voltage ON Driving
OUT5 Low-level
Output Voltage ON Driving
OUT7 High-level
Output Voltage ON Driving
OUT7 Low-level
Output Voltage ON Driving
【 Step-up / down Selection 】
Step
down
Step
up
UDSEL12,
UDSEL3
Control Voltage
【ＳＴＢ1～7】
STBControl Voltage
STB Pull-down Resistor
【 Circuit Current 】
Stand by
Current
◎This product is not designed for normal operation within a radioactive environment.
REV. D
STB1～7=3V
INV=2.5V
Test
Circuit
5/21
ＢＤ９７４５
Ｌｏｔ Ｎｏ．
1pin
Notice : Do not use the dotted line area
For soldering
Fig. 1 PACKAGE
Fig. 2 PIN ASSIGNMENT
REV. D
6/21
○PIN DESCRIPTION
PIN No.
22
31
21
2
33
17-18,6-7,43
NAME
VBAT
VCC
PVCC
PVCC5
GND
PGND12,34,567
I/O
-
Description
Power supply for the start-up circuit
Power supply
Power supply for Nch Driver
Power supply for CH5 Pch Driver.
Ground
Power Ground for the Built-in FET.
30
VREGA
O
Output of REGA
34
VREF
O
Output of CH5 Reference.
1
OUT5
O
42
OUT7
O
14,20,9,4
15-16,19,8,5,44
46,40
45,41
26,25,27,28,36,38
35
37
Hx1,2,3,4
Lx1,2,3,4,6
HS6H, HS7H
HS6L, HS7L
INV1,2,3,4,6,7
NON5
INV7I
O
O
I
O
I
I
I
Connect to the Gate of CH5 external
Pch FET.
Connect to the Gate of CH7 external
Nch FET.
Power supply for Built-in Pch FET.
Connect to the inductor.
Power supply for Built-in High side-SW.
Output of Built-in High side-SW.
Error AMP inverted input.
Error AMP non-inverted input.
Error AMP inverted input.
For Current Feed Back
29
RT
-
32
SCP
-
23,24,3
UDSEL1,2,4
I
13,12,11,10,48,47,39
STB1,2,3,4,5,6,7
I
A resistor is placed to set the OSC
frequency.
Connect to a capacitor to set up
the delay time of the SCP.
Step-up/down switching mode
selection H: step-down L: step-up
ON/OFF SW H: Operating Over 1.5V
REV. D
NOTES
Drive over 1.5V
Drive over 2.5V
Drive over 2.5V
Output
Voltage=2.5V
Output
Voltage=1.0V
Output Voltage=1.0V
CLK frequency 1.2MHz
connecting 62kΩ to GND.
Charge up current
4μA until 1.0V.
All Low; Stand-by
32.SCP
31.VCC
33.GND
7/21
30.VREGA
REG A
PVCC
U.V.L.O
To Control Block
TIMER
LATCH
S
R
Q
SCP CMOM1,5,6,7
+
2.2V
SS
26.INV1
22.VBAT
To Driver
STB1
VBAT
+
ERRCOMP1
+
+
ERRAMP1
Start-Up
OSC
CH1 Step up
/down
Current mode
control
0.8V
Pch
DRIVER
BG
CTL
15-16.Lx1
PVCC
Nch
DRIVER
17-18.PGND12
STEP UP/DOWN
SELECTOR1
SCPCOMP2
+
21.PVCC
UDSEL1
25.INV2
20.Hx2
+
+
0.8V
14.Hx1
CH2 Step up
/down
Current mode
control
ERRAMP2
Pch
DRIVER
BG
CTL
19.Lx2
PVCC
Nch
DRIVER
STEP UP/DOWN
SELECTOR2
SCPCOMP3
+
27.INV3
0.8V
UDSEL2
9.Hx3
+
+
ERRAMP3
CH3
Step down
Current mode
control
SCP COMP4
+
28.INV4
0.8V
To ERRAMP
34.VREF
+
+
ERRAMP4
CH4 Step up
/down
Current mode
control
Pch
DRIVER
8.Lx3
PVCC
Nch
DRIVER
Pch
DRIVER
BG
CTL
4.Hx4
5.Lx4
PVCC
Nch
DRIVER
6-7.PGND34
STEP UP/DOWN
SELECTOR4
UDSEL4
VOLTAGE
REFERENNCE
VREGA
SS5
2.PVCC5
ERRAMP5
+
35.NON5
PWM COMP5
++
Pch
DRIVER
1.OUT5
46.HS6H
Rood
SW
VREGA
45.HS6L
36.INV6
0.8V
PWM COMP6
-+
+
+
+
ERRAMP6
PVCC
44.Lx6
Nch
DRIVER
43.PGND567
40.HS7H
VREGA
Rood
SW
41.HS7L
ERRAMP7V
38.INV7
+
+
7V,7I priority L
0.8V
37.INV7I
PWM COMP7
+
+
+
-
PVCC
Nch
DRIVER
+
+
0.4V ERRAMP7I
SS_CLK
OSC
ON/OFF
LOGIC
Fig. 3 Block diagram
REV. D
23.UDSEL1
24.UDSEL2
3.UDSEL4
SOFT
START
13.STB1
12.STB2
11.STB3
10.STB4
48.STB5
47.STB6
39.STB7
STB
29.RT
UVLO
42.OUT7
SCP
VCC
GND
8/21
UNREG
1.8～3.0V
VREGA
REG A
PVCC
U.V.L.O
To Control Block
TIMER
LATCH
S
R
Q
SCP CMOM1,5,6,7
+
2.2V
SS
Vo1
+
VBAT
To Driver
STB1
VBAT
Vo1
(Feed Back 1ch)
Start-Up
OSC
ERRCOMP1
INV1
Hx1
-+
+
ERRAMP1
0.8V
CH1 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
BG
CTL
Nch
DRIVER
Lx1
5.0V
for Analog,IC
PGND12
STEP UP/DOWN
SELECTOR1
Vo2
PVCC
SCPCOMP2
UDSEL1
+
Hx2
INV2
++
0.8V
ERRAMP2
CH2 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
BG
CTL
Lx2
Nch
DRIVER
Vo2
(Feed Back 2ch)
2.8V
for Digital
STEP UP/DOWN
SELECTOR2
Vo3
SCPCOMP3
+
UDSEL2
Hx3
INV3
0.8V
++
ERRAMP3
CH3
Step down
Current mode
control
Vo4
SCPCOMP4
+
Pch
DRIVER
Lx3
1.2V
for ASIC
PVCC
Nch
DRIVER
Hx4
INV4
0.8V
++
ERRAMP4
CH4 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
Vo3
(Feed Back 3ch)
BG
CTL
Nch
DRIVER
Lx4
Vo4
(Feed Back 4ch)
3.4V
for Analog
PGND34
STEP UP/DOWN
SELECTOR4
To ERRAMP
VREF
UDSEL4
VOLTAGE
REFERENNCE
VREGA
SS5
PVCC5
ERRAMP5
+
NON5
Vo5
PWM COMP5
-+
+
OUT5
Pch
DRIVER
-8V
for CCD
HS6H
HS6L
Rood
SW
VREGA
Vo5
(Feed Back 5ch)
Vo6
(Feed Back 6ch)
Vo6
INV6
0.8V
PWM COMP6
++
++
ERRAMP6
12V
for CCD
PVCC
Lx6
Nch
DRIVER
PGND567
HS7H
VREGA
Rood
SW
HS7L
Vo7
ERRAMP7V
INV7
-+
+
7V,7I priority L
0.8V
PWM COMP7
+
+
+
-
OUT7
Nch
DRIVER
LED
INV7I
++
0.4V ERRAMP7I
INV7I
Vo7
(Feed Back 7ch)
PVCC
For BACK LIGHT
OSC
UDSEL4
ON/OFF
LOGIC
UDSEL2
SS_CLK
UDSEL1
SOFT
START
RT
STB
STB1
STB2
STB3
STB4
STB5
STB6
STB7
UVLO
VBAT
Fig. 4（１） Application Circuit for NiH2 2cell
※ Note
The following application circuit is recommended. Make sure to confirm its characteristics.
When making changes to the external components, make sure to leave adequate margin
such as static and transitional characteristics, as well as dispersion of the IC.
REV. D
SCP
VCC
GND
9/21
UNREG
2.5～4.2V
VREGA
REG A
PVCC
U.V.L.O
To Control Block
TIMER
LATCH
S
R
Q
SCP CMOM1,5,6,7
+
2.2V
SS
Vo1
+
VBAT
To Driver
STB1
VBAT
Vo1
(Feed Back 1ch)
Start-Up
OSC
ERRCOMP1
INV1
Hx1
+
+
ERRAMP1
0.8V
CH1 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
BG
CTL
Nch
DRIVER
Lx1
5.0V
for Analog,IC
PGND12
STEP UP/DOWN
SELECTOR1
Vo2
PVCC
SCPCOMP2
UDSEL1
+
Hx2
INV2
+
+
0.8V
ERRAMP2
CH2 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
BG
CTL
Lx2
Vo2
(Feed Back 2ch)
2.8V
for Digital
Nch
DRIVER
STEP UP/DOWN
SELECTOR2
Vo3
SCPCOMP3
+
UDSEL2
Hx3
INV3
0.8V
+
+
ERRAMP3
CH3
Step down
Current mode
control
Vo4
SCPCOMP4
+
Pch
DRIVER
Lx3
Vo3
(Feed Back 3ch)
1.2V
for ASIC
PVCC
Nch
DRIVER
Hx4
INV4
+
+
0.8V
ERRAMP4
CH4 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
BG
CTL
Nch
DRIVER
Lx4
Vo4
(Feed Back 4ch)
3.4V
for Analog
PGND34
STEP UP/DOWN
SELECTOR4
To ERRAMP
VREF
UDSEL4
VOLTAGE
REFERENNCE
VREGA
SS5
PVCC5
ERRAMP5
+
NON5
Vo5
PWM COMP5
++
OUT5
Pch
DRIVER
-8V
for CCD
HS6H
HS6L
Rood
SW
VREGA
Vo5
(Feed Back 5ch)
Vo6
(Feed Back 6ch)
Vo6
INV6
PWM COMP6
-+
+
+
+
0.8V
12V
for CCD
PVCC
Lx6
Nch
DRIVER
PGND567
ERRAMP6
HS7H
VREGA
Rood
SW
HS7L
Vo7
ERRAMP7V
INV7
+
+
7V,7I priority L
0.8V
PWM COMP7
+
+
+
-
OUT7
Nch
DRIVER
LED
INV7I
+
+
0.4V ERRAMP7I
INV7I
Vo7
(Feed Back 7ch)
PVCC
For BACK LIGHT
OSC
UDSEL4
ON/OFF
LOGIC
UDSEL2
SS_CLK
UDSEL1
SOFT
START
RT
STB
STB1
STB2
STB3
STB4
STB5
STB6
STB7
UVLO
VBAT
Fig. 4（2） Application Circuit for Li battery 1cell
※ Note
The following application circuit is recommended. Make sure to confirm its characteristics.
When making changes to the external components, make sure to leave adequate margin
such as static and transitional characteristics, as well as dispersion of the IC.
REV. D
10/21
○ I/O Equivalent Circuit Diagrams
Input /
Pin.
Pin
Description
Output
No
Name
26
INV1
I
25
INV2
I
Error amp inverting input pin.
27
INV3
I
28
INV4
I
36
INV6
I
38
INV7
I
37
INV7I
I
35
NON5
I
Error amp non-inverting input
pin.
29
RT
－
Pin circuit
Note
VCC
VCC
Connect to resistor to set up
the OSC frequency.
VCC
RT
32
SCP
－
Connect to capacitor to set up
the delay time for the
timer-latch.
VCC
SCP
REV. D
11/21
Pin.
No
30
Pin
Name
VREGA
Input /
Output
O
Description
Pin circuit
REGA output voltage
VCC
Note
VCC
VREGA
34
VREF
O
Reference voltage for CH5.
VREGA
VCC
VREF
23
24
3
22
UDSEL1
UDSEL2
UDSEL4
VBAT
I
I
I
-
Step-up/down switching
mode selection
H= Step-down L= Step-up
Battery input.
VBAT
UDSEL
13
12
11
10
48
47
39
STB1
STB2
STB3
STB4
STB5
STB6
STB7
I
I
I
I
I
I
I
CH1～7 ON/OFF
Switches, High = Operating
VCC
STB
REV. D
12/21
Pin.
No
14,20,4
15, -16,19,5
17-18,6-7
Input /
Pin
Description
Output
Name
Hx1, 2,4
O
Pch FET source.
Lx1, 2,4
O
Nch, Pch FET Drain.
PGND12, 34
Ground.
Pin circuit
Note
Hx
Lx
VCC
PGND
9
8
Hx3
Lx3
O
O
Pch FET source
Nch, Pch FET Drain
Hx3
Lx3
VCC
PGND34
21
42
PVCC
OUT7
43
PGND567
O
-
Power supply for Nch Driver.
Connect to the gate of CH7
external Nch FET.
Ground.
VCC
PVCC
VCC
OUT7
VCC
PGND567
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Pin.
No
2
1
Pin
Name
PVCC5
OUT5
Input /
Output
43
PGND567
-
O
Description
Pin circuit
Power supply for Driver.
Connect to the gate of CH5 external
Pch FET.
Ground.
Note
PVCC5
VCC
OUT5
PGND567
44
45
Lx6
PGND567
O
-
Nch FET Drain.
Lx6
VCC
PGND567
46,40
45,41
HS6H, 7H
HS6L, 7L
I
O
Input of PMOS High-side SW.
Output of PMOS High-side SW.
HS6H,7H
HS6L,7L
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○ BLOCK DESCRIPTION
1. REGA
This is an internal regulator that generates a 2.5V regulated output voltage.
REGA supplies power for all the remaining circuit blocks.
The output voltage can be supplied to external devices from VREGA (30pin).
To prevent any oscillations at the output, a 1μF external capacitor is recommended.
2． Short Circuit Protect, Timer Latch
When Error Amp’s output of CH1,5～7 voltages rise beyond 2.2 V, or INV pin voltage of CH2,3,4 fall under
80% of reference, the timer circuit is activated. This will charge up the capacitor connected to SCP (32pin) by
approximately 4μA current.
When the voltage reaches 1.0 V, the latch circuit is activated. While this protection circuit is activated, the entire
channel’s output is turned OFF.
In order to reset the latch circuit, two methods can be used: 1) disable the STB pin before enabling it.
2) Removing or refreshing the power supply voltage.
3． U.V.L.O
This circuit protects the IC from a transient surge at power-on or a momentary drop of the power supply
voltage. Under voltage lockout is activated when the VCC pin voltage falls below 2.4V.
During activation, the output drive pins for all Channels is turned OFF.
4． VOLTAGE REFERENCE (VREF)
The reference voltage circuit for CH5 generates a 1.0V output voltage. The reference voltage can be supplied
from VREF (34pin).
This reference voltage is used to set the output voltage of CH5. When STB5 is enable, the reference is ramping
to 1V. Inverting voltage of CH5 is following this reference.
To prevent any oscillations at the output, a 1μF external capacitor is recommended.
5．OSC
The BD9745EKN include a triangular waveform oscillator for voltage-mode PWM controllers, and slope
oscillator for current-mode PWM controllers.
To set the oscillator frequency, connect a timing resistor to the RT (29 pin).
When the resistor is 62kΩ, it is set 1.2MHz(CH1～4), 600kHz(CH5～7).
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6．SOFT START , SS1
The circuit prevents inrush current in startup by ramping DC/DC output voltage.
The soft-start time of each channel is designed below.
a. CH1・・・・・・・Typical IC Design’s output startup time is 4.2msec. Only CH1, the startup time doesn’t
depend on OSC frequency.
b. CH5・・・・・・・The soft start function of CH5 is accomplished by ramping the VREF pin (30pin) from 0V
to 1V over period of about 10000 SLOPE cycle(7.7msec at 1.2MHz).
c. CH2,3,4,6,7・・・The soft start function of these channel is accomplished by internal reference over
period of about 10000 SLOPE cycle(8.5msec at 1.2MHz).
7．ERRAMP 1～7
This amplifier monitors the output voltage of the switching regulator channels and outputs a PWM controlled
signal accordingly.
ERRAMP1, 2,3,4,6,7’s reference voltage is set by applying voltage of 0.8V. ERRAMP5’s reference
voltage connected to GND, ERRAMP7I’s reference voltage is set to 0.4V.
And all channels have the R-C component for internal compensation.
8．ERRCOMP , Start Up OSC
The Error Comparator monitors the output voltage of the switching regulator and outputs a PFM controlled
signal accordingly. The Start Up OSC operates when power supply voltage reaches 1.5V, and is switched
ON/OFF by output of ERRCOMP. This OSC oscillates at around 300kHz.
When VCC voltage is above 2.6V, or CH1 soft-start time is over, this circuit stops to oscillate.
9．Current mode control block
DC/DC converter of CH1～4 operates on current-mode PWM. In current-mode PWM controller, Main FET turn
on to detect CLK edge, and turn off to detect a peak current of inductor.
Using UDSEL pins, DC/DC converter of CH1～4 is switched to Step-up converter or Step-down converter.
10．PWM COMP
The PWM comparators are voltage - pulse width converters that control the output pulse on time according to
the input voltage. The circuit supplies a pulse width controlled signal to the driver, by comparing the triangular
wave oscillator with the error amplifier’s output voltage.
The maximum on-duty is established internally at approximately 85%.
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11．Nch DRIVER
This CMOS inverting output circuit is a Driver block with built-in and external Nch FET. PVCC pin voltage for
DRIVER must have same voltage with VCC pin voltage for main block.
12．Pch DRIVER
This CMOS inverting output circuit is a Driver block with built-in and external Pch FET.
13．Road SW
This circuit controls high-side load switch with CH6, 7. HS6H, 7H (40,46pin) is input, and HS6L, 7L (41,45) is
output. This circuit controls by ramping the HS6L, 7L voltage on startup to decrease in-rush current.
14．Back gate Control
This circuit controls to switch back-gate voltage of Built-in Pch-FET. (CH1, 2,4) In monolithic IC of P-Sub, the
parasitic diode remains between back-gate (cathode), and source, drain (anode). This circuit cut current pass
through the parasitic diode in step-up situation on STB OFF.
15．ON/OFF LOGIC
The output of each channel can be turned on and off by the input voltage applied on the STB pin.
The channel is “ON” when the voltage of the STB pin is above 1.5 V.
The channel is “OFF” when the voltage applied at STB pin is 0 V or the pin is left open.
When all channels are “OFF”, the device is at Stand-by State.
Each logic pin is connected to GND via a 400kΩpull-down resistor.
16．UDSEL LOGIC
The output of CH1, 2, 4 can be switched step-down/up by input voltage applied on the UDSEL pin.
The output is at step-up mode when UDSEL is GND, and step-down mode when UDSEL is VBAT.
UDSEL pin must be connected to GND or VBAT to prevent unstable logic state, due to this logic is
CMOS inverter powered VBAT.
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○APPLICATION INFORMATION
１.) CH1 Start up sequence.
Using step up function in CH1, please take below measure to prevent operation faults and destruction on start-up.
ａ：CH1 output input to VCC
It must be put schottky Di between Lx1 and Hx1 to clamp Lx1 voltage the input of VBAT pin must short to VCC line and input through C-R filter.
(Ref Fig-7)
ｂ：A battery input to VCC, or external power supply input to VCC.（Fig－5）
The ERRCOMP circuit that adjust CH1 output voltage on UVLO condition, switches Lx1 NMOS ON/OFF to compare INV1 and soft-start output.
In this circuit, if it is late to switch from start up OSC to main current mode control, it is possible that the output voltage is overshot (Ref, Fig－6)
As a rule, VCC voltage is applied before applying STB voltage, or applied at the same time. At the worst, when VCC voltage is applied late
from STB, UVLO function must be canceled within 1msec from applying STB voltage.
STB1
ｔ
Within 1msec
VCC
2.6V
ｔ
0
Fig－5
● ERRCOMP: To compare SS and INV1
STB1
UVLO and UDSEL ⇒ ON
SS
Hx1
ON/OFF
-
Start-Up
OSC
+
Pch
DRIVER
ERRCOMP
Lx1
INV1
+
+
Nch
DRIVER
Current mode
UVLO ⇒ ON
ERRAMP
Control Block
PGND12
0.8V
STB,UVLO
Fig - 6 CH1 Block diagram: Start up circuit
UDSEL pin of
Step-down short to VBAT
VCC
UDSEL
VBAT pin connect
to VCC,PVCC line
VBAT
C
Vo1
(Feed Back 1ch)
R
Hx1
RB551V-30
5.0V
CH1 Step up
Pch
DRIVER
/down
PVCC
Current mode
control
Nch
DRIVER
C
BG
CTL
UNREG
Lx1
L
A parameter of C-R
PGND12
Capacitance[uF]
PVCC
Fig – 7. Recommended application circuit of CH1
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Resistance[Ω]
10
1～10
4.7
2.2～10
1
10
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２.) Applying condition of VBAT voltage.
The up/down selector UDSEL1,2,4 is constructed by inverter circuit whose
STB
power is VBAT, therefore it is possible that operation faults is happen to apply STB
voltage without applying VBAT voltage.
ｔ
As a rule, VBAT voltage is applied before applying STB voltage, or applied at the
Within 50μsec
same time.
At the worst, when VBAT voltage is applied late from STB, VBAT voltage must be applied
VBAT
within 50μsec from applying STB voltage.
ｔ
Fig-8
３.) Recommended operating condition of using back-gate control.
The DC/DC converters of CH1,2,4 have back-gate control to cut the current pass of pmos parasitic diode. Using the back-gate control, it is limited by
the ability of pmos parasitic diode and pmos switching back-gate position.
When synchronous rectifying FET is OFF in normal operation and STB OFF, the inductor current flows to Hx through pmos parasitic diode (D2)
and pmos switching back-gate position (M2). As a result, the voltage of Lx increase to “output voltage + D2 forward voltage Vf + voltage drop of M2”.
When Hx voltage is set to 5V, this voltage exceed absolute maximum voltage of Lx by increasing input current to about 1.2A. So that it is possible to
break built-in FET.
Fig-10 shows recommended operating area of using back-gate control. When the relation between output voltage and input current is out of range,
it must be added schottky barrier diode between Lx and Hx. Using schottky barrier diode, back-gate control can be used not to exceed absolute
maximum voltage of Lx.
The DC/DC converter of CH1 must be added schottky barrier diode as it is explained in item 1).
Hx
( )
2.0
M2
Normally L
②
D2
( )
OFF
M3
Normally H
①
Lx
M4
1.5A @3.6V
1.5
Input Current
① D2 Forward voltage Vf
Input current [A]
M1
ON
( )
D1
1.2A @4.2V
1.0
0.8A @5.0V
Recommended region
0.5
② M2 Drop due to On
resistance △V
0.0
0
PGND
1
2
3
4
5
6
Output voltage [V]
Fig - 10 Recommended operating area of using back-gate
Fig - 9 Back gate control
４.) Setting the detection time for the short-circuit-protector (SCP).
The detection time for the SCP is user-adjustable by varying the capacitor connected at SCP (pin32).
The detection time [sec] = Cscp × Vtsc / Iscp
(Cscp : The capacitance、Vtsc : The Threshold voltage SCP、Iscp :The SCP output current)
Ex）Cscp = 0.1μF
-6
-6
The detection time = 0.1×10 × 1 / {4×10 } = 25msec
As the built-in FET breaks by heat in shorting output, it is recommended that the SCP capacitor is used below 0.47μF.
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５.) Built-in Pch FET(CH1～4,CH67),the drop of current ability in low battery voltage situation
The ON resistance of the built-in Pch FET increase because the FET operates in the saturation region below VGS=1.3V.
Therefore when CH6, 7 step-up converter or step-down channel from a battery is used below 1.8V, the drop is must be considered.
If operating condition below 1.8V should be anticipated, it is recommended that the converter is formed from other channel’s output and is not used
high side switch.
100
100
IDS=200mA
PMOS ON resistance[Ω]
PMOS ON Resistance[Ω]
IDS=200mA
10
Recommended region
1
0.1
10
Recommended region
1
0.1
0
1
2
3
4
5
0
1
2
3
4
5
Gate - Source Voltage VGS[V]
Gate - Source Voltage VGS[V]
b. CH７ Highside Switch
a. CH４
Fig - 11 Built-in PMOS ON resistance - VGS
６.) Setting the oscillator frequency.
The oscillator frequency is user-adjustable by varying the resistor connected to RT (29pin). The CH1～4 frequency is set 1.2MHz to connect 62kΩ,and
the RT value is inverse proportional relation to the frequency.
The CH5～7 frequency is set half value of the CH1～4 frequency.
Fig.12 shows the relation the RT value and the frequency.
Oscillator frequency [kHz]
10000
CH1～4
1000
CH5～6
100
10
100
RT [kΩ]
Fig -12 Oscillator frequency – RT resister (EX)
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20/21
７.) Setting the output voltage.
a. Setting for positive to negative converter (CH5).
ＶＲEF
Ｒ１
ERROR AMP5
NON5
＋
－
Ｒ２
NON is connected to GND .
CH5 output
Fig-13 setting for CH5 feed back resistor
The reference of CH5 Error AMP is internally connected to ground. So the high accuracy regulator can be formed up to set up a resistor
divider to Fig.13, It is recommended that R1 resistance is over 20kΩ, because current ability of VREF is about 100μA.
= －
CH5 output
R2
R1
× VREF （ = 1V ） = －
R2
(Example)
R1 = 20kΩ, R2 = 160kΩ
R1
CH5 output = -8.0V
b. Setting the feed back of CH7
Vo7
CH7 Output
R1
INV7
ERROR AMP7V
+
R2
0.8V
Io7
Priority L
INV7I
ERROR AMP7I
+
R3
0.4V
Fig -14 Setting for Voltage and current of CH7.
CH7 has two ERRORAMP whose reference is different. ERROR AMP 7I controls constant current feed back for LED Back light, and
ERRORAMP7V controls over voltage feed back and constant voltage feedback.
Each ERRORAMP setting shows below formula.
CH7 output current =
CH7 output voltage =
0.4V
R3
R1+R2
R2
（Example R3 = 20Ω⇒ Io7 = 20mA）
× 0.8V
（Example R1 =180kΩ, R2=15kΩ⇒Vo7=13V）
The lower output of two ERRAMP controls the DC/DC output. There fore, if it is used only one ERRORAMP, other ERRORAMP input must
be shorted to GND.
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○Operation Notes
１.) Absolute maximum ratings
This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute
maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be difficult
to determine. (E.g. short mode, open mode) Therefore, physical protection counter-measures (like fuse) should be implemented
when operating conditions beyond the absolute maximum ratings anticipated.
２.) GND potential
Make sure GND is connected at lowest potential. All pins except NON5, must not have voltage below GND. Also, NON5 pin must
not have voltage below - 0.3V on start up.
３.) Setting of heat
Make sure that power dissipation does not exceed maximum ratings.
４.) Pin short and mistake fitting
Avoid placing the IC near hot part of the PCB. This may cause damage to IC. Also make sure that the output-to-output and output
to GND condition will not happen because this may damage the IC.
５.) Actions in strong magnetic field
Exposing the IC within a strong magnetic field area may cause malfunction.
６.) Mutual impedance
Use short and wide wiring tracks for the main supply and ground to keep the mutual impedance as small as possible. Use inductor and
capacitor network to keep the ripple voltage minimum.
７.) Voltage of STB pin
The threshold voltages of STB pin are 0.3V and 1.5V. STB state is set below 0.3V while action state is set beyond 1.5V.
The region between 0.3V and 1.5V is not recommended and may cause improper operation.
The rise and fall time must be under 10msec. In case to put capacitor to STB pin, it is recommended to use under 0.01μF.
８.) Thermal shutdown circuit (TSD circuit)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only
to shut the IC off to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue
to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.
９.)IC Terminal Input
This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements. A P-N junction
is formed between the P-layer and the N-layer of each element, and various types of parasitic elements are then formed.
For example, an application where a resistor and a transistor are connected to a terminal (shown in Fig.15):
○ When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction operates as
a parasitic diode.
○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the NHayers of other
elements in the proximity of the aforementioned parasitic diode.
Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic elements induces
the interference of circuit operations, causing malfunctions and possibly the destruction of the IC. Please be careful not to use the IC in
a way that would cause parasitic elements to operate. For example, by applying a voltage that is lower than the GND (P-board) to
the input terminal.
Transistor (NPN)
B
（Terminal B）C
Resistor
（Terminal A）
E
GND
（TerminalＡ）
P
P＋
N
N
P-board
P
P＋
P＋
N
N
Ｎ
Parasitic element
～
N
P＋
Parasitic element
N
P-board
Parasitic element
GND
Fig - 15 Simplified structure of a Bipolar IC
REV. D
GND
Notice
Notes
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The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
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The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
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R1120A