Order Now Product Folder Support & Community Tools & Software Technical Documents Reference Design AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 AMC1301-Q1 Precision, ±250-mV Input, 3-µs Delay, Reinforced Isolated Amplifier 1 Features 3 Description • • The AMC1301-Q1 device is a precision, isolated amplifier with an output separated from the input circuitry by an isolation barrier that is highly resistant to magnetic interference. This barrier is certified to provide reinforced galvanic isolation of up to 7 kVPEAK according to VDE V 0884-10 and UL1577. Used in conjunction with isolated power supplies, this device prevents noise currents on a high common-mode voltage line from entering the local ground and interfering with or damaging sensitive circuitry. 1 • • • • • • • Qualified for Automotive Applications AEC-Q100 Qualified with the Following Results: – Temperature Grade 1: –40°C to 125°C – HBM ESD Classification Level 2 – CDM ESD Classification Level C6 Low Offset Error and Drift: ±200 µV at 25°C, ± 3 µV/°C Fixed Gain: 8.2 Very Low Gain Error and Drift: ±0.3% at 25°C, ± 50 ppm/°C Very Low Nonlinearity and Drift: 0.03%, 1 ppm/°C 3.3-V Operation on High-Side and Low-Side System-Level Diagnostic Features Safety-Related Certifications: – 7000-VPK Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 – 5000-VRMS Isolation for 1 Minute per UL1577 – CAN/CSA No. 5A-Component Acceptance Service Notice The AMC1301-Q1 device is available in a wide-body 8-pin SOIC (DWV) package. Device Information(1) PART NUMBER AMC1301-Q1 2 Applications • The input of the AMC1301-Q1 device is optimized for direct connection to shunt resistors or other low voltage-level signal sources. The excellent performance of the device supports accurate current control resulting in system-level power savings and, especially in motor control applications, lower torque ripple. The integrated common-mode overvoltage and missing high-side supply voltage detection features of the AMC1301-Q1 device simplify system-level design and diagnostics. Shunt-Based Current Sensing or Resistor-DividerBased Voltage Sensing In: – Traction Inverters – Onboard Chargers (OBC) – DC-DC Converters – Battery Management Systems (BMS) PACKAGE SOIC (8) BODY SIZE (NOM) 5.85 mm × 7.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic Floating Power Supply Gate Driver 3.3 V or 5.0 V AMC1301-Q1 GND1 RSHUNT VDD2 VDD1 VINN To Load VINP Reinforced Isolation HV+ 3.3 V or 5.0 V GND2 VOUTP ADC121S101-Q1 12-Bit ADC VOUTN Gate Driver 1 HV- Copyright © 2016, Texas Instruments Incorporated An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 4 4 4 4 4 5 6 6 6 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Power Ratings........................................................... Insulation Specifications............................................ Safety-Related Certifications..................................... Safety Limiting Values .............................................. Electrical Characteristics........................................... Insulation Characteristics Curves .......................... Typical Characteristics ............................................ 7 Parameter Measurement Information ................ 16 8 Detailed Description ............................................ 17 7.1 Timing Diagrams ..................................................... 16 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 17 17 17 18 Application and Implementation ........................ 19 9.1 Application Information............................................ 19 9.2 Typical Applications ................................................ 19 9.3 Do's and Don'ts ...................................................... 23 10 Power Supply Recommendations ..................... 24 11 Layout................................................................... 25 11.1 Layout Guidelines ................................................. 25 11.2 Layout Example .................................................... 25 12 Device and Documentation Support ................. 26 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 26 26 26 26 26 26 13 Mechanical, Packaging, And Orderable Information ........................................................... 26 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (April 2017) to Revision A • 2 Page Changed maximum specification of Supply voltage row in Absolute Maximum Ratings table from 6.5 V to 7 V ................. 4 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 5 Pin Configuration and Functions DWV Package 8-Pin SOIC Top View VDD1 1 8 VDD2 VINP 2 7 VOUTP VINN 3 6 VOUTN GND1 4 5 GND2 Not to scale Pin Functions PIN NAME NO. I/O DESCRIPTION GND1 4 — High-side analog ground GND2 5 — Low-side analog ground VDD1 1 — High-side power supply, 3.0 V to 5.5 V. See the Power Supply Recommendations section for decoupling recommendations. VDD2 8 — Low-side power supply, 3.0 V to 5.5 V. See the Power Supply Recommendations section for decoupling recommendations. VINN 3 I Inverting analog input VINP 2 I Noninverting analog input VOUTN 6 O Inverting analog output VOUTP 7 O Noninverting analog output Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 3 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) Supply voltage, VDD1 to GND1 or VDD2 to GND2 Analog input voltage at VINP, VINN Input current to any pin except supply pins MIN MAX UNIT –0.3 7 V GND1 – 6 VDD1 + 0.5 V –10 10 mA 150 °C 150 °C Junction temperature, TJ Storage temperature, Tstg (1) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) ±2000 Charged device model (CDM), per AEC Q100-011 ±1000 UNIT V AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. 6.3 Recommended Operating Conditions over operating ambient temperature range (unless otherwise noted) MIN NOM MAX 3.0 5.0 5.5 Low-side supply voltage (VDD2 to GND2) 3.0 3.3 Operating ambient temperature –40 VDD1 High-side supply voltage (VDD1 to GND1) VDD2 TA UNIT V 5.5 V 125 °C 6.4 Thermal Information AMC1301-Q1 THERMAL METRIC (1) DWV (SOIC) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 110.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51.7 °C/W RθJB Junction-to-board thermal resistance 66.4 °C/W ψJT Junction-to-top characterization parameter 16.0 °C/W ψJB Junction-to-board characterization parameter 64.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics, SPRA953. 6.5 Power Ratings PARAMETER TEST CONDITIONS PD Maximum power dissipation (both sides) PD1 Maximum power dissipation (high-side supply) PD2 Maximum power dissipation (low-side supply) 4 VDD1 = VDD2 = 5.5 V Submit Documentation Feedback VALUE UNIT 81.4 mW 45.65 mW 35.75 mW Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 6.6 Insulation Specifications over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VALUE UNIT Shortest pin-to-pin distance through air ≥9 mm Shortest pin-to-pin distance across the package surface ≥9 mm ≥ 0.027 mm ≥ 600 V GENERAL CLR External clearance (1) CPG External creepage (1) DTI Distance through insulation Minimum internal gap (internal clearance) of the double insulation (2 × 0.0135 mm) CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 Material group According to IEC 60664-1 Overvoltage category per IEC 60664-1 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM Maximum repetitive peak isolation voltage VIOWM Maximum-rated isolation working voltage VIOTM Maximum transient isolation voltage VIOSM Maximum surge isolation voltage (3) Barrier capacitance, input to output (5) CIO RIO I-IV Rated mains voltage ≤ 600 VRMS I-III Rated mains voltage ≤ 1000 VRMS I-II (2) Apparent charge (4) qpd I Rated mains voltage ≤ 300 VRMS Insulation resistance, input to output (5) At ac voltage (bipolar) 1500 VPK At ac voltage (sine wave) 1000 VRMS At dc voltage 1500 VDC VTEST = VIOTM, t = 60 s (qualification test) 7000 VTEST = 1.2 × VIOTM, t = 1 s (100% production test) 8400 Test method per IEC 60065, 1.2/50-μs waveform, VTEST = 1.6 × VIOSM = 10000 VPK (qualification) 6250 Method a, after input/output safety test subgroup 2 / 3, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 1800 VPK, tm = 10 s ≤5 Method a, after environmental tests subgroup 1, Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 2400 VPK, tm = 10 s ≤5 Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 2812.5 VPK, tm = 1 s ≤5 VIO = 0.5 VPP at 1 MHz 1.2 VPK VPK pC pF 9 VIO = 500 V at TS = 150°C > 10 Pollution degree 2 Climatic category 40/125/21 Ω UL1577 VISO (1) (2) (3) (4) (5) Withstand isolation voltage VTEST = VISO = 5000 VRMS or 7000 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test) 5000 VRMS Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications. This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits. Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. Apparent charge is electrical discharge caused by a partial discharge (pd). All pins on each side of the barrier are tied together, creating a two-pin device. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 5 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 6.7 Safety-Related Certifications VDE UL Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12, DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08, and DIN EN 60065 (VDE 0860): 2005-11 Recognized under 1577 component recognition and CSA component acceptance NO 5 programs Reinforced insulation Single protection Certificate number: 40040142 File number: E181974 6.8 Safety Limiting Values Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER TEST CONDITIONS MIN TYP MAX θJA = 110.1°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 206 θJA = 110.1°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 315 PS Safety input, output, or total power θJA = 110.1°C/W, TJ = 150°C, TA = 25°C 1135 (1) TS Maximum safety temperature Safety input, output, or supply current IS (1) UNIT mA mW 150 °C Input, output, or the sum of input and output power must not exceed this value. The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. 6.9 Electrical Characteristics Minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VINP = –250 mV to +250 mV, and VINN = 0 V. Typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT VClipping Differential input voltage before clipping output VINP – VINN VFSR Specified linear differential full-scale VINP – VINN –250 250 VCM Specified common-mode input voltage (VINP + VINN) / 2 to GND1 –0.16 VDD1 – 2.1 V Absolute common-mode input voltage (1) (VINN + VINP) / 2 to GND1 –2 VDD1 V VCMov Common-mode overvoltage detection level VOS Input offset voltage TCVOS Input offset drift CMRR Common-mode rejection ratio CIND Differential input capacitance RIN Single-ended input resistance RIND Differential input resistance IIB Input bias current TCIIB Input bias current drift BWIN Input bandwidth (1) 6 ±302.7 mV VDD1 – 2 Initial, at TA = 25°C, VINP = VINN = GND1 V –200 ±50 200 –3 ±1 3 fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –93 fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max –93 VINN = GND1 –82 µV µV/°C dB 1 pF 18 kΩ 22 VINP = VINN = GND1 mV –60 1 1000 kΩ –48 µA nA/°C kHz Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal operation. Observe analog input voltage range as specified in Absolute Maximum Ratings. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 Electrical Characteristics (continued) Minimum and maximum specifications apply from TA = –40°C to +125°C, VDD1 = 3.0 V to 5.5 V, VDD2 = 3.0 V to 5.5 V, VINP = –250 mV to +250 mV, and VINN = 0 V. Typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Nominal gain EG Gain error TCEG Gain error drift 8.2 Initial, at TA = 25°C Nonlinearity –0.3% ±0.05% –50 ±15 –0.03% ±0.01% Nonlinearity drift THD SNR 0.3% 50 ppm/°C 0.03% 1 ppm/°C Total harmonic distortion fIN = 10 kHz –87 dB Output noise VINP = VINN = GND1, fIN = 0 Hz, BW = 100 kHz 220 μVRMS Signal-to-noise ratio fIN = 1 kHz, BW = 10 kHz 80 fIN = 10 kHz, BW = 100 kHz 84 dB 71 vs VDD1, at dc –94 vs VDD1, 100-mV and 10-kHz ripple –90 PSRR Power-supply rejection ratio vs VDD2, 100-mV and 10-kHz ripple –94 tr Rise time See Figure 45 2.0 tf Fall time See Figure 45 2.0 VIN to VOUT signal delay (50% – 10%) See Figure 46, unfiltered output 0.7 2.0 µs VIN to VOUT signal delay (50% – 50%) See Figure 46, unfiltered output 1.6 2.6 µs VIN to VOUT signal delay (50% – 90%) See Figure 46, unfiltered output 2.5 3.0 CMTI Common-mode transient immunity |GND1 – GND2| = 1 kV VCMout Common-mode output voltage vs VDD2, at dc Output resistance BW Output bandwidth VFAILSAFE Failsafe differential output voltage µs µs 15 1.39 Output short-circuit current ROUT dB –100 1.44 1.49 ±13 on VOUTP or VOUTN V mA < 0.2 190 VCM ≥ VCMov, or VDD1 missing µs kV/µs Ω 210 kHz –2.563 –2.545 3.0 V ≤ VDD1 ≤ 3.6 V 5.0 6.9 4.5 V ≤ VDD1 ≤ 5.5 V 5.9 8.3 3.0 V ≤ VDD2 ≤ 3.6 V 4.4 5.6 4.5 V ≤ VDD2 ≤ 5.5 V 4.8 6.5 3.0 V ≤ VDD1 ≤ 3.6 V 16.5 24.84 4.5 V ≤ VDD1 ≤ 5.5 V 29.5 45.65 3.0 V ≤ VDD2 ≤ 3.6 V 14.52 20.16 4.5 V ≤ VDD2 ≤ 5.5 V 24 35.75 V POWER SUPPLY IDD1 High-side supply current IDD2 Low-side supply current PDD1 High-side power dissipation PDD2 Low-side power dissipation Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 mA mA mW mW 7 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 6.10 www.ti.com Insulation Characteristics Curves 500 VDD1 = VDD2 = 3.6 V VDD1 = VDD2 = 5.5 V 300 PS (mW) IS (mA) 400 200 100 0 0 50 100 TA (°C) 150 200 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 50 100 TA (°C) D043 Figure 1. Thermal Derating Curve for Safety-Limiting Current per VDE 150 200 D044 Figure 2. Thermal Derating Curve for Safety-Limiting Power per VDE TA up to 150°C, stress voltage frequency = 60 Hz Figure 3. Reinforced Isolation Capacitor Lifetime Projection 8 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 6.11 Typical Characteristics 3.8 3.8 3.4 3.4 3 3 VCMov (V) 1.8 1.8 1.4 1.4 1 1 -40 5.5 40 40 -200 200 175 150 125 75 100 50 0 25 -25 -50 0 -75 0 -100 D002 20 10 -125 110 125 30 10 D003 VOS (PV) 95 200 20 80 175 30 -150 20 35 50 65 Temperature (°C) 150 Devices (%) 50 -175 5 Figure 5. Common-Mode Overvoltage Detection Level vs Temperature 50 -200 -10 125 Figure 4. Common-Mode Overvoltage Detection Level vs High-Side Supply Voltage D004 VOS (PV) VDD1 = 3.3 V VDD1 = 5 V Figure 6. Input Offset Voltage Histogram Figure 7. Input Offset Voltage Histogram 200 200 vs VDD1 vs VDD2 150 150 100 100 50 50 VOS (PV) VOS (PV) -25 D001 75 5.25 100 5 50 4.75 0 4.25 4.5 VDD1 (V) 25 4 -75 3.75 -100 3.5 -125 3.25 -150 3 Devices (%) 2.2 -25 2.2 2.6 -50 2.6 -175 VCMov (V) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) 0 0 -50 -50 -100 -100 -150 -150 -200 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 -200 -40 Device 1 Device 2 Device 3 -25 D005 Figure 8. Input Offset Voltage vs Supply Voltage -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D006 Figure 9. Input Offset Voltage vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 9 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Typical Characteristics (continued) 70 60 60 50 50 D007 TCVOS (PV/qC) D008 TCVOS (PV/qC) VDD1 = 3.3 V 3 2.5 2 1.5 1 0 0.5 -1 -3 3 2.5 2 1.5 1 -2 0 0 0.5 0 -1 10 -0.5 10 -1.5 20 -2.5 20 -0.5 30 -1.5 30 40 -2 40 -2.5 Devices (%) 70 -3 Devices (%) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) VDD1 = 5 V Figure 10. Input Offset Drift Histogram Figure 11. Input Offset Drift Histogram 0 -60 -65 -20 -70 -75 CMRR (dB) CMRR (dB) -40 -60 -80 -80 -85 -90 -95 -100 -100 -105 -120 0.001 0.01 0.1 0.5 2 3 5 10 20 fIN (kHz) 100 -110 -40 1000 -25 -10 5 D009 Figure 12. Common-Mode Rejection Ratio vs Input Frequency 20 35 50 65 Temperature (°C) 80 95 110 125 D011 Figure 13. Common-Mode Rejection Ratio vs Temperature 60 -46 -50 40 -54 -58 0 IIB (PA) IIB (PA) 20 -20 -62 -66 -70 -40 -74 -60 -80 -0.5 -78 -82 0 0.5 1 1.5 VCM (V) 2 2.5 3 3 3.25 D012 Figure 14. Input Bias Current vs Common-Mode Input Voltage 10 Submit Documentation Feedback 3.5 3.75 4 4.25 4.5 VDD1 (V) 4.75 5 5.25 5.5 D013 Figure 15. Input Bias Current vs High-Side Supply Voltage Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) -46 0 -50 -10 Normalized Gain (dB) -54 -62 -66 -70 -74 -20 -30 -40 -50 -60 -70 -78 -80 0.01 110 125 D014 40 40 -0.3 0.3 0.25 0.2 0.15 0.1 0 0.05 -0.1 -0.05 -0.15 0 -0.2 0 -0.25 10 D016 0.3 20 10 -0.3 D015 0.25 20 VDD1 = 3.3 V EG (%) D017 VDD1 = 5 V Figure 18. Gain Error Histogram Figure 19. Gain Error Histogram 0.3 0.3 vs VDD1 vs VDD2 0.25 0.2 Device 1 Device 2 Device 3 0.25 0.2 0.15 0.15 0.1 0.1 0.05 0.05 EG (%) EG (%) 1000 30 0.2 30 0.15 Devices (%) 50 50 EG (%) 1 10 100 Input Signal Frequency (kHz) Figure 17. Normalized Gain vs Input Frequency Figure 16. Input Bias Current vs Temperature Devices (%) 0.1 0.1 95 0 80 0.05 20 35 50 65 Temperature (°C) -0.1 5 -0.05 -10 -0.15 -25 -0.2 -82 -40 -0.25 IIB (PA) -58 0 -0.05 0 -0.05 -0.1 -0.1 -0.15 -0.15 -0.2 -0.2 -0.25 -0.25 -0.3 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 -0.3 -40 -25 D018 Figure 20. Gain Error vs Supply Voltage -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 21. Gain Error vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 D019 11 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Typical Characteristics (continued) 90 80 80 70 70 60 60 Devices (%) 90 50 40 50 40 30 20 20 10 10 0 0 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 30 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 Devices (%) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) D020 TCEG (ppm/qC) VDD1 = 5 V Figure 22. Gain Error Drift Histogram Figure 23. Gain Error Drift Histogram 0.03 5 VOUTP VOUTN 4.5 0.025 0.02 4 0.015 Nonlinearity (%) 3.5 VOUT (V) D021 TCEG (ppm/qC) VDD1 = 3.3 V 3 2.5 2 1.5 0.01 0.005 0 -0.005 -0.01 -0.015 1 -0.02 0.5 -0.025 0 -350 -250 -150 -50 50 150 Differential Input Voltage (mV) 250 -0.03 -250 -200 -150 -100 -50 0 50 100 150 Differential Input Voltage (mV) 350 D022 Figure 24. Output Voltage vs Input Voltage D024 0.03 vs VDD1 vs VDD2 0.025 0.02 0.025 0.02 0.015 0.015 0.01 Nonlinearity (%) Nonlinearity (%) 250 Figure 25. Nonlinearity vs Input Voltage 0.03 0.005 0 -0.005 -0.01 -0.015 0.01 0.005 0 -0.005 -0.01 -0.015 -0.02 -0.02 -0.025 -0.025 -0.03 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 -0.03 -40 Device 1 Device 2 Device 3 -25 D025 Figure 26. Nonlinearity vs Supply Voltage 12 200 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D026 Figure 27. Nonlinearity vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) -60 -60 vs VDD1 vs VDD2 -65 -70 -70 -75 -75 -80 -80 THD (dB) THD (dB) -65 -85 -90 -95 -100 -100 -105 -105 3 3.25 3.5 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 Device 1 Device 2 Device 3 -110 -40 5.5 -25 -10 5 20 35 50 65 Temperature (°C) D027 Figure 28. Total Harmonic Distortion vs Supply Voltage 80 75 77.5 70 75 65 72.5 60 55 80 95 110 125 D028 Figure 29. Total Harmonic Distortion vs Temperature 80 SNR (dB) SNR (dB) -90 -95 -110 vs VDD1 vs VDD2 70 67.5 50 65 45 62.5 60 40 0 50 100 150 200 |VINP - VINN| (mV) 250 3 300 3.25 3.5 D029 Figure 30. Signal-to-Noise Ratio vs Input Voltage 3.75 4 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D030 Figure 31. Signal-to-Noise Ratio vs Supply Voltage 80 Input Referred Noise Density (nV/—Hz) 10000 77.5 75 SNR (dB) -85 72.5 70 67.5 65 Device 1 Device 2 Device 3 62.5 60 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 1000 100 10 0.01 D031 Figure 32. Signal-to-Noise Ratio vs Temperature 0.1 1 10 Frequency (kHz) 100 1000 D032 Figure 33. Input-Referred Noise Density vs Frequency Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 13 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Typical Characteristics (continued) 0 0 -20 -20 -40 -40 PSRR (dB) PSRR (dB) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) -60 -60 -80 -80 -100 -100 -120 0.001 0.01 0.1 1 10 Ripple Frequency (kHz) 100 -120 0.001 1000 vs VDD1 4 3.8 3.5 3.4 1000 D042 50% - 10% 50% - 50% 50% - 90% 3 Signal Delay (Ps) 2.5 2 1.5 1 2.6 2.2 1.8 1.4 1 0.5 0.6 0 -40 0.2 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3 3.25 3.5 3.75 4 D034 Figure 36. Output Rise and Fall Time vs Temperature 4.25 4.5 VDD2 (V) 4.75 5 5.25 5.5 D035 Figure 37. VIN to VOUT Signal Delay vs Low-Side Supply Voltage 1.49 3.8 3 Output Common-Mode Voltage (V) 50% - 10% 50% - 50% 50% - 90% 3.4 Signal Delay (Ps) 100 Figure 35. Power-Supply Rejection Ratio vs Ripple Frequency 3 2.6 2.2 1.8 1.4 1 0.6 0.2 -40 1.48 1.47 1.46 1.45 1.44 1.43 1.42 1.41 1.4 1.39 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3 3.25 D036 Figure 38. VIN to VOUT Signal Delay vs Temperature 14 0.1 1 10 Ripple Frequency (kHz) vs VDD2 Figure 34. Power-Supply Rejection Ratio vs Ripple Frequency Rise/Fall Time (Ps) 0.01 D033 3.5 3.75 4 4.25 4.5 VDD2 (V) 4.75 5 5.25 5.5 D010 Figure 39. Output Common-Mode Voltage vs Low-Side Supply Voltage Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 Typical Characteristics (continued) at VDD1 = 5 V, VDD2 = 3.3 V, VINP = –250 mV to 250 mV, VINN = 0 V, and fIN = 10 kHz (unless otherwise noted) 240 1.49 1.48 1.47 220 1.45 BW (kHz) VCMout (V) 1.46 1.44 1.43 200 1.42 180 1.41 1.4 1.39 -40 160 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 3 110 125 3.25 3.5 3.75 4 D037 4.25 4.5 VDD2 (V) 4.75 5.25 5.5 D038 Figure 40. Output Common-Mode Voltage vs Temperature Figure 41. Output Bandwidth vs Low-Side Supply Voltage 190 8.5 IDD1 vs VDD1 IDD2 vs VDD2 8 200 7.5 7 IDDx (mA) 210 BW (kHz) 5 220 230 6.5 6 5.5 5 4.5 240 4 250 -40 3.5 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 3 3.25 3.5 3.75 4 D039 Figure 42. Output Bandwidth vs Temperature 4.25 4.5 VDDx (V) 4.75 5 5.25 5.5 D040 Figure 43. Supply Current vs Supply Voltage 8.5 IDD1 IDD2 8 7.5 IDDx (mA) 7 6.5 6 5.5 5 4.5 4 3.5 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 D041 Figure 44. Supply Current vs Temperature Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 15 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 7 Parameter Measurement Information 7.1 Timing Diagrams 0.5 V VINP - VINN 0V VOUTN 90% 10% VOUTP tr tf Figure 45. Rise and Fall Time Test Waveforms 0.5 V VINP - VINN 50% 0V 50% - 50% 50% - 90% 50% - 10% VOUTN 90% 50% VOUTP 10% Figure 46. Delay Time Test Waveforms 16 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 8 Detailed Description 8.1 Overview The AMC1301-Q1 device is a fully-differential, precision, isolated amplifier. The input stage of the device consists of a fully-differential amplifier that drives a second-order, delta-sigma (ΔΣ) modulator. The modulator uses the internal voltage reference and clock generator to convert the analog input signal to a digital bitstream. The drivers (called TX in the Functional Block Diagram) transfer the output of the modulator across the isolation barrier that separates the high-side and low-side voltage domains. The received bitstream and clock are synchronized and processed by a fourth-order analog filter on the low-side and presented as a differential output of the device, as shown in the Functional Block Diagram. The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the AMC1301-Q1 device and the isolation barrier characteristics result in high reliability and common-mode transient immunity. 8.2 Functional Block Diagram VDD2 VDD1 AMC1301-Q1 Isolation Barrier Band-Gap Reference Band-Gap Reference VINP + û -Modulator Data TX RX ± VINN CLK RX GND1 TX Retiming and 4th-Order Active Low-Pass Filter VOUTP VOUTN Oscillator GND2 Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description 8.3.1 Analog Input The AMC1301-Q1 device incorporates front-end circuitry that contains a fully-differential amplifier followed by a ΔΣ modulator sampling stage. The gain of the differential amplifier is set by internal precision resistors to a factor of 4 with a differential input impedance of 22 kΩ. Consider the input impedance of the AMC1301-Q1 device in designs with high-impedance signal sources that may cause degradation of gain and offset specifications. The importance of this effect, however, depends on the desired system performance. Additionally, the input bias current caused by the internal common-mode voltage at the output of the differential amplifier causes an offset that is dependent on the actual amplitude of the input signal. See the Isolated Voltage Sensing section for more details on reducing this effect. There are two restrictions on the analog input signals (VINP and VINN). First, if the input voltage exceeds the range GND1 – 6 V to VDD1 + 0.5 V, then the input current must be limited to 10 mA because the device input electrostatic discharge (ESD) protection turns on. In addition, the linearity and noise performance of the device are ensured only when the analog input voltage remains within the specified linear full-scale range (FSR) and within the specified common-mode input voltage range. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 17 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Feature Description (continued) 8.3.2 Fail-Safe Output The AMC1301-Q1 device offers a fail-safe output that simplifies diagnostics on system level. The fail-safe output is active in two cases: • When the high-side supply VDD1 of the AMC1301-Q1 device is missing, or • When the common-mode input voltage, that is VCM = (VINP + VINN) / 2, exceeds the minimum commonmode over-voltage detection level VCMov of VDD1 – 2 V. The fail-safe output of the AMC1301-Q1 device is a negative differential output voltage value that differs from the negative clipping output voltage, as shown in Figure 47 and Figure 48. As a reference value for the fail-safe detection on a system level, use the VFAILSAFE maximum value of –2.545 V. Figure 47. Typical Negative Clipping Output of the AMC1301-Q1 Device Figure 48. Typical Failsafe Output of the AMC1301-Q1 Device 8.4 Device Functional Modes The AMC1301-Q1 device is operational when the power supplies VDD1 and VDD2 are applied, as specified in Recommended Operating Conditions. 18 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The AMC1301-Q1 device offers unique linearity, high input common-mode and power-supply rejection, low ac and dc errors, and low temperature drift. These features make the AMC1301-Q1 device a robust, highperformance, isolated amplifier for automotive applications where high voltage isolation is required. 9.2 Typical Applications 9.2.1 Traction Inverter Application Figure 49 shows a typical operation of application. Phase current measurement shunt). The differential input and the high reliable and accurate operation even in inverter). the AMC1301-Q1 device for current sensing in a traction inverter is done through the shunt resistor, RSHUNT (in this case, a two-pin common-mode transient immunity of the AMC1301-Q1 device ensure high-noise environments (such as the power stage of the traction Additionally, the AMC1301-Q1 device may also be used for isolated voltage measurement of the dc-link, as described in Isolated Voltage Sensing. AMC1301-Q1 R1 Gate Driver 5.1 V D1 C1 10 F GND1 RSHUNT VINN To Load VDD2 VDD1 C2 0.1 F VINP Reinforced Isolation HV+ Floating Power Supply 15 V 3.3 V C4 0.1 F C5 2.2 F GND2 VOUTP TMS570L R2 C3 ADC VOUTN R3 Gate Driver Copyright © 2016, Texas Instruments Incorporated HV- Figure 49. Using the AMC1301-Q1 Device for Current Sensing in Traction Inverters Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 19 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com Typical Applications (continued) 9.2.1.1 Design Requirements Table 1 lists the parameters for the typical application in Figure 49. Table 1. Design Requirements PARAMETER VALUE High-side supply voltage 3.3 V or 5 V Low-side supply voltage 3.3 V or 5 V Voltage drop across the shunt for a linear response ± 250 mV (maximum) 9.2.1.2 Detailed Design Procedure The high-side power supply (VDD1) for the AMC1301-Q1 device is derived from the power supply of the upper gate driver. Further details are provided in the Power Supply Recommendations section. The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected to the negative input of the AMC1301-Q1 device (VINN). If a four-pin shunt is used, the inputs of the AMC1301-Q1 device are connected to the inner leads and GND1 is connected to one of the outer shunt leads. Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured current: VSHUNT = I × RSHUNT. Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT: • The voltage drop caused by the nominal current range must not exceed the recommended differential input voltage range: VSHUNT ≤ ± 250 mV • The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes a clipping output: VSHUNT ≤ VClipping For best performance, use an RC filter (components R2, R3, and C3 in Figure 49) to minimize the noise of the differential output signal. Tailor the bandwidth of this RC filter to the bandwidth requirement of the system. TI recommends an NP0-type capacitor to be used for C3. For more information on the general procedure to design the filtering and driving stages of SAR ADCs, consult the TI Precision Designs 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise (SLAU515) and 18-Bit Data Acquisition Block (DAQ) Optimized for Lowest Power (SLAU513), available for download at www.ti.com. 20 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 9.2.1.3 Application Curves In traction inverter applications, the power switches must be protected in case of an overcurrent condition. To allow for fast powering off of the system, a low delay caused by the isolated amplifier is required. Figure 50 shows the typical full-scale step response of the AMC1301-Q1 device. Consider the delay of the required window comparator and the MCU to calculate the overall response time of the system. VIN VOUTP VOUTN Figure 50. Step Response of the AMC1301-Q1 Device The high linearity and low temperature drift of offset and gain errors of the AMC1301-Q1 device, as shown in Figure 51, allows design of motor drives with low torque ripple. 0.03 0.025 0.02 Nonlinearity (%) 0.015 0.01 0.005 0 -0.005 -0.01 -0.015 -0.02 -0.025 -0.03 -250 -200 -150 -100 -50 0 50 100 150 Differential Input Voltage (mV) 200 250 D024 Figure 51. Typical Nonlinearity of the AMC1301-Q1 Device Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 21 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 9.2.2 Isolated Voltage Sensing The AMC1301-Q1 device is optimized for usage in current-sensing applications using low-impedance shunts. However, the device may also be used in isolated voltage-sensing applications if the effect of the (usually higher) impedance of the resistor divider used in this case is considered. High Voltage Potential 3.3 V or 5 V R1 AMC1301-Q1 Front-End VDD1 R2 R4 VINP IIB R5 + RIN R3 û -Modulator ± VINN R3' R4' R5' GND1 VCM = 2 V Copyright © 2016, Texas Instruments Incorporated Figure 52. Using the AMC1301-Q1 Device for Isolated Voltage Sensing 9.2.2.1 Design Requirements Figure 52 shows a simplified circuit typically used in high-voltage sensing applications. The high-impedance resistors (R1 and R2) dominate the current value that flows through the resistive divider. The resistance of the sensing resistor R3 is chosen to meet the input voltage range of the AMC1301-Q1 device. This resistor and the input impedance of the device (RIN = 18 kΩ) also create a voltage divider that results in an additional gain error. With the assumption of R1 and R2 having a considerably higher value than R3 and omitting R3' for the moment, the resulting total gain error is estimated using Equation 1, with EG being the initial gain error of the AMC1301Q1 device. R3 EGtot EG RIN (1) This gain error may be easily minimized during the initial system-level gain calibration procedure. 9.2.2.2 Detailed Design Procedure As indicated in Figure 52, the output of the integrated differential amplifier is internally biased to a common-mode voltage of 2 V. This voltage results in a bias current IIB through the resistive network R4 and R5 (or R4' and R5') used for setting the gain of the amplifier. The value of this current is specified in the Pin Configuration and Functions section. This bias current generates additional offset and gain errors that depend on the value of the resistor R3. Because the value of this bias current depends on the actual common-mode amplitude of the input signal (as shown in Figure 53), the initial system offset calibration eliminates the offset but not the gain error component. Therefore, in systems with high accuracy requirements, a series resistor is recommended to be used at the negative input (VINN) of the AMC1301-Q1 device with a value equal to the shunt resistor R3 (that is, R3' = R3 in Figure 52) to eliminate the effect of the bias current. This additional series resistor (R3') influences the gain error of the circuit. The effect is calculated using Equation 2 with R4 = R4' = 12.5 kΩ. The effect of the internal resistors R5 = R5' cancels in this calculation. R4 · § EG (%) ¨1 ¸ * 100 % R 4' R 3' ¹ © (2) 22 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 9.2.2.3 Application Curve Figure 53 shows the dependency of the input bias current on the common-mode voltage at the input of the AMC1301-Q1 device. 60 40 IIB (PA) 20 0 -20 -40 -60 -80 -0.5 0 0.5 1 1.5 VCM (V) 2 2.5 3 D012 Figure 53. Input Current vs Input Common-Mode Voltage 9.3 Do's and Don'ts Do not leave the inputs of the AMC1301-Q1 device unconnected (floating) when the device is powered up. If both device inputs are left floating, the input bias current drives them to the output common-mode of the analog front-end of approximately 2 V. If the high-side supply voltage VDD1 is below 4 V, the internal common-mode overvoltage detector turns on and the output functions as described in the Fail-Safe Output section, which may lead to an undesired reaction on the system level. Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 23 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 10 Power Supply Recommendations In a typical traction inverter application, the high-side power supply (VDD1) for the device is derived from the floating power supply of the upper gate driver. For lowest cost, a Zener diode may be used to limit the voltage to 5 V (or 3.3 V, depending on the design) ± 10%. Alternatively a low-cost, low-dropout (LDO) regulator (for example, the LP2951-XX-Q1) may be used to minimize noise on the power supply. TI recommends a low-ESR decoupling capacitor of 0.1 µF to filter this power-supply path. Place this capacitor (C2 in Figure 54) as close as possible to the VDD1 pin of the AMC1301-Q1 device for best performance. If better filtering is required, an additional 10-µF capacitor may be used. The floating ground reference (GND1) is derived from the end of the shunt resistor, which is connected to the negative input (VINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads, and GND1 is connected to one of the outer leads of the shunt. To decouple the digital power supply on the controller side, use a 0.1-µF capacitor placed as close to the VDD2 pin of the AMC1301-Q1 device as possible, followed by an additional capacitor from 1 µF to 10 µF. R1 800 Gate Driver Z1 1N751A C1 10 F AMC1301-Q1 5.1 V C2 0.1 F GND1 RSHUNT VINN To Load 3.3 V or 5.0 V VDD2 VDD1 Reinforced Isolation HV+ Floating Power Supply 20 V C4 0.1 F GND2 VOUTP VOUTN VINP C5 2.2 F ADC121S101-Q1 12-Bit ADC Gate Driver HV- Copyright © 2016, Texas Instruments Incorporated Figure 54. Zener-Diode-Based, High-Side Power Supply 24 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 AMC1301-Q1 www.ti.com SBAS792A – APRIL 2017 – REVISED APRIL 2017 11 Layout 11.1 Layout Guidelines A layout recommendation showing the critical placement of the decoupling capacitors (as close as possible to the AMC1301-Q1 device) and placement of the other components required by the device is shown in Figure 55. For best performance, place the shunt resistor close to the VINP and VINN inputs of the AMC1301-Q1 device and keep the layout of both connections symmetrical. 11.2 Layout Example Clearance area, to be kept free of any conductive materials. 0.1 µF 2.2 µF SMD 0603 SMD 0603 SMD 0603 Shunt Resistor To Floating Power Supply 0.1 µF VDD1 VDD2 VINP VOUTP To Filter or ADC AMC1301-Q1 VINN VOUTN GND1 GND2 LEGEND Copper Pour and Traces High-Side Area Low-Side Area Via to Ground Plane Copyright © 2016, Texas Instruments Incorporated Via to Supply Plane Figure 55. Recommended Layout of the AMC1301-Q1 Device Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 25 AMC1301-Q1 SBAS792A – APRIL 2017 – REVISED APRIL 2017 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Isolation Glossary • ADC121S101-Q1 Single-Channel, 0.5 to 1-Msps, 12-Bit Analog-to-Digital Converter • LP2951-xx-Q1 Adjustable Micropower Voltage Regulators With Shutdown • TMS570LS0232 16- and 32-Bit RISC Flash Microcontroller • ISO72x Digital Isolator Magnetic-Field Immunity • 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise • 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, And Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 26 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Product Folder Links: AMC1301-Q1 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) AMC1301QDWVQ1 PREVIEW SOIC DWV 8 64 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 1301Q1 AMC1301QDWVRQ1 PREVIEW SOIC DWV 8 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 1301Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2017 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF AMC1301-Q1 : • Catalog: AMC1301 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device AMC1301QDWVRQ1 Package Package Pins Type Drawing SOIC DWV 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 12.05 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.15 3.3 16.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Apr-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AMC1301QDWVRQ1 SOIC DWV 8 1000 367.0 367.0 38.0 Pack Materials-Page 2 PACKAGE OUTLINE DWV0008A SOIC - 2.8 mm max height SCALE 2.000 SOIC C SEATING PLANE 11.5 0.25 TYP PIN 1 ID AREA 0.1 C 6X 1.27 8 1 2X 3.81 5.95 5.75 NOTE 3 4 5 0.51 0.31 0.25 C A 8X A 7.6 7.4 NOTE 4 B B 2.8 MAX 0.33 TYP 0.13 SEE DETAIL A (2.286) 0.25 GAGE PLANE 0 -8 0.46 0.36 1.0 0.5 (2) DETAIL A TYPICAL 4218796/A 09/2013 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. www.ti.com EXAMPLE BOARD LAYOUT DWV0008A SOIC - 2.8 mm max height SOIC 8X (1.8) SEE DETAILS SYMM 8X (0.6) SYMM 6X (1.27) (10.9) LAND PATTERN EXAMPLE 9.1 mm NOMINAL CLEARANCE/CREEPAGE SCALE:6X METAL SOLDER MASK OPENING SOLDER MASK OPENING 0.07 MAX ALL AROUND METAL 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4218796/A 09/2013 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DWV0008A SOIC - 2.8 mm max height SOIC 8X (1.8) SYMM 8X (0.6) SYMM 6X (1.27) (10.9) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4218796/A 09/2013 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. 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TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated