TI1 AMC1106M05 Small, high-precision, basic isolated delta-sigma modulator Datasheet

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AMC1106E05, AMC1106M05
SBAS789 – OCTOBER 2017
AMC1106x Small, High-Precision, Basic Isolated Delta-Sigma Modulators
1 Features
3 Description
•
The AMC1106 device is a precision, delta-sigma (ΔΣ)
modulator with the output separated from the input
circuitry by a capacitive isolation barrier that is highly
resistant to magnetic interference.
1
•
•
•
•
•
•
±50-mV Input Voltage Range Optimized for
Current Measurement With Shunt Resistors
Manchester Coded or Uncoded Bitstream Options
Excellent DC Performance for High-Precision
Sensing on System Level:
– Offset Error and Drift: ±50 µV, ±1 µV/°C (max)
– Gain Error and Drift: ±0.2%, ±40 ppm/°C (max)
3.3-V Operation for Reduced Power Dissipation
on Both Sides of the Isolation Barrier
System-Level Diagnostic Features
High Electromagnetic Field Immunity
(see the ISO72x Digital Isolator Magnetic-Field
Immunity Application Report)
Safety-Related Certifications:
– 5657-VPK Basic Isolation per DIN V VDE V
0884-11 (VDE V 0884-11): 2017-01
– 4000-VRMS Isolation for 1 Minute per UL1577
– CAN/CSA No. 5A-Component Acceptance
Service Notice,
IEC 60950-1, and IEC 60065 End Equipment
Standards
The input stage of the AMC1106 is optimized for
direct connection to shunt resistors or other low
voltage-level signal sources commonly used in multiphase electricity meters to achieve excellent ac and
dc performance. The device low input voltage range
of ±50-mV allows use of small shunt resistor values
to minimize power dissipation. Decimate the output
bitstream of the AMC1106 with an appropriate digital
filter. The MSP430F67x, TMS320F2807x, and
TMS320F2837x microcontrollers, and the AMC1210
integrate these digital filters for seamless operation
with the AMC1106.
On the high-side, the modulator is supplied by a
3.3-V or 5-V power supply (AVDD). The isolated
digital interface operates from a 3.0-V, 3.3-V, or 5-V
power supply (DVDD).
The AMC1106 is specified over the extended
industrial temperature range of –40°C to +125°C.
Device Information(1)
PART NUMBER
2 Applications
AMC1106x
Shunt-Resistor-Based Current Sensing In 3-Phase
Electricity Meters
PACKAGE
SOIC (8)
BODY SIZE (NOM)
5.85 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Phase Phase Phase
A
B
C
3.3 V
AMC1106M05
û
Modulator
AVDD2
Isolation
AVDD1
MSP430F67641A
SD24_B
Module
Decimation
Filter
AMC1106M05
û
Modulator
Isolation
Neutral
Decimation
Filter
Clock
Generator
System
Interface
AMC1106M05
û
Modulator
Isolation
AVDD3
Metrology
Calculation
Engine
Level-Shifted
Voltage Divider
Level-Shifted
Voltage Divider
Decimation
Filter
10-Bit
SAR
ADC
Level-Shifted
Voltage Divider
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC1106E05, AMC1106M05
SBAS789 – OCTOBER 2017
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
8.1
8.2
8.3
8.4
1
1
1
2
3
3
4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
17
17
18
22
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application .................................................. 24
10 Power Supply Recommendations ..................... 27
11 Layout................................................................... 28
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Power Ratings........................................................... 4
Insulation Specifications............................................ 5
Safety-Related Certifications..................................... 6
Safety Limiting Values .............................................. 6
Electrical Characteristics: AMC1106x....................... 7
Timing Requirements .............................................. 9
Switching Characteristics ........................................ 9
Insulation Characteristics Curves ......................... 10
Typical Characteristics .......................................... 11
11.1 Layout Guidelines ................................................. 28
11.2 Layout Example .................................................... 28
12 Device and Documentation Support ................. 29
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
29
29
29
29
29
30
30
30
13 Mechanical, Packaging, and Orderable
Information ........................................................... 30
Detailed Description ............................................ 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
October 2017
*
Initial release.
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5 Device Comparison Table
PART NUMBER
DIGITAL OUTPUT INTERFACE
AMC1106E05
Manchester coded CMOS
AMC1106M05
Uncoded CMOS
6 Pin Configurations and Functions
DWV Package
8-Pin SOIC
Top View
AVDD
1
8
DVDD
AINP
2
7
CLKIN
AINN
3
6
DOUT
AGND
4
5
DGND
Not to scale
Pin Functions
PIN
I/O
NO.
NAME
DESCRIPTION
1
AVDD
—
2
AINP
I
Noninverting analog input
3
AINN
I
Inverting analog input
4
AGND
—
Analog (high-side) ground reference
5
DGND
—
Digital (controller-side) ground reference
6
DOUT
O
Modulator data output. This pin is a Manchester coded output for the AMC1106E05.
7
CLKIN
I
Modulator clock input
8
DVDD
—
Analog (high-side) power supply, 3.0 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
Digital (controller-side) power supply, 2.7 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
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7 Specifications
7.1 Absolute Maximum Ratings (1)
Supply voltage, AVDD to AGND or DVDD to DGND
Analog input voltage at AINP, AINN
Digital output voltage at DOUT, or digital input voltage on CLKIN
Input current to any pin except supply pins
MIN
MAX
UNIT
–0.3
6.5
V
AGND – 6
AVDD + 0.5
V
DGND – 0.5
DVDD + 0.5
V
–10
Junction temperature, TJ
Storage temperature, Tstg
(1)
–65
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
AVDD
Analog (high-side) supply voltage (AVDD to AGND)
3.0
5.0
5.5
UNIT
V
DVDD
Digital (controller-side) supply voltage (DVDD to DGND)
2.7
3.3
5.5
V
TA
Operating ambient temperature
–40
125
°C
7.4 Thermal Information
AMC1106x
THERMAL METRIC (1)
DWV (SOIC)
UNIT
8 PINS
RθJA
112.2
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
47.6
°C/W
RθJB
Junction-to-board thermal resistance
60.0
°C/W
ψJT
Junction-to-top characterization parameter
23.1
°C/W
ψJB
Junction-to-board characterization parameter
60.0
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
Junction-to-ambient thermal resistance
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings
PARAMETER
PD
Maximum power dissipation
(both sides)
PD1
Maximum power dissipation
(high-side supply)
PD2
Maximum power dissipation
(low-side supply)
4
TEST CONDITIONS
MIN
TYP
MAX
AMC1106E05, AVDD = DVDD = 5.5 V
91.85
AMC1106M05, AVDD = DVDD = 5.5 V
86.90
AVDD = 5.5 V
53.90
AMC1106E05, AVDD = DVDD = 5.5 V
37.95
AMC1106M05, AVDD = DVDD = 5.5 V
33.00
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UNIT
mW
mW
mW
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7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
External clearance (1)
Shortest pin-to-pin distance through air
≥9
mm
CPG
External creepage (1)
Shortest pin-to-pin distance across the package surface
≥9
mm
DTI
Distance through insulation
Minimum internal gap (internal clearance) of the double
insulation (2 × 0.0105 mm)
≥ 0.021
mm
CTI
Comparative tracking index
DIN EN 60112 (VDE 0303-11); IEC 60112
≥ 600
V
Material group
According to IEC 60664-1
Overvoltage category per IEC 60664-1
I
Rated mains voltage ≤ 300 VRMS
I-IV
Rated mains voltage ≤ 600 VRMS
I-IV
At ac voltage (bipolar)
849
VPK
At ac voltage (sine wave)
600
VRMS
At dc voltage
849
VDC
VTEST = VIOTM, t = 60 s (qualification test)
5657
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
6789
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 8486 VPK (qualification)
6000
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01 (2)
VIORM
Maximum repetitive peak isolation voltage
VIOWM
Maximum-rated isolation working voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage (3)
Apparent charge (4)
qpd
Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1019 VPK, tm = 10 s
≤5
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.6 × VIORM = 1359 VPK, tm = 10 s
≤5
Method b1, at routine test (100% production) and
preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.875 × VIORM = 1592 VPK, tm = 1 s
≤5
CIO
Barrier capacitance, input to output (5)
VIO = 0.5 VPP at 1 MHz
RIO
Insulation resistance, input to output (5)
VIO = 500 V at TS = 150°C
VPK
VPK
pC
1.2
pF
> 109
Ω
Pollution degree
2
Climatic category
40/125/21
UL1577
VISO
(1)
(2)
(3)
(4)
(5)
Withstand isolation voltage
VTEST = VISO = 4000 VRMS or 5657 VDC, t = 60 s
(qualification), VTEST = 1.2 × VISO = 4800 VRMS, t = 1 s
(100% production test)
4000
VRMS
Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
Apparent charge is electrical discharge caused by a partial discharge (pd).
All pins on each side of the barrier are tied together, creating a two-pin device.
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7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN V VDE V 0884-11 (VDE V 0884-11):
2017-01, DIN EN60950-1 (VDE 0805 Teil 1): 2014-08, and
DIN EN 60065 (VDE 0860): 2005-11
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
Reinforced insulation
Single protection
Certificate number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output (I/O) circuitry.
A failure of the I/O may allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
IS
TEST CONDITIONS
Safety input, output, or supply current,
see Figure 3
PS
Safety input, output, or total power,
see Figure 4
TS
Maximum safety temperature
(1)
MIN
TYP
MAX
θJA = 112.2°C/W, VDD1 = VDD2 = 5.5 V,
TJ = 150°C, TA = 25°C
202.5
θJA = 112.2°C/W, VDD1 = VDD2 = 3.6 V,
TJ = 150°C, TA = 25°C
309.4
θJA = 112.2°C/W, TJ = 150°C, TA = 25°C
1114 (1)
UNIT
mA
150
mW
°C
Input, output, or the sum of input and output power must not exceed this value.
The maximum safety temperature is the maximum junction temperature specified for the device. The power
dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines
the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that
of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended
maximum input voltage times the current. The junction temperature is then the ambient temperature plus the
power times the junction-to-air thermal resistance.
6
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7.9 Electrical Characteristics: AMC1106x
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
VClipping
Differential input voltage before clipping output
VIN = AINP – AINN
FSR
Specified linear differential full-scale
VIN = AINP – AINN
Absolute common-mode input voltage (1)
VCM
±64
mV
–50
50
(AINP + AINN) / 2 to AGND
–2
AVDD
V
Operating common-mode input voltage
(AINP + AINN) / 2 to AGND
–0.032
AVDD – 2.1
V
VCMov
Common-mode overvoltage detection level (2)
(AINP + AINN) / 2 to AGND
AVDD – 2
CIN
Single-ended input capacitance
AINN = AGND
CIND
Differential input capacitance
IIB
Input bias current
AINP = AINN = AGND, IIB = IIBP + IIBN
RIN
Single-ended input resistance
AINN = AGND
4.75
kΩ
RIND
Differential input resistance
4.9
kΩ
IIO
Input offset current
±10
CMTI
Common-mode transient immunity
CMRR
V
4
pF
2
Common-mode rejection ratio
–97
–72
pF
–57
µA
nA
15
kV/µs
AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max
–99
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max
–98
dB
Input bandwidth (3)
BW
mV
800
kHz
DC ACCURACY
DNL
Differential nonlinearity
INL
Integral nonlinearity (4)
EO
Offset error
TCEO
Offset error thermal drift (5)
EG
Gain error
TCEG
Gain error thermal drift (6)
PSRR
Resolution: 16 bits
0.99
LSB
–4
±1
4
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V
–5
±1.5
5
–50
±2.5
50
µV
–1
±0.25
1
μV/°C
–0.2%
±0.005%
0.2%
–40
±20
40
Initial, at 25°C, AINP = AINN = AGND
Initial, at 25°C
Power-supply rejection ratio
–0.99
Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc
–108
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple
–107
LSB
ppm/°C
dB
AC ACCURACY
SNR
Signal-to-noise ratio
fIN = 1 kHz
78
82.5
dB
SINAD
Signal-to-noise + distortion
fIN = 1 kHz
77.5
82.3
dB
THD
Total harmonic distortion
SFDR
(1)
(2)
(3)
(4)
(5)
Spurious-free dynamic range
–98
–84
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz
–93
–83
fIN = 1 kHz
dB
83
100
dB
Steady-state voltage supported by the device in case of a system failure. See the specified common-mode input voltage VCM for normal
operation. Observe the analog input voltage range as specified in the Absolute Maximum Ratings table.
The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
This parameter is the –3-dB, second-order, roll-off frequency of the integrated differential input amplifier to consider for antialiasing filter
designs.
Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
Offset error drift is calculated using the box method, as described by the following equation:
TCE O
(6)
4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz
value MAX value MIN
TempRange
Gain error drift is calculated using the box method, as described by the following equation:
TCE G ( ppm )
§ value MAX value MIN
¨¨
© value u TempRange
·
¸¸ u 10 6
¹
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Electrical Characteristics: AMC1106x (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,
AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are
at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS (CMOS Logic With Schmitt-Trigger)
DGND ≤ VCLKIN ≤ DVDD
IIN
Input current
CIN
Input capacitance
VIH
High-level input voltage
0.7 × DVDD
DVDD + 0.3
V
VIL
Low-level input voltage
–0.3
0.3 × DVDD
V
VOH
High-level output voltage
VOL
Low-level output voltage
CLOAD
Output load capacitance
0
7
4
IOH = –20 µA
DVDD – 0.1
IOH = –4 mA
DVDD – 0.4
µA
pF
V
IOL = 20 µA
0.1
IOL = 4 mA
0.4
30
V
pF
POWER SUPPLY
IAVDD
IDVDD
8
High-side supply current
Controller-side supply current
3.0 V ≤ AVDD ≤ 3.6 V
6.3
8.5
4.5 V ≤ AVDD ≤ 5.5 V
7.2
9.8
AMC1106E05, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
4.1
5.5
AMC1106M05, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
3.3
4.8
AMC1106E05, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
5.0
6.9
AMC1106M05, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
3.9
6.0
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mA
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7.10 Timing Requirements
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
4.5 V ≤ AVDD ≤ 5.5 V
5
21
3.0 V ≤ AVDD ≤ 5.5 V
5
20
4.5 V ≤ AVDD ≤ 5.5 V
47.6
200
3.0 V ≤ AVDD ≤ 5.5 V
50
200
UNIT
fCLKIN
CLKIN clock frequency
MHz
tCLKIN
CLKIN clock period,
see Figure 1
tHIGH
CLKIN clock high time, see Figure 1
20
25
120
ns
tLOW
CLKIN clock low time, see Figure 1
20
25
120
ns
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tH
DOUT hold time after rising edge
AMC1106M05 (1), CLOAD = 15 pF
of CLKIN, see Figure 1
3.5
tD
Rising edge of CLKIN to DOUT
valid delay, see Figure 1
ns
7.11 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
tr
DOUT rise time, see Figure 1
tf
DOUT fall time, see Figure 1
AMC1106M05 (1), CLOAD = 15 pF
15
10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.8
3.5
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF
0.8
3.5
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF
1.8
3.9
tISTART
Interface startup time,
see Figure 2
DVDD at 2.7 V (min) to DOUT valid with
AVDD ≥ 3.0 V
tASTART
Analog startup time,
see Figure 2
AVDD step to 3.0 V with DVDD ≥ 2.7 V,
0.1% settling
(1)
ns
ns
ns
ns
32
32
tCLKIN
0.5
ms
The output of the Manchester encoded versions of the AMC1106E05 can change with every edge of CLKIN with a typical delay of 6 ns;
see the Manchester Coding Feature section for additional details.
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tCLKIN
tHIGH
CLKIN
tLOW
tH
tr / tf
tD
DOUT
Figure 1. Digital Interface Timing
AVDD
DVDD
tASTART
CLKIN
...
DOUT
Bitream not valid
(analog settling)
Test Pattern
Valid bitstream
tISTART
Figure 2. Device Startup Timing
7.12 Insulation Characteristics Curves
1200
500
AVDD = DVDD = 3.6 V
AVDD = DVDD = 5.5 V
1100
1000
400
900
PS (mW)
IS (mA)
800
300
200
700
600
500
400
300
100
200
100
0
0
0
50
100
TA (°C)
150
200
Figure 3. Thermal Derating Curve for Safety-Limiting
Current per VDE
10
0
50
D001
100
TA (°C)
150
200
D002
Figure 4. Thermal Derating Curve for Safety-Limiting
Power per VDE
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7.13 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
4
3.3
3.5
3.25
3.2
VCMov (V)
VCM (V)
3
2.5
2
1.5
3.1
3.05
3
1
2.95
0.5
3
3.5
4
4.5
AVDD (V)
5
2.9
-40
5.5
0
40
-20
20
CMRR (dB)
-20
20 35 50 65
Temperature (qC)
80
95
110 125
D004
-60
-80
-40
-100
-60
0
0.5
1
1.5
VCM (V)
2
2.5
3
-120
0.1 0.2
3.5
0.5
1
D005
Figure 7. Input Bias Current vs
Common-Mode Input Voltage
2 3 4 5 7 10 2030 50 100 200
fIN (kHz)
500 1000
D006
Figure 8. Common-Mode Rejection Ratio vs
Input Signal Frequency
100
4
AVDD = 5 V
AVDD = 3.3 V
3.5
75
3
50
2.5
25
EO (µV)
INL (|LSB|)
5
-40
0
2
0
1.5
-25
1
-50
0.5
-75
0
-40
-10
Figure 6. Common-Mode Overvoltage Detection Level vs
Temperature
60
-80
-0.5
-25
D003
Figure 5. Maximum Operating Common-Mode Input Voltage
vs High-Side Supply Voltage
IIB (PA)
3.15
-100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 9. Integral Nonlinearity vs Temperature
3
3.5
D008
4
4.5
AVDD (V)
5
5.5
D009
Figure 10. Offset Error vs High-Side Supply Voltage
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Typical Characteristics (continued)
100
100
80
80
60
60
40
40
20
20
EO (µV)
EO (PV)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
0
-20
-40
0
-20
-40
-60
-60
Device 1
Device 2
Device 3
-80
-100
-40
-80
-100
-25
-10
5
20 35 50 65
Temperature (°C)
80
95
110 125
5
0.2
0.2
0.1
0.1
0
-0.1
-0.2
-0.2
-0.3
4
4.5
AVDD (V)
5
-0.3
-40
5.5
0.2
-20
0.1
-40
0
-80
-0.2
-100
-0.3
17
12
-10
5
21
-120
0.1
1
D014
Figure 15. Gain Error vs Clock Frequency
D011
20 35 50 65
Temperature (qC)
80
95
110 125
D013
-60
-0.1
13
fCLKIN (MHz)
21
Figure 14. Gain Error vs Temperature
0
PSRR (dB)
EG (%)
Figure 13. Gain Error vs High-Side Supply Voltage
9
-25
D012
0.3
5
17
0
-0.1
3.5
13
fCLKIN (MHz)
Figure 12. Offset Error vs Clock Frequency
0.3
EG (%)
EG (%)
Figure 11. Offset Error vs Temperature
0.3
3
9
D010
10
100
Ripple Frequency (kHz)
1000
D015
Figure 16. Power-Supply Rejection Ratio vs
Ripple Frequency
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
90
90
SNR
SINAD
89
88
SNR and SINAD (dB)
SNR and SINAD (dB)
88
87
86
85
84
83
87
86
85
84
83
82
82
81
81
80
3
3.5
4
4.5
AVDD (V)
5
80
-40
5.5
-25
-10
5
D016
Figure 17. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs High-Side Supply Voltage
20 35 50 65
Temperature (qC)
80
95
110 125
D017
Figure 18. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Temperature
90
88
SNR
SINAD
89
86
88
84
SNR and SINAD (dB)
SNR and SINAD (dB)
SNR
SINAD
89
87
86
85
84
83
82
80
78
76
82
74
81
72
80
5
9
13
fCLKIN (MHz)
17
SNR
SINAD
70
0.1
21
1
10
100
fIN (kHz)
D018
Figure 19. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Clock Frequency
D019
Figure 20. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Input Signal Frequency
90
-86
-88
85
-90
-92
75
-94
THD (dB)
SNR and SINAD (dB)
80
70
65
60
-96
-98
-100
-102
-104
55
-106
50
SNR
SINAD
-108
90
-110
4.5
45
0
10
20
30
40
50
60
VIN (mVpp)
70
80
100
4.75
D020
5
AVDD (V)
5.25
5.5
D021
fCLKIN = 21 MHz
Figure 21. Signal-to-Noise Ratio and Signal-to-Noise +
Distortion vs Input Signal Amplitude
Figure 22. Total Harmonic Distortion vs
High-Side Supply Voltage
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Typical Characteristics (continued)
-86
-86
-88
-88
-90
-90
-92
-92
-94
-94
THD (dB)
THD (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
-96
-98
-100
-96
-98
-100
-102
-102
-104
-104
-106
-106
-108
-108
-110
3
3.5
4
4.5
AVDD (V)
5
-110
-40
5.5
-25
-10
5
D039
20 35 50 65
Temperature (°C)
80
95
110 125
D022
fCLKIN = 20 MHz
Figure 23. Total Harmonic Distortion vs
High-Side Supply Voltage
Figure 24. Total Harmonic Distortion vs Temperature
-85
-86
-88
-90
-90
-92
-95
THD (dB)
THD (dB)
-94
-96
-98
-100
-102
-100
-105
-110
-104
-106
-115
-108
-110
5
9
13
fCLKIN (MHz)
17
-120
0.1
21
Figure 25. Total Harmonic Distortion vs Clock Frequency
-65
118
-70
114
-75
110
D024
106
SFDR (dB)
THD (dB)
10
Figure 26. Total Harmonic Distortion vs
Input Signal Frequency
-80
-85
-90
-95
102
98
94
-100
90
-105
-110
86
-115
82
0
10
20
30
40
50
60
VIN (mVpp)
70
80
90
100
3
3.5
D025
Figure 27. Total Harmonic Distortion vs
Input Signal Amplitude
14
1
fIN (kHz)
D023
4
4.5
AVDD (V)
5
5.5
D026
Figure 28. Spurious-Free Dynamic Range vs
High-Side Supply Voltage
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Typical Characteristics (continued)
118
118
114
114
110
110
106
106
SFDR (dB)
SFDR (dB)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
102
98
102
98
94
94
90
90
86
86
82
-40
82
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
5
110 125
Figure 29. Spurious-Free Dynamic Range vs Temperature
118
120
114
115
110
110
17
21
D028
105
SFDR (dB)
SFDR (dB)
13
fCLKIN (MHz)
Figure 30. Spurious-Free Dynamic Range vs
Clock Frequency
106
102
98
94
100
95
90
85
90
80
86
75
82
0.1
70
1
fIN (kHz)
0
10
10
20
30
D029
Figure 31. Spurious-Free Dynamic Range vs
Input Signal Frequency
40
50
60
VIN (mVpp)
70
80
90
100
D030
Figure 32. Spurious-Free Dynamic Range vs
Input Signal Amplitude
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
9
D027
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
5
10
15
20
25
Frequency (kHz)
30
35
40
0
5
10
D031
4096-point FFT, VIN = 100 mVPP
Figure 33. Frequency Spectrum With 1-kHz Input Signal
15
20
25
Frequency (kHz)
30
35
40
D032
4096-point FFT, VIN = 100 mVPP
Figure 34. Frequency Spectrum With 10-kHz Input Signal
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, AINP = –50 mV to 50 mV, AINN = AGND, fCLKIN = 20 MHz, and sinc3 filter with
OSR = 256 (unless otherwise noted)
10
10
9.5
9.5
9
9
8.5
8.5
8
IAVDD (mA)
IAVDD (mA)
8
7.5
7
6.5
7
6.5
6
6
5.5
5.5
5
5
4.5
4.5
4
3
3.5
4
4.5
AVDD (V)
5
4
-40
5.5
10
8
9.5
7.5
9
7
8.5
6.5
5
20 35 50 65
Temperature (°C)
80
95
110 125
D034
AMC1106M05
AMC1106E05
IDVDD (mA)
6
7.5
7
6.5
5.5
5
4.5
6
4
5.5
3.5
5
3
4.5
2.5
4
5
9
13
fCLKIN (MHz)
17
2
2.7
21
3.5
3.9
4.3
DVDD (V)
4.7
5.1
5.5
D036
Figure 38. Controller-Side Supply Current vs
Controller-Side Supply Voltage
8
8
AMC1106M05, DVDD = 3.3 V
AMC1106M05, DVDD = 5 V
AMC1106E05, DVDD = 3.3 V
AMC1106E05, DVDD = 5 V
7.5
7
6.5
AMC1106M05, DVDD = 3.3 V
AMC1106M05, DVDD = 5 V
AMC1106E05, DVDD = 3.3 V
AMC1106E05, DVDD = 5 V
7.5
7
6.5
6
IDVDD (mA)
6
5.5
5
4.5
5.5
5
4.5
4
4
3.5
3.5
3
3
2.5
2.5
2
-40
3.1
D035
Figure 37. High-Side Supply Current vs Clock Frequency
IDVDD (mA)
-10
Figure 36. High-Side Supply Current vs Temperature
8
2
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
5
9
D037
Figure 39. Controller-Side Supply Current vs Temperature
16
-25
D033
Figure 35. High-Side Supply Current vs
High-Side Supply Voltage
IAVDD (mA)
7.5
13
fCLKIN (MHz)
17
21
D038
Figure 40. Controller-Side Supply Current vs
Clock Frequency
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8 Detailed Description
8.1 Overview
The analog input stage of the AMC1106 is a fully differential amplifier that feeds the second-order, delta-sigma
(ΔΣ) modulator that digitizes the input signal into a 1-bit output stream. The isolated data output DOUT of the
converter provides a stream of digital ones and zeros that is synchronous to the externally-provided clock source
at the CLKIN pin with a frequency as specified in the Switching Characteristics table. The time average of this
serial bitstream output is proportional to the analog input voltage.
The Functional Block Diagram section shows a detailed block diagram of the AMC1106. The analog input range
is tailored to directly accommodate a voltage drop across a shunt resistor used for current sensing. The silicondioxide (SiO2) based capacitive isolation barrier supports a high level of magnetic field immunity as described in
the ISO72x Digital Isolator Magnetic-Field Immunity application report, available for download at www.ti.com. The
external clock input simplifies the synchronization of multiple current-sensing channels on the system level. The
extended frequency range of up to 21 MHz supports higher performance levels compared to the other solutions
available on the market.
8.2 Functional Block Diagram
AVDD
DVDD
Isolation
Barrier
AMC1106x05
Receiver
AINP
DOUT
Interface
û Modulator
Bandgap
Reference
VCM, AVDD
Diagnostic
AGND
Receiver
AINN
CLKIN
DGND
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8.3 Feature Description
8.3.1 Analog Input
The AMC1106 incorporates front-end circuitry that contains a differential amplifier and sampling stage, followed
by a ΔΣ modulator. The gain of the differential amplifier is set by internal precision resistors to a factor of 20 with
a differential input resistance of 4.9 kΩ. For reduced offset and offset drift, the differential amplifier is chopperstabilized with the switching frequency set at fCLKIN / 32. Figure 41 shows that the switching frequency generates
a spur. The impact of this spur on the overall system-level performance depends on the digital filter settings.
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
-160
0.1
1
10
100
Frequency (kHz)
1000
10000
D007
sinc3 filter, OSR = 2, fCLKIN = 20 MHz, fIN = 1 kHz
Figure 41. Quantization Noise Shaping
There are two restrictions on the analog input signals (AINP and AINN). First, if the input voltage exceeds the
range AGND – 6 V to AVDD + 0.5 V, the input current must be limited to 10 mA because the device input
electrostatic discharge (ESD) diodes turn on. In addition, the linearity and noise performance of the device are
ensured only when the differential analog input voltage remains within the specified linear full-scale range (FSR)
and within the specified input common-mode voltage range (VCM).
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Feature Description (continued)
8.3.2 Modulator
The modulator implemented in the AMC1106 (such as the one conceptualized in Figure 42) is a second-order,
switched-capacitor, feed-forward ΔΣ modulator. The analog input voltage VIN and the output V5 of the 1-bit
digital-to-analog converter (DAC) are subtracted, providing an analog voltage V1 at the input of the first integrator
stage. The output of the first integrator feeds the input of the second integrator stage, resulting in output voltage
V3 that is subtracted from the input signal VIN and the output of the first integrator V2. Depending on the polarity
of the resulting voltage V4, the output of the comparator is changed. In this case, the 1-bit DAC responds on the
next clock pulse by changing its analog output voltage V5, causing the integrators to progress in the opposite
direction and forcing the value of the integrator output to track the average value of the input.
fCLKIN
V1
VIN
V2
Integrator 1
V4
V3
Integrator 2
CMP
0V
V5
DAC
Figure 42. Block Diagram of a Second-Order Modulator
The modulator shifts the quantization noise to high frequencies; see Figure 41. Therefore, use a low-pass digital
filter at the output of the device to increase the overall performance. This filter is also used to convert from the 1bit data stream at a high sampling rate into a higher-bit data word at a lower rate (decimation). TI's
microcontroller family MSP430F67x offers a path to directly access the integrated sinc-filters of the SD24_B
ADCs for a simple system-level solution for multichannel, isolated current sensing. Also, the microcontroller
families TMS320F2807x and TMS320F2837x offer a suitable programmable, hardwired filter structure termed a
sigma-delta filter module (SDFM) optimized for usage with the AMC1106. An additional option is to use a suitable
application-specific device, such as the AMC1210 (a four-channel digital sinc-filter). Alternatively, a fieldprogrammable gate array (FPGA) can be used to implement the filter.
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Feature Description (continued)
8.3.3 Isolation Channel Signal Transmission
The AMC1106 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream
across the capacitive SiO2-based isolation barrier. The transmitter modulates the bitstream at TX IN in Figure 43
with an internally-generated, 480-MHz carrier across the isolation barrier to represent a digital one and sends a
no signal to represent the digital zero. The receiver demodulates the signal after advanced signal conditioning
and produces the output. The symmetrical design of each isolation channel improves the CMTI performance and
reduces the radiated emissions caused by the high-frequency carrier. Figure 43 shows a block diagram of an
isolation channel integrated in the AMC1106.
Transmitter
Receiver
OOK
Modulation
TX IN
TX Signal
Conditioning
SiO2-Based
Capacitive
Reinforced
Isolation
Barrier
RX Signal
Conditioning
Envelope
Detection
RX OUT
Oscillator
Figure 43. Block Diagram of an Isolation Channel
Figure 44 shows the concept of the on-off keying scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
Figure 44. OOK-Based Modulation Scheme
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Feature Description (continued)
8.3.4 Digital Output
A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A
differential input of 50 mV produces a stream of ones and zeros that are high 89.06% of the time. With 16 bits of
resolution on the decimation filter, that percentage ideally corresponds to code 58368. A differential input of –50
mV produces a stream of ones and zeros that are high 10.94% of the time and ideally results in code 7168 with a
16-bit resolution decimation filter. This –50-mV to 50-mV input voltage range is also the specified linear range
FSR of the AMC1106 with performance as specified in this document. If the input voltage value exceeds this
range, the output of the modulator shows nonlinear behavior where the quantization noise increases. The output
of the modulator clips with a stream of only zeros with an input less than or equal to –64 mV or with a stream of
only ones with an input greater than or equal to 64 mV. In this case, however, the AMC1106 generates a single 1
(if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see the FailSafe Output section for more details). Figure 45 shows the input voltage versus the modulator output signal.
Modulator Output
+FS (Analog Input)
-FS (Analog Input)
Analog Input
Figure 45. Analog Input versus AMC1106 Modulator Output
Equation 1 calculates the density of ones in the output bitstream for any input voltage value (with the exception
of a full-scale input signal, as described in the Output Behavior in Case of a Full-Scale Input section):
VIN
VClipping
2 u VClipping
(1)
The AMC1106 system clock is provided externally at the CLKIN pin. For more details, see the Switching
Characteristics table and the Manchester Coding Feature section.
8.3.5 Manchester Coding Feature
The AMC1106E05 offers the IEEE 802.3-compliant Manchester coding feature that generates at least one
transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc
components and supports single-wire data and clock transfer without having to consider the setup and hold time
requirements of the receiving device. The Manchester coding combines the clock and data information using
exclusive or (XOR) logical operation. Figure 46 shows the resulting bitstream. The duty cycle of the Manchester
encoded bitstream depends on the duty cycle of the input clock CLKIN.
Clock
Uncoded
Bitstream
1
0
1
0
1
1
1
0
0
1
1
0
0
0
1
Machester
Coded
Bitstream
Figure 46. Manchester Coded Output of the AMC1106E05
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8.4 Device Functional Modes
8.4.1 Fail-Safe Output
In the case of a missing AVDD high-side supply voltage, the output of the ΔΣ modulator is not defined and can
cause a system malfunction. In systems with high safety requirements, this behavior is not acceptable.
Therefore, as shown in Figure 47, the AMC1106 implements a fail-safe output function that ensures that the
DOUT output of the device offers a steady-state bitstream of logic 0's in case of a missing AVDD.
Similarly, as also shown in Figure 47, if the common-mode voltage of the input reaches or exceeds the specified
common-mode overvoltage detection level VCMov as defined in the Electrical Characteristics table, the AMC1106
generates a steady-state bitstream of logic 1's at the DOUT output.
tASTART
tISTART
CLKIN
...
AVDD
VCM
DOUT
AVDD good
Missing AVDD
VCM • 9CMov
VCM < VCMov
Valid bitstream
AVDD good
µ0¶
µ1¶
Test pattern
VCM < VCMov
µ1¶
Bitstream not valid
Valid bitstream
Figure 47. Fail-Safe Output of the AMC1106
8.4.2 Output Behavior in Case of a Full-Scale Input
If a full-scale input signal is applied to the AMC1106 (that is, |VIN| ≥ |VClipping|), Figure 48 shows that the device
generates a single one or zero every 128 bits at DOUT, depending on the actual polarity of the signal being
sensed. In this way, differentiating between a missing AVDD and a full-scale input signal is possible on the
system level.
CLKIN
...
DOUT
...
AINP - $,11 ” -64 mV
DOUT
...
...
...
...
AINP ± $,11 • 64 mV
127 tCLKIN
127 tCLKIN
Figure 48. Overrange Output of the AMC1106
22
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Digital Filter Usage
The modulator generates a bit stream that is processed by a digital filter to obtain a digital word similar to a
conversion result of a conventional analog-to-digital converter (ADC). A very simple filter, shown in Equation 2,
built with minimal effort and hardware, is a sinc3-type filter:
H z
§ 1 z OSR
¨¨
1
© 1 z
·
¸¸
¹
3
(2)
This filter provides the best output performance at the lowest hardware size (count of digital gates) for a secondorder modulator. All the characterization in this document is also done with a sinc3 filter with an oversampling
ratio (OSR) of 256 and an output word width of 16 bits.
An example code for implementing a sinc3 filter in an FPGA is discussed in application note Combining ADS1202
with FPGA Digital Filter for Current Measurement in Motor Control Applications, available for download at
www.ti.com.
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9.2 Typical Application
ΔΣ ADCs are widely used for current measurement in electricity meters because of the high ac accuracy
obtained over a wide dynamic range that is achieved by averaging in the digital filter. As a result of their inherent
isolation, current transformers (CT) were commonly used as current sensors in 3-phase electricity meters in the
past. A strong magnetic field can saturate a CT and stop proper energy measurement. Shunt resistors are
immune to magnetic fields and can be used to design temper-free electricity meters. The input structure of the
AMC1106 is optimized for use with low-impedance shunt resistors to minimize the power dissipation of the
circuit. The transformerless galvanic isolation of the bitstream as implemented in the AMC1106 is tailored for
shunt-based current sensing in modern 3-phase electricity meter designs.
Figure 49 shows a simplified schematic of the AMC1106 in a shunt-based, 3-phase electricity meter application.
Source
Phase C
Neutral
Phase A
Isolation
Barrier
Phase B
DVDD
MSP430F67641A
RSHUNT
AVDD1
SD24_B
Filter 1
AMC1106
RSHUNT
AVDD2
SD24_B
Filter 2
AMC1106
RSHUNT
AVDD3
Metrology
Calculation
Engine
SD24_B
Filter 3
AMC1106
System
Interface
Clock &
Trigger
Generator
Level-Shifted
Voltage Divider
Level-Shifted
Voltage Divider
ADC10
Module
Neutral
Level-Shifted
Voltage Divider
Phase A
DGND
Phase B
Phase C
Load
Isolated
Power Supply
Generation
Copyright © 2017, Texas Instruments Incorporated
Figure 49. The AMC1106 in a 3-Phase Electricity Meter Application
24
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 lists the parameters for the this typical application.
Table 1. Design Requirements
PARAMETER
VALUE
AVDD1, AVDD2, and AVDD3 high-side supply voltages
3.3 V or 5 V
DVDD low-side supply voltage
3.3 V or 5 V
Voltage drop across the shunt for a linear response
±50 mV (maximum)
Accuracy
Class 0.5 or better
9.2.2 Detailed Design Procedure
The high-side power supply (AVDD) for the AMC1106 is externally derived from either a capacitive-drop or a
coreless transformer power-supply circuit. Further details are provided in the Power Supply Recommendations
section.
The floating ground reference (AGND) is derived from one of the ends of the shunt resistor that is connected to
the analog inputs of the AMC1106. If a four-pin shunt is used, the inputs of the device are connected to the inner
leads and AGND is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the voltage drop across the shunt resistor (VSHUNT) for the desired measured
current: VSHUNT = I × RSHUNT.
Consider the following two restrictions to choose the proper value of the shunt resistor RSHUNT:
• The voltage drop caused by the nominal current range must not exceed the recommended differential input
voltage range: VSHUNT ≤ ±50 mV
• The voltage drop caused by the maximum allowed overcurrent must not exceed the input voltage that causes
a clipping output: |VSHUNT| ≤ |VClipping|
Use an RC filter in front of the AMC1106 to improve the overall signal-to-noise performance of the system and
improve the immunity of the circuit to high-frequency electromagnetic fields.
For the AMC1106 output bitstream averaging, a poly-phase device version from TI's MSP430F67x family of lowpower microcontrollers (MCUs) is recommended. This family offers the sigma-delta module (SD24_B) that allows
for bypassing the internal modulator and directly accessing the digital filter. The integrated trigger and clock
generator support synchronization of all three AMC1106 devices and the internal 10-bit SAR ADC that is used to
deliver the voltage information of all phases.
Figure 50 shows a voltage divider circuit with a common-mode set to 1/3 of the supply voltage that is used to
adjust the mains voltage signal to the input voltage range of the SAR ADC used in the MSP430F67641A.
DVDD
Neutral
20 k
Phase
1M
1M
1M
1M
1M
1M
10-Bit
SAR
ADC
10 k
1M
MSP430F67641A
DGND
Copyright © 2017, Texas Instruments Incorporated
Figure 50. Level-Shifted Voltage Divider
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For further design recommendations and system level considerations, see the Multi-Phase Power Quality
Measurement With Isolated Shunt Sensors or the Magnetically Immune Transformerless Power Supply for
Isolated Shunt Current Measurement reference designs offered by TI.
9.2.3 Application Curve
In electricity metering applications, the initial calibration of the offset, gain, and phase errors is absolutely
necessary to correctly sense the current and voltage signals, and calculate the power with the required system
level accuracy as per regional regulations. After system calibration, an electricity meter circuit based on the shunt
resistors, the AMC1106, and the MSP430F67x support error levels below ±0.2%, as shown in Figure 51 and the
documentation of the reference designs listed previously.
0.4
0.3
Error (%)
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
10
20
30
40
50
Current (A)
60
70
80
90
D039
Figure 51. Active Energy Error
9.2.4 Do's and Don'ts
Do not leave the inputs of the AMC1106 unconnected (floating) when the device is powered up. If both modulator
inputs are left floating, the input bias current drives these inputs to the output common-mode voltage level of the
differential amplifier of approximately 1.9 V. If that voltage is above the specified input common-mode range, the
gain of the differential amplifier diminishes and the modulator outputs a bitstream resembling a zero differential
input voltage.
26
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10 Power Supply Recommendations
For lowest system-level cost, the high-side power supply (AVDD) for the AMC1106 is derived from an external
capacitive-drop power supply. The Magnetically Immune Transformerless Power Supply for Isolated Shunt
Current Measurement reference design and Figure 52 shows a proven solution based on a 6.2-V diode and the
TLV70450 5-V low dropout (LDO) regulator. A low equivalent series resistance (ESR) decoupling capacitor of 0.1
µF is recommended for filtering this power-supply path. Place this capacitor (C5 in Figure 52) as close as
possible to the AVDD pin of the AMC1106 for best performance.
The floating ground reference (AGND) is derived from the end of the shunt resistor that is also connected to the
negative input (AINN) of the device. If a four-pin shunt is used, the device inputs are connected to the inner leads
and AGND is connected to one of the outer leads of the shunt.
For decoupling of the digital power supply on the controller side, TI recommends using a 0.1-µF capacitor (C6 in
Figure 52) assembled as close to the DVDD pin of the AMC1106 as possible, followed by an additional capacitor
in the range of 1 µF to 10 µF.
Phase
Neutral
C1
R1
470 Ÿ
Isolation
Barrier
D2
TLV70450
IN
RSHUNT
470 nF / 400 V
2200 …F
D1
6.2 V
0.1 …F
AVDD
OUT
DVDD
GND
2.2 …F
0.1 …F
0.1 …F
2.2 …F
C6
C7
AMC1106
C2
C3
C4
C5
AGND
DGND
DGND
Copyright © 2017, Texas Instruments Incorporated
Figure 52. Capacitive-Drop Solution for the AMC1106 AVDD Supply
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11 Layout
11.1 Layout Guidelines
Figure 53 shows a layout recommendation example based on an on-board, 4-wire shunt resistor that details the
critical placement of the decoupling capacitors (as close as possible to the AMC1106 supply pins) and the
placement of the other components required by the device. For best performance, place the shunt resistor close
to the AINP and AINN inputs of the AMC1106 and keep the layout of both connections symmetrical.
11.2 Layout Example
Clearance area,
to be kept free of any
conductive materials.
Shunt Resistor
To Floating
Power
Supply
RFLT
RFLT
SMD
0603
SMD
0603
2.2 µF
0.1 µF
SMD
0603
SMD
0603
AVDD
CFLT
SMD
0603
1
16
0.1 µF
2.2 µF
SMD
0603
SMD
0603
DVDD
CLKIN
From Clock
Source
AINN
DOUT
To Digital
Filter
(MCU)
AGND
DGND
AINP
AMC1106x
LEGEND
Copper Pour and Traces
High-Side Area
Controller-Side Area
Via to Ground Plane
Via to Supply Plane
Copyright © 2017, Texas Instruments Incorporated
Figure 53. Recommended Layout of the AMC1106
28
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Isolation Glossary
See the Isolation Glossary
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• AMC1210 Quad Digital Filter for 2nd-Order Delta-Sigma Modulator
• MSP430F67x Polyphase Metering SoCs
• TMS320F2807x Piccolo™ Microcontrollers
• TMS320F2837xD Dual-Core Delfino™ Microcontrollers
• TLV704 24-V Input Voltage, 150-mA, Ultralow IQ Low-Dropout Regulators
• ISO72x Digital Isolator Magnetic-Field Immunity
• Combining ADS1202 with FPGA Digital Filter for Current Measurement in Motor Control Applications
• Multi-Phase Power Quality Measurement With Isolated Shunt Sensors
• Magnetically Immune Transformerless Power Supply for Isolated Shunt Current Measurement
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
AMC1106E05
Click here
Click here
Click here
Click here
Click here
AMC1106M05
Click here
Click here
Click here
Click here
Click here
12.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.5 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.6 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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PACKAGE OPTION ADDENDUM
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12-Nov-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AMC1106E05DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1106E05
AMC1106E05DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1106E05
AMC1106M05DWV
ACTIVE
SOIC
DWV
8
64
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1106M05
AMC1106M05DWVR
ACTIVE
SOIC
DWV
8
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
1106M05
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
AMC1106E05DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
AMC1106M05DWVR
SOIC
DWV
8
1000
330.0
16.4
12.05
6.15
3.3
16.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
AMC1106E05DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
AMC1106M05DWVR
SOIC
DWV
8
1000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
SCALE 2.000
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
3.81
5.95
5.75
NOTE 3
4
5
0.51
0.31
0.25
C A
8X
A
7.6
7.4
NOTE 4
B
B
2.8 MAX
0.33
TYP
0.13
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0 -8
0.46
0.36
1.0
0.5
(2)
DETAIL A
TYPICAL
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
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EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SYMM
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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