SMPS IC SmartrectifierTM IR11688S DUAL SYNCHRONOUS RECTIFICATION CONTROL IC Product Summary Features • • • • • • • • • • • • • • • Secondary-side high speed synchronous rectification controller for resonant half bridge converters Direct sensing of MOSFET drain voltage up to 200V Operates up to 400kHz switching frequency Programmable Minimum On Time Anti-bounce logic and UVLO protection Linear turn-off phase to compensate for premature switch off due to parasitic inductance 4A peak turn off drive current Micropower start-up & ultra-low quiescent current 50ns turn-off propagation delay Wide Vcc operating range 4.75V to 18V Cycle by Cycle MOT Protection Auto low power mode standby mode Improved noise immunity Compatible with Energy Star low standby power Lead-free Topology LLC Half-bridge VD 200V VOUT Vcc Io+ & I o- +1A & -4A Package Options 8-Pin SOIC Typical Applications • Desktop SMPS, Server SMPS, AC-DC adapters, LCD & PDP TV, Telecom SMPS Ordering Information Standard Pack Base Part Number IR11688S 1 Package Type SOIC8N Complete Part Number Form Quantity Tape and Reel 2500 IR11688STRPBF 2016-1-18 IR11688S Typical Connection Diagram Gate2 8 VCC 2 GND 7 MOT 3 VD1 4 2 IR11688 Gate1 1 VS 6 Cout LOAD VD2 5 2016-1-18 IR11688S Table of Contents Page Ordering Information 1 Description 4 Absolute Maximum Ratings 5 Electrical Characteristics 6 Functional Block Diagram 8 Input/Output Pin Equivalent Circuit Diagram 9 Pin Definitions 10 Pin Assignments 10 Application Information and Additional Details 12 Package Details 23 Tape and Reel Details 24 Part Marking Information 25 Qualification Information 26 3 2016-1-18 IR11688S Description The IR11688 is a dual smart secondary-side controller IC optimized to drive two N-Channel power MOSFETs configured for synchronous rectification in resonant converter applications. Each channel can drive one or multiple parallel MOSFETs to emulate the behavior of Schottky diode rectifiers, bypassing the body diodes for the majority of each conduction period to minimize power dissipation and remaining off during the blocking period. The drain to source voltage of each rectifier MOSFET is sensed to determine the source to drain current and turn each gate on rapidly at the start of each conduction cycle and off in close proximity to the zero current transitions for each branch of the output rectifier circuit. Ruggedness and noise immunity are accomplished using an advanced blanking scheme and double-pulse suppression that allows reliable operation in fixed and variable frequency applications. The programmable minimum on time (MOT) function provides flexibility to work over a wide range of switching frequencies. The cycle-by-cycle MOT protection circuit is able to automatically detect a light or no load condition so that the gate drives may be disabled to avoid unwanted reverse currents flowing through the MOSFETs. The IR11688 has a wide Vcc supply voltage range from 4.75V to 18V, enabling its supply to be derived from the output and eliminating the need for an auxiliary supply circuit in systems with output voltage as low as 5V. The IR11688 also has very low quiescent current when the gate drives are not switching to offer minimal power consumption in standby mode. 4 2016-1-18 IR11688S Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any pin. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Parameters Supply Voltage Cont. Drain Sense Voltage Pulse Drain Sense Voltage Source Sense Voltage Gate Voltage MOT Voltage Operating Junction Temperature Storage Temperature Thermal Resistance Package Power Dissipation Symbol VCC VD1,2 VD1,2 VS VGATE1,2 VMOT TJ TS RθJA PD Min. -0.3 -1 -3 -1 -0.3 -0.3 -40 -55 Max. 20 200 200 5 Vcc+0.3 3.5 150 150 128 970 Units V V V V V V °C °C °C/W mW Remarks SOIC-8 SOIC-8, TAMB=25°C Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VCC VD Definition TJ Max. 18 200 125 Units Supply voltage Drain Sense Voltage Junction Temperature Min. 4.75 ① -3 -40 Fsw Switching Frequency --- 400 kHz Min. 20 Max. 150 Units kΩ V °C ① VD -3V negative spike width ≤100ns Recommended Component Values Symbol RMOT 5 Component MOT pin resistor value 2016-1-18 IR11688S Electrical Characteristics VCC=12V, TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to GND (pin7). Supply Section Parameters Supply Voltage Operating Range VCC Turn On Threshold VCC Turn Off Threshold (Under Voltage Lock Out) VCC Turn On/Off Hysteresis Typ. Max. Units 4.75 4.35 4.55 18 4.75 V V VCC UVLO 4.15 4.35 4.55 V VCC HYST --- 0.2 --- V ICC --- 13 15 mA Start-up Current Quiescent waiting time IQCC ICC START TWAIT ----340 320 40 570 500 80 800 µA µA µS Comparator Section Parameters Turn-off Threshold Regulation Threshold Turn-on Threshold Hysteresis Input Bias Current Input Bias Current Turn-on Blanking time Symbol VTH1 VTHR VTH2 VHYST IIBIAS1 IIBIAS2 TBon Min. -7 -50 -263 ---7.5 ----- Typ. -4 -40 -230 230 -5 7 150 Max. 0 -30 -197 ----10 --- Units mV mV mV mV µA µA ns One-Shot Section Parameters Blanking pulse duration Reset Threshold Reset Delay Hysteresis Symbol tBLANK VTH3 tBRST VHYST3 Min. 8 1.06 ----- Typ. 15 1.18 400 40 Max. 24 1.31 ----- Units µs V ns mV GBD Min. 375 0.75 Typ. 500 1 Max. 625 1.25 Units Remarks RMOT =24kΩ, VCC=5V ns RMOT =50kΩ, VCC=5V µs Operating Current Symbol Min. VCC VCC ON Quiescent Current Minimum On Time Section Parameters Symbol Minimum on time 6 TOnmin Remarks CLOAD =1nF, fSW = 400kHz, RMOT=50kΩ No switching at VD pins and after TWAIT is exceeded, VD=2V, RMOT=50kΩ VCC=VCC ON - 0.1V Remarks VS=0V 10mV hysteresis (-50mV/-40mV) GBD VD = -50mV VD = 200V GBD Remarks 2016-1-18 IR11688S Electrical Characteristics VCC=12V, TA = 25°C unless otherwise specified. The output voltage and current (VO and IO) parameters are referenced to GND (pin7). Gate Driver Section Parameters Gate Low Voltage Symbol VGLO Gate High Voltage VGTH tr tf Min. ----------- Typ. 0.15 11.9 4.9 20 10 Max. 0.25 ----38 22 Turn on Propagation Delay tDon --- 200 250 Turn off Propagation Delay Pull up Resistance Pull down Resistance Output Peak Current (source) Output Peak Current (sink) tDoff rup rdown ------- 42 6 1.5 60 ----- IO source IO sink ----- 1 4 ----- Rise Time Fall Time Units Remarks V IGATE = 100mA GBD V GBD ns CLOAD = 1nF ns CLOAD = 1nF VDS to VGATE – VDS goes down ns from 6V to -1V VDS to VGATE –VDS goes up from ns -1V to 6V GBD Ω IGATE = -100mA Ω A A GBD GBD GBD – parameter is guaranteed by design and is not tested. 7 2016-1-18 IR11688S Functional Block Diagram VCC UVLO & Internal Bias VTHR VTH3 VCC 150ns RESET Min ON Time (With Cycle by Cycle MOT Check Circuit) VD1 VS GATE1 Min OFF Time MOT PGEN MOT 150ns Shoot-through Protection Logic Min ON Time (With Cycle by Cycle MOT Check Circuit) VD2 GATE2 Min OFF Time VCC GND RESET VTH3 8 VTHR 2016-1-18 IR11688S I/O Pin Equivalent Circuit Diagram VCC VD1 VD2 ESD Diode RESD ESD Diode GATE1 GATE2 200V Diode GND 9 ESD Diode GND 2016-1-18 IR11688S Pin Definitions PIN# 1 2 3 4 5 6 7 8 Symbol GATE1 VCC MOT VD1 VD2 VS GND GATE2 Description Gate Drive Output 1 Supply Voltage Minimum On Time Programmable pin Sync FET 1 Drain Voltage Sense Sync FET 2 Drain Voltage Sense Sync FET Source Voltage Sense Analog and Power Ground Gate Drive Output 2 Pin Assignments Gate2 8 VCC 2 GND 7 MOT 3 VD1 4 10 IR11688 Gate1 1 VS 6 VD2 5 2016-1-18 IR11688S Detailed Pin Description VCC: Power Supply This is the supply voltage pin of the IC, monitored by the under voltage lockout circuit. It is possible to turn off the IC entering UVLO mode by pulling this pin below the minimum turn off threshold voltage for micro power consumption. To prevent noise interfering with operation, a ceramic decoupling capacitor should be connected from Vcc to GND and located as close to the IC as possible. A low value series resistor may also be added to the Vcc supply circuit for filtering if required. Vcc is internally clamped at around 20V. GND: Ground This is power ground connection to the IC. Internal circuit blocks and gate drivers are referenced to this point. MOT: Minimum On Time The MOT programming pin controls the amount of minimum on time. Once VTH2 is crossed at either VD input, the corresponding gate drive output will transition high to turn on the SR MOSFET. Spurious ringing and oscillations can falsely trigger the input comparator to prematurely switch the output off. During the MOT period the input comparator is disabled maintaining conduction through the MOSFET on for this preset minimum period. The MOT is typically programmed between 500ns and 2us by means of an external resistor referenced to GND. VD1 and VD2: Drain Voltage Sense The VD pins are the voltage sensing inputs for the SR MOSFET drains. These are high voltage inputs therefore particular care must be taken in properly routing the connections. Additional RC filters can be placed at these inputs to improve noise immunity, however only a small resistor (≤1kΩ) and capacitor value (in the pF range) may be used to avoid introducing excessive delay to the control input. VS: Source Voltage Sense This is the signal ground for the sources of the two SR power MOSFETs to provide an accurate differential voltage measurement. Kelvin connect this pin to the source of MOSFET2 (channel 2 MOSFET) is recommended if the two MOSFETs are far apart to each other. GATE1 and GATE2: Gate Drive Outputs Each gate driver output has +1A/-4A peak drive capability. Although these pins can be directly connected to the SR MOSFET gates the use of gate resistors is recommended, especially when using several MOSFETs in parallel. Care must be taken to keep the gate loop as short and as tight as possible in order to achieve optimal switching performance. 11 2016-1-18 IR11688S Application Information and Additional Details State Diagram POWER ON Gate Inactive UVLO/SLEEP MODE VCC < VCCon Gate Inactive ICC max = 200uA VCC > VCCon, VDS>VTH3 two edges VCC < VCCuvlo or No VD edge > Twait NORMAL Gate Active Gate PW ≥ MOT Cycle by Cycle MOT Check Enabled VDS>VTH1 @ MOT VDS<VTH1 @ MOT MOT PROTECTION MODE Gate Output Disabled UVLO/SLEEP Mode The IC remains in the UVLO/SLEEP condition until the voltage at the VCC pin first exceeds the VCC turn on threshold voltage, VCC ON. While in the UVLO/SLEEP state, the gate drive outputs are inactive and only a very small quiescent current of ICC START is drawn. UVLO mode is accessible from any other state of operation whenever the IC supply voltage condition of Vcc < VCC UVLO occurs. If during normal operation, the drain inputs remain inactive such that no edges are detected for a period longer than TWAIT the IC enters SLEEP mode. It remains in a low power state until woken up by a voltage transition at either VD input. Normal Mode The IC enters into normal operating mode when the VCC ON threshold has been exceeded. On entering Normal Mode from the UVLO Mode the GATE outputs remain disabled until VDS transitions above VTH3 two times. This ensures that the GATE output cannot be enabled in the middle of a switching cycle since this can cause undesired reverse conduction. The cycle by cycle minimum on time (MOT) protection circuit also becomes activated to prevent reverse currents occurring when conduction time is short, which may also happen during system power up and down. The gate drives will continuously drive the MOSFETs after this startup sequence is completed. MOT Protection Mode If secondary current conduction time in either rectifier circuit branch is shorter than the set MOT, the subsequent gate driver output pulse is skipped. This function avoids reverse current from occurring when the system is switching at very low duty-cycles under very light or zero load conditions. The cycle by cycle MOT check circuit always remains active in Normal Mode and MOT Protection Mode so that the IC will automatically resume normal operation only after the load increases to a level where the secondary current conduction time exceeds MOT. System standby power consumption is significantly reduced in this mode while the gate outputs are inactive. 12 2016-1-18 IR11688S General Description TM The IR11688 dual SMART RECTIFIER controller is a high-voltage IC for synchronous rectification designed for resonant converter applications. As stated, it emulates the operation of two diodes configured with a center tapped transformer secondary by correctly switching on and off the synchronous rectifier MOSFETs in the two rectifier circuit branches. The core of this device consists of two high-voltage drain sensing inputs feeding high speed comparators to differentially sense the drain to source voltage at each SR MOSFET. The SR MOSFET source to drain current is detected from the voltage across the conducting body diode or the RDSON resistance when switched on. Internal control logic allows the corresponding gate drive output to be switched on and off at the correct time to bypass the body diode for the majority of the conduction period. The IR11688 further simplifies synchronous rectifier control by offering the following power management features: • • • Wide VCC operating range allows the IC to be supplied from the converter output Shoot through protection logic that prevents both GATE outputs from ever being high at the same time Turn-off phase regulation to compensate for power device package inductance and avoid premature turnoff Optimized negative turn on voltage threshold detection and leading edge noise filter to minimize false triggering due to ringing oscillations • The IR11688 control technique senses SR MOSFET source to drain voltages comparing them with three different negative thresholds (VTH1, VTH2 and VTHR) to precisely control gate turn on and off as shown in figure 1: VGATE VTH2 VTHR VTH1 VDS Figure 1: Input comparator thresholds Turn-on phase When the conduction phase of each SR MOSFET begins, the device is off so therefore current starts to flow through the body diode producing a negative VDS voltage across it. The body diode has a much higher voltage drop than the one resulting from the MOSFET on resistance and is therefore sufficient to trigger the turn-on threshold VTH2. When either VDS input remains below VTH2 for more than TBon (150ns), the gate of the corresponding SR MOSFET is driven high, which causes VDS to reduce rapidly to ID x RDSON. The internal delay timer will be reset if VDS rises above VTH2 before TBon times out. This turn-on blanking time helps to avoid misfiring that could be triggered by high frequency ringing in DCM operation. The voltage drop at switch on is usually accompanied by some amount of ringing, which could potentially trigger the input comparator to turn off the gate drive very quickly. However the minimum on time (MOT) blanking period prevents this. The turn-on blanking time (TBon) and the MOT limit the minimum conduction time for the secondary rectifiers determining the switching frequency upper limit that the IR11688 may effectively operate at. 13 2016-1-18 IR11688S Regulation phase After the gate has been driven high at switch on, the SR MOSFET remains on until the source to drain current falls to the level where VDS reaches the regulation threshold VTHR. At the end of the MOT, the gate output is no longer driven high and reverts to a high impedance state. When VDS<VTHR a weak pull down gradually discharges the gate voltage held by the SR MOSFET input capacitance. As the gate voltage drops, the MOSFET channel resistance increases as it enters the linear region. This causes VDS to once again exceed VTHR so that weak pull down will cease until the conduction current falls to the point where VDS again drops below VTHR. This regulating process continues so that the conduction period is extended until the current has fallen to a very low level. In this way premature turn off, which can arise due to parasitic inductances in PCB traces and the MOSFET package, is prevented. This period of conduction through the SR MOSFET body diodes is thereby reduced to a minimum improving overall system efficiency. Turn-off and reset phases At the end of the switching cycle the conduction rectifier current reduces to zero so the VDS voltage will cross the turn-off threshold VTH1. When this happens the gate is driven low to switch off the SR MOSFET. Any residual current will again start flowing through the body diode causing a negative step in VDS. When this occurs VDS could potentially trigger turn-on once again by crossing VTH2. To prevent this possibility, turn on is blanked for a time period, tBLANK after turn off has occurred. The blanking time is internally set and can be reset only when VDS crosses the positive threshold VTH3. Reset occurs only when VDS remains higher than VTH3 for more than the reset blanking time, tBRST. This protects against false triggering due to ringing after the turn-off phase. Once reset the IR11688 is re-armed so that turn on may be triggered for the next conduction cycle. VTH3 DCM ringing IDS VDS (across MOSFET) T1 T2 VTH1 VTHR VTH2 Tbrst TDon TBon TDoff <TBon Gate Drive VDS pulse < TBon Gate stays off VDS pulse > TBon Gate turns on Blanking MOT tBLANK MOT time Figure 2: Secondary currents and voltages Programmable Minimum On Time The minimum on time is set by an external resistor (RMOT) connected between the MOT pin and ground. The minimum on time can be calculated based on below equation: TMOT = RMOT x 2 x 10-11 + 20ns where 20ns is the typical internal comparator propagation delay. RMOT value should remain within the upper and lower limits specified under recommended operating conditions. 14 2016-1-18 IR11688S MOT protection Under very light load or zero load conditions, the current in the SR MOSFETs becomes discontinuous and may be shorter than the MOT time in some cases. If this happens, reverse current will flow from the drain to source at the end of the MOT since the gate drive has been kept on. This reverse current discharges the converter output capacitor sending energy back to the transformer and resonating to cause voltage ringing at VDS at switch off. Such ringing may potentially trigger gate turn on leading to further reverse current and subsequent multiple falsely triggered erroneous gate pulses as illustrated below in Figure 4: VDS IDS Gate MOT Figure 3: Waveform without MOT protection The cycle-by-cycle MOT protection function detects reverse current at the end of the MOT period and disables the following gate output pulse preventing further reverse current. The internal comparator and MOT pulse generator continue to operate under the protection mode even when the gate drive is disabled. This enables the circuit to continuously monitor the system load current and automatically revert to normal operating mode once the load current conduction time has again increased to be longer than the MOT. This protection function reduces standby power losses and can also prevent voltage spikes caused by false triggering at light load. VDS IDS Gate Low Figure 4: Waveform under MOT protection mode Synchronized Enable Function Sync Enable function ensures that gate turn on always occurs at the beginning of a switching cycle. VGATE VDS UVLO Idrain Vth3 IC activated in the middle of a conduction cycle, VGATE stays low. VD>Vth3 for 2 cycles Vgate has output from the 3rd cycle Figure 5: Synchronized Enable Function 15 2016-1-18 IR11688S Driving Logic Level MOSFET An external gate clamping circuit is recommended when driving logic level SR MOSFETs. The clamping circuit keeps the gate voltage below 1V during system power up when the IR11688 is not fully biased in UVLO mode, especially when Vcc is less than 2V. It is not recommended to drive logic level MOSFETs with the IR11688 without a safety clamping circuit. Note the gate regulation feature will be lost when using PNP transistor clamping circuit. Use MOSFET clamping circuit (figure 7) if regulation function is needed. SR MOSFET 1 Rg1 Gate2 8 VCC 2 GND 7 MOT 3 VD1 4 IR11688 CVcc Gate1 1 VS 6 VD2 5 RMOT Rb1 SR MOSFET 2 Rg2 Rb2 Figure 6: PNP transistor gate clamping circuit for driving logic level MOSFET SR MOSFET Rg1 Gate2 8 VCC 2 GND 7 CVcc 3 4 Clamp FET1 IR11688 Gate1 1 Rg2 SR MOSFET 6 5 Clamp FET2 250k 2M Clamp FET3 1M Figure 7: Signal MOSFET gate clamping circuit for driving logic level MOSFET 16 2016-1-18 IR11688S VTH1 VDS VTH2 t Don t Doff VGate 90% 10% t rise tfall Figure 8: VD and gate drive output timing 17 2016-1-18 IR11688S Figure 9: Undervoltage Lockout vs. Temperature Figure 10: Icc Quiescent Current vs. Temperature Figure 11: Icc supply current at 1nF load vs. Temperature Figure 12: Icc Startup Current vs. Temperature 18 2016-1-18 IR11688S Figure 13: VD bias at -50mV vs. Temperature Figure 14: VD bias at 200V vs. Temperature Figure 15: VTH1 Threshold vs. Temperature Figure 16: VTH2 Threshold vs. Temperature (Red curve channel 1, Blue curve channel 2) 19 2016-1-18 IR11688S Figure 17: VTH3 Threshold vs. Temperature Figure 18: TBRST Reset Time vs. Temperature Figure 19: VTHR+ Threshold vs. Temperature Figure 20: VTHR- Threshold vs. Temperature 20 2016-1-18 IR11688S Figure 21: Minimum On Time vs. Temperature Figure 23: TBLANK Blanking Time vs. Temperature 21 Figure 22: TWAIT Wait Time vs. Temperature Figure 24: Gate Pull Down Resistance vs. Temperature 2016-1-18 IR11688S Figure 25: Gate Rise and Fall Time vs. Temperature (CH1) Figure 26: Gate Rise and Fall Time vs. Temperature (CH2) Figure 27: TDON Propagation Delay vs. Temperature 22 Figure 28: TDOFF Propagation Delay vs. Temperature 2016-1-18 IR11688S Package Details: SOIC8N 23 2016-1-18 IR11688S Tape and Reel Details: SOIC8N LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 11.70 12.30 D 5.45 5.55 E 6.30 6.50 F 5.10 5.30 G 1.50 n/a H 1.50 1.60 8SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.46 0.484 0.214 0.218 0.248 0.255 0.200 0.208 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 8SOICN Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 18.40 G 14.50 17.10 H 12.40 14.40 24 Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 0.724 0.570 0.673 0.488 0.566 2016-1-18 IR11688S Part Marking Information Part number Date code Pin 1 Identifier ? MARKING CODE P Lead Free Released 25 11688 YWW ? IR logo C XXXX Lot Code (Prod mode – 4 digit SPN code) Assembly site code Per SCOP 200-002 2016-1-18 IR11688S Qualification Information† †† Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. ††† MSL2 260°C SOIC8N (per IPC/JEDEC J-STD-020) Class A (per JEDEC standard JESD22-A115) Class 1C (per EIA/JEDEC standard EIA/JESD22-A114) Class I Level A (per JESD78) Yes † Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/productinfo/reliability/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. 26 2016-1-18 IR11688S Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2015 All Rights Reserved. IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury. 27 2016-1-18