ON AX8052F100-1 Ultra-low power microcontroller Datasheet

DATASHEET
AX8052F100
Ultra-Low Power
Microcontroller
Revision 2
2
Table of Contents
1.
Overview .................................................................................................................. 4
1.1. Features .................................................................................................................... 4
1.2. Applications ............................................................................................................... 6
2.
Block Diagram .......................................................................................................... 7
3.
Pin Function Descriptions ......................................................................................... 8
3.1. Alternate Pin Functions ................................................................................................ 9
3.2. Pinout Drawing .......................................................................................................... 10
4.
Specifications ......................................................................................................... 11
4.1. Absolute Maximum Ratings ......................................................................................... 11
4.2. DC Characteristics ..................................................................................................... 12
Supplies .................................................................................................................... 12
Logic ........................................................................................................................ 13
4.3. AC Characteristics ...................................................................................................... 13
Crystal Oscillator ........................................................................................................ 13
Low Frequency Crystal Oscillator .................................................................................. 14
Internal Low Power Oscillator ...................................................................................... 14
Internal RC Oscillator.................................................................................................. 14
Microcontroller ........................................................................................................... 15
ADC / Comparator / Temperature Sensor ...................................................................... 16
5.
Circuit Description.................................................................................................. 17
5.1. Microcontroller .......................................................................................................... 18
Memory Architecture .................................................................................................. 18
Memory Map.............................................................................................................. 19
Power Management .................................................................................................... 21
Clocking .................................................................................................................... 21
Reset and Interrupts .................................................................................................. 22
Debugging ................................................................................................................ 23
5.2. Timer, Output Compare and Input Capture ................................................................... 24
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AX8052F100
Table of Contents
5.3. UART ....................................................................................................................... 24
5.4. Dedicated Radio SPI Master Controller.......................................................................... 24
5.5. SPI Master/Slave Controller ........................................................................................ 24
5.6. ADC, Analog Comparators and Temperature Sensor ....................................................... 25
5.7. DMA Controller .......................................................................................................... 26
5.8. AES Engine ............................................................................................................... 26
5.9. Crystal Oscillator ....................................................................................................... 26
5.10.
6.
Ports ................................................................................................................... 27
Application Information ......................................................................................... 28
6.1. Typical Application Diagram ........................................................................................ 28
7.
QFN28 Package Information .................................................................................. 29
7.1. Package Outline QFN28 .............................................................................................. 29
7.2. QFN28 Soldering Profile .............................................................................................. 30
7.3. QFN28 Recommended Pad Layout ................................................................................ 31
7.4. Assembly Process ...................................................................................................... 31
Stencil Design & Solder Paste Application ...................................................................... 31
8.
References ............................................................................................................. 33
9.
Device Versions ...................................................................................................... 34
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AX8052F100
3
4
Overview
1. Overview
1.1. Features
without utilizing a UART or
GPIO pins
Ultra-low power microcontroller
•
QFN28 package
•
Supply range 1.8 V - 3.6 V
•
-40°C to 85°C
•
Ultra-low power consumption:
o
CPU active mode 150 μA/MHz
o
Sleep mode with 256 Byte RAM
retention and wake-up timer
running 850 nA
o
Sleep mode 4 kByte RAM
retention and wake-up timer
running 1.5 μA
•
•
Sleep mode 8 kByte RAM
retention and wake-up timer
running 2.2 μA
o
•
•
Memory
o
64 kByte FLASH
100 000 erase cycles
10 year data retention
o
8.25 kByte RAM
o
High performance memory
crossbar
Clocking
o
4 clock sources
•
on-chip 20 MHz RCoscillator
AX8052 Core
o
Industry standard 8052
instruction set
•
10 kHz/640 Hz ultralowpower RC-oscillator
o
High performance core, most
instructions require only 1
clock per instruction byte
•
fast crystal oscillator
•
low power tuning fork
crystal oscillator
o
20 MIPS
o
Dual DPTR for high speed
memory copies
o
22 interrupt vectors
o
Fully automatic calibration of
on-chip RC oscillators to a
reference clock
o
Clock monitor can detect
failures of the main clock and
switch to the on-chip fast RC
oscillator
o
Watchdog
Debugger
o
o
o
o
3-wire (1 dedicated, 2 shared
with GPIO Pins) debugger
interface
True hardware debugger with
breakpoints and single
stepping support
•
User programmable 64bit key
to restrict debugging to
authorized personnel
DebugLink interface allows
"printf" style debugging
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Power Modes
o
Standby, sleep and deep sleep
power modes for very low idle
power consumption
o
On-chip power-on reset and
brown out detection
o
Unrestricted operation from
1.8 V - 3.6 V VDD_IO
AX8052F100
Overview
•
•
16-bit Wakeup Timer
2 counting registers
o
o
4 event registers allow
flexible wakeup and software
schedules
5-9 bit word length, 1-2 stop
bits
o
Uses one of the General
Purpose Timers as baud rate
generator
GPIO
24 GPIO pins
o
PB0-PB7, PC0-PC3 and PR0PR5 5 V tolerant inputs
o
All GPIO pins support
individually programmable
pull-ups and interrupt on
change
Dedicated Radio Master SPI
Interface
o
Compatible to AXSEM RF and
other peripherals
o
Efficient CPU access
o
Easy access to transceiver
registers by mapping
transceiver registers into X
address space
o
Transceiver crystal may clock
MCU
Flexible allocation of GPIO
pins to peripherals
16-bit General Purpose Timer (3x)
o
Saw tooth and triangle modes
o
Sigma-Delta mode converts
timer into a DAC
o
Optional double buffering of
the PERIOD register allows
controlled frequency changes
o
Optional high-byte buffering
allows atomic 16-bit accesses
o
Flexible clocking options, can
use any internal or an
external clock source
•
Master/Slave SPI
o
•
o
10-bit 500 kSamples/s ADC
o
Up to 8 channels
o
Single ended and differential
sampling
o
x0.1, x1 and x10 gain
amplifier
o
Internal 1 V reference
o
Flexibly programmable
conversion schedule
o
Built-in temperature sensor
Pre-scaler included
o
Used together with a General
Purpose Timer to create PWM
waveforms
Optional double buffering
•
16-bit Input Capture Unit (2x)
o
used together with a General
Purpose Timer to time events
on an external or internal
signal
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Supports 3 and 4 wire
variants
ADC
16-bit Output Compare Unit (2x)
o
•
•
o
o
•
UART (2x)
o
o
•
•
Analog Comparators
o
Internal or external reference
o
Output signal may be routed
to GPIO, read by software, or
used as input capture trigger
AX8052F100
5
6
Overview
•
DMA controller
o
2 independent DMA channels
o
Moves data between X-RAM
and most on-chip peripherals
o
o
•
Cycle-steal and round-robin
memory arbitration ensure
minimal impact on AX8052
core
Chained buffer descriptors
allow arbitrarily elaborate
buffering schemes and
flexible interrupt generation
AES1
o
o
stream from X-RAM and
strobe output data into X-RAM
•
Dedicated AES crypto
controller
o
Multi Megabit/s data rates
o
Supports AES-128, AES-192
and AES-256 international
standards
o
Programmable round number
and software key schedule
generation allow longer key
lengths for higher security
applications
o
ECB, CFB and OFB chaining
modes
True Random Number Generator
(RNG)1
o
Dedicated DMA engine to
fetch input data and key
Cryptographic random
numbers
1.2. Applications
•
Ultra-low power microcontroller
applications, especially in
conjunction with AXSEM radio IC
•
Sensor Applications
•
Home Automation
•
Automatic Meter Reading
•
Remote Keyless Entry
•
Active RFID
•
Wireless Audio
1
The AES engine and the random number generator require software enabling and support.
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AX8052F100
Block Diagram
Block Diagram
DMA
Controller
Timer
Counter 0
8k
PA0
PA1
PA2
PA3
PA4
PA5
Timer
Counter 1
I-Bus
256
Axsem
8052
Timer
Counter 2
Debug
Interface
Output
Comp 0
System
Controller
Output
Comp 1
Reset, Clocks, Power
Input
Capt 0
AES
Crypto Engine
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
Input
Capt 1
ADC
Comparators
Temp Sensor
UART 0
POR
SFR-Bus
SPI M/S
X-Bus
RESET_N
GND
VDD_IO
GPIO
P-Bus
DBG_EN
FLASH
64k
RAM
PR0
PR1
PR2
PR3
PR4
PR5
DMA Req
AX8052F100
IRQ Req
2.
UART 1
I/O Multiplexer
Figure 1 Functional block diagram of the AX8052F100
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AX8052F100
7
8
Pin Function Descriptions
3.
Pin Function Descriptions
Symbol
Pin(s)
PR5
1
Type
I/O/PU
Description
General Purpose I/O
VDD_CORE
2
P
PR4
3
I/O/PU
General Purpose I/O
PR3
4
I/O/PU
General Purpose I/O
PR2
5
I/O/PU
General Purpose I/O
PR1
6
I/O/PU
General Purpose I/O
PR0
7
I/O/PU
General Purpose I/O
PC3
8
I/O/PU
General Purpose I/O
PC2
9
I/O/PU
General Purpose I/O
PC1
10
I/O/PU
General Purpose I/O
PC0
11
I/O/PU
General Purpose I/O
PB0
12
I/O/PU
General Purpose I/O
PB1
13
I/O/PU
General Purpose I/O
PB2
14
I/O/PU
General Purpose I/O
PB3
15
I/O/PU
General Purpose I/O
PB4
16
I/O/PU
General Purpose I/O
PB5
17
I/O/PU
General Purpose I/O
PB6, DBG_DATA
18
I/O/PU
General Purpose I/O, debugger data line
PB7, DBG_CLK
19
I/O/PU
General Purpose I/O, debugger clock line
DBG_EN
20
I/PD
In-Circuit Debugger Enable
RESET_N
21
I/PU
Optional reset pin. If this pin is not used it must be
connected to VDD_IO
VDD_IO
22
P
PA0
23
I/O/PU
General Purpose I/O
PA1
24
I/O/PU
General Purpose I/O
PA2
25
I/O/PU
General Purpose I/O
PA3
26
I/O/PU
General Purpose I/O
PA4
27
I/O/PU
General Purpose I/O
PA5
28
I/O/PU
General Purpose I/O
GND
Center pad
P
A =
I =
O =
PU =
analog signal
digital input signal
digital output signal
pull-up
Regulated output voltage
Unregulated power supply
Ground on center pad of QFN, must be connected
I/O
N
P
PD
=
=
=
=
digital input/output signal
not to be connected
power or ground
pull-down
All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL
compatible. Port A Pins (PA0 - PA7) must not be driven above VDD_IO, all other digital inputs are
5V tolerant. Pull-ups are programmable for all GPIO pins.
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AX8052F100
Pin Function Descriptions
3.1. Alternate Pin Functions
GPIO Pins are shared with dedicated Input/Output signals of on-chip peripherals. The following
table lists the available functions on each GPIO pin.
GPIO
Alternate Functions
PA0
T0OUT
IC1
ADC0
XTALP
PA1
T0CLK
OC1
ADC1
XTALN
PA2
OC0
U1RX
ADC2
COMPI00
PA3
T1OUT
ADC3
LPXTALP
PA4
T1CLK
COMPO0
ADC4
LPXTALN
PA5
IC0
U1TX
ADC5
COMPI10
PB0
U1TX
IC1
EXTIRQ0
PB1
U1RX
OC1
PB2
IC0
T2OUT
PB3
OC0
T2CLK
PB4
U0TX
T1CLK
PB5
U0RX
T1OUT
PB6
DBG_DATA
PB7
DBG_CLK
PC0
SSEL
T0OUT
EXTIRQ0
PC1
SSCK
T0CLK
COMPO1
PC2
SMOSI
U0TX
PC3
SMISO
U0RX
PR0
RSEL
PR1
RSYSCLK
PR2
RCLK
PR3
RMISO
PR4
RMOSI
PR5
RIRQ
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EXTIRQ1
DSWAKE
COMPO0
AX8052F100
9
Pin Function Descriptions
PA3/ADC3/T1OUT/LPXTALP
PA2/ADC2/OC0/U1RX/COMPI00
PA1/ADC1/T0CLK/OC1/XTALP
27
26
25
24 23
PA0/ADC0/T0OUT/IC1/XTALN
PA4/ADC4/T1CLK/COMPO0/LPXTALN
28
VDD_IO
PA5/ADC5/IC0/U1TX/COMPI10
3.2. Pinout Drawing
22
21 RESET_N
RIRQ/PR5 1
VDD_CORE 2
20 DBG_EN
RMOSI/PR4 3
19 PB7/DBG_CLK
AX8052F100
RMISO/PR3 4
18 PB6/DBG_DATA
RCLK/PR2 5
17 PB5/U0RX/T1OUT
RSEL/PR0 6
16 PB4/U0TX/T1CLK
RSYSCLK/PR1 7
8
9
10
11
12
13
14
U0TX/SMOSI/PC2
COMPO1/T0CLK/SSCK/PC1
EXTIRQ0/T0OUT/SSEL/PC0
EXTIRQ0/IC1/U1TX/PB0
OC1/U1RX/PB1
T2OUT/IC0/PB2
15 PB3/OC0/T2CLK/EXTIRQ1/DSWAKE
COMPO0/U0RX/SMISO/PC3
10
Figure 2 Pin-out drawing (Top view)
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AX8052F100
Specifications
4.
Specifications
4.1. Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device.
This is a stress rating only; functional operation of the device at these or any other conditions
above those listed in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
SYMBOL
DESCRIPTION
VDD_IO
Supply voltage
CONDITION
MIN
MAX
UNIT
-0.5
5.5
V
IDD
Supply current
100
mA
PTOT
Total power consumption
800
mW
II1
DC current into any pin
-10
10
mA
II2
DC current into pins
-100
100
mA
IO
Output Current
40
mA
Via
Input Voltage digital pins
-0.5
5.5
V
Ves
Electrostatic handling
-2000
2000
V
Tamb
Operating temperature
-40
85
°C
Tstg
Storage temperature
-65
150
°C
Tj
Junction Temperature
150
°C
HBM
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AX8052F100
11
12
Specifications
4.2.
DC Characteristics
Supplies
SYMBOL
DESCRIPTION
TAMB
CONDITION
MIN
TYP
MAX
UNIT
Operational ambient
temperature
-40
27
85
°C
VDD_IO
I/O and voltage
regulator supply voltage
1.8
3.0
3.6
V
VDDIO_R1
I/O voltage ramp for
reset activation; Note 1
Ramp starts at VDD_IO≤0.1V
0.1
V/ms
VDDIO_R2
I/O voltage ramp for
reset activation; Note 1
Ramp starts at 0.1V<VDD_IO<0.7V
3.3
V/ms
VBOUT
Brown-out Threshold
Note 2
IDEEPSLEEP
Deep Sleep current
ISLEEP256PIN
Sleep current, 256 Bytes
RAM retained
ISLEEP256
1.3
V
50
nA
Wakeup from dedicated pin
450
nA
Sleep current, 256 Bytes
RAM retained
Wakeup Timer running at 640 Hz
850
nA
ISLEEP4K
Sleep current, 4.25
kBytes RAM retained
Wakeup Timer running at 640 Hz
1.5
μA
ISLEEP8K
Sleep current, 8.25
kBytes RAM retained
Wakeup Timer running at 640 Hz
2.2
μA
IMCU
Micro-controller Running
Power consumption
All peripherals disabled
150
IVSUP
Voltage Supervisor
Run and Standby mode
85
μA
IXTALOSC
Crystal oscillator current
20 MHz
160
μA
ILFXTALOSC
Low Frequency Crystal
Oscillator current
32 kHz
700
nA
IRCOSC
Internal Oscillator
current
20 MHz
210
μA
ILPOSC
Internal Low Power
Oscillator current
10 kHz
650
nA
640 Hz
210
nA
IADC
ADC current
311 kSample/s, DMA 5 MHz
1.1
mA
μA/
MHz
Notes
1.
2.
1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset
Digital circuitry is functional down to typically 1V
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AX8052F100
Specifications
Logic
SYMBOL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
DIGITAL INPUTS
VT+
Schmitt trigger low to high
threshold point
VT-
Schmitt trigger high to low
threshold point
VIL
Input voltage, low
VIH
Input voltage, high
2.0
VIPA
Input voltage range, Port A
-0.5
VDD_IO
VIPBC
Input voltage range, Ports B, C
-0.5
5.5
V
IL
Input leakage current
-10
10
μA
RPU
Programmable Pull-Up
Resistance
VDD_IO = 3.3V
1.55
V
1.25
V
0.8
V
V
V
kΩ
65
DIGITAL OUTPUTS
IOH
P[ABC]x Output Current, high
VOH= 2.4V
8
mA
IOL
P[ABC]x Output Current, low
VOL= 0.4V
8
mA
IPROH
PRx Output Current, high
VOH= 2.4V
2
mA
IPROL
PRx Output Current, low
VOL= 0.4V
2
mA
IOZ
Tri-state output leakage current
-10
10
μA
4.3. AC Characteristics
Crystal Oscillator
SYMBOL
DESCRIPTION
fXTAL
Crystal frequency
Transconductance oscillator
gmxosc
Note 2
RINxosc
CONDITION
MIN.
TYP.
MAX.
UNIT
20
MHz
8
XTALOSCGM=0001
0.5
XTALOSCGM=0010
1.0
XTALOSCGM=1110
4.5
XTALOSCGM=1111
11.0
Input DC impedance
10
mS
kΩ
Notes
3.
During normal operation the oscillator transconductance is automatically adjusted for lowest power consumption
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AX8052F100
13
14
Specifications
Low Frequency Crystal Oscillator
SYMBOL
DESCRIPTION
fLPXTAL
Crystal frequency
gmlpxosc
RINlpxosc
CONDITION
Transconductance oscillator
MIN
TYP
MAX
UNIT
32
150
kHz
LPXOSCGM=00110
3.5
LPXOSCGM=01000
4.6
LPXOSCGM=01100
6.9
LPXOSCGM=10000
9.1
Input DC impedance
µS
MΩ
10
Internal Low Power Oscillator
SYMBOL
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
630
640
650
Hz
10.08
10.24
10.39
kHz
LPOSCFAST=0
fLPOSC
Oscillation Frequency
Factory calibration
applied.
Over the full
temperature and
voltage range
LPOSCFAST=1
Factory calibration
applied.
Over the full
temperature and
voltage range
Internal RC Oscillator
SYMBOL
FFRCOSC
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
Oscillation Frequency
Factory calibration
applied.
Over the full
temperature and
voltage range
19.8
20
20.2
MHz
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AX8052F100
Specifications
Microcontroller
SYMBOL
DESCRIPTION
CONDITION
MIN
TSYSCLKL
SYSCLK Low
27
ns
TSYSCLKH
SYSCLK High
21
ns
TSYSCLKP
SYSCLK Period
47
ns
TFLWR
FLASH Write Time
2 Bytes
TFLPE
FLASH Page Erase
1 kBytes
TFLE
FLASH Secure Erase
64 kBytes
TFLEND
FLASH Endurance: Erase Cycles
10 000
TYP
MAX
UNIT
20
µs
2
ms
10
ms
100 000
Cycles
O
TFLRETroom
FLASH Data Retention
TFLREThot
25 C
See Figure 3
for the lower
limit set by
the memory
qualification
100
85OC
See Figure 3
for the lower
limit set by
the memory
qualification
10
Years
Data retention time [years]
100000
10000
1000
100
10
15
25
35
45
55
65
75
85
o
Temperature [ C]
Figure 3 FLASH memory qualification limit for data retention after 10k erase cycles
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AX8052F100
15
16
Specifications
ADC / Comparator / Temperature Sensor
SYMBOL
DESCRIPTION
ADCSR
ADC sampling rate GPADC mode
30
ADCSR_T
ADC sampling rate temperature
sensor mode
10
ADCRES
ADC resolution
VADCREF
ADC reference voltage & comparator
internal reference voltage
ZADC00
Input capacitance
DNL
Differential nonlinearity
INL
Integral nonlinearity
OFF
Offset
GAIN_ERR
Gain error
CONDITION
MIN
TYP
15.6
MAX
UNIT
500
kHz
30
kHz
10
0.95
1
Bits
1.05
V
2.5
pF
+/- 1
LSB
+/- 1
LSB
3
LSB
0.8
%
ADC in Differential Mode
VABS_DIFF
Absolute voltages & common mode
voltage in differential mode at each
input
VFS_DIFF01
Full swing input for differential
signals
VFS_DIFF10
Gain x1
Gain x10
0
VDD_IO
V
-500
500
mV
-50
50
mV
ADC in Single Ended Mode
VMID_SE
Mid code input voltage in single
ended mode
VIN_SE00
Input voltage in single ended mode
VFS_SE01
Full swing input for single ended
signals
VFS_SE10
0.5
Gain x1
Gain x10
V
0
VDD_IO
V
0
1
V
0.45
0.55
V
Comparators
VCOMP_ABS
Comparator absolute input voltage
0
VDD_IO
V
VCOMP_COM
Comparator input common mode
0
VDD_IO0.8
V
VCOMPOFF
Comparator input offset voltage
20
mV
Temperature Sensor
TRNG
Temperature range
TRES
Temperature resolution
TERR_CAL
Temperature error
-40
85
0.1607
Factory
calibration
applied
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-2
°C
°C/LSB
+2
°C
AX8052F100
Circuit Description
5.
Circuit Description
The AX8052F100 is a single chip ultra-lowpower microcontroller primarily for use in radio
applications. The AX8052F100 contains a high speed microcontroller compatible to the industry
standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal SRAM.
The AX8052F100 features 3 16-bit general purpose timers with Σ∆ capability, 2 output compare
units for generating PWM signals, 2 input compare units to record timings of external signals, 2
16-bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a 10-bit 500
kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA
controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware
debug interface controller that connects using a 3-wire protocol (1 dedicated wire, 2 shared with
GPIO) to the PC hosting the debug software.
The system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from
one of the following clock sources: the crystal oscillator, an internal high speed 20 MHz oscillator,
an internal low speed 640 Hz/10 kHz oscillator, or the low frequency crystal oscillator. Pre-scalers
offer additional flexibility with their programmable divide by a power of two capability. To improve
the accuracy of the internal oscillators, both oscillators may be slaved to the crystal oscillator.
AX8052F100 can be operated from a 1.8 V to 3.6 V power supply over a temperature range of
-40oC to 85oC. The AX8052F100 features make it an ideal interface for integration into various
battery powered SRD solutions such as ticketing or as transceiver for telemetric applications e.g. in
sensors.
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AX8052F100
17
18
Circuit Description
5.1. Microcontroller
The AX8052F100 microcontroller core executes the industry standard 8052 instruction set. Unlike
the original 8052, many instructions are executed in a single cycle. The system clock and thus the
instruction rate can be programmed freely from DC to 20 MHz.
Memory Architecture
AES
Cache
Prefetch
AX8052
DMA
X Bus
SFR Bus
IRAM Bus
Code Bus
Arbiter
Arbiter
Arbiter
Arbiter
Arbiter
Arbiter
XRAM
XRAM
X Registers
SFR Registers
IRAM
FLASH
0000-0FFF
1000-1FFF
4000-7FFF
80-FF
00-FF
0000-FFFF
Figure 4 AX8052 Memory Architecture
The AX8052 Microcontroller features the highest bandwidth memory architecture of its class.
Figure 4 shows the memory architecture. Three bus masters may initiate bus cycles:
•
The AX8052 Microcontroller Core
•
The Direct Memory Access (DMA) Engine
•
The Advanced Encryption Standard (AES) Engine
Bus targets include:
•
Two individual 4 kBytes RAM blocks located in X address space, which can be
simultaneously accessed and individually shut down or retained during sleep mode
•
A 256 Byte RAM located in internal address space, which is always retained during sleep
mode
•
A 64 kBytes FLASH memory located in code space.
•
Special Function Registers (SFR) located in internal address space accessible using direct
address mode instructions
•
Additional Registers located in X address space (X Registers)
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AX8052F100
Circuit Description
The upper half of the FLASH memory may also be accessed through the X address space. This
simplifies and makes the software more efficient by reducing the need for generic pointers1.
SFR Registers are also accessible through X address space, enabling indirect access to SFR
registers. This allows driver code for multiple identical peripherals (such as UARTs or Timers) to be
shared.
The 4 word × 16 bit fully associative cache and a pre-fetch controller hide the latency of the
FLASH.
The AX8052 Memory Architecture is fully parallel. All bus masters may simultaneously access
different bus targets during each system clock cycle. Each bus target includes an arbiter that
resolves access conflicts. Each arbiter ensures that no bus master can be starved.
Both 4 kBytes RAM blocks may be individually retained or switched off during sleep mode. The 256
Byte RAM is always retained during sleep mode.
The AES engine accesses memory 16bits at a time. It is therefore slightly faster to align its buffers
on even addresses.
Memory Map
I (internal) Space
Address
P (Code) Space
X Space
direct access
IRAM
0000-007F
0080-00FF
XRAM
SFR
indirect access
IRAM
0100-1FFF
IRAM
2000-207F
2080-3F7F
3F80-3FFF
FLASH
SFR
4000-4FFF
RREG
5000-5FFF
RREG (nb)
6000-7FFF
XREG
8000-FBFF
FLASH
FC00-FFFF
Calibration Data
Calibration Data
Figure 5 AX8052 Memory Map
The AX8052, like the other industry standard 8052 compatible microcontrollers, uses a Harvard
architecture. Multiple address spaces are used to access code and data. Figure 5 shows the
AX8052 memory map.
1
Generic pointers include, in addition to the address, an address space tag.
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AX8052F100
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Circuit Description
The AX8052 uses P or Code Space to access its program. Code space may also be read using the
MOVC instruction.
Smaller amounts of data can be placed in the Internal 2 or Data Space. A distinction is made in the
upper half of the Data Space between direct accesses (MOV reg,addr; MOV addr,reg) and indirect
accesses (MOV reg,@Ri; MOV @Ri,reg; PUSH; POP); Direct accesses are routed to the Special Function
Registers, while indirect accesses are routed to the internal RAM.
Large amounts of data can be placed in the External or X Space. It can be accessed using the
MOVX instructions. Special Function Registers, as well as additional Microcontroller Registers
(XREG) and the Radio Registers (RREG) are also mapped into the X Space.
Detailed documentation of the Special Function Registers (SFR) and additional Microcontroller
Registers can be found in the AX8052 Programming Manual.
The Radio Registers are documented in the Programming Manual of the connected Radio chip.
Register Addresses given in the Radio chip’s Programming Manual are relative to the beginning of
RREG, i.e. 0x4000 must be added to these addresses. If an AXSEM Radio chip is connected, the
appropriate AXSEM provided ax8052f1xx.h header file should be used.
Normally, accessing Radio Registers through the RREG address range is adequate. Since Radio
Register accesses have a higher latency than other AX8052 registers, the AX8052 provides a
method for non-blocking access to the Radio Registers. Accessing the RREG (nb) address range
initiates a Radio Register access, but does not wait for its completion. The details of mechanism is
documented in the Radio Interface section of the AX8052 Programming Manual.
The FLASH memory is organized as 64 pages of 1 kBytes each. Each page can be individually
erased. The write word size is 16 Bits. The last 1 kByte page is dedicated to factory calibration
data and should not be overwritten.
2
The origin of Internal versus External (X) Space is historical. External Space used to be outside of
the chip on the original 8052 Microcontrollers.
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AX8052F100
Circuit Description
Power Management
The micro-controller supports the following power modes:
PCON
register
Name
Description
RUNNING
The microcontroller and all peripherals are running. Current consumption depends on
the system clock frequency and the enabled peripherals and their clock frequency.
STANDBY
The microcontroller is stopped. All register and memory contents are retained. All
peripherals continue to function normally. Current consumption is determined by the
enabled peripherals. STANDBY is exited when any of the enabled interrupts become
active.
10
SLEEP
The micro-controller and its peripherals, except GPIO and the system controller, are
shut down. Their register settings are lost. The internal RAM is retained. The external
RAM is split into two 4 kByte blocks. Software can determine individually for both
blocks whether contents of that block are to be retained or lost. SLEEP can be exited
by any of the enabled GPIO or system controller interrupts. For most applications this
will be a GPIO or wakeup timer interrupt.
11
DEEPSLEEP
The micro-controller, all peripherals and the transceiver are shut down. Only 4 bytes
of scratch RAM are retained. DEEPSLEEP can only be exited by tying the PB3 pin low.
00
01
Clocking
WDT
LPOSC
Calib
FRCOSC
XOSC
Glitch Free Clock Switch
FRCOSC
Calib
LPOSC
Internal Reset
Wakeup
Timer
Interrupt
Prescaler
System Clock
÷1,2,4,...
Clock
Monitor
LPXOSC
RSYSCLK
Figure 6 Clock System Diagram
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AX8052F100
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Circuit Description
The system clock can be derived from any of the following clock sources:
•
The crystal oscillator
•
The low speed crystal oscillator
•
The internal high speed RC (20 MHz) oscillator
•
The internal low power (640 Hz/10 kHz) oscillator
An additional pre-scaler allows the selected oscillator to be divided by a power of two. After reset,
the microcontroller starts with the internal high speed RC oscillator selected and divided by two.
I.e. at start-up, the micro-controller runs with 10 MHz ± 10%. Clocks may be switched any time
by writing to the CLKCON register. In order to prevent clock glitches, the switching takes
approximately 2·(T1+T2), where T1 and T2 are the periods of the old and the new clock. Switching
may take longer if the new oscillator first has to start up. Internal oscillators start up
instantaneously, but crystal oscillators may take a considerable amount of time to start the
oscillation. CLKSTAT can be read to determine the clock switching status.
A programmable clock monitor resets the CLKCON register when no system clock transitions are
found during a programmable time interval, thus reverts to the internal RC oscillator.
Both internal oscillators can be slaved to one of the crystal oscillators to increase the accuracy of
the oscillation frequency. While the reference oscillator runs, the internal oscillator is slaved to the
reference frequency by a digital frequency locked loop. When the reference oscillator is switched
off, the internal oscillator continues to run unslaved with the last frequency setting.
Reset and Interrupts
After reset, the microcontroller starts executing at address 0x0000. All registers except
SCRATCH0…SCRATCH3 are set to default values. RAM is either retained (SLEEP mode) or
undefined.
Several events can lead to resetting the micro-controller core:
•
POR or hardware RESET_N pin activated and released
•
Leaving SLEEP or DEEPSLEEP mode
•
Watchdog Reset
•
Software Reset
The reset cause can be determined by reading the PCON register.
After POR or reset all registers are set to their default values.
AX8052F100 has an integrated power-on-reset block which is edge sensitive to VDD_IO. For
many common application cases no external reset circuitry is required. However, if VDD_IO ramps
cannot be guaranteed, an external reset circuit is recommended. For detailed recommendations
and requirements see the AX8052 Application Note: Power On Reset.
The RESET_N pin contains a weak pull-up. However, it is strongly recommended to connect the
RESET_N pin to VDD_IO if not used, for additional robustness.
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AX8052F100
Circuit Description
The micro-controller supports 22 interrupt sources. Each interrupt can be individually enabled and
can be programmed to have one of two possible priorities. The interrupt vectors are located at
0x0003, 0x000B, …, 0x00AB.
Debugging
A hardware debug unit considerably eases debugging compared to other 8052 microcontrollers. It
allows to reliably stop the micro-controller at breakpoints even if the stack is smashed. The debug
unit communicates with the host PC running the debugger using a 3 wire interface. One wire is
dedicated (DBG_EN), while two wires are shared with GPIO pins (PB6, PB7). When DBG_EN is
driven high, PB6 and PB7 convert to debug interface pins and the GPIO functionality is no longer
available. A pin emulation feature however allows bits PINB[7:6] to be set and PORTB[7:6] and
DIRB[7:6] to be read by the debugger software. This allows for example switches or LEDs
connected to the PB6, PB7 pins to be emulated in the debugger software whenever the debugger is
active.
In order to protect the intellectual property of the firmware developer, the debug interface can be
locked using a developer-selectable 64-bit key. The debug interface is then disabled and can only
be enabled with the knowledge of this 64-bit key. Therefore, unauthorized persons cannot read the
firmware through the debug interface, but debugging is still possible for authorized persons.
Secure erase can be initiated without key knowledge; secure erase ensures that the main FLASH
array is completely erased before erasing the key, reverting the chip into factory state.
The DebugLink peripheral looks like an UART to the microcontroller, and allows exchange of data
between the micro-controller and the host PC without disrupting program execution.
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AX8052F100
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Circuit Description
5.2. Timer, Output Compare and Input Capture
The AX8052F100 features three general purpose 16-bit timers. Each timer can be clocked by the
system clock, any of the available oscillators, or a dedicated input pin. The timers also feature a
programmable clock inversion, a programmable prescaler that can divide by powers of two, and an
optional clock synchronisation logic that synchronises the clock to the system clock. All three
counters are identical and feature four different counting modes, as well as a Σ∆ mode that can be
used to output an analog value on a dedicated digital pin only employing a simple RC lowpass
filter.
Two output compare units work in conjunction with one of the timers to generate PWM signals.
Two input capture units work in conjunction with one of the timers to measure transitions on an
input signal.
For software timekeeping, two additional 16 bit wakeup timers with 4 16-bit event registers are
provided, generating an interrupt on match events.
5.3. UART
The AX8052F100 features two universal asynchronous receiver transmitters. They use one of the
timers as baud rate generator. Word length can be programmed from 5 to 9 bits.
5.4. Dedicated Radio SPI Master Controller
The AX8052F100 features a dedicated Radio master SPI controller. It is compatible with AXSEM
RF chips as well as some third party SPI slave devices. It features efficient access by the CPU. RF
IC registers are mapped into the CPU X address space.
5.5. SPI Master/Slave Controller
The AX8052F100 features a master/slave SPI controller. Both 3 and 4 wire SPI variants are
supported. In master mode, any of the on-chip oscillators or the system clock may be selected as
clock source. An additional pre-scaler with divide by two capability provides additional clocking
flexibility. Shift direction, as well as clock phase and inversion, are programmable.
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AX8052F100
Circuit Description
System Clock
SYSCLK
LPXOSC
XOSC
VDDIO
LPOSC
Temperature
Sensor
FRCOSC
ADCCLKSRC
5.6. ADC, Analog Comparators and Temperature Sensor
Free Running
One Shot
PA6
Timer 0
PA5
Timer 1
Prescaler
÷1,2,4,8,...
PA7
PA4
PA3
PA2
PA1
Clock
PA0
Timer 2
PC4
ADC Core
PPP
ADC Result
Ref
×0.1, ×1, ×10
Gain
ADCCONV
Trigger
VREF
1V
0.5V
Single Ended
NNN
ACOMP0IN
ACOMP0REF
ACOMP0ST/PA4/PC3
ACOMP0INV
System Clock
ACOMP1IN
ACOMP1REF
ACOMP1ST/PA7/PC1
ACOMP1INV
Figure 7 ADC Block Diagram
The AX8052F100 features a 10-bit, 500 kSample/s Analog to Digital converter. The ADC supports
both single ended and differential measurements. It uses an internal reference of 1 V. ×1, ×10
and ×0.1 gain modes are provided. The ADC may digitize signals on PA0…PA7, as well as VDD_IO
and an internal temperature sensor. The user can define four channels which are then converted
sequentially and stored in four separate result registers. Each channel configuration consists of the
multiplexer and the gain setting.
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AX8052F100
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Circuit Description
The AX8052F100 contains an on-chip temperature sensor. Built-in calibration logic allows the
temperature sensor to be calibrated in °C, °F or any other user defined temperature scale.
The AX8052F100 also features two analog comparators. Each comparator can either compare two
voltages on dedicated PA pins, or one voltage against the internal 1 V reference. The comparator
output can be routed to a dedicated digital output pin or can be read by software. The comparators
are clocked with the system clock.
5.7. DMA Controller
The AX8052F100 features a dual channel DMA engine. Each DMA channel can either transfer data
from XRAM to almost any peripheral on chip, or from almost any peripheral to XRAM. Both
channels may also be cross-linked for memory-memory transfers. The DMA channels use buffer
descriptors to find the buffers where data is to be retrieved or placed, thus enabling very flexible
buffering strategies.
The DMA channels access XRAM in a cycle steal fashion. They access XRAM whenever XRAM is not
used by the micro-controller. Their priority is lower than the micro-controller, thus interfering very
little with the micro-controller. Additional logic prevents starvation of the DMA controller.
5.8. AES Engine
The AX8052F100 contains a dedicated engine for the government mandated Advanced Encryption
Standard (AES). It features a dedicated DMA engine and reads input data as well as key stream
data from the XRAM, and writes output data into a programmable buffer in the XRAM. The round
number is programmable; the chip therefore supports AES-128, AES-192, and AES-256, as well as
higher security proprietary variants. Key stream (key expansion) is performed in software, adding
to the flexibility of the AES engine. ECB (electronic codebook), CFB (cipher feedback) and OFB
(output feedback) modes are directly supported without software intervention. In conjunction with
the true random number generator a high degree of security can be achieved.
5.9. Crystal Oscillator
The on-chip crystal oscillator allows the use of an inexpensive quartz crystal as timing reference.
Normally, the oscillator operates fully automatically. It is powered on whenever the system clock
or any peripheral clock is programmed to be derived from the crystal clock. To hide crystal startup
latencies, the oscillator may also be forced on using the OSCFORCERUN register.
The transconductance of the oscillator is automatically controlled to ensure fast startup and low
steady state current consumption. For lowest phase noise applications, transconductance may be
programmed manually using the XTALOSC register.
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AX8052F100
Circuit Description
5.10. Ports
VDDIO
PORTx.y
65 kΩ
DIRx.y
Special Function
PALTx.y
INTCHGx.y
Interrupt
PINx.y
PINx read clock
ANALOGx.y
Figure 8 Port Pin Schematic
Figure 8 shows the GPIO logic. The DIR register bit determines whether the port pin acts as an
output (1) or an input (0).
If configured as an output, the PALT register bit determines whether the port pin is connected to a
peripheral output (1), or used as a GPIO pin (0). In the latter case, the PORT register bit
determines the port pin drive value.
If configured as an input, the PORT register bit determines whether a pull-up resistor is enabled
(1) or disabled (0). Inputs have schmitt-trigger characteristic. Port A inputs may be disabled by
setting the ANALOGA register bit; this prevents additional current consumption if the voltage level
of the port pin is mid-way between logic low and logic high, when the pin is used as an analog
input.
Port A, B and C pins may interrupt the microcontroller if their level changes. The INTCHG register
bit enables the interrupt. The PIN register bit reflects the value of the port pin. Reading the PIN
register also resets the interrupt if interrupt on change is enabled.
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AX8052F100
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Application Information
6.
Application Information
6.1. Typical Application Diagram
Figure 9 Typical Application Diagram
Figure 9 shows a typical application schematic.
Short Jumper JP1-1 if it is desired to supply the target board from the Debug Adapter (50mA
max). Connect the bottom exposed pad of the AX8052F100 to ground.
If the debugger is not running, PB6 and PB7 are not driven by the Debug Adapter. If the debugger
is running, the PB6 and PB7 values the software reads may be set using the Pin Emulation feature
of the debugger.
PB3 is driven by the debugger only to bring the AX8052F100 out of Deep Sleep. It is high
impedance otherwise.
Port Pins PR0—PR5 may be used to connect an AXSEM Radio Chip, or as General Purpose I/O.
Crystals are optional. Crystal Load Capacitances should be chosen according to the Crystal
Datasheet.
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AX8052F100
QFN28 Package Information
7.
QFN28 Package Information
7.1. Package Outline QFN28
ON
AX8052F100-V
AWLYYWW
DIMENSION
MIN
TYP
MAX
UNIT
A
0.800
0.850
0.900
mm
Notes
1.
2.
3.
4.
5.
6.
7.
8.
JEDEC ref MO-220
All dimensions are in millimetres
Pin 1 is identified by chamfer on corner of exposed
die pad.
Package warp shall be 0.050 maximum
Coplanarity applies to the exposed pad as well as
the terminal
AWLYYWW is the packaging lot code
V is the device version
RoHS
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AX8052F100
29
QFN28 Package Information
7.2. QFN28 Soldering Profile
Preheat
Reflow
Cooling
tp
Tp
Temperature
30
T
tL
L
TsMAX
TsMIN
ts
25°C
t25° to Peak
Time
Profile Feature
Pb-Free Process
Average Ramp-Up Rate
3 °C/sec max.
Preheat Preheat
Temperature Min
TsMIN
150°C
Temperature Max
TsMAX
200°C
Time (TsMIN to TsMAX)
ts
60 – 180 sec
Time 25°C to Peak Temperature
T25 ° to Peak
8 min max.
Liquidus Temperature
TL
217°C
Time over Liquidus Temperature
tL
60 – 150 sec
Peak Temperature
tp
260°C
Time within 5°C of actual Peak
Temperature
Tp
20 – 40 sec
Reflow Phase
Cooling Phase
Ramp-down rate
6°C/sec max.
Notes:
All temperatures refer to the top side of the package, measured on the package body surface.
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AX8052F100
QFN28 Package Information
7.3. QFN28 Recommended Pad Layout
1.
PCB land and solder masking recommendations are shown in Figure 10.
A=
Clearance from PCB thermal pad to solder mask opening,
0.0635 mm minimum
B = Clearance from edge of PCB thermal pad to PCB land, 0.2
mm minimum
C = Clearance from PCB land edge to solder mask opening to be
as tight as possible to ensure that some solder mask remains
between PCB pads
D = PCB land length = QFN solder pad length + 0.1mm
E = PCB land width = QFN solder pad width + 0.1 mm
Figure 10 PCB land and solder mask recommendations
2.
3.
Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal
conductivity from the device to a copper ground plane area on the reverse side of the printed
circuit board. The number of vias depends on the package thermal requirements, as
determined by thermal simulation or actual testing.
Increasing the number of vias through the printed circuit board will improve the thermal
conductivity to the reverse side ground plane and external heat sink. In general, adding more
metal through the PC board under the IC will improve operational heat transfer, but will
require careful attention to uniform heating of the board during assembly.
7.4. Assembly Process
Stencil Design & Solder Paste Application
1.
Stainless steel stencils are recommended for solder paste application.
2.
A stencil thickness of 0.125 – 0.150 mm (5 – 6 mils) is recommended for screening.
3.
For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil
with an array of smaller openings that sum to 50% of the QFN exposed pad area. Solder
paste should be applied through an array of squares (or circles) as shown in Figure 11.
4.
The aperture opening for the signal pads should be between 50-80% of the QFN pad area as
shown in Figure 12.
5.
Optionally, for better solder paste release, the aperture walls should be trapezoidal and the
corners rounded.
6.
The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit
board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to
application of the solder paste.
7.
No-clean flux is recommended since flux from underneath the thermal pad will be difficult to
clean if water-soluble flux is used.
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AX8052F100
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QFN28 Package Information
Figure 11 Solder paste application on exposed pad
Minimum
50% coverage
62% coverage
Maximum
80% coverage
Figure 12 Solder paste application on pins
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AX8052F100
References
8.
References
[1]
ON Semiconductor AX8052 Programming Manual, see http://www.onsemi.com
[2]
ON Semiconductor AX8052 Silicon Errata, see http://www.onsemi.com
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AX8052F100
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Device Versions
9.
Device Versions
The revision of the AX8052 silicon can be determined by the device marking or by
reading the SILICONREV register. [2] documents the differences between silicon
revisions.
SILICONREV
Device Marking
AX8052 Version
AX8052F100-1
1
0x8E (10001110)
AX8052F100-2
1C
0x8F (10001111)
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AX8052F100
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