ISSI IS61WV5128ALL/ALS 512k x 8 high-speed asynchronous cmos static ram Datasheet

IS61WV5128ALL/ALS
IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
512K x 8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM
AUGUST 2009
FEATURES
HIGH SPEED: (IS61/64WV5128ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low stand-by power: 7 mW (typical)
CMOS standby
LOW POWER: (IS61/64WV5128ALS/BLS)
• High-speed access time: 25, 35 ns
• Low Active Power: 35 mW (typical)
• Low stand-by power: 0.6 mW (typical)
CMOS standby
• Single power supply
— Vdd 1.65V to 2.2V (IS61WV5128Axx)
— Vdd 2.4V to 3.6V (IS61/64WV5128Bxx)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Industrial and Automotive temperature support
• Lead-free available
DESCRIPTION
The ISSI IS61WV5128Axx and IS61/64WV5128Bxx
are very high-speed, low power, 524,288-word by
8-bit CMOS static RAMs. The IS61WV5128Axx and
IS61/64WV5128Bxx are fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CE is HIGH (deselected), the device assumes
a standby mode at which the power dissipation can be
reduced down with CMOS input levels.
The IS61WV5128Axx and IS61/64WV5128Bxx operate
from a single power supply.
The IS61WV5128ALL and IS61/64WV5128BLL are available in 36-pin 400-mil SOJ, 36-pin mini BGA, and 44-pin
TSOP (Type II) packages.
The IS61WV5128ALS and IS61/64WV5128BLS are
available in 32-pinTSOP (Type I), 32-pin sTSOP (Type I),
32-pin SOP and 32-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
1
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (HIGH SPEED) (61/64WV5128ALL/BLL)
44-Pin TSOP (Type II)
36 mini BGA
1
2
3
4
5
6
A
A0
A1
NC
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
NC
A5
C
I/O5
D
GND
VDD
E
VDD
GND
F
I/O6
G
I/O7
H
A9
2
I/O2
A18
A17
OE
CE
A16
A15
I/O3
A10
A11
A12
A13
A14
PIN DESCRIPTIONS
A0-A18
CE OE WE I/O0-I/O7
Vdd
GND
NC
I/O1
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
No Connection
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
36-Pin SOJ
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
CE
6
31
OE
I/O0
7
30
I/O7
I/O1
8
29
I/O6
VDD
9
28
GND
GND
10
27
VDD
I/O2
11
26
I/O5
I/O3
12
25
I/O4
WE
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
PIN CONFIGURATION (LOW POWER) (61/64WV5128ALS/BLS)
32-pin TSOP (TYPE I), (Package Code T)
32-pin sTSOP (TYPE I) (Package Code H)
A11
A9
A8
A13
WE
A18
A15
VDD
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
32-pin SOP
32-pin TSOP (TYPE II)
(Package Code T2)
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A18
CE
OE WE I/O0-I/O7
Vdd
GND
Address Inputs
Chip Enable 1 Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
3
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min., Ioh = –4.0 mA
Output LOW Voltage
Vdd = Min., Iol = 8.0 mA
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
Vdd + 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol Parameter
Test Conditions
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
Vol
Output LOW Voltage
Vdd = Min., Iol = 1.0 mA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage(1)
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width <10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min, Ioh = -0.1 mA
Output LOW Voltage
Vdd = Min, Iol = 0.1 mA
Input HIGH Voltage
Input LOW Voltage
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
Vdd + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width <10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width <10 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
TRUTH TABLE
Mode
WE
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
CE
H
OE
X
L
L
L
H
L
X
I/O Operation Vdd Current
High-Z
Isb1, Isb2
High-Z
Dout
Din
Icc
Icc
Icc
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vterm
Vdd
Tstg
Pt
Parameter
Terminal Voltage with Respect to GND
Vdd Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to Vdd + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Cin
CI/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
5
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
HIGH SPEED (IS61WV5128ALL/BLL)
OPERATING RANGE (Vdd) (IS61WV5128ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
20ns
20ns
20ns
OPERATING RANGE (Vdd) (IS61WV5128BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (8 ns)1
3.3V + 5%
3.3V + 5%
Vdd (10 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%,
the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV5128BLL)
Range
Automotive
Ambient Temperature
–40°C to +125°C
Vdd (10 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
50
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
55
Auto.
—
—
typ.(2)
Icc1
Operating
Vdd = Max.,
Com.
—
35
Supply Current
Iout = 0 mA, f = 0
Ind.
—
40
Auto.
—
—
Isb1
TTL Standby Current
Vdd = Max.,
Com.
—
10
(TTL Inputs)
Vin = Vih or Vil
Ind.
—
15
CE ≥ Vih, f = 0
Auto.
—
—
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
7
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
10
Vin ≥ Vdd – 0.2V, or
Auto.
—
—
Vin ≤ 0.2V, f = 0
typ.(2)
-10
Min. Max.
—
40
—
45
—
65
25
—
35
—
40
—
60
—
10
—
15
—
30
—
7
—
10
—
20
2
-20
Min. Max.
Unit
—
40
mA
—
45
—
65
—
—
—
—
—
—
—
—
—
30
mA
40
60
10
mA
15
30
7
mA
10
20
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
LOW POWER (IS61WV5128ALS/BLS)
OPERATING RANGE (Vdd) (IS61WV5128ALS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
35ns
35ns
35ns
OPERATING RANGE (Vdd) (IS61WV5128BLS)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd
2.4V-3.6V
2.4V-3.6V
Speed
25 ns
25 ns
OPERATING RANGE (Vdd) (IS64WV5128BLS)
Range
Automotive
Ambient Temperature
–40°C to +125°C
Vdd
2.4V-3.6V
Speed
35 ns
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
Symbol Parameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max.,
Com.
—
20
Supply Current
Iout = 0 mA, f = fmax
Ind.
—
25
Auto.
—
50
typ.(2)
11
Icc1
Operating
Vdd = Max.,
Com.
—
10
Supply Current
Iout = 0 mA, f = 0
Ind.
—
12
Auto.
—
20
TTL Standby Current
Vdd = Max.,
Com.
—
5
Isb1
(TTL Inputs)
Vin = Vih or Vil
Ind.
—
7
CE ≥ Vih, f = 0
Auto.
—
10
Isb2
CMOS Standby
Vdd = Max.,
Com.
—
1
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
2
Vin ≥ Vdd – 0.2V, or
Auto.
—
10
Vin ≤ 0.2V, f = 0
typ.(2)
0.2
-35
Min. Max.
Unit
—
20
mA
—
25
—
50
—
—
—
—
—
—
—
—
—
10
mA
12
20
5
mA
7
10
1
mA
2
10
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
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Rev. I
08/10/09
7
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0V to 3V
1V/ ns
1.5V
Unit
(3.3V + 10%)
0V to 3V
1V/ ns
1.5V
Unit
(1.65V-2.2V)
0V to 1.8V
1V/ ns
0.9V
See Figures 1 and 2
See Figures 1 and 2
See Figures 1 and 2
AC TEST LOADS
319 Ω
ZO = 50Ω
1.5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
8
3.3V
50Ω
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
trc
Read Cycle Time
taa
Address Access Time
toha
Output Hold Time
tace
CE Access Time
tdoe
OE Access Time
thzoe(2)
OE to High-Z Output
(2)
tlzoe
OE to Low-Z Output
thzce(2
CE to High-Z Output
tlzce(2)
CE to Low-Z Output
tpu
Power Up Time
tpd
Power Down Time
Min.
8
—
2.0
—
—
—
0
0
3
0
—
-8
Max.
—
8
—
8
4.5
3
—
3
—
—
8
-10
Min. Max.
10
—
—
10
2.0
—
—
10
—
4.5
—
4
0
—
0
4
3
—
0
—
—
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
9
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tace
tdoe
thzoe(2)
tlzoe(2)
thzce(2
tlzce(2)
tpu
tpd
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
Power Up Time
Power Down Time
-20 ns -25 ns
Min. Max.
Min. Max.
20 —
25 —
— 20
— 25
2.5 —
4 —
— 20
— 25
— 8
— 12
0 8
0 8
0 —
0 —
0 8
0 8
3 —
10 —
0 —
0 —
— 20
— 25
-35 ns
Min. Max.
35 —
— 35
4 —
— 35
— 15
0 10
0 —
0 10
10 —
0 —
— 35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil)
t RC
ADDRESS
t AA
t OHA
DOUT
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t LZCE
DOUT
t ACE
HIGH-Z
t HZCE
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
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Rev. I
08/10/09
11
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8
Symbol
twc
tsce
taw
tha
tsa
tpwe1
tpwe2
tsd
thd
thzwe(2)
tlzwe(2)
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width (OE = HIGH)
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
Min.
8
6.5
6.5
Max.
—
—
—
0
0
6.5
8.0
5
0
—
2
—
—
—
—
—
—
3.5
—
-10
Min.
10
8
8
0
0
8
10
6
0
—
2
Max.
—
—
—
Unit
ns
ns
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—­ns
5
ns
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one
can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that
terminates the write. Shaded area product in development
12
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Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwe1
tpwe2
tsd
thd
thzwe(3)
tlzwe(3)
-20 ns-25 ns-35 ns
Parameter Min. Max.
Min. Max.
Min. Max.
Write Cycle Time 20 —
25 —
35 —
CE to Write End 12 —
18 —
25 —
Address Setup Time 12 —
15 —
25 —
to Write End
Address Hold from Write End
0 —
0 —
0 —
Address Setup Time
0 —
0 —
0 —
WE Pulse Width (OE = HIGH) 12 —
18 —
30 —
WE Pulse Width (OE = LOW) 17 —
20 —
30 —
Data Setup to Write End
9 —
12 —
15 —
Data Hold from Write End
0 —
0 —­0 —
WE LOW to High-Z Output
WE HIGH to Low-Z Output
— 9
3 —
— 12
5 —
— 20
5 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions for IS61WV6416LL assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse
levels of 0.4V to Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
13
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
WRITE CYCLE NO. 2(1,2) (WE Controlled: OE is HIGH During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > Vih.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
15
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
HIGH SPEED (IS61WV5128ALL/BLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
Parameter
Test Condition
Options
Min.
Typ.(1)
Vdr
Vdd for Data Retention
See Data Retention Waveform
2.0
—
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
Com.
—
2
Ind.
—
—
Auto.
tsdr
Data Retention Setup Time See Data Retention Waveform
0
—
trdr
Recovery Time
See Data Retention Waveform
trc
—
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Max. Unit
3.6
V
6
mA
8
15
—
ns
—
ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
Parameter
Test Condition
Options
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Com.
Ind.
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Min.
1.2
—
—
0
trc
Typ.(1)
—
2
—
—
—
Max.
3.6
6
8
—
—
Unit
V
mA
ns
ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
16
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
LOW POWER (IS61WV5128ALS/BLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol
Parameter
Test Condition
Options
Min.
Typ.(1)
Vdr
Vdd for Data Retention
See Data Retention Waveform
2.0
—
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
Com.
—
0.2
Ind.
—
—
Auto.
tsdr
Data Retention Setup Time See Data Retention Waveform
0
—
trdr
Recovery Time
See Data Retention Waveform
trc
—
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Max. Unit
3.6
V
1
mA
2
10
—
ns
—
ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol
Parameter
Test Condition
Options
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
Com.
Ind.
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Min.
1.2
—
—
0
trc
Typ.(1)
—
0.2
—
—
—
Max.
3.6
1
2
—
—
Unit
V
mA
ns
ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
CE ≥ VDD - 0.2V
17
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
ORDERING INFORMATION (HIGH SPEED)
Commercial Range: 0°C to +70°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10 (81)
Order Part No.
IS61WV5128BLL-10TL
Package
TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10 (81)
Order Part No.
IS61WV5128BLL-10BI
IS61WV5128BLL-10BLI
IS61WV5128BLL-10TI
IS61WV5128BLL-10TLI
IS61WV5128BLL-10KLI
Package
36-ball mini BGA (6mm x 8mm)
36-ball mini BGA (6mm x 8mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
400-mil Plastic SOJ, Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
20
Order Part No.
IS61WV5128ALL-20BI
IS61WV5128ALL-20TI
Package
36-ball mini BGA (6mm x 8mm)
TSOP (Type II)
Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
Order Part No.
10
IS64WV5128BLL-10BA3
IS64WV5128BLL-10BLA3
IS64WV5128BLL-10CTA3
IS64WV5128BLL-10CTLA3
18
Package
36-ball mini BGA (6mm x 8mm)
36-ball mini BGA (6mm x 8mm), Lead-free
TSOP (Type II), Copper Leadframe
TSOP (Type II), Copper Leadframe
Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
ORDERING INFORMATION (LOW POWER)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
25
Order Part No.
IS61WV5128BLS-25TLI
Package
TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
19
20
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.
3. Dimension b2 does not include dambar protrusion/intrusion.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
12/20/2007
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
21
22
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
23
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
24
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
IS61WV5128ALL/ALS, IS61WV5128BLL/BLS
IS64WV5128BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. I
08/10/09
25
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