IDT ICS8543I Four differential lvds output pair Datasheet

Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
ICS8543I
DATA SHEET
General Description
Features
The ICS8543I is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential
Signaling (LVDS) the ICS8543I provides a low power, low noise, solution for distributing clock signals over controlled impedances of
100. The ICS8543I has two selectable clock inputs. The CLK,
nCLK pair can accept most standard differential input levels. The
PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
•
•
•
Four differential LVDS output pairs
•
PCLK/nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
•
•
Maximum output frequency: 650MHz
•
•
•
•
•
•
•
Additive phase Jitter, RMS: 0.164ps (typical)
Guaranteed output and part-to-part skew characteristics make the
ICS8543I ideal for those applications demanding well defined performance and repeatability.
Block Diagram
Selectable differential CLK/nCLK or LVPECL clock inputs
CLK/nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
Output skew: 40ps (maximum)
Part-to-part skew: 600ps (maximum)
Propagation delay: 2.6ns (maximum)
Full 3.3Vsupply mode
-40°C to 85°C ambient operating temperature
Available in lead-free packages
Pin Assignment
CLK_EN Pullup
Q0
nQ0
GND
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
Q1
nQ1
OE
GND
VDD
D
Q
LE
CLK Pulldown
nCLK Pullup
00
PCLK Pulldown
nPCLK Pullup
1
1
CLK_SEL Pulldown
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDD
Q1
nQ1
Q2
nQ2
GND
Q3
nQ3
Q2
nQ2
ICS8543I
Q3
nQ3
6.5mm x 4.4mm x 0.925mm
20-Lead TSSOP
OE Pullup
ICS8543BGI REVISION E NOVEMBER 15, 2012
package body
G Package
Top View
1
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
Name
1, 9, 13
GND
Power
Type
Description
2
CLK_EN
Input
Pullup
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
3
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects PCLK/nPCLK inputs.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
4
CLK
Input
Pulldown
Non-inverting differential clock input.
5
nCLK
Input
Pullup
6
PCLK
Input
Pulldown
7
nPCLK
Input
Pullup
Inverting differential LVPECL clock input.
8
OE
Input
Pullup
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
10, 18
VDD
Power
Positive supply pins.
11, 12
nQ3, Q3
Output
Differential output pair. LVDS interface levels.
14, 15
nQ2, Q2
Output
Differential output pair. LVDS interface levels.
16, 17
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
19, 20
nQ0, Q0
Output
Differential output pair. LVDS interface levels.
Power supply ground.
Inverting differential clock input.
Non-inverting differential LVPECL clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
ICS8543BGI REVISION E NOVEMBER 15, 2012
Test Conditions
2
Minimum
Typical
Maximum
Units
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
CLK_EN
CLK_SEL
0
X
X
1
0
0
1
0
1
1
Selected Source
Q0:Q3
nQ0:nQ3
Hi-Z
Hi-Z
CLK/nCLK
Disabled; Low
Disabled; High
1
PCLK/nPCLK
Disabled; Low
Disabled; High
1
0
CLK/nCLK
Enabled
Enabled
1
1
PCLK/nPCLK
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Enabled
Disabled
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0:nQ3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK or PCLK
nCLK or nPCLK
Q[0:3]
nQ[0:3]
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non-Inverting
1
0
HIGH
LOW
Differential to Differential
Non-Inverting
0
Biased; NOTE 1
LOW
HIGH
Single-Ended to Differential
Non-Inverting
1
Biased; NOTE 1
HIGH
LOW
Single-Ended to Differential
Non-Inverting
Biased; NOTE 1
0
HIGH
LOW
Single-Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single-Ended to Differential
Inverting
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
73.2C/W (0 lfpm)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VDD
Positive Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
50
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
IIL
Input Low Current
OE, CLK_EN
VDD = VIN = 3.465V
5
µA
CLK_SEL
VDD = VIN = 3.465V
150
µA
OE, CLK_EN
VDD = 3.465V, VIN = 0V
-150
µA
CLK_SEL
VDD = 3.465V, VIN = 0V
-5
µA
Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
0.5
VDD – 0.85
V
CLK
VDD = VIN = 3.465V
150
µA
nCLK
VDD = VIN = 3.465V
5
µA
CLK
VDD = 3.465V, VIN = 0V
-5
µA
nCLK
VDD = 3.465V, VIN = 0V
-150
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
0.3
1
V
VCMR
Common Mode Input Voltage;
NOTE 1, 2
1.5
VDD
V
PCLK
VDD = VIN = 3.465V
150
µA
nPCLK
VDD = VIN = 3.465V
5
µA
PCLK
VDD = 3.465V, VIN = 0V
-5
µA
nPCLK
VDD = 3.465V, VIN = 0V
-150
µA
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4E. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOD
Differential Output Voltage
200
280
360
mV
VOD
VOD Magnitude Change
0
40
mV
VOS
Offset Voltage
1.25
1.375
V
VOS
VOS Magnitude Change
5
25
mV
IOz
High Impedance Leakage
-10
+10
µA
IOFF
Power Off Leakage
-20
±1
+20
µA
IOSD
Differential Output Short Circuit
Current
-3.5
-5
mA
IOS
Output Short Circuit Current
-3.5
-5
mA
VOH
Output Voltage High
1.34
1.6
V
VOL
Output Voltage Low
1.125
0.9
1.06
Minimum
Typical
V
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Maximum Output Frequency
Test Conditions
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tPD
Propagation Delay; NOTE 1
2.6
ns
tsk(o)
Output Skew; NOTE 2, 4
40
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
600
ps
t R / tF
Output Rise/Fall Time
450
ps
odc
Output Duty Cycle
55
%
153.6MHz, Integration
Range: 12kHz – 20MHz
ƒ  650MHz
20% to 80% @ 50MHz
odc
Maximum
Units
650
MHz
0.164
1.5
150
45
50
ps
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output crosspoints.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 153.6MHz
12kHz to 20MHz = 0.164ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
ICS8543BGI REVISION E NOVEMBER 15, 2012
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information
VDD
SCOPE
Qx
VDD
3.3V±5%
POWER SUPPLY
+ Float GND –
nCLK,
nPCLK
V
Cross Points
PP
V
CMR
CLK,
PCLK
nQx
GND
3.3V LVDS Output Load AC Test Circuit
Differential Input Level
VDD
nQx
Qx
nQ[0:3]
V
Cross Points
OD
nQy
Q[0:3]
Qy
V
tsk(o)
OS
GND
Differential Output Level
Output Skew
nCLK,
nPCLK
Par t 1
nQx
CLK,
PCLK
Qx
nQy
Par t 2
nQ[0:3]
Q[0:3]
Qy
tPD
tsk(pp)
Part-to-Part Skew
ICS8543BGI REVISION E NOVEMBER 15, 2012
Propagation Delay
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
nQ[0:3]
Q[0:3]
nQ[0:3]
80%
80%
t PW
VOD
t
PERIOD
20%
20%
Q[0:3]
tF
tR
odc =
t PW
x 100%
t PERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
VDD
VDD
out
out
DC Input
LVDS
DC Input
out
LVDS
100
VOS/Δ VOS
out
ä
Offset Voltage Setup
Differential Output Voltage Setup
VDD
out
➤
3.3V±5% POWER SUPPLY
+
Float GND
_
out
IOZ
DC Input
LVDS
DC Input
➤
➤
LVDS
IOSD
out
IOZ
out
High Impedance Leakage Current Setup
ICS8543BGI REVISION E NOVEMBER 15, 2012
Differential Output Short Circuit Setup
8
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Parameter Measurement Information, continued
VDD
➤
out
DC Input
IOS
LVDS
LVDS
➤
➤
IOSB
out
VDD
IOFF
Output Short Circuit Current Setup
Power Off Leakage Setup
Applications Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and VCMR
input requirements. Figures 3A to 3F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 3A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
Zo = 50Ω
nCLK
nCLK
Differential
Input
LVHSTL
R1
50Ω
IDT
LVHSTL Driver
R2
50Ω
Differential
Input
LVPECL
R1
50Ω
R2
50Ω
R2
50Ω
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100Ω
Zo = 50Ω
nCLK
Differential
Input
LVPECL
R1
84Ω
R2
84Ω
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
2.5V
3.3V
3.3V
2.5V
*R3
33Ω
R3
120Ω
Zo = 50Ω
R4
120Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33Ω
R1
50Ω
R2
50Ω
Differential
Input
SSTL
R1
120Ω
R2
120Ω
Differential
Input
*Optional – R3 and R4 can be 0Ω
Figure 3F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the S
PCLK/nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
3.3V
R1
50Ω
3.3V
Zo = 50Ω
R2
50Ω
Zo = 50Ω
PCLK
R1
100Ω
PCLK
Zo = 50Ω
nPCLK
Zo = 50Ω
nPCLK
CML
LVPECL
Input
CML Built-In Pullup
LVPECL
Input
Figure 4B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 4A. PCLK/nPCLK Input Driven by a
CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125Ω
3.3V
R4
125Ω
3.3V
Zo = 50Ω
R3
84
3.3V LVPECL
PCLK
Zo = 50Ω
C1
Zo = 50Ω
C2
R4
84
PCLK
Zo = 50Ω
nPCLK
nPCLK
LVPECL
Input
LVPECL
R1
84Ω
R2
84Ω
R5
100 - 200
R6
100 - 200
R1
125
LVPECL
Input
R2
125
Figure 4D. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 4C. PCLK/nPCLK Input Driven by a
3.3V LVPECL Driver
2.5V
3.3V
2.5V
R3
120
3.3V
R4
120
3.3V
Zo = 50Ω
Zo = 60Ω
PCLK
PCLK
R1
100Ω
Zo = 60Ω
nPCLK
SSTL
R1
120
R2
120
LVPECL
Input
Zo = 50Ω
Figure 4F. PCLK/nPCLK Input Driven by a
3.3V LVDS Driver
Figure 4E. PCLK/nPCLK Input Driven by an
SSTL Driver
ICS8543BGI REVISION E NOVEMBER 15, 2012
nPCLK
LVPECL
Input
LVDS
11
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVDS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
PCLK/nPCLK Inputs
For applications not requiring the use of the differential input, both
PCLK and nPCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from PCLK to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 5A can be used
with either type of output structure. Figure 5B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO  ZT
ZT
LVDS
Receiver
Figure 5A. Standard Termination
LVDS
Driver
ZO  ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 5B. Optional Termination
LVDS Termination
ICS8543BGI REVISION E NOVEMBER 15, 2012
12
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8543I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8543I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 73.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.173W * 73.2°C/W = 97.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (single layer or multi-layer).
Table 6. Thermal Resitance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
Transistor Count
The transistor count for ICS8543I is: 636
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
Symbol
N
A
A1
A2
b
c
D
E
E1
e
L

aaa
All Dimensions in Millimeters
Minimum
Maximum
20
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40
6.60
6.40 Basic
4.30
4.50
0.65 Basic
0.45
0.75
0°
8°
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8543BGI REVISION E NOVEMBER 15, 2012
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©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8543BGILF
8543BGILFT
Marking
ICS8543BGILF
ICS8543BGILF
Package
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
Shipping Packaging
Tube
Tape & Reel
Temperature
-40C to 85C
-40C to 85C
NOTE: "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS8543BGI REVISION E NOVEMBER 15, 2012
15
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
3
Updated Figure 1, CLK_EN Timing Diagram.
10/17/01
A
3
Updated Figure 1, CLK_EN Timing Diagram.
11/2/01
A
1
6 - 10
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
5/6/02
Features - deleted bullet "Designed to meet or exceed the requirements of
ANSI TIA/EIA-644".
LVDS Table - changed VOD typical value from 350mV to 280mV.
9/19/02
1
B
4E
5
T2
2
4
9
10
11
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
Updated format throughout data sheet.
1/5/04
T4B
1
3
4
2/27/08
T9
10
11
12
13
15
Features section - added lead-free bullet.
Updated Figure 1, CLK_EN Timing Diagram.
LVCMOS DC Characteristics Table - corrected typo in VIH max. from
VDD - 0.3V to VDD + 0.3V.
Updated Differential Clock Input Interface section.
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
Ordering Information Table - added lead-free Part/Order Number, Marking and note.
Updated format throughout the datasheet.
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Plot.
Parameter Measurement Information - updated Output Rise/Fall Time diagram.
9/9/08
Updated format throughout the datasheet.
Deleted HiPerClockS references throughout.
Updated figure 4D.
Updated LVDS Driver Termination section.
Deleted quantity from Tape & Reel.
10/8/12
Removed leaded orderable parts from the Ordering Information table
11/15/12
C
D
E
T5
T9
All
1, 10, 11
11
12
15
T9
15
E
E
1
6
7
9
ICS8543BGI REVISION E NOVEMBER 15, 2012
16
©2012 Integrated Device Technology, Inc.
ICS8543I Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
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