® OPA124 OPA 124 Low Noise Precision Difet ® OPERATIONAL AMPLIFIER FEATURES APPLICATIONS ● LOW NOISE: 6nV/√Hz (10kHz) ● LOW BIAS CURRENT: 1pA max ● PRECISION PHOTODIODE PREAMP ● MEDICAL EQUIPMENT ● LOW OFFSET: 250µV max ● LOW DRIFT: 2µV/°C max ● HIGH OPEN-LOOP GAIN: 120dB min ● OPTOELECTRONICS ● DATA ACQUISITION ● TEST EQUIPMENT ● HIGH COMMON-MODE REJECTION: 100dB min ● AVAILABLE IN 8-PIN PLASTIC DIP AND 8-PIN SOIC PACKAGES Substrate +VCC 8 7 DESCRIPTION The OPA124 is a precision monolithic FET operational amplifier using a Difet (dielectrical isolation) manufacturing process. Outstanding DC and AC performance characteristics allow its use in the most critical instrumentation applications. Bias current, noise, voltage offset, drift, open-loop gain, common-mode rejection and power supply rejection are superior to BIFET and CMOS amplifiers. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. This cascode design also allows high precision input specifications and reduced susceptibility to flicker noise. Laser trimming of thinfilm resistors gives very low offset and drift. Compared to the popular OPA111, the OPA124 gives comparable performance and is available in an 8-pin PDIP and 8-pin SOIC package. –In 2 +In 3 Noise-Free Cascode(2) Output 6 Trim(1) 10kΩ 1 Trim(1) 10kΩ 2kΩ 2kΩ 2kΩ 2kΩ 5 OPA124 Simplified Circuit –V CC 4 NOTES: (1) Omitted on SOIC. (2) Patented. BIFET® National Semiconductor Corp., Difet ® Burr-Brown Corp. International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1993 Burr-Brown Corporation SBOS028 PDS-1203C 1 OPA124 Printed in U.S.A. March, 1998 SPECIFICATIONS ELECTRICAL At VCC = ±15VDC and TA = +25°C, unless otherwise noted. OPA124U, P PARAMETER CONDITION MIN MAX 80 40 15 8 1.2 3.3 15 0.8 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±200 ±4 110 100 ±800 ±7.5 VCM = 0VDC ±1 VCM = 0VDC ±1 VCM = 0VDC TA = TMIN to TMAX VCC = ±10V to ±18V TA = TMIN to TMAX BIAS CURRENT(1) Input Bias Current 88 84 TYP MAX 40 15 8 6 0.7 1.6 9.5 0.5 MIN OPA124PB TYP INPUT NOISE Voltage, fO = 10Hz(4) fO = 100Hz(4) fO = 1kHz(4) fO = 10kHz(5) fB = 10Hz to 10kHz(5) fB = 0.1Hz to 10Hz Current, fB = 0.1Hz to 10Hz fO = 0.1Hz thru 20kHz OFFSET VOLTAGE(1) Input Offset Voltage vs Temperature Supply Rejection vs Temperature OPA124UA, PA TYP MAX UNITS ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ nV/√Hz nV/√Hz nV/√Hz nV/√Hz µVrms µVp-p fAp-p fA/√Hz ±150 ±2 ✻ ✻ ±500 ±4 ±100 ±1 ✻ ✻ ±250 ±2 µV µV/°C dB dB ±5 ±0.5 ±2 ±0.35 ±1 pA ±5 ±0.5 ±1 ±0.25 ±0.5 pA 90 86 MIN 100 90 CURRENT(1) OFFSET Input Offset Current IMPEDANCE Differential Common-Mode ✻ ✻ 1013 || 1 1014 || 3 VOLTAGE RANGE Common-Mode Input Range Common-Mode Rejection vs Temperature Ω || pF Ω || pF VIN = ±10VDC TA = TMIN to TMAX ±10 92 86 ±11 110 100 ✻ 94 ✻ ✻ ✻ ✻ ✻ 100 90 ✻ ✻ ✻ V dB dB RL ≥ 2kΩ 106 125 ✻ ✻ 120 ✻ dB 20Vp-p, RL = 2kΩ VO = ±10V, RL = 2kΩ 16 1 ✻ ✻ ✻ ✻ ✻ ✻ MHz kHz V/µs % µs µs ✻ µs ✻ ✻ ✻ ✻ ✻ V mA Ω pF mA OPEN-LOOP GAIN, DC Open-Loop Voltage Gain FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate THD Settling Time, 0.1% 0.01% Overload Recovery, 50% Overdrive(2) ✻ ✻ Gain = –1, RL = 2kΩ 10V Step 1.5 32 1.6 0.0003 6 10 Gain = –1 5 RATED OUTPUT Voltage Output Current Output Output Resistance Load Capacitance Stability Short Circuit Current RL = 2kΩ VO = ±10VDC DC, Open Loop Gain = +1 POWER SUPPLY Rated Voltage Voltage Range, Derated Current, Quiescent TEMPERATURE RANGE Specification Storage θ Junction-Ambient: PDIP SOIC ±11 ±5.5 10 ±5 IO = 0mADC TMIN and TMAX ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ±12 ±10 100 1000 40 ✻ ✻ ✻ ±15 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 2.5 –25 –65 ±18 3.5 ✻ +85 +125 ✻ ✻ ✻ ✻ ✻ 90 100 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ VDC VDC mA °C °C °C/W °C/W ✻ Specification same as OPA124U, P NOTES: (1) Offset voltage, offset current, and bias current are measured with the units fully warmed up. For performance at other temperatures see Typical Performance Curves. (2) Overload recovery is defined as the time required for the output to return from saturation to linear operation following the removal of a 50% input overdrive. (3) For performance at other temperatures see Typical Performance Curves. (4) Sample tested, 98% confidence. (5) Guaranteed by design. ® OPA124 2 CONNECTION DIAGRAMS Top View DIP Offset Trim 1 8 Top View Substrate –In 2 7 +VS +In 3 6 Output –VS 4 5 Offset Trim SOIC NC 1 8 Substrate –In 2 7 +VS +In 3 6 Output –VS 4 5 NC NC = No Connect PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA124U OPA124P OPA124UA OPA124PA OPA124PB 8-Lead SOIC 8-Pin Plastic DIP 8-Lead SOIC 8-Pin Plastic DIP 8-Pin Plastic DIP 182 006 182 006 006 TEMPERATURE RANGE BIAS CURRENT pA, max OFFSET DRIFT µV/°C, max –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C 5 5 2 2 1 7.5 7.5 4 4 2 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC DISCHARGE SENSITIVITY Supply ........................................................................................... ±18VDC Internal Power Dissipation(2) ......................................................... 750mW Differential Input Voltage(3) .......................................................... ±36VDC Input Voltage Range(3) ................................................................. ±18VDC Storage Temperature Range .......................................... –65°C to +150°C Operating Temperature Range ....................................... –40°C to +125°C Lead Temperature (soldering, 10s) ................................................ +300°C Output Short Circuit Duration(4) ............................................... Continuous Junction Temperature .................................................................... +175°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTES: (1) Stresses above these ratings may cause permanent damage. (2) Packages must be derated based on θJA = 90°C/W for PDIP and 100°C/W for SOIC. (3) For supply voltages less than ±18VDC, the absolute maximum input voltage is equal to +18V > VIN > –VCC – 6V. See Figure 2. (4) Short circuit may be to power supply common only. Rating applies to +25°C ambient. Observe dissipation limit and TJ. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 OPA124 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. INPUT CURRENT NOISE SPECTRAL DENSITY INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k Voltage Noise (nV/√Hz) Current Noise (fA/√Hz) 100 10 1 PB 100 U, P PB 10 1 0.1 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k Frequency (Hz) Frequency (Hz) TOTAL(1) INPUT VOLTAGE NOISE SPECTRAL DENSITY vs SOURCE RESISTANCE TOTAL(1) INPUT VOLTAGE NOISE (PEAK-TO-PEAK) vs SOURCE RESISTANCE 1k 1M 1k R S = 1MΩ Voltage Noise (µVp-p) Voltage Noise (nV/√Hz) R S = 10MΩ 100 R S = 100kΩ PB 10 R S = 100 Ω NOTE: (1) Includes contribution from source resistance. 1 100 PB fB = 0.1Hz to 10Hz 10 1 0.1 1 10 100 1k 10k 100k 10 4 10 5 10 6 10 7 10 8 10 9 10 Frequency (Hz) Source Resistance (Ω) VOLTAGE AND CURRENT NOISE SPECTRAL DENSITY vs TEMPERATURE TOTAL INPUT VOLTAGE NOISE SPECTRAL DENSITY AT 1kHz vs SOURCE RESISTANCE 12 8 1 6 0.1 4 –25 0 25 50 75 100 Current Noise (fA/√Hz) 10 RS 100 OPA124PB + Resistor 10 Resistor Noise Only 1 0.01 125 100 1k 10k 100k 1M Source Resistance (Ω) Temperature (°C) ® OPA124 Voltage Noise, EO (nV/√Hz) EO 10 –50 10 1k 100 f O = 1kHz Voltage Noise (nV/√Hz) NOTE: (1) Includes contribution from source resistance. 4 10M 100M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. BIAS AND OFFSET CURRENT vs TEMPERATURE 1k 1k 100 10 10 10 1 1 0.1 Bias Current (pA) PB 10 1 1 Bias Current Offset Current 0.1 0.1 0.01 –50 0 –25 25 50 75 0.01 125 100 0.01 0.01 –15 –10 Ambient Temperature (°C) 0 5 10 15 COMMON-MODE REJECTION vs FREQUENCY 140 140 120 120 Common-Mode Rejection (dB) 100 80 60 40 20 0 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M 1 10 100 Frequency (Hz) 1k 10k 100k 1M 10M Frequency (Hz) COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE OPEN-LOOP FREQUENCY RESPONSE 140 120 120 –45 Voltage Gain (dB) 110 100 90 100 80 –90 Phase Margin ≈ 65° 60 Gain 40 –135 Phase Shift (Degrees) Power Supply Rejection (dB) –5 Common-Mode Voltage (V) POWER SUPPLY REJECTION vs FREQUENCY Common-Mode Rejection (dB) 0.1 Offset Current (pA) 100 Offset Current (pA) Bias Current (pA) BIAS AND OFFSET CURRENT vs INPUT COMMON-MODE VOLTAGE 80 20 70 –15 0 –10 –5 0 5 10 15 –180 1 Common-Mode Voltage (V) 10 100 1k 10k 100k 1M 10M Frequency (Hz) ® 5 OPA124 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. 3 3 2 2 1 1 0 –50 –25 0 25 50 75 100 Gain Bandwidth (MHz) 4 Slew Rate (V/µs) Gain Bandwidth (MHz) 4 3 3 2 2 1 1 0 0 125 0 0 5 20 MAXIMUM UNDISTORTED OUTPUT VOLTAGE vs FREQUENCY OPEN-LOOP GAIN vs TEMPERATURE 30 Output Voltage (Vp-p) 140 130 Voltage Gain (dB) 15 Supply Voltage (±VCC ) Ambient Temperature (°C) 120 110 20 10 0 100 –50 –25 0 25 50 75 100 1k 125 10k 100k 1M Frequency (Hz) Ambient Temperature (°C) SMALL SIGNAL TRANSIENT RESPONSE LARGE SIGNAL TRANSIENT RESPONSE 15 60 10 40 Output Voltage (mV) Output Voltage (V) 10 5 0 –5 20 0 –20 –40 –10 –60 –15 0 10 20 30 40 0 50 ® OPA124 1 2 3 Time (µs) Time (µs) 6 4 5 Slew Rate (V/µs) GAIN-BANDWIDTH AND SLEW RATE vs SUPPLY VOLTAGE GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VCC = ±15VDC, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE SETTLING TIME vs CLOSED-LOOP GAIN 4 100 Supply Current (mA) Settling Time (µs) 80 60 0.01% 40 0.1% 3 2 1 20 0 0 1 10 100 –50 1k 0 25 50 75 Ambient Temperature (°C) INPUT OFFSET VOLTAGE WARM-UP DRIFT INPUT OFFSET VOLTAGE CHANGE DUE TO THERMAL SHOCK 100 125 150 Offset Voltage Change (µV) 20 Offset Voltage Change (µV) –25 Closed-Loop Gain (V/V) 10 0 –10 U, P 75 PB 0 +25°C +85°C TA = +25°C to TA = +85°C Air Environment –75 –150 –20 0 1 2 3 4 5 –1 6 0 1 2 3 4 5 Time From Thermal Shock (Minutes) Time From Power Turn-On (Minutes) ® 7 OPA124 APPLICATIONS INFORMATION +VCC OFFSET VOLTAGE ADJUSTMENT The OPA124 offset voltage is laser-trimmed and will require no further trim for most applications. In order to reduce layout leakage errors, the offset adjust capability has been removed from the SOIC versions (OPA124UA and OPA124U). The PDIP versions (OPA124PB, OPA124PA, and OPA124P) do have pins available for offset adjustment. As with most amplifiers, externally trimming the remaining offset can change drift performance by about 0.3µV/°C for each 100µV of adjusted offset. The correct circuit configuration for offset adjust for the PDIP packages is shown in Figure 1. 2 3 OPA124P 6 1 5 10kΩ to 1MΩ trim potentiometer. (100kΩ recommended). ±10mV typical trim range. 4 –VCC FIGURE 1. Offset Voltage Trim for PDIP packages. 2 Input Current (mA) I IN INPUT PROTECTION Conventional monolithic FET operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input FET gate-to-substrate isolation diodes are forward-biased. Most BIFET amplifiers can be destroyed by the loss of –VCC. Maximum Safe Current 1 V 0 –1 Maximum Safe Current Unlike BIFET amplifiers, the Difet OPA124 requires input current limiting resistors only if its input voltage is greater than 6V more negative than –VCC. A 10kΩ series resistor will limit input current to a safe level with up to ±15V input levels, even if both supply voltages are lost (Figure 2). Static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers (both bipolar and FET types), this may cause a noticeable degradation of offset voltage and drift. Static protection is recommended when handling any precision IC operational amplifier. –2 –15 –10 –5 0 5 10 15 Input Voltage (V) FIGURE 2. Input Current vs Input Voltage with ±VCC Pins Grounded. Non-Inverting 2 GUARDING AND SHIELDING As in any situation where high impedances are involved, careful shielding is required to reduce “hum” pickup in input leads. If large feedback resistors are used, they should also be shielded along with the external input circuitry. In Buffer 2 8 OPA124 6 In OPA124 3 In 8 Out 3 8 OPA124 6 Bottom View 2 3 8 Out Inverting Leakage currents across printed circuit boards can easily exceed the bias current of the OPA124. To avoid leakage problems, the OPA124 should be soldered directly into a printed circuit board. Utmost care must be used in planning the board layout. A “guard” pattern should completely surround the high impedance input leads and should be connected to a low impedance point which is at the signal input potential. 6 1 Out 7 6 5 4 Board layout for PDIP input guarding: guard top and bottom of board. FIGURE 3. Connection of Input Guard. The amplifier substrate should be connected to any input shield or guard via pin 8 minimizing both leakage and noise pickup (see Figure 3). If guarding is not required, pin 8 should be connected to ground. ® OPA124 NOTE: No trim on SOIC. 7 8 PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) OPA124P OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PA OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PA2 OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124PB OBSOLETE PDIP P 8 TBD Call TI Call TI OPA124U ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA ACTIVE SOIC D 8 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UAE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UAG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR OPA124UG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 75 75 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 7-Apr-2009 information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant OPA124U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA124UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Feb-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA124U/2K5 SOIC D 8 2500 346.0 346.0 29.0 OPA124UA/2K5 SOIC D 8 2500 346.0 346.0 29.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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