Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 LDC2112, LDC2114 Inductive Touch Solution for Low-Power HMI and Button Applications 1 Features 3 Description • Inductive sensing technology enables touch button design on a wide variety of materials such as metal, glass, plastic, and wood, by measuring small deflections of conductive targets. The sensor for an inductive touch system is a coil that can be implemented on a small, compact PCB located behind the panel and protected from the environment. The LDC2112/LDC2114 can reliably detect material deflections of less than 200 nm. • • • • • • • • • Low Power Consumption: – One Button: 6 µA at 0.625 SPS – Two Buttons: 85 µA at 20 SPS Configurable Button Scan Rates – 0.625 SPS to 80 SPS Force Level Measurement of Touch Buttons Independent Channel Operation – Two Channels for LDC2112 – Four Channels for LDC2114 Integrated Algorithms to Enable: – Adjustable Force Threshold per Button – Environmental Shift Compensation – Simultaneous Button Press Detection Supports Independent Operation without MCU Robust EMI Performance – CISPR 22 Class B and CISPR 24 Compliant Supply Voltage: 1.8 V ± 5% Temperature Range: –40 °C to +85 °C Interface: – I2C – Dedicated Logic Output per Button 2 Applications Touch buttons and force level measurements on different materials, including metal, plastic, and glass for: • • Consumer electronics: – Smartphones – Smart watches and other wearable devices – Smart speakers – Tablets/PCs – Virtual reality headsets – Sound bars Industrial applications: – Televisions – Handheld devices – Home appliances – HMI panels and keypads The LDC2112/LDC2114 is a multi-channel low-noise inductance to digital converter with integrated algorithms to implement inductive touch applications. The device employs an innovative LC resonator that offers high rejection of noise and interference. The LDC2112/LDC2114 includes an ultra-low power mode intended for power on/off buttons in battery powered applications. The LDC2112/LDC2114 is available in a 16-pin WCSP or TSSOP package. The 0.4 mm pitch WCSP package has a very small 1.6 × 1.6 mm nominal body size. The 1.2 mm pitch TSSOP package has a 5.0 × 4.4 mm nominal body size. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LDC2112/LDC2114 WCSP (16) 1.6 mm × 1.6 mm LDC2112/LDC2114 TSSOP (16) 5.0 mm × 4.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic VDD LDC2114 OUT0 Digital Algorithm IN0 OUT1 OUT2 OUT3 IN1 IN2 Resonant Circuit Driver Inductive Sensing Core INTB Logic LPWRB IN3 COM I2C SCL SDA GND Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. ADVANCE INFORMATION 1 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 5 5 5 5 6 7 7 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Digital Interface ......................................................... I2C Interface .............................................................. Typical Characteristics .............................................. 7.4 Device Functional Modes........................................ 15 7.5 Register Maps ......................................................... 15 8 Application and Implementation ........................ 27 8.1 Application Information............................................ 27 8.2 Typical Application .................................................. 38 9 Power Supply Recommendations...................... 40 10 Layout................................................................... 40 10.1 Layout Guidelines ................................................. 40 10.2 Layout Example .................................................... 41 10.3 WCSP Light Sensitivity ........................................ 41 11 Device and Documentation Support ................. 42 11.1 11.2 11.3 11.4 11.5 11.6 Detailed Description ............................................ 10 ADVANCE INFORMATION 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 11 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Export Control Notice ........................................... Glossary ................................................................ 42 42 42 42 42 42 12 Mechanical, Packaging, and Orderable Information ........................................................... 42 4 Revision History 2 DATE REVISION NOTES December 2016 * Initial release. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 5 Pin Configuration and Functions LDC2112 16-Pin WCSP Top View (Bumps Down) A NC B NC C VDD 2 3 IN0 IN1 ADDR INTB LPW SDA 4 COM 1 16 SCL GND 2 15 OUT0 LPWRB 3 14 SDA VDD 4 13 OUT1 GND NC OUT1 RB GND D COM SCL LDC2112 INTB 5 12 NC NC 6 11 ADDR NC 7 10 GND IN1 8 9 IN0 OUT0 ADVANCE INFORMATION 1 LDC2112 16-Pin TSSOP Top View Pin Functions - LDC2112 PIN NAME NO. VDD C1 GND D1 A4 I/O (1) DESCRIPTION P Power supply G Ground (2) INTB B2 O Interrupt output Polarity can be configured in Register 0x11. Default is active low. LPWRB C2 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 A Channel 0 LC sensor input IN1 A2 A Channel 1 LC sensor input OUT0 D4 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 O Channel 1 logic output Polarity can be configured in Register 0x1C. ADDR B3 I I2C address When ADDR = Low, I2C address = 0x2A. When ADDR = High, I2C address = 0x2B. SCL D3 I I2C clock SDA C3 I/O I2C data — No connect Leave them floating. A1 NC B1 B4 (1) (2) I = Input, O = Output, P=Power, G=Ground, A=Analog Both pins should be connected to the system ground on the PCB. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 3 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com LDC2114 16-Pin WCSP Top View (Bumps Down) A B 1 2 3 4 IN2 IN1 IN0 GND IN3 INTB OUT3 LDC2114 16-Pin TSSOP Top View COM 1 16 SCL GND 2 15 OUT0 LPWRB 3 14 SDA VDD 4 13 OUT1 OUT2 LDC2114 C VDD LPW SDA OUT1 RB GND D COM SCL OUT0 INTB 5 12 OUT2 IN3 6 11 OUT3 IN2 7 10 GND IN1 8 9 IN0 ADVANCE INFORMATION Pin Functions - LDC2114 PIN NAME NO. VDD C1 D1 GND A4 I/O (1) DESCRIPTION P Power supply G Ground (2) INTB B2 O Interrupt output Polarity can be configured in Register 0x11. Default is active low. LPWRB C2 I Normal / Low Power Mode select Set LPWRB to VDD for Normal Power Mode or ground for Low Power Mode. COM D2 A Common return current path for all LC resonator sensors A capacitor should be connected from this pin to GND. Refer to Setting COM Pin Capacitor. IN0 A3 A Channel 0 LC sensor input IN1 A2 A Channel 1 LC sensor input IN2 A1 A Channel 2 LC sensor input IN3 B1 A Channel 3 LC sensor input OUT0 D4 O Channel 0 logic output Polarity can be configured in Register 0x1C. OUT1 C4 O Channel 1 logic output Polarity can be configured in Register 0x1C. OUT2 B4 O Channel 2 logic output Polarity can be configured in Register 0x1C. OUT3 B3 O Channel 3 logic output Polarity can be configured in Register 0x1C. SCL D3 I I2C clock SDA C3 I/O (1) (2) 4 I2C data I2C address = 0x2A. I = Input, O = Output, P=Power, G=Ground, A=Analog Both pins should be connected to the system ground on the PCB. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 6 Specifications 6.1 Absolute Maximum Ratings Over operating free-air temperature range unless otherwise noted. (1) MAX UNIT Supply voltage MIN 2 V Vi Voltage on any pin –0.3 2 (2) V TJ Junction temperature –40 85 ℃ Tstg Storage temperature –65 125 °C VDD (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum voltage across any two pins is VDD + 0.3 V 6.2 ESD Ratings VALUE (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 UNIT ±1000 Charged device model (CDM), per JEDEC specification JESD22C101 (2) V ±250 ADVANCE INFORMATION V(ESD) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions Over operating free-air temperature range unless otherwise noted. MIN NOM MAX UNIT VDD Supply voltage 1.71 1.89 V TJ Junction temperature –40 85 °C 6.4 Thermal Information LDC2112/LDC2114 THERMAL METRIC (1) YFD (WCSP) (TSSOP) 16 PINS 16 PINS UNIT RθJA Junction-to-ambient thermal resistance 81.8 105.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.4 40.3 °C/W RθJB Junction-to-board thermal resistance 18.2 50.2 °C/W ΨJT Junction-to-top characterization parameter 0.3 3.6 °C/W ΨJB Junction-to-board characterization parameter 18 49.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 5 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 6.5 Electrical Characteristics Over operating free-air temperature range unless otherwise noted. VDD = 1.8 V, TJ = 25 °C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.71 1.8 1.89 V POWER VDD Supply voltage Normal power mode supply current (1) IDDNP (1) 4 buttons, 40 SPS per button, 1 ms sampling window, LPRWB = 1, QSENSOR = 11, LSENSOR = 0.85 µH, CSENSOR = 58 pF, RP = 0.7 kΩ 0.47 mA 1 button, 1.25 SPS, 1 button, 1.25 SPS, 1 ms sampling window, LPRWB = 0, QSENSOR = 11, LSENSOR = 0.85 µH, CSENSOR = 58 pF, RP = 0.7 kΩ 9 µA 5 IDDLP Low power mode supply current IDDSB Standby supply current No button active (EN = 0x00) ISENSORMAX Sensor maximum current drive Registers SENSORn_CONFIG: RPn = 0 (n = 0, 1, 2, or 3) RP, min Minimum sensor RP RP, max Maximum sensor RP 10 µA SENSOR ADVANCE INFORMATION fSENSOR MIN Minimum sensor quality factor QSENSOR, MAX Maximum sensor quality factor mA 350 Ω 10 Sensor resonant frequency QSENSOR, 2.5 1 kΩ 30 MHz 5 30 VSENSOR Sensor oscillation amplitude (peak-topeak) CIN Sensor pin input capacitance Measured on the INn (n = 0, 1, 2, or 3) pins with reference to COM. 0.9 V 17 pF CONVERTER SRNP, min Minimum normal power mode scan rate (2) SRNP, max Maximum normal power mode scan rate (2) SRLP, min Minimum low power mode scan rate SRLP, max Maximum low power mode scan rate (2) Resolution Output code width (1) (2) 6 (2) LPWRB = 1 7 10 13 SPS LPWRB = 1 56 80 104 SPS LPWRB = 0 0.438 0.625 0.813 SPS LPWRB = 0 3.5 5 6.5 SPS 12 Bits 2 I C read/write communication and pull-up resistors current through SCL, SDA not included. For typical percentage offset distribution of the scan rates, refer to Figure 8. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 6.6 Digital Interface Over operating free-air temperature range (unless otherwise noted). VDD = 1.8 V, TA = 25 °C. Pins: LPWRB, INTB, OUT0, OUT1, OUT2, and OUT3. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE LEVELS VIH Input high voltage VIL Input low voltage 0.8 × VDD VOH Output high voltage ISOURCE = 400 µA VOL Output low voltage ISINK = 400 µA IL Digital input leakage current V 0.2 × VDD 0.7 × VDD V V 0.3 × VDD V 500 nA MAX UNIT –500 6.7 I2C Interface MIN TYP VOLTAGE LEVELS Input high voltage VIL Input low voltage VOL Output low voltage HYS Hysteresis (1) 0.7 × VDD V 2-mA sink current 0.3 × VDD V 0.2 × VDD V 0.05 × VDD ADVANCE INFORMATION VIH V I2C TIMING CHARACTERISTICS fSCL Clock frequency tLOW Clock low time 1.3 µs tHIGH Clock high time 0.6 µs tHD;STA Hold time repeated START condition 0.6 µs tSU;STA Set-up time for a repeated START condition 0.6 µs tHD;DAT Data hold time 0 µs tSU;DAT Data set-up time 100 µs tSU;STO Set-up time for STOP condition 0.6 µs tBUF Bus free time between a STOP and START condition 1.3 µs tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs tSP Pulse width of spikes that must be suppressed by the input filter (1) 50 ns (1) 400 After this period, the first clock pulse is generated kHz This parameter is specified by design and/or characterization and is not tested in production. SDA tLOW tf tHD;STA tr tf tr tBUF tSP SCL tSU;STA tHD;STA tHIGH tHD;DAT START tSU;STO tSU;DAT REPEATED START STOP START Figure 1. I2C Timing Diagram Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 7 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 6.8 Typical Characteristics Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C. 1600 25 Average Supply Current (PA) 1400 1200 Average Supply Current (PA) 10 SPS 20 SPS 40 SPS 80 SPS 1000 800 600 400 0.625 SPS 1.25 SPS 2.5 SPS 5 SPS 20 15 10 5 200 0 0 0 1 2 3 4 5 6 Sensor RP (k:) 7 8 9 10 0 ADVANCE INFORMATION Figure 2. Supply Current vs Sensor RP for Normal Power Mode. Average Supply Current (PA) Average Supply Current (PA) 120 110 100 90 8 9 10 D002 130 120 110 100 90 -20 0 20 40 Temperature (qC) 60 80 9 8 7 7 6 5 4 3 -40qC -25qC 0qC 85qC 0 1.7 1.75 D005 Figure 6. Standby Current vs Temperature D004 3 1 100 1.9 4 1 80 1.85 5 2 60 85qC 6 2 20 40 Temperature (qC) 1.8 VDD (V) 0qC 25qC Figure 5. Supply Current vs VDD, Sensor RP = 650 Ω 8 0 1.75 D003 9 -20 -40qC -25qC 80 1.7 100 Standby Current (PA) Standby Current (PA) 7 140 Figure 4. Supply Current vs Temperature, Sensor RP = 650 Ω 8 4 5 6 Sensor RP (k:) 150 130 0 -40 3 160 VDD = 1.71 V VDD = 1.8 V VDD = 1.89 V 140 80 -40 2 Figure 3. Supply Current vs Sensor RP for Low Power Mode. 160 150 1 D001 1.8 VDD (V) 1.85 1.9 D006 Figure 7. Standby Current vs VDD Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Typical Characteristics (continued) Over recommended operating conditions unless specified otherwise. VDD = 1.8 V, TJ = 25 °C. 450 400 350 Occurences 300 250 200 150 100 50 0 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 Percentage Offset ( ) 1 2 3 4 D007 ADVANCE INFORMATION Figure 8. Scan Rate Percentage Offset Distribution at 30 °C Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 9 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 7 Detailed Description 7.1 Overview The LDC2112/LDC2114 is a multi-channel, low-noise, high-resolution inductance-to-digital converter (LDC) optimized for inductive touch applications constructed of monolithic surfaces. Button presses form surface microdeflections which cause frequency shifts in the resonant sensors. The LDC2112/LDC2114 can measure such frequency shifts and determines when button presses have occurred. With adjustable sensitivity per input channel, the LDC2112/LDC2114 can reliably operate with a wide range of physical button structures and materials. The high resolution measurement enables the implementation of multi-level buttons. The LDC2112/LDC2114 incorporates customizable post-processing algorithms for enhanced robustness. The LDC2112/LDC2114 can operate in an ultra-low power mode for optimal battery life, or can be toggled into a higher scan rate for more responsive button press detection for game play or other low latency applications. The LDC2112/LDC2114 is operational from –40 °C to +85 °C with a 1.8 V ± 5% power supply voltage. The LDC2112/LDC2114 is configured through 400 kHz I2C. Button presses can be reported through the I2C interface or with configurable polarity dedicated push-pull outputs. The only external components necessary for operation are supply bypassing capacitors and a COM pin capacitor to ground. ADVANCE INFORMATION 7.2 Functional Block Diagram VDD LDC2112 OUT0 Digital Algorithm OUT1 IN0 Resonant Circuit Driver Inductive Sensing Core INTB Logic LPWRB IN1 COM ADDR I2C SCL SDA GND Copyright © 2016, Texas Instruments Incorporated Figure 9. Block Diagram of LDC2112 10 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Functional Block Diagram (continued) VDD LDC2114 OUT0 OUT1 Digital Algorithm IN0 OUT2 OUT3 IN1 IN2 Resonant Circuit Driver Inductive Sensing Core INTB Logic LPWRB IN3 SCL I2C COM SDA GND Figure 10. Block Diagram of LDC2114 7.3 Feature Description 7.3.1 Multi-Button and Single-Button Operation The LDC2112 provides two independent sensing channels; the LDC2114 provides four independent sensing channels. In the following sections, some parameters, such as DATAn and SENSORn_CONFIG, contain a channel index n. In those instances, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. Any of LDC2112/LDC2114’s available channels can be independently enabled by setting the ENn and LPENn (n = 0, 1, 2, or 3) bit fields in Register EN (Address 0x0C). The low-power-enable bit LPENn only takes effect if the corresponding ENn bit is also set. If only one channel is set active, the LDC2112/LDC2114 periodically samples the single active channel. When several channels are set active, the LDC2112/LDC2114 operates in multichannel mode, and the LDC2112/LDC2114 will sequentially sample the active channels at the configured scan rate. Each button can be enabled independently to be active in Low Power Mode and Normal Power Mode. 7.3.2 Button Output Interfaces Button events may be reported by using two methods. The first method is to monitor the OUTn pins (n = 0, 1, 2, or 3), which are push-pull outputs and can be used as interrupts to a micro-controller. The polarities of these pins are programmable through Register OPOL_DPOL (Address 0x1C). Any button press or error condition is also reported by the interrupt pin, INTB. Its polarity is configurable through Register INTPOL (Address 0x11). The second method is by use of the LDC2112/LDC2114’s I2C interface. The Register OUT (Address 0x01) contains the fields OUT0, OUT1, OUT2, and OUT3, which indicate when a button press has been detected. For more advanced button press measurements, the output DATAn registers (n = 0, 1, 2, or 3, Addresses 0x02 through 0x09), which are 12-bit two’s complements, can be retrieved for all active buttons, and processed on a micro-controller. A valid button push is represented by a positive value. The polarity is configurable in Register OPOL_DPOL (Address 0x1C). The DATAn values can be used to implement multi-level buttons, where the data value is correlated to the amount of force applied to the button. 7.3.3 Programmable Button Sensitivity The GAINn registers (Addresses 0x0E, 0x10, 0x12, and 0x14) enable sensitivity enhancement of individual buttons to ensure consistent behavior of different mechanical structures. The sensitivity has a tunable 64-level gain factor over a range of 232 times. Each gain step increases the gain by a factor of between 1.06 and 1.12. The gain required for an application is primarily determined by the mechanical rigidity of each individual button. The individual gain steps are listed in the Gain Table. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 11 ADVANCE INFORMATION Copyright © 2016, Texas Instruments Incorporated LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Feature Description (continued) 7.3.4 Baseline Tracking The LDC2112/LDC2114 incorporates a baseline tracking algorithm to automatically compensate for any slow change in the sensor output caused by environmental variations, such as temperature drift. The baseline tracking is configured independently for Normal Power Mode and Low Power Mode. For more information, refer to Tracking Baseline. 7.3.5 Integrated Button Algorithms The LDC2112/LDC2114 features several algorithms that can mitigate false button detections due to mechanical non-idealities. The algorithms look for correlated button responses, for example, similar or opposite responses between two neighboring buttons, to determine if there is any undesirable mechanical crosstalk. For more information, refer to Mitigating False Button Detections. 7.3.6 I2C Interface ADVANCE INFORMATION The LDC2112/LDC2114 features an I2C Interface that can be used to program the internal registers and read channel data. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2 or 3, Addresses 0x02 through 0x05) registers, the user should always read Register STATUS (Address 0x00) first to lock the data. The LDC2112/LDC2114 supports burst mode with auto-incrementing register addresses. For the write sequence, there is a special handshake process that has to take place to ensure data integrity. The sequence of register write is illustrated as follows: • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 1 to start the register write session • Poll for RDY_TO_WRITE (Register STATUS, Address 0x00) bit = 1 • I2C write to configure registers • Set CONFIG_MODE (Register RESET, Address 0x0A) bit = 0 to terminate the register write session After CONFIG_MODE is de-asserted, the new scan cycle will start in less than 1 ms. The waveform of the above process is shown in Figure 11. 25 ms scan cycle 25 ms scan cycle Sampling Sampling STATE_RESET < 1 ms (Register RESET) RDY_TO_WRITE (Register STATUS) Program registers only after confirming RDY_TO_WRITE = 1 Figure 11. Timing Diagram Representing the States of the CONFIG_MODE and RDY_TO_WRITE Bits for an I2C Write Handshake 7.3.6.1 Selectable I2C Address (LDC2112 Only) The LDC2112 provides an I2C address select pin, ADDR. Connecting this pin to ground will set the LDC2112 I2C address to 0x2A. Connecting ADDR to VDD will set the LDC2112 I2C address to 0x2B. The LDC2114 has a fixed I2C address of 0x2A. 7.3.6.2 I2C Interface Specifications The maximum speed of the I2C interface is 400 kHz. This sequence uses the standard I2C 7-bit slave address followed by an 8-bit pointer to set the register address. For both write and read, the address pointer will autoincrement as long as the master acknowledges. 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Feature Description (continued) 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 Start by Master D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address 1 9 SCL (continued) D7 D6 D5 D4 D3 D2 D1 D0 Stop by Master Ack by Slave ADVANCE INFORMATION SDA (continued) Frame 3 Data Byte Figure 12. I2C Sequence of Writing a Single Register 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address (ADDR) from Master 1 9 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 Ack by Slave D1 D0 Ack by Slave Frame 3 Data Byte to Register ADDR Frame 4 Data Byte to Register ADDR+1 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Stop by Master Frame N+3 Data Byte to Register ADDR+N Figure 13. I2C Sequence of Writing Consecutive Registers Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 13 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Feature Description (continued) 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Start by Master Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address from Master 1 1 9 9 SCL (continued) SDA (continued) A6 A5 A4 A3 A2 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 No Ack by Master Ack by Slave Repeat Start by Master ADVANCE INFORMATION Frame 3 Serial Bus Address Byte from Master Stop by Master Frame 4 Data Byte from Slave Figure 14. I2C Sequence of Reading a Single Register 1 9 1 9 SCL SDA A6 A5 A4 A3 A2 A1 A0 R/W Start by Master D7 D6 D5 D4 D3 D2 D1 D0 Ack by Slave Ack by Slave Frame 1 Serial Bus Address Byte from Master Frame 2 Slave Register Address (ADDR) from Master 1 9 1 9 SCL (continued) SDA (continued) A6 A5 A4 A3 A2 A1 A0 D7 R/W Repeat Start by Master D6 D5 D4 D3 D2 D1 D0 Ack by Master Ack by Slave Frame 3 Serial Bus Address Byte from Master Frame 4 Data Byte from Slave Register ADDR 1 9 1 9 SCL (continued) SDA (continued) D7 D6 D5 D4 D3 D2 D1 D7 D0 D6 D5 D4 D3 D2 D1 No Ack by Master Ack by Master Frame 5 Data Byte from Slave Register ADDR+1 D0 Stop by Master Frame N+4 Data Byte from Slave Register ADDR+N Figure 15. I2C Sequence of Reading Consecutive Registers 14 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Feature Description (continued) 7.3.6.3 I2C Bus Control In the unlikely event where the clock (SCL) is stuck LOW, power cycle the device to activate the mandatory internal Power-On Reset (POR) circuit. For POR timing constraint, refer to Defining Power-On Timing. If the data line (SDA) is stuck LOW, the master should send nine clock pulses. The device that held the bus LOW should release it sometime within those nine clocks. If not, then power cycle to clear the bus. The LDC2112/LDC2114 has built-in monitors to check that the device is currently working. In the unlikely event of a device fault, the device state will be reset internally, and all the registers will be reset with default settings. The user should check the value of a modified register periodically to monitor the device status and reload the register settings if needed. 7.4 Device Functional Modes The LDC2112/LDC2114 supports two power modes of operation, a Normal Power Mode for active sampling at 10, 20, 40, or 80 SPS, and a Low Power Mode for reduced current consumption at 0.625, 1.25, 2.5, or 5 SPS. Refer to for details. When the LPWRB input pin is HIGH, all enabled channels operate in Normal Power Mode. Each channel can be enabled independently through Register EN (Address 0x0C). For the electrical specification of Normal Power Mode Scan Rate, refer to Electrical Characteristics. 7.4.2 Low Power Mode When the LPWRB input pin is LOW, only the low-power-enabled channels are active. Each channel can be enabled independently to operate in Low Power Mode through Register EN (Address 0x0C). For a channel to operate in the Low Power Mode, both the LPENn and ENn bits (n is the channel index) must be set to 1. The Low Power Mode allows for energy-saving monitoring of button activity. In this mode, the device is in an inactive power-saving state for the majority of the time. To achieve the lowest current possible, the lowest scan rate, i.e., 0.625 SPS should be used. In addition, the individual button sampling window should be set to the lowest effective setting (this is system dependent, but typically 1 ms). For the electrical specification of the configurable Low Power Mode Scan Rate, refer to Electrical Characteristics. 7.4.3 Configuration Mode Before configuring any register settings, the device must be put into the configuration mode first. Setting CONFIG_MODE = 1 through Register RESET (Address 0x0A) stops data conversion and holds the device in configuration mode. Any device configuration changes can then be made. The current consumption in this mode is typically 0.3 mA. After all changes have been written, set CONFIG_MODE = 0 for normal operation. Refer to I2C Interface for more information. 7.5 Register Maps Registers indicated with Reserved must be written only with indicated values. Improper device operation may occur otherwise. Table 1. Register List ADDRESS NAME DEFAULT VALUE DESCRIPTION 0x00 STATUS 0x00 Device status. 0x01 OUT 0x00 Channel output logic states. 0x02 DATA0_LSB 0x00 The lower 8 bits of the Button 0 data (Two’s complement). 0x03 DATA0_MSB 0x00 The upper 4 bits of the Button 0 data (Two’s complement). 0x04 DATA1_LSB 0x00 The lower 8 bits of the Button 1 data (Two’s complement). 0x05 DATA1_MSB 0x00 The upper 4 bits of the Button 1 data (Two’s complement). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 15 ADVANCE INFORMATION 7.4.1 Normal Power Mode LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Register Maps (continued) Table 1. Register List (continued) ADDRESS ADVANCE INFORMATION 16 NAME DEFAULT VALUE DESCRIPTION 0x06 DATA2_LSB 0x00 The lower 8 bits of the Button 2 data (Two’s complement). 0x07 DATA2_MSB 0x00 The upper 4 bits of the Button 2 data (Two’s complement). 0x08 DATA3_LSB 0x00 The lower 8 bits of the Button 3 data (Two’s complement). 0x09 DATA3_MSB 0x00 The upper 4 bits of the Button 3 data (Two’s complement). 0x0A RESET 0x00 Reset device and register configurations. 0x0B RESERVED 0x00 Reserved. Set to 0x00. 0x0C EN 0x1F Enable channels and low power modes. 0x0D NP_SCAN_RATE 0x01 Normal Power Mode scan rate. 0x0E GAIN0 0x28 Gain for Channel 0 sensitivity adjustment. 0x0F LP_SCAN_RATE 0x02 Low Power Mode scan rate. 0x10 GAIN1 0x28 Gain for Channel 1 sensitivity adjustment. 0x11 INTPOL 0x01 Interrupt polarity. 0x12 GAIN2 0x28 Gain for Channel 2 sensitivity adjustment. 0x13 LP_BASE_INC 0x06 Low power base increment. 0x14 GAIN3 0x28 Gain for Channel 3 sensitivity adjustment. 0x15 NP_BASE_INC 0x04 Normal power base increment. 0x16 MAXWIN 0x00 Max-win. 0x17 LC_DIVIDER 0x03 LC oscillation frequency divider. 0x18 HYST 0x08 Hysteresis for threshold. 0x19 TWIST 0x00 Anti-twist. 0x1A COMMON_DEFORM 0x00 Anti-common and anti-deformation. Reserved. Set to 0x00. 0x1B RESERVED 0x00 0x1C OPOL_DPOL 0x0F Output polarity. 0x1D RESERVED 0x00 Reserved. Set to 0x00. 0x1E CNTSC 0x55 Counter scale. 0x1F RESERVED 0x00 Reserved. Set to 0x00. Sensor 0 cycle count, frequency, RP range. 0x20 SENSOR0_CONFIG 0x04 0x21 RESERVED 0x00 Reserved. Set to 0x00. 0x22 SENSOR1_CONFIG 0x04 Sensor 1 cycle count, frequency, RP range. 0x23 RESERVED 0x00 Reserved. Set to 0x00. 0x24 SENSOR2_CONFIG 0x04 Sensor 2 cycle count, frequency, RP range. 0x25 FTF0 0x00 Sensor 0 fast tracking factor. 0x26 SENSOR3_CONFIG 0x04 Sensor 3 cycle count, frequency, RP range. 0x27 RESERVED 0x00 Reserved. Set to 0x00. 0x28 FTF1_2 0x00 Sensors 1 and 2 fast tracking factors. Reserved. Set to 0x00. 0x29 RESERVED 0x00 0x2A RESERVED 0x00 Reserved. Set to 0x00. 0x2B FTF3 0x00 Sensor 3 fast tracking factor. 0xFC MANUFACTURER_ID_LSB 0x49 Manufacturer ID lower byte 0xFD MANUFACTURER_ID_MSB 0x54 Manufacturer ID upper byte Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Register Maps (continued) Table 1. Register List (continued) ADDRESS NAME DEFAULT VALUE DESCRIPTION 0xFE DEVICE_ID_LSB 0x00 Device ID lower byte 0xFF DEVICE_ID_MSB 0x00 Device ID upper byte 7.5.1 Individual Register Listings Fields indicated with Reserved must be written only with indicated values. Improper device operation may occur otherwise. The R/W column indicates the Read-Write status of the corresponding field. A ‘R/W’ entry indicates read and write capability, a ‘R’ indicates read-only, and a ‘W’ indicates write-only. Before reading the OUT (Address 0x01) or channel DATAn (n = 0, 1, 2, or 3, Addresses 0x02 through 0x05) registers, the user should always read the STATUS register (Address 0x00) first to lock the data. The LDC2114 supports burst mode with auto-incrementing register addresses. BIT FIELD TYPE RESET DESCRIPTION 7 OUT_STATUS R 0 Output Status Logic OR of output bits from Register OUT (Address 0x01). This field is cleared by reading this register. 6 CHIP_READY R 1 Chip Ready Status b0: chip not ready after internal reset. b1: chip ready after internal reset. 5 RDY_TO_WRITE R 0 Ready to Write Indicates if registers are ready to be written. See I2C Interface for more information. b0: registers not ready. b1: registers ready. 4 MAXOUT R 0 Max-Out Error Indicates button max-out. Reports an error when output data reaches maximum value (±0x7FF). Cleared by a read of the status register. b0: no max-out error. b1: max-out error. 3 FSM_WD R 0 Finite-State Machine Watchdog Error Reports an error has occurred and conversions have been halted. Cleared by a read of the status register. b0: no error in finite state machine. b1: error in finite state machine. 2 LC_WD R 0 LC Sensor Watchdog Error Reports an error when any LC oscillator fails to start. Cleared by a read of the status register. b0: no error in LC oscillator initialization. b1: error in LC oscillator initialization. 1 TIMEOUT R 0 Button Timeout Reports when any button is asserted for more than 50 seconds. Cleared by a read of the status register. b0: no timeout error. b1: timeout error. 0 RESERVED R 0 Reserved. Set to b0. Table 3. Register OUT – Address 0x01 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3 OUT3 R 0 Output Logic State for Channel 3 (LDC2114 Only) b0: No button press detected on Channel 3. b1: Button press detected on Channel 3. 2 OUT2 R 0 Output Logic State for Channel 2 (LDC2114 Only) b0: No button press detected on Channel 2. b1: Button press detected on Channel 2. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 17 ADVANCE INFORMATION Table 2. Register STATUS – Address 0x00 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table 3. Register OUT – Address 0x01 (continued) BIT FIELD TYPE RESET DESCRIPTION 1 OUT1 R 0 Output Logic State for Channel 1 b0: No button press detected on Channel 1. b1: Button press detected on Channel 1. 0 OUT0 R 0 Output Logic State for Channel 0 b0: No button press detected on Channel 0. b1: Button press detected on Channel 0. Table 4. Register DATA0_LSB – Address 0x02 BIT FIELD TYPE RESET 7:0 DATA0[7:0] R 0000 0000 The lower 8 bits of Channel 0 data (Two’s complement). DESCRIPTION Table 5. Register DATA0_MSB – Address 0x03 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA0[11:8] R 0000 The upper 4 bits of Channel 0 data (Two’s complement). Table 6. Register DATA1_LSB – Address 0x04 ADVANCE INFORMATION BIT FIELD TYPE RESET 7:0 DATA1[7:0] R 0000 0000 The lower 8 bits of Channel 1 data (Two’s complement). DESCRIPTION Table 7. Register DATA1_MSB – Address 0x05 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA1[11:8] R 0000 The upper 4 bits of Channel 1 data (Two’s complement). Table 8. Register DATA2_LSB – Address 0x06 BIT FIELD TYPE RESET 7:0 DATA2[7:0] R 0000 0000 The lower 8 bits of Channel 2 data (Two’s complement). (LDC2114 Only) DESCRIPTION Table 9. Register DATA2_MSB – Address 0x07 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA2[11:8] R 0000 The upper 4 bits of Channel 2 data (Two’s complement). (LDC2114 Only) Table 10. Register DATA3_LSB – Address 0x08 BIT FIELD TYPE RESET 7:0 DATA3[7:0] R 0000 0000 The lower 8 bits of Channel 3 data (Two’s complement). (LDC2114 Only) DESCRIPTION Table 11. Register DATA3_MSB – Address 0x09 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R 0000 Reserved. Set to b0000. 3:0 DATA3[11:8] R 0000 The upper 4 bits of Channel 3 data (Two’s complement). (LDC2114 Only) Table 12. Register RESET – Address 0x0A BIT FIELD TYPE RESET DESCRIPTION 7:5 RESERVED R 000 Reserved. Set to b000. FULL_RESET R/W 0 Device Reset b0: Normal operation. b1: Resets the device and register configurations. All registers will be returned to default values. Normal operation will not resume until STATUS:CHIP_READY = 1. RESERVED R 000 Reserved. Set to b000. 4 3:1 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Table 12. Register RESET – Address 0x0A (continued) BIT 0 FIELD TYPE RESET DESCRIPTION CONFIG_MODE R/W 0 Configuration Mode b0: Normal operation. b1: Holds the device in configuration mode (no data conversion), but maintains current register configurations. Any device configuration changes should be made with this bit set to 1. After all configuration changes have been written, set this bit to 0 for normal operation. BIT FIELD TYPE RESET DESCRIPTION 7 LPEN3 R/W 0 Channel 3 Low-Power-Enable (LDC2114 Only) b0: Disable Channel 3 in Low Power Mode. b1: Enable Channel 3 in Low Power Mode. EN3 must also be set to 1. 6 LPEN2 R/W 0 Channel 2 Low-Power-Enable (LDC2114 Only) b0: Disable Channel 2 in Low Power Mode. b1: Enable Channel 2 in Low Power Mode. EN2 must also be set to 1. 5 LPEN1 R/W 0 Channel 1 Low-Power-Enable b0: Disable Channel 1 in Low Power Mode. b1: Enable Channel 1 in Low Power Mode. EN1 must also be set to 1. 4 LPEN0 R/W 1 Channel 0 Low-Power-Enable b0: Disable Channel 0 in Low Power Mode. b1: Enable Channel 0 in Low Power Mode. EN0 must also be set to 1. 3 EN3 R/W 1 Channel 3 Enable b0: Disable Channel 3. b1: Enable Channel 3. 2 EN2 R/W 1 Channel 2 Enable b0: Disable Channel 2. b1: Enable Channel 2. 1 EN1 R/W 1 Channel 1 Enable b0: Disable Channel 1. b1: Enable Channel 1. 0 EN0 R/W 1 Channel 0 Enable b0: Disable Channel 0. b1: Enable Channel 0. ADVANCE INFORMATION Table 13. Register EN – Address 0x0C Table 14. Register NP_SCAN_RATE – Address 0x0D BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. 1:0 NPSR R/W 01 Normal Power Mode Scan Rate Refer to Configuring Button Scan Rate for more information. b00: 80 SPS b01: 40 SPS (Default) b10: 20 SPS b11: 10 SPS Table 15. Register GAIN0 – Address 0x0E BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R 00 Reserved. Set to b00. 5:0 GAIN0 R/W b10 1000 Gain for Channel 0 Refer to the Gain Table for detailed configuration. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 19 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table 16. Register LP_SCAN_RATE – Address 0x0F BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. 1:0 LPSR R/W 10 Low Power Mode Scan Rate Refer to Configuring Button Scan Rate for more information. b00: 5 SPS b01: 2.5 SPS b10: 1.25 SPS (Default) b11: 0.625 SPS Table 17. Register GAIN1 – Address 0x10 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R 00 Reserved. Set to b00. 5:0 GAIN1 R/W b10 1000 Gain for Channel 1 Refer to the Gain Table for detailed configuration. Table 18. Register INTPOL – Address 0x11 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. INTPOL R/W 0 Interrupt Polarity b0: Set INTB pin polarity to active low. b1: Set INTB pin polarity to active high. R 01 Reserved. Set to b01. 2 ADVANCE INFORMATION 1:0 RESERVED Table 19. Register GAIN2 – Address 0x12 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R 00 Reserved. Set to b00. 5:0 GAIN2 R/W b10 1000 Gain for Channel 2 (LDC2114 Only) Refer to the Gain Table for detailed configuration. Table 20. Register LP_BASE_INC – Address 0x13 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. 2:0 LPBI R/W b100 Baseline Tracking Increment in Low Power Mode Refer to Baseline Tracking for more information. Valid values: [b000 : b111]. b110: LPBI = 6 (Default) Table 21. Register GAIN3 – Address 0x14 BIT FIELD TYPE RESET DESCRIPTION 7:6 RESERVED R 00 Reserved. Set to b00. 5:0 GAIN3 R/W b10 1000 Gain for Channel 3 (LDC2114 Only) Refer to the Gain Table for detailed configuration. Table 22. Register NP_BASE_INC – Address 0x15 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. 2:0 NPBI R/W b100 Baseline Tracking Increment in Normal Power Mode Refer to Baseline Tracking for more information. Valid values: [b000 : b111]. b100: NPBI = 4 (Default) Table 23. Register MAXWIN – Address 0x16 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R b0000 Reserved. Set to b0000. MAXWIN3 R/W 0 Max-Win Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Channel 3 is excluded from the max-win group. b1: Channel 3 is included in the max-win group. 3 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Table 23. Register MAXWIN – Address 0x16 (continued) BIT FIELD TYPE RESET DESCRIPTION 2 MAXWIN2 R/W 0 Max-Win Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Channel 2 is excluded from the max-win group. b1: Channel 2 is included in the max-win group. 1 MAXWIN1 R/W 0 Max-Win Algorithm Setting for Channel 1 Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Channel 1 is excluded from the max-win group. b1: Channel 1 is included in the max-win group. 0 MAXWIN0 R/W 0 Max-Win Algorithm Setting for Channel 0 Refer to Resolving Simultaneous Button Presses (Max-Win) for more information. b0: Channel 0 is excluded from the max-win group. b1: Channel 0 is included in the max-win group. BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. 2:0 LCDIV R/W b011 LC Oscillation Frequency Divider The frequency divider sets the button sampling window in conjunction with SENCYCn. Valid values: [b000:b111]. Refer to Programming Button Sampling Window for more information. b011: LCDIV = 3 (Default) ADVANCE INFORMATION Table 24. Register LC_DIVIDER – Address 0x17 Table 25. Register HYST – Address 0x18 BIT FIELD TYPE RESET DESCRIPTION 7:4 RESERVED R b0000 Reserved. Set to b0000. 3:0 HYST R/W b1000 Hysteresis Defines the hysteresis for button triggering threshold. Valid values: [b0000:b1111]. Hysteresis = HYST × 4 b1000: HYST = 8, Hysteresis = 32 (Default) Refer to Setting Button Triggering Threshold for more information. Table 26. Register TWIST – Address 0x19 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. 2:0 ANTITWIST R/W b000 Anti-Twist When set to 0, the anti-twist algorithm is not enabled. When greater than 0, all buttons are enabled for the anti-twist algorithm. The validation of all buttons is void if any button’s DATA is negative by a threshold. Anti-twist Threshold = ANTITWIST × 4. Refer to Overcoming Case Twisting (Anti-Twist) for more information. Table 27. Register COMMON_DEFORM – Address 0x1A BIT FIELD TYPE RESET DESCRIPTION 7 ANTICOM3 R/W 0 Anti-Common Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 3 from the anti-common group. b1: Include Channel 3 in the anti-common group. 6 ANTICOM2 R/W 0 Anti-Common Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 2 from the anti-common group. b1: Include Channel 2 in the anti-common group. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 21 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table 27. Register COMMON_DEFORM – Address 0x1A (continued) BIT ADVANCE INFORMATION FIELD TYPE RESET DESCRIPTION 5 ANTICOM1 R/W 0 Anti-Common Algorithm Setting for Channel 1 Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 1 from the anti-common group. b1: Include Channel 1 in the anti-common group. 4 ANTICOM0 R/W 0 Anti-Common Algorithm Setting for Channel 0 Refer to Eliminating Common-Mode Change (Anti-Common) for more information. b0: Exclude Channel 0 from the anti-common group. b1: Include Channel 0 in the anti-common group. 3 ANTIDFORM3 R/W 0 Anti-Deform Algorithm Setting for Channel 3 (LDC2114 Only) Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 3 from the anti-deform group. b1: Include Channel 3 in the anti-deform group. 2 ANTIDFORM2 R/W 0 Anti-Deform Algorithm Setting for Channel 2 (LDC2114 Only) Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 2 from the anti-deform group. b1: Include Channel 2 in the anti-deform group. 1 ANTIDFORM1 R/W 0 Anti-Deform Algorithm Setting for Channel 1 Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 1 from the anti-deform group. b1: Include Channel 1 in the anti-deform group. 0 ANTIDFORM0 R/W 0 Anti-Deform Algorithm Setting for Channel 0 Refer to Mitigating Metal Deformation (Anti-Deform) for more information. b0: Exclude Channel 0 from the anti-deform group. b1: Include Channel 0 in the anti-deform group. Table 28. Register OPOL_DPOL – Address 0x1C 22 BIT FIELD TYPE RESET DESCRIPTION 7 OPOL3 R/W 0 Output Polarity for OUT3 Pin (LDC2114 Only) b0: Active low (Default) b1: Active high 6 OPOL2 R/W 0 Output Polarity for OUT2 Pin (LDC2114 Only) b0: Active low (Default) b1: Active high 5 OPOL1 R/W 0 Output Polarity for OUT1 Pin b0: Active low (Default) b1: Active high 4 OPOL0 R/W 0 Output Polarity for OUT0 Pin b0: Active low (Default) b1: Active high 3 DPOL3 R/W 1 Data Polarity for Channel 3 (LDC2114 Only) b0: DATA3 decreases as fSENSOR3 increases. b1: DATA3 increases as fSENSOR3 increases. (Default) 2 DPOL2 R/W 1 Data Polarity for Channel 2 (LDC2114 Only) b0: DATA2 decreases as fSENSOR2 increases. b1: DATA2 increases as fSENSOR2 increases. (Default) 1 DPOL1 R/W 1 Data Polarity for Channel 1 b0: DATA1 decreases as fSENSOR1 increases. b1: DATA1 increases as fSENSOR1 increases. (Default) 0 DPOL0 R/W 1 Data Polarity for Channel 0 b0: DATA0 decreases as fSENSOR0 increases. b1: DATA0 increases as fSENSOR0 increases. (Default) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 (1) BIT FIELD TYPE RESET DESCRIPTION 7:6 CNTSC3 R/W 01 Counter Scale for Channel 3 (LDC2114 Only) Refer to Scaling Frequency Counter Output for more information. b00: CNTSC3 = 0 b01: CNTSC3 = 1 (Default) b10: CNTSC3 = 2 b11: CNTSC3 = 3 5:4 CNTSC2 R/W 01 Counter Scale for Channel 2 (LDC2114 Only) Refer to Scaling Frequency Counter Output for more information. b00: CNTSC2 = 0 b01: CNTSC2 = 1 (Default) b10: CNTSC2 = 2 b11: CNTSC2 = 3 3:2 CNTSC1 R/W 01 Counter Scale for Channel 1 Refer to Scaling Frequency Counter Output for more information. b00: CNTSC1 = 0 b01: CNTSC1 = 1 (Default) b10: CNTSC1 = 2 b11: CNTSC1 = 3 1:0 CNTSC0 R/W 01 Counter Scale for Channel 0 Refer to Scaling Frequency Counter Output for more information. b00: CNTSC0 = 0 b01: CNTSC0 = 1 (Default) b10: CNTSC0 = 2 b11: CNTSC0 = 3 ADVANCE INFORMATION Table 29. Register CNTSC – Address 0x1E (1) The Counter Scale sets a scaling factor for the internal frequency counter. The formula for calculating counter scale is CNTSCn = LCDIV + ceiling(log2 (0.0861×(SENCYCn+1)/fSENSORn)), where n = 0, 1, 2, or 3 Table 30. Register SENSOR0_CONFIG – Address 0x20 BIT FIELD TYPE RESET DESCRIPTION RP0 R/W 0 Channel 0 Sensor RP Range Select Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350Ω ≤ RP ≤ 4kΩ (Default) b1: 800Ω ≤ RP ≤ 10kΩ 6:5 FREQ0 R/W 00 Channel 0 Sensor Frequency Range Select Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC0 R/W b0 0100 Channel 0 Sensor Cycle Count SENCYC0 sets the Channel 0 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. 7 Table 31. Register SENSOR1_CONFIG – Address 0x22 BIT 7 FIELD TYPE RESET DESCRIPTION RP1 R/W 0 Channel 1 Sensor RP Range Select Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 23 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table 31. Register SENSOR1_CONFIG – Address 0x22 (continued) BIT FIELD TYPE RESET DESCRIPTION 6:5 FREQ1 R/W 00 Channel 1 Sensor Frequency Range Select Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC1 R/W b0 0100 Channel 1 Sensor Cycle Count SENCYC1 sets the Channel 1 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. Table 32. Register SENSOR2_CONFIG – Address 0x24 BIT FIELD TYPE RESET DESCRIPTION RP2 R/W 0 Channel 2 Sensor RP Range Select (LDC2114 Only) Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ 6:5 FREQ2 R/W 00 Channel 2 Sensor Frequency Range Select (LDC2114 Only) Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved 4:0 SENCYC2 R/W b0 0100 Channel 2 Sensor Cycle Count (LDC2114 Only) SENCYC2 sets the Channel 2 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. 7 ADVANCE INFORMATION Table 33. Register FTF0 – Address 0x25 BIT FIELD TYPE RESET DESCRIPTION 7:3 RESERVED R b0 0000 Reserved. Set to b0 0000. 2:1 FTF0 R/W 00 Fast Tracking Factor for Channel 0 Defines baseline tracking speed for negative values of DATA0. Refer to Tracking Baseline for more information. b00: FTF0 = 0 (Default) b01: FTF0 = 1 b10: FTF0 = 2 b11: FTF0 = 3 R 0 Reserved. Set to b0. 0 RESERVED Table 34. Register SENSOR3_CONFIG – Address 0x26 BIT 7 6:5 24 FIELD TYPE RESET DESCRIPTION RP3 R/W 0 Channel 3 Sensor RP Range Select (LDC2114 Only) Set based on the actual sensor RP physical parameter. RP = 1/RS × L/C where RS is the AC series resistance in the LC resonator, L is the inductance, and C is the capacitance. Refer to Designing Sensor Parameters for more information. b0: 350 Ω ≤ RP ≤ 4 kΩ (Default) b1: 800 Ω ≤ RP ≤ 10 kΩ FREQ3 R/W 00 Channel 3 Sensor Frequency Range Select (LDC2114 Only) Refer to Designing Sensor Parameters for more information. b00: 1 MHz to 3.3 MHz (Default) b01: 3.3 MHz to 10 MHz b10: 10 MHz to 30 MHz b11: Reserved Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Table 34. Register SENSOR3_CONFIG – Address 0x26 (continued) BIT FIELD TYPE RESET DESCRIPTION 4:0 SENCYC3 R/W b0 0100 Channel 3 Sensor Cycle Count (LDC2114 Only) SENCYC3 sets the Channel 3 button sampling window in conjunction with LCDIV. Refer to Programming Button Sampling Window for more information. BIT FIELD TYPE RESET DESCRIPTION 7:6 FTF2 R/W 00 Fast Tracking Factor for Channel 2 (LDC2114 Only) Defines baseline tracking speed for negative values of DATA2. Refer to Tracking Baseline for more information. b00: FTF2 = 0 (Default) b01: FTF2 = 1 b10: FTF2 = 2 b11: FTF2 = 3 5:4 FTF1 R/W 00 Fast Tracking Factor for Channel 1 Defines baseline tracking speed for negative values of DATA1. Refer to Tracking Baseline for more information. b00: FTF1 = 0 (Default) b01: FTF1 = 1 b10: FTF1 = 2 b11: FTF1 = 3 3:0 RESERVED R b0000 Reserved. Set to b0000. ADVANCE INFORMATION Table 35. Register FTF1_2 – Address 0x28 Table 36. Register FTF3 – Address 0x2B BIT FIELD TYPE RESET DESCRIPTION 7:2 RESERVED R b00 0000 Reserved. Set to b00 0000. 1:0 FTF3 R/W 00 Fast Tracking Factor for Channel 3 (LDC2114 Only) Defines baseline tracking speed for negative values of DATA3. Refer to Tracking Baseline for more information. b00: FTF3 = 0 (Default) b01: FTF3 = 1 b10: FTF3 = 2 b11: FTF3 = 3 Table 37. Register MANUFACTURER_ID_LSB – Address 0xFC BIT FIELD 7:0 MANUFACTURER_ID [7:0] TYPE RESET DESCRIPTION R 0x49 Manufacturer ID [7:0] Table 38. Register MANUFACTURER_ID_MSB – Address 0xFD BIT FIELD TYPE RESET DESCRIPTION 7:0 MANUFACTURER_ID [15:8] R 0x54 Manufacturer ID [15:8] Table 39. Register DEVICE_ID_LSB – Address 0xFE BIT FIELD TYPE RESET DESCRIPTION 7:0 DEVICE_ID [7:0] R 0x00 Device ID [7:0] Table 40. Register DEVICE_ID_MSB – Address 0xFF BIT FIELD TYPE RESET DESCRIPTION 7:0 DEVICE_ID [15:8] R 0x00 Device ID [15:8] 7.5.1.1 Gain Table for Registers GAIN0, GAIN1, GAIN2, and GAIN3 Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR 0 1.0 32 16 1 1.0625 33 17 2 1.1875 34 19 3 1.3125 35 21 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 25 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Table 41. GAINn Bit Values in Decimal and Corresponding Normalized Gain Factors (continued) ADVANCE INFORMATION 26 BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR BIT VALUE IN DECIMAL NORMALIZED GAIN FACTOR 4 1.4375 36 23 5 1.5625 37 25 6 1.6875 38 27 7 1.8125 39 29 8 2.0 40 32 9 2.125 41 34 10 2.375 42 38 11 2.625 43 42 12 2.875 44 46 13 3.125 45 50 14 3.375 46 54 15 3.625 47 58 16 4.0 48 64 17 4.25 49 68 18 4.75 50 76 19 5.25 51 84 20 5.75 52 92 21 6.25 53 100 22 6.75 54 108 23 7.25 55 116 24 8.0 56 128 25 8.5 57 136 26 9.5 58 152 27 10.5 59 168 28 11.5 60 184 29 12.5 61 200 30 13.5 62 216 31 14.5 63 232 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LDC2112/LDC2114 supports multiple buttons. Each button can be configured in various ways for optimal operation. 8.1.1 Understanding Theory of Operation ADVANCE INFORMATION An AC current flowing through an inductor will generate an AC magnetic field. If a conductive material, such as a metal object, is deflected toward the inductor as shown in Figure 16, the magnetic field will induce a circulating current (eddy current) on the surface of the conductor. The eddy current is a function of the distance, size, and composition of the conductor. Figure 16. Metal Deflection The eddy current generates its own magnetic field, which opposes the original field generated by the inductor. This effect reduces the effective inductance of the system, resulting in an increase in sensor frequency. Figure 17 shows the inductance and frequency response of an example sensor. As the sensitivity of an inductive sensor increases with closer targets, the conductive plate should be placed quite close to the sensor—typically 10% of the sensor diameter for circular coils. For rectangular or race-track-shaped coils, the target to sensor distance should typically be less than 10% of the shorter side of the coil. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 27 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Application Information (continued) 7 5 6.5 4.75 4.5 5.5 4.25 5 4 4.5 3.75 4 Sensor Frequency (MHz) Sensor Inductance (PH) 6 3.5 3.5 3.25 Sensor Inductance (PH) Sensor Frequency (MHz) 3 0 1 2 3 4 5 6 Distance between Sensor and Target (mm) 7 8 9 3 10 D010 Figure 17. Sensor Inductance and Frequency vs Target Distance ADVANCE INFORMATION The output DATAn registers (Addresses 0x02 through 0x09) of the LDC2112/LDC2114 contain the processed values of the changes in sensor frequencies. 8.1.2 Designing Sensor Parameters Each inductive touch button uses an LC resonator sensor, as illustrated in Figure 18, where L is the inductor, C is the capacitor, and RS is the AC series resistance of the sensor at the frequency of operation. The key parameters of the LC sensor include its frequency, effective parallel resistance RP, and quality factor Q. These parameters must be within the ranges as specified in the Sensor section of the Electrical Characteristics table. L C RS Figure 18. LC Resonator The LC sensor frequency, as defined by the equation below, must be between 1 MHz and 30 MHz. 1 fSENSOR 2S LC (1) The sensor quality factor, as defined by the equation below, must be between 5 and 30. QSENSOR 1 RS L C (2) The series resistance can be represented as an equivalent parallel resistance, RP, which is given by L RP RS C 28 Submit Documentation Feedback (3) Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Application Information (continued) L RP C Figure 19. Equivalent Parallel Circuit In summary, the LDC2112/LDC2114 requires that the sensor parameters are within the following ranges: • 1 MHz ≤ fSENSOR ≤ 30 MHz • 5 ≤ Q ≤ 30 • 350 Ω ≤ RP ≤ 10 kΩ 8.1.3 Setting COM Pin Capacitor The COM pin requires a bypass capacitor to ground. The capacitor must be a low ESL, low ESR type. CCOM must be sized so that: 100 × CSENSORn/QSENSORn < CCOM < 1250 × CSENSORn/QSENSORn (4) is valid for all channels. The value of QSENSORn when the sensor is at the minimum target distance should be used. The maximum acceptable value for CCOM is 20 nF. The CCOM range for a particular sensor configuration can be obtained with the Spiral_Inductor_Designer tab of the LDC Tools Spreadsheet. 8.1.4 Defining Power-On Timing The low power architecture of the LDC2112/LDC2114 makes it possible for the device to be active all the time. When not being used, the LDC2112/LDC2114 can operate in Low Power Mode with a single standby power button, which typically consumes less than 10 µA. If additional power-saving is desired, or in the rare event where a power-on reset becomes necessary (see I2C Interface), the output data will become ready after 50 ms startup time, about 1 ms optional register loading time, and two sampling windows for all active channels. The power-on timing of the LDC2112/LDC2114 is illustrated in Figure 20 below. Only Channels 0 and 1 are enabled. Scan rate: 40 SPS. 1 ms 25 ms scan cycle 25 ms scan cycle 50 ms startup time Sampling Sampling VDD IN0 IN1 Events Power up 50 ms startup time is independent of scan rate. Optional register loading DATA is ready after all active channels finish two conversions. Figure 20. Power-On Timing Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 29 ADVANCE INFORMATION RP can be viewed as the load on the sensor driver. This load corresponds to the current drive needed to maintain the oscillation amplitude. RP must be between 350 Ω and 10 kΩ. LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Application Information (continued) 8.1.5 Configuring Button Scan Rate The LDC2112/LDC2114 periodically samples all active channels at the selected scan rate. The device can operate at eight different scan rates to meet various power consumption requirements, where a lower scan rate achieves lower power consumption. In Normal Power Mode, the scan rate can be programmed to 80, 40, 20, or 10 SPS through Register NP_SCAN_RATE (Address 0x0D). In Low Power Mode, the scan rate can be programmed to 5, 2.5, 1.25, or 0.625 SPS through Register LP_SCAN_RATE (Address 0x0F). The mode is selected by setting the LPWRB pin to VDD (Normal Power) or ground (Low Power). In either mode, each button can be independently enabled through a bit in Register EN (Address 0x0C). Table 42. Button Scan Rates ADVANCE INFORMATION SCAN RATE (SPS) LPSR (0x0F) SETTING NPSR (0x0D) SETTING LPWRB PIN SETTING 0.625 b11 Not Applicable Low (0) 1.25 b10 Not Applicable Low (0) 2.5 b01 Not Applicable Low (0) 5 b00 Not Applicable Low (0) 10 Not Applicable b11 High (1) 20 Not Applicable b10 High (1) 40 Not Applicable b01 High (1) 80 Not Applicable b00 High (1) 8.1.6 Programming Button Sampling Window The button sampling window (BSW) is the actual duration per scan cycle for active data sampling of the sensor frequency. It is programmed with the global divider, LCDIV, in Register LC_DIVIDER (Address 0x17), and the individual sensor cycle counter SENCYCn (n = 0, 1, 2, or 3) in Registers SENSORn_CONFIG (n = 0, 1, 2, or 3, Addresses 0x20, 0x22, 0x24, 0x26). For most touch button applications, the button sampling window should be set to between 1 ms and 8 ms. The recommended minimum sensor conversion time is 1 ms. Longer conversion time can be used to achieve better signal-to-noise ratio if needed. If multiple channels are enabled, the active channels will sample sequentially, as illustrated in Figure 21. Button Sampling Window: set by LCDIV, SENCYCn, and fSENSORn IN0 IN1 IN2 IN3 Scan Rate: set by NPSR, LPSR, and LPWRP pin Figure 21. Configurable Scan Rate and Button Sampling Window The LDC2112/LDC2114 is designed to work with LC resonator sensors with oscillation frequencies ranging from 1 MHz to 30 MHz. The exact definition of the button sampling window is given by the equation below. 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Number of Sensor Oscillation Cycles Sensor Frequency Button Sampling Window tSAMPLE 128 u SENCYCn 1 u 2LCDIV fSENSORn , n 0, 1, 2, or 3 where : tSAMPLE is the sampling window in Ps, SENCYCn and LCDIV are the linear and exponential scalers that set the number of sensor oscillation cycles, fSENSORn is the sensor frequency in MHz. (5) In the equation above, LCDIV (0 to 7, default 3) is the exponential LC divider that sets the approximate ranges for all channels, and SENCYCn (0 to 31, default 4) is the linear sensor cycle scaler that fine-tunes each individual channel. Together they set the number of sensor oscillation cycles used to determine the button sampling window. Alternatively, from the button sampling window and sensor frequency, the LCDIV can be read off from Figure 22. For example, 1 ms button sampling window and 9.2 MHz sensor frequency intersect at the region where LCDIV = 2. Then SENCYCn can be calculated accordingly. 30 LCDIV=7 Maximum fSENSOR (MHz) 25 LCDIV=6 20 LCDIV=5 15 LCDIV=4 10 LCDIV=3 LCDIV=2 5 LCDIV=1 LCDIV=0 0 0 1 2 3 4 5 6 Sample Interval (ms) 7 8 9 D008 Figure 22. LCDIV as a Function of Sensor Frequency and Button Sampling Window 8.1.7 Scaling Frequency Counter Output The LDC2112/LDC2114 requires this internal frequency counter scaler to be set based on the button sampling window to avoid data overflow. The scaler in Register CNTSC (Address 0x1E) must be set by the following formula § 0.0861u SENCYCn 1 · LCDIV ceiling ¨¨ log2 ¸¸ , n fSENSORn © ¹ where fSENSORn is the sensor frequency in MHz. CNTSCn 0, 1, 2, or 3 (6) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 31 ADVANCE INFORMATION For example, if the LC sensor frequency is 9.2 MHz, and it is desirable to get 1 ms button sampling window, then this can be achieved by setting SENCYCn = 17 and LCDIV = 2. LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 8.1.8 Setting Button Triggering Threshold Every material shows some hysteresis when it deforms then returns to the original state. The amount of hysteresis is a function of material properties and physical parameters, such as size and thickness. This feature modifies the hysteresis of the button signal threshold according to different materials and various button shapes and sizes. Hysteresis can be programmed in Register HYST (Address 0x18). By default, the button triggering hysteresis is set to 32. The nominal button triggering threshold is 128. With hysteresis, the effective on-threshold is 128 + 32 = 160. This means if the DATAn (n = 0, 1, 2, or 3) reaches 160, the LDC considers that as a button press. When the DATAn decreases to 128 – 32 = 96, the LDC considers the button to be released. ThresholdON = 128 + Hysteresis ThresholdOFF = 128 – Hysteresis (7) (8) OUTn Logic High (Button asserted) ADVANCE INFORMATION Logic Low (Not asserted) DATAn 128-HYSTx4 128 128+HYSTx4 Figure 23. Button Triggering Threshold with Hysteresis 8.1.9 Tracking Baseline The LDC2112/LDC2114 automatically tracks slow changes in the baseline signal and compensates for environmental drifts and variations. In Normal Power Mode, the effective baseline increment per scan cycle is approximately 2NPBI / 72, where NPBI is configured in Register NP_BASE_INC (Address 0x15). In Low Power Mode, the effective baseline increment per scan cycle is approximately 2LPBI / 9, where LPBI is configured in Register LP_BASE_INC (Address 0x13). As a result of baseline tracking, a button press with a constant force only lasts for a finite amount of time. The duration of a button press is defined by the equation below (DATAn > ThresholdON). Duration of Button Press DATAn ThresholdOFF BINC where : Duration of Button Press is the number of scan cycles that a button is asserted, DATA n is the button press signal at the beginning of a press, BINC is the baseline increment per scan cycle. (9) If DATAn is negative, the tracking speed will be scaled by the fast tracking factor as specified in Registers FTF0 (Address 0x25), FTF1_2 (Address 0x28), or FTF3 (Address 0x2B). The scaling factors for various FTFn settings are shown in Table 43. 32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Button Pressed Button Released Baseline DATAn Base Increment Figure 24. Baseline Tracking in the Presence of a Button Press Table 43. Fast Tracking Factor Settings FTFn Setting Fast Tracking Factor b00 1 b01 4 b10 8 b11 16 8.1.10 Mitigating False Button Detections The LDC2112/LDC2114 offers several algorithms that can mitigate false button detections due to mechanical non-idealities. These are listed below. 8.1.10.1 Eliminating Common-Mode Change (Anti-Common) This algorithm eliminates false detection when a user presses the middle of two or more buttons, which could lead to a common-mode response on multiple buttons. All the buttons can be individually enabled to have this feature by programming Register COMMON_DEFORM (Address 0x1A). Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 33 ADVANCE INFORMATION Fast tracking if DATAn is negative LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Common-mode change to both Buttons 0 and 1. Button 0 Button 1 Intentional Press of Button 1 DATA Threshold = 128+HYST×4 Time Button 0 OUTPUT without Anti-common (High = Button Press Detected) Button 1 Button 0 OUTPUT with Anti-common (High = Button Press Detected) Button 1 ADVANCE INFORMATION Figure 25. Illustration of the Anti-Common Feature 8.1.10.2 Resolving Simultaneous Button Presses (Max-Win) This algorithm enables the system to select the button pressed with maximum force when multiple buttons are pressed at the same time. This could happen when two buttons are physically very close to each other, and pressing one causes a residual reaction on the other. Buttons can be individually enabled to join the “max-win” group by configuring Register MAXWIN (Address 0x16). Intentional Press of Button 0 with coupled response of Button 1 Intentional Press of Button 1 Button 0 Button 1 DATA Threshold = 128+HYST×4 Time Button 0 OUTPUT without Max-Win (High = Button Press Detected) Button 1 Button 0 OUTPUT with Max-Win (High = Button Press Detected) Button 1 Figure 26. Illustration of the Max-Win Feature 8.1.10.3 Overcoming Case Twisting (Anti-Twist) The anti-twist algorithm reduces the likelihood of false detection when the case is twisted, which could cause unintended mechanical activation of the buttons, or an opposite reaction in two adjacent buttons. When this algorithm is enabled, detection of button presses is suppressed if any button’s output data is negative by a configurable threshold. The anti-twist algorithm can be enabled by configuring Register TWIST (Address 0x19). 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Button 0 Button 1 Intentional Press of Button 1. Twisting effect of Buttons 0 and 1. DATA Threshold = 128+HYST×4 Time Button 0 OUTPUT without Anti-twist (High = Button Press Detected) Button 1 Button 1 Figure 27. Illustration of the Anti-Twist Feature 8.1.10.4 Mitigating Metal Deformation (Anti-Deform) This function filters changes due to metal deformation in the vicinity of one or more buttons. Such metal deformation can be accidentally caused by pressing a neighboring button that does not have sufficient mechanical isolation. The user can specify which buttons to join the anti-deform group by configuring Register COMMON_DEFORM (Address 0x1A). 8.1.11 Reporting Interrupts for Button Presses and Error Conditions INTB, the LDC2112/LDC2114 interrupt pin, is asserted when a button press or an error condition occurs. The default polarity is active low and can be configured through Register INTPOL (Address 0x11). Figure 28 shows the LDC2112/LDC2114 response to a single button press on Channel 0. At the end of the button sampling window following a press of Button 0, the OUT0 pin and INTB pin are asserted. The OUT_STATUS bit changes from 0 to 1, and remains so until a read of the STATUS register clears it. The OUTn (n = 0, 1, 2, or 3) and INTB pins are asserted until the end of the button sampling window following the release of the button. OUTn DQG ,17% DUH SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle Sampling 25 ms scan cycle Sampling Sampling OUT0 Pin INTB Pin STATUS Register Events Button 0 pressed OUT0 and INTB asserted, OUT_STATUS bit asserted Reading the Status Register clears the OUT_STATUS bit. Button 0 released OUT0 de-asserted Figure 28. Timing Diagram of a Single Button Press Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 35 ADVANCE INFORMATION Button 0 OUTPUT with Anti-twist (High = Button Press Detected) LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com Figure 29 shows the LDC2112/LDC2114 response to multiple button presses. In this example, after Button 0 is pressed, the OUT0 pin is asserted. After that, Button 1 is also pressed, following which Button 0 is released. The OUT0 pin is de-asserted and OUT1 pin asserted at the end of the next button sampling window. The INTB pin remains continuously asserted as long as at least one of the buttons is pressed. The OUT_STATUS bit only changes from 0 to 1 after the first button assertion. OUTn DQG ,17% DUH SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle Sampling 25 ms scan cycle Sampling Sampling OUT0 Pin OUT1 Pin INTB Pin ADVANCE INFORMATION STATUS Register Events Button 0 pressed OUT0 and INTB asserted Button 1 Button 0 pressed released OUT0 de-asserted OUT1 asserted Button 1 released OUT1 and INTB de-asserted Reading the Status Register clears the OUT_STATUS bit. Figure 29. Timing Diagram of Multiple Button Presses Figure 30 shows the INTB pin asserting due to an error condition. At the end of the next button sampling window, the INTB pin is asserted and the error is reported in the STATUS register (Address 0x00). Refer to Register STATUS (Address 0x00) for possible error conditions. ,17% LV SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle Sampling 25 ms scan cycle Sampling INTB Pin STATUS Register Events Error Error reported in Reading the Status Register clears the error bit. occurred the Status Register Figure 30. Timing Diagram of INTB Pin Triggered by an Error Condition Figure 31 shows the error condition in the presence of a button press. For example, this can be caused by pressing the button with excessive force, which triggers a max-out error. 36 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 OUTn DQG ,17% DUH SURJUDPPHG WR ³$FWLYH /RZ´. Scan Rate: 40 SPS. 25 ms scan cycle 25 ms scan cycle Sampling Sampling 25 ms scan cycle Sampling OUT0 Pin INTB Pin STATUS Register Events Button 0 pressed Max-out error MAXOUT bit changes Button 0 from 0 to 1. ocurred. released OUT_STATUS bit changes from 0 to 1. Reading the Status Register Reading the Status Register clears the OUT_STATUS bit. clears the MAXOUT bit. OUT0 and INTB de-asserted 8.1.12 Estimating Supply Current When the LDC2112/LDC2114 is active (in either Normal Power Mode or Low Power Mode), its current consumption has several components, which include the static current (independent of sensor frequency), dynamic current (linear with sensor frequency), LC sensor current, and current during the transitional period while channels switching on and off. IACTIVE = ISTATIC + IDYNAMIC + ISENSOR + ITRANS (10) The static current is about 1.45 mA. ISTATIC = 1.45 mA (11) The dynamic current is a function of the supply voltage and sensor frequency. IDYNAMIC = ((7.644 × VDD – 3.53) × fSENSOR + 19) × 1000 (mA) (12) where: VDD is the supply voltage, fSENSOR is the sensor frequency in MHz. The sensor current is inversely proportional to the sensor RP. ISENSOR = A / RP (13) where: A is an empirical parameter dependent on the sensor RP in kΩ and supply voltage VDD in V. A = 0.72 × exp(0.1 × RP) + (1.11 × VDD – 2) (14) The current during the transitional period is characterized by the following equation: ITRANS × tTRANS = 260 × VDD2 – 212 × VDD + 69 (mQ) (15) The LDC2112/LDC2114 is only actively sampling the enabled channels during a fraction of the scan window. So the average supply current is: IDD = ((IACTIVE × NCH × tSAMPLE) + ITRANS × tTRANS) / tSCAN + 0.005 (mA) (16) where: IACTIVE is the current consumed when the device is active as defined by Equation 10, NCH is the number of channels enabled, tSAMPLE is the button sampling window in ms, ITRANS × tTRANS is the charge transferred during the transition period as defined by Equation 15, tSCAN is the button scan window in ms. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 37 ADVANCE INFORMATION Figure 31. Timing Diagram of an Error Condition in the Presence of a Button Press LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 8.2 Typical Application 8.2.1 Touch Button Design The low power architecture of LDC2112/LDC2114 makes them ideal for driving button sensors in consumer electronics, such as mobile phones. Most mobile phones today have three buttons along the edges, namely the power button, volume up, and volume down. The LDC2112 can support two buttons, and LDC2114 can support four. On a typical smartphone, the two volume buttons are next to each other, so they may be susceptible to false detections such as simultaneous button presses. To prevent such mis-triggers, they can be grouped together to take advantage of the various features that mitigate false detections as explained in Mitigating False Button Detections. For example, if MAXWIN is applied to the two volume buttons, only the one with the greater force will be triggered. The phone case does not require any mechanical cutouts at the button locations. This can support reduced manufacturing cost for the case and enhance the case’s resistance to moisture intrusion, dust and dirt. This is a great advantage compared to mechanical buttons in the market today. 8.2.1.1 Design Requirements ADVANCE INFORMATION The sensor parameters, including frequency, RP, and Q factor have to be within the design space of the LDC2112/LDC2114 as specified in Electrical Characteristics. 8.2.1.2 Detailed Design Procedure The LDC2112/LDC2114 is a multi-channel device. The italic n in the parameters below refers to the nth channel, that is, n = 0 or 1 for LDC2112, and n = 0, 1, 2, or 3 for LDC2114. 1. Select system-based options: • Select Normal or Low Power Mode of operation by connecting the LPWRB pin to VDD or GND, respectively. Configure the enable bits for all channels in Register EN (Address 0x0C). • Select polarities of OUTn and INTB pins by configuring Register OPOL_DPOL (Address 0x1C) and Register INTPOL (Address 0x11). • Configure sensor frequency setting in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26). 2. Choose sampling rate (80, 40, 20, 10, 5, 2.5, 1.25, or 0.625 SPS) based on system power consumption requirement, and configure Register NP_SCAN_RATE (Address 0x0D) or Register LP_SCAN_RATE (Address 0x0F). 3. Choose button sampling window based on power consumption and noise requirements (recommended: 1 ms to 8 ms). While a longer button sampling window provides better noise performance, 1 ms is typically sufficient for most applications. Set SENCYCn and LCDIV in Registers SENSORn_CONFIG (Addresses 0x20, 0x22, 0x24, 0x26) and Register LC_DIVIDER (Address 0x17) in the following steps: • Calculate LCDIV = ceiling (log2 (fSENSORn × tSAMPLE) – 12), where fSENSORn is sensor frequency in MHz, tSAMPLE is button sampling window in µs • If LCDIV < 0, set it to 0 • Adjust SENCYCn to get desired tSAMPLE according to tSAMPLE = 128 × (SENCYCn + 1) × 2LCDIV / fSENSORn 4. Calibrate gain in the appropriate Registers GAINn (Addresses 0x0E, 0x10, 0x12, 0x14). The gain setting can be used to tune the sensitivity of the touch button. GAINn is a 6-bit field with 64 different gain levels corresponding to a relative gain of 1 to 232. A good mechanical and sensor design typically requires a gain level of around 32 to 50, corresponding to relative gains of 16 to 76 (normalized to gain level of 0). Use the following sequence to determine the appropriate gain for each button: • Apply minimum desired force to the button. • Read initial DATAn value after the button press. Note that the baseline tracking will affect this value. • Calculate gain factor needed to increase DATAn to the programmed threshold (default is 160). • Look up the Gain Table to find the required gain setting. 5. Enable special features to mitigate button interference if there is any. Registers MAXWIN, TWIST, COMMON_DEFORM (Addresses 0x16, 0x19, 0x1A). 38 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Typical Application (continued) 8.2.1.3 Application Curves 400 Channel 0 Channel 1 Threshold 350 Conversion DATA 300 250 200 150 100 50 0 -50 0 2 4 Time (s) 6 8 D009 ADVANCE INFORMATION Figure 32. Conversion DATA vs Time for Channels 0 and 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 39 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 9 Power Supply Recommendations The LDC2114 power supply should be bypassed with a 1-μF and a 0.1-μF pair of capacitors in parallel to ground. The smaller value 0.1-µF capacitor should be placed closer to the VDD pin than the 1-μF capacitor. The capacitors should be a low ESL, low ESR type. To enable close positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is recommended. Refer to Recommended Operating Conditions for more details. 10 Layout 10.1 Layout Guidelines The COM pin must be bypassed to ground with an appropriate value capacitor. CCOM must be placed as close as possible to the COM pin. The COM signal must be tied to a small copper fill placed underneath the INn signals. To enable closer positioning of the capacitors, use of 0201 footprint devices for the bypass capacitors is recommended. ADVANCE INFORMATION Each active channel needs to have an LC resonator connected to the corresponding INn pins. The sensor capacitor must be placed within 10 mm of the corresponding INn pin, and the inductor (NOT shown in Figure 33) must be placed at the appropriate location next to (but not touching) the metal target. The INn traces must be at least 6 mil (0.15 mm) wide to minimize parasitic inductances. For the chip-scale package, the inner 4 device pads (INTB, OUT3, LPWRB, and SDA) must be routed out on an inner layer through vias, with the traces offset to reduce coupling with other signals. For many layouts, these 4 vias may need to use blind vias or microvias to bring the signals out. The PCB layer stackup must use a thinner (4 mil or 0.1 mm thickness) dielectric between the top copper and next copper layer so that microvias can be used. 40 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 Figure 33. Layout of LDC2114 (WCSP-16) With Decoupling Capacitors and Sensor Capacitors 10.3 WCSP Light Sensitivity Exposing the WCSP device to direct light may cause incorrect operation of the device. Light sources such as halogen lamps can affect electrical performance if they are situated in proximity to the device. Light with wavelengths in the red and infrared part of the spectrum have the most detrimental effect. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 41 ADVANCE INFORMATION 10.2 Layout Example LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 44. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LDC2112 Click here Click here Click here Click here Click here LDC2114 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. ADVANCE INFORMATION TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 42 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 PACKAGE OUTLINE YFD0016 DSBGA - 0.4 mm max height SCALE 8.000 DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER ADVANCE INFORMATION D 0.4 MAX C SEATING PLANE 0.175 0.125 BALL TYP 0.05 C 1.2 TYP SYMM D 1.2 TYP C SYMM B 0.4 TYP 16X 0.015 C A 0.285 0.185 B A 1 2 3 4 0.4 TYP 4222547/A 12/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. www.ti.com Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 43 LDC2112, LDC2114 SNOSD15 – DECEMBER 2016 www.ti.com EXAMPLE BOARD LAYOUT YFD0016 DSBGA - 0.4 mm max height DIE SIZE BALL GRID ARRAY 16X ( (0.4) TYP 0.225) A (0.4) TYP B SYMM ADVANCE INFORMATION C D 2 1 3 4 SYMM LAND PATTERN EXAMPLE SCALE:40X 0.05 MAX ( 0.225) METAL METAL UNDER SOLDER MASK 0.05 MIN ( 0.225) SOLDER MASK OPENING SOLDER MASK OPENING NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4222547/A 12/2015 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009). www.ti.com 44 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 LDC2112, LDC2114 www.ti.com SNOSD15 – DECEMBER 2016 EXAMPLE STENCIL DESIGN YFD0016 DSBGA - 0.4 mm max height DIE SIZE BALL GRID ARRAY (0.4) TYP (R0.05) TYP 16X ( 0.25) ADVANCE INFORMATION A (0.4) TYP B SYMM METAL TYP C D 1 3 2 4 SYMM SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:40X 4222547/A 12/2015 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. www.ti.com Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: LDC2112 LDC2114 45 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LDC2112PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2112PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2112YFDR PREVIEW DSBGA YFD 16 3000 TBD Call TI Call TI -40 to 85 LDC2112YFDT PREVIEW DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 LDC2114PWR PREVIEW TSSOP PW 16 2000 TBD Call TI Call TI -40 to 85 LDC2114PWT PREVIEW TSSOP PW 16 250 TBD Call TI Call TI -40 to 85 LDC2114YFDR PREVIEW DSBGA YFD 16 3000 TBD Call TI Call TI -40 to 85 LDC2114YFDT PREVIEW DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 PLDC2114YFDT ACTIVE DSBGA YFD 16 250 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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