AKM LRCK 96khz sampling ds 20bit adc Datasheet

ASAHI KASEI
[AK5352]
AK5352
96kHz Sampling ∆Σ 20bit ADC
GENERAL DESCRIPTION
The AK5352 is a 20-bit, 96kHz sampling rate for DAT and DVD, 64x oversampling rate(64fs), 2-channel A/D
converter for stereo digital systems. The ∆Σ modulator in the AK5352 uses the new developed Enhanced Dual
bit architecture. This new architecture achieves the wider dynamic range, while keeping much the same
superior distortion characteristics as the conventional Single bit way.
The AK5352 is available in a small 24pin VSOP package which will reduce your system space.
FEATURES
†
†
†
†
†
†
†
†
†
Sampling Rate up to 96kHz
Full-differential inputs
S/(N+D): 97dB
DR, S/N: 104dB
Linear phase digital filter
• Pass band: 0 ∼ 22kHz(@fs=48kHz)
• Pass band ripple: ± 0.005dB
• Stop band attenuation: 80dB
Digital HPF for DC-offset cancel
Master clock: 256fs/384fs
Power supply: 5V±5%
Small package: 24pinVSOP
0155-E-00
1997/1
-1-
ASAHI KASEI
[AK5352]
„ Ordering Guide
AK5352-VF
-10∼ 70°C
AKD5351/2
Evaluation Board
24pin VSOP
„ Pin Layout
„ Replacement from AK5350 to AK5352
Package
fc of HPF(@fs=48kHz)
AK5350
28VSOP
AK5352
24VSOP
*)Interchangeable with AK5352
1Hz
7Hz
0155-E-00
1997/1
-2-
ASAHI KASEI
[AK5352]
PIN/FUNCTION
No.
Pin Name
I/O
1
2
3
AINR+
AINRVREF
I
I
O
4
5
6
7
8
10
11
14
9
VA
AGND
AINL+
AINLTST1
TST2
TST3
TST4
HPFE
I
I
12
13
16
VD
DGND
PD
I
17
MCLK
I
18
SCLK
I/O
19
LRCK
I/O
20
FSYNC
I/O
I
FUNCTION
Right channel analog positive input pin
Right channel analog negative input pin
Voltage Reference output pin
(VA-2.6V)
Normally connected to VA with a 0.1uF ceramic capacitor in
parallel with a 10uF electrolytic capacitor.
Analog section Analog Power Supply, +5V
Analog section Analog Ground
Left channel analog positive input pin
Left channel analog negative input pin
Test pin
(Pull-down pin)
Should be left floating.
High Pass Filter Enable pin
(Pull-up pin)
"H": ON
"L": OFF
Digital section Digital Power Supply pin, +5V
Digital section Digital Ground pin
Power Down pin
"L" brings the device into power-down mode. Must be done
once after power-on.
Master Clock input pin
CMODE="H" : 384fs
CMODE="L" : 256fs
Serial Data Clock pin
Data is clocked out at the falling edge of SCLK.
Slave mode: 64fs clock is input usually.
Master mode: SCLK outputs a 64fs clock.
SCLK stays low during the power-down mode(PD="L").
L/R Channel Clock Select pin
Slave mode: An fs clock is fed to this LRCK pin.
Master mode: LRCK output an fs clock.
LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"
during reset when SMODE1 "H".
Frame Synchronization Signal pin
Slave mode: When "H", data bits are clocked out on SDATA.
2
As I S slave mode ignores FSYNC, it should hold "L" or
"H".
Master mode: FSYNC outputs 2fs clock.
Stay low during the power-down mode(PD="L").
0155-E-00
1997/1
-3-
ASAHI KASEI
[AK5352]
21
SDATA
O
22
CMODE
I
23
15
SMODE1
SMODE2
I
I
24
VB
-
Serial Data Output pin
Data are output with MSB first, in 2's complement format.
After 20 bits are output it turns to "L". It also remains "L" at a
power-down mode(PD="L").
Master Clock Selection pin
"L": MCLK=256fs
"H": MCLK=384fs
Serial Interface Mode Select pin
Defines the directions of LRCK, SCLK and FSYNC pins and
Output Data Format. SMODE2 is pull-down pin.
SMODE1 SMODE2
MODE
LRCK
L
L
Slave mode: MSB justified
: H/L
2
H
L
Master mode: Similar to I S
: H/L
2
L
H
Slave mode: I S
: L/H
2
H
H
Master mode: I S
: L/H
Substrate Power Supply, +5V
0155-E-00
1997/1
-4-
ASAHI KASEI
[AK5352]
ABSOLUTE MAXIMUM RATINGS
(AGND,DGND=0V; Note 1 )
Parameter
DC Power Supply:Analog Power(VA pin)
Digital Power(VD pin) (Note 2 )
Substrate Power(VB pin)
Input Current (Any pin except supplies)
Analog Input Voltage
AINL+,AINL-,AINR+,AINR-pins (Note 2 )
Digital Input Voltage
(Note 2 )
Ambient Temperature
Storage Temperature
Symbol
min
max
Units
VA
VD
VB
IIN
VINA
-0.3
-0.3
-0.3
-0.3
6.0
6.0/VB+0.3
6.0
± 10
V
V
6.0/VA+0.3
mA
V
VIND
Ta
Tstg
-0.3
-10
-65
6.0/VB+0.3
70
150
°C
°C
V
Note 1 : All voltage with respect to ground.
Note 2 : Absolute maximum value is the highest voltage in 6.0V, VA+0.3V and VB+0.3V.
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND,DGND=0V; Note 1 )
Parameter
DC Power Supplies: Analog Power
Digital Power(VD pin)
Substrate Power(VB pin)(Note 3 )
Symbol
VA
VD
VB
min
4.75
4.75
4.75
typ
5.0
5.0
5.0
max
5.25
VB
5.25
Units
V
V
V
Note 1 : All voltages with respect to ground.
Note 3 : The VA and VB are connected together through the chip substrate and have several ohms
resistance. VA and VD must be same voltage.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
0155-E-00
1997/1
-5-
ASAHI KASEI
[AK5352]
ANALOG CHARACTERISTICS (fs=48kHz)
(Ta=25°C ; VA,VD,VB=5.0V; fs=48kHz; 20bit; Input signal frequency=1kHz,
Measurement Bandwidth=10Hz∼ 20kHz; unless otherwise specified.)
Parameter
min
Resolution
Analog Input Characteristics (Analog source impedance: 330Ω )
S/(N+D)
(Note 4 )
Dynamic Range (A-weighted) (Note 5 )
S/N
(A-weighted) (Note 6 )
Interchannel Isolation
(f=1kHz)
Interchannel Gain Mismatch
Gain drift
Input Voltage Range
Input Impedance
88
98
98
100
±3.26
50
typ
max
Units
20
Bits
97
104
104
120
0.1
±200
±3.47
80
dB
dB
dB
dB
dB
ppm/°C
0.3
±3.68
Vp-p
kΩ
25
9
mA
mA
Power Supplies
Power Supply Current
(Note 7 )
Normal Operation
(PD="H")
VA+VB
VD
Power-Down mode (PD="L")
VA+VB
VD
Power Consumption
(Note 7 )
Normal Operation
Power-Down mode
Power Supply Rejection Ratio
15
6
20
10
105
150
50
uA
uA
170
mW
uW
dB
Note 4 : The ratio of the rms value of the signal to the sum of all other spectral components up to 20kHz
except for the signal (included harmonic component, excluded DC component, analog input
signal is -0.5dB). Inversed of THD+N.
Note 5 : S/(N+D) with an input signal of 60dB below full-scale.
Note 6 : When using only 20kHzLPF, S/N and DR are 100dB(typ.). When using CCIR-ARM filter,
S/N is 100dB(typ.).
Note 7 : Almost no current is supplied from VB pin.
0155-E-00
1997/1
-6-
ASAHI KASEI
[AK5352]
ANALOG CHARACTERISTICS (fs=96kHz)
(Ta=25°C ; VA,VD,VB=5.0V; fs=96kHz; 20bit; Input signal frequency=1kHz,
Measurement Bandwidth=10Hz ∼ 40kHz; unless otherwise specified.)
Parameter
min
Resolution
Analog Input Characteristics (Analog source impedance: 330Ω )
S/(N+D)
(Note 8 )
Dynamic Range
(Note 9 )(Note 10 )
S/N
(Note 10 )
Interchannel Isolation
(f=1kHz)
Interchannel Gain Mismatch
Gain drift
Input Voltage Range
Input Impedance
86
90
90
100
±3.26
25
typ
max
Units
20
Bits
96
99
99
120
0.1
±200
±3.47
40
dB
dB
dB
dB
dB
ppm/°C
0.3
±3.68
Vp-p
kΩ
25
18
mA
mA
Power Supplies
Power Supply Current
(Note 11 )
Normal Operation
(PD="H")
VA+VB
VD
Power-Down mode (PD="L")
VA+VB
VD
Power Consumption
(Note 11 )
Normal Operation
Power-Down mode
Power Supply Rejection Ratio
15
12
20
10
135
150
50
uA
uA
215
mW
uW
dB
Note 8 : The ratio of the rms value of the signal to the sum of all other spectral components up to 40kHz
except for the signal (included harmonic component, excluded DC component, analog input
signal is -0.5dB). Inversed of THD+N.
Note 9 : S/(N+D) with an input signal of 60dB below full-scale.
Note 10 : These value are measured by 40kHz flat, without A-weighted. When using A-weighted, S/N and
DR are 104dB(typ.).
Note 11 : Almost no current is supplied from VB pin.
0155-E-00
1997/1
-7-
ASAHI KASEI
[AK5352]
DIGITAL FILTER CHARACTERISTICS
(Ta=25°C ; VA,VD,VB=5.0V±5%; fs=48kHz)
Low Pass Filter characteristics
Passband
-0.005dB
-0.02dB
-0.06dB
(Note 12 )
Stopband
(Note 13 )
Passband Ripple
(Note 14 )
Stopband Attenuation (Note 13 ,Note 15 )
Group Delay Distortion
Group Delay
(Note 16 )
Symbol
min
PB
0
SB
PR
SR
∆ GD
26.5
typ
max
Units
21.5
21.768
22.0
kHz
GD
29.3
kHz
dB
dB
us
1/fs
FR
1.0
2.9
6.5
Hz
Hz
Hz
±0.005
80
0
High Pass Filter characteristics
Frequency Response -3dB (Note 12 )
-0.5dB
-0.1dB
Note 12 :
Note 13 :
Note 14 :
Note 15 :
These frequencies scale with the sampling frequency(fs).
Stopband is 26.5kHz to 3.0455MHz at fs=48kHz.
Passband is DC to 21.5kHz at fs=48kHz.
The analog modulator samples the input at 3.072MHz for a system sampling rate of
fs=48kHz. These is no rejection of input signals at those bandwidths which are multiples of
the sampling frequency (n x 3.072MHz ±22kHz ;n=0,1,2,3… ).
Note 16 : The calculation delay time occurred by digital filtering. This is the time from the input of
analog signal to setting the 20bit data of both channels to the output registers. GD=29.3/fs.
ELECTRICAL CHARACTERISTICS
„ Digital Characteristics
(Ta=25° C; VA,VD,VB=5.0V±5%)
Parameter
High-Level Input voltage
Low-Level Input voltage
High-Level Output voltage
Low-Level Output voltage
Input Leakage Current
Iout=-20uA
Iout=20uA
(Note 17 )
Symbol
min
typ
max
Units
VIH
VIL
VOH
VOL
Iin
70%VD
VD-0.1
-
-
30%VD
0.1
±10
V
V
V
V
uA
Note 17 : Except for pull-down and pull-up pins. TST1, TST2, TST3, TST4, SMODE2 pins have internal
pull-down device, HPFE pin has internal pull-up device. (TYP.50kΩ)
0155-E-00
1997/1
-8-
ASAHI KASEI
[AK5352]
„ SWITCHING CHARACTERISTICS
(Ta=25°C ; VA,VD,VB=5.0V±5%; CL=20pF)
Parameter
Control Clock Frequency
Master Clock 256fs: (fs = ∼ 98kHz)
Pulse width Low
Pulse width High
384fs: (fs = ∼ 54kHz)
Pulse width Low
Pulse width High
Serial Data Output Clock
Channel Select Clock(Sampling Frequency)
Duty Cycle
Serial Interface Timing
(Note 18 )
Slave Mode(SMODE1="L")
SCLK Period
SCLK Pulse width Low
Pulse width High
SCLK Rising to LRCK Edge
(Note 19 )
LRCK Edge to SCLK Rising
(Note 19 )
LRCK Edge to SDATA MSB Valid
SCLK Falling to SDATA Valid
SCLK Rising to FSYNC Edge (Note 19 )
FSYNC Edge to SCLK Rising (Note 19 )
Master Mode(SMODE1="H")
SCLK Frequency
Duty Cycle
FSYNC Frequency
Duty Cycle
SCLK Falling to LRCK Edge
LRCK Edge to FSYNC Rising
SCLK Falling to SDATA Valid
SCLK Falling to FSYNC Edge
Power down timing
PD Pulse width
PD Rising to SDATA Valid
(Note 20 )
Symbol
min
typ
max
Unit
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fSLK
fs
4.096
15.9
15.9
6.144
20.83
20.83
12.288
25.088
18.432
20.736
3.072
48
6.144
98
75
MHz
ns
ns
MHz
ns
ns
MHz
kHz
%
tSLK
tSLKL
tSLKH
tSLR
tLRS
tDLR
tDSS
tSF
tFS
159.4
65
65
30
30
16
25
50
50
30
30
fSLK
64fs
50
2fs
50
fFSYNC
tSLR
tLRF
tDSS
tSF
-20
tPDW
tPDV
150
20
1
50
20
-20
516
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
Hz
%
ns
tslk
ns
ns
ns
1/fs
Note 18 : Refer to Serial Data Interface.
Note 19 : Specified LRCK and FSYNC edges not to coincide with the rising edges of SCLK.
Note 20 : The number of LRCK rising edges after PD brought high. The value is in master mode.
In slave mode it becomes one LRCK clock(1/fs) longer.
0155-E-00
1997/1
-9-
ASAHI KASEI
[AK5352]
„ Timing Chart
0155-E-00
1997/1
- 10 -
ASAHI KASEI
[AK5352]
OPERATION OVERVIEW
„ System clock
In slave mode, MCLK(256fs/384fs), LRCK(fs) and SCLK(64fs) are required for AK5352. Use a signal divided
from the MCLK for LRCK. In master mode, only MCLK is needed. A LRCK clock rate meets standard audio
rates (32kHz, 44.1kHz, 48kHz, 96kHz). MCLK=384fs does not correspond to 96kHz sampling. In slave mode,
the MCLK should be synchronized with LRCK but the phase is free of care.
The AK5352 includes the phase detect circuit for LRCK clock, the AK5352 is reset automatically when the
synchronization is out of phase by changing the clock frequencies. (Please refer to the "Asynchronization reset.") When changing sampling frequency(fs) after power-up, AK5352 should be reset.
During the operation (PD ="H") following external clocks should never be stopped : CLK in master mode and
MCLK, SCLK and LRCK in slave mode. When the clocks stop there is a possibility that the device comes into
a malfunction because of over currents in the dynamic logic. If the external clocks are not present, the AK5352
should be in the power-down mode. ( PD ="L")
fs
32.0kHz
44.1kHz
48.0kHz
96.0kHz
Master Clock (MCLK)
256fs
SCLK(64fs)
384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
24.5760MHz
N/A
Table 1 . System Clock
2.0480MHz
2.8224MHz
3.0720MHz
6.1440MHz
„ Clock Circuit
CMODE
MCLK
L
256fs
H
384fs
AK5352 has an internal divider as shown in the above figure. The device can interface either or an external
MCLK(256fs or 384fs) by controlling CMODE pin.
0155-E-00
1997/1
- 11 -
ASAHI KASEI
[AK5352]
„ Serial Data Interface
Audio Serial Interface has four kinds of mode, it can be changed by SMODE1 and SMODE2 pins. Data format
is MSB first, 2's complement.
Figure
Figure 1
Figure 2
Figure 3
Figure 4
SMODE1
L
H
L
H
SMODE2
Mode
L
Slave Mode: 20bit, MSB justified
2
L
Master Mode: Similar to I S
2
H
Slave Mode: I S
2
H
Master Mode: I S
Table 2 . Serial Interface
L/R polarity
Lch=H, Rch=L
Lch=H, Rch=L
Lch=L, Rch=H
Lch=L, Rch=H
1) SLAVE mode
An output channel is defined by LRCK. Both channel data are output in sequence, in order of the Lch first then
Rch at the rate of fs. Data bits are clocked out via the SDATA pin at SCLK rate. Figure 1 and Figure 3 shows
data output timing at SCLK=64fs. FSYNC enables SCLK to start clocking out data. The MSB is clocked out by
2
the LRCK edge. SCLK causes the ADC to output succeeding bits when FSYNC is high. However, as I S slave
mode ignores FSYNC, it should hold "L" or "H".
2) MASTER mode
In MASTER mode, the A/D converter is driven from a master clock(MCLK:256fs/384fs) and outputs all other
clocks(LRCK, SCLK). The falling edge of SCLK causes the ADC to output each bit. Figure 2 and Figure 4
shows the output timing. 2x fs clock of 50% duty is output via the FSYNC pin. FSYNC rises one SCLK cycle
after the transition of LRCK edges and stays high during 16 serial clocks(16*tSLK). Upper 16 bit data is output
during FSYNC "H", lower 4 bit is output after FSYNC "L" transition.
Figure 1 . Data Output Timing (Slave mode)
0155-E-00
1997/1
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ASAHI KASEI
[AK5352]
0155-E-00
1997/1
- 13 -
ASAHI KASEI
[AK5352]
„ Power-down mode
The AK5352 has to be reset once by bringing PD "L" upon power-up. All internal registers of the digital filter
and so on in the AK5352 are reset by this operation. When exiting the power-down mode( PD ="H"), the
internal timing starts clocking by first MCLK "↑ "(rising edge). In master mode internal counter starts at once, in
slave mode internal counter starts after synchronizing with the first rising edge of LRCK. The serial output data
is available after 516 counting clock of LRCK cycle.
„ Asynchronization-reset
In slave mode, if the phase difference between LRCK and internal control signals is larger than +1/16 ∼ -1/16
of word period(1/fs), the synchronization of internal control signals with LRCK is done automatically at the first
rising edge of LRCK.
„ High Pass Filter(HPFE pin)
The AK5352 has a Digital High Pass Filter(HPF) for DC-offset cancel. When HPFE pin goes "H", HPF is
enabled. The cut-off frequency of the HPF is 1Hz(@fs=48kHz). It also scales with the sampling frequency(fs).
The HPF can be disabled by bringing HPFE pin "L". In this case, the AK5352 has the DC-offset of a few mV.
0155-E-00
1997/1
- 14 -
ASAHI KASEI
[AK5352]
SYSTEM DESIGN
Figure 5 shows the system connection diagram. Figure 6 shows the input buffer circuit. An evaluation
board[AKD5351/2] is available which demonstrates the optimum layout, power supply arrangement and
measurement results.
Figure 5 . System Connection Diagram Example
NOTE: +5V Analog should be powered the same time or earlier than +5V Digital.
Figure 6 . Input Buffer Circuit Example
0155-E-00
1997/1
- 15 -
ASAHI KASEI
[AK5352]
„ Grounding and Power Supply Decoupling
The AK5352 requires careful attention to power supply and grounding arrangements. The VA and VB are
connected together through the chip substrate and have several ohm resistance. The power to VB should
come up at the same time or faster than the power to VD, when they are fed separately to the device (Figure 5 ).
As to the connections of decoupling capacitors, refer to Figure 5 . The 0.1uF of decoupling capacitors
connected power supply pins should be as near as possible to the power supply pin.
As AINL± pins is near VD pin, ground pattern should be inserted between VD line and AINL±lines to avoid
digital noise coupling. Refer to evaluation board manual of AKD5352/1 Rev.B about board layout.
„ Analog connections
Analog signal is differentially input into the modulator via the AIN+ and the AIN- pins. The input voltage is the
difference between AIN+ and AIN- pins. The full-scale of each pin is ±3.47Vp-p on its reference
voltage(VREF). In case that the positive input is more than its full-scale, the AK5352 outputs positive
7FFFFH(Hex, Full-scale). In case that the negative input is more than its full-scale, the AK5352 outputs
negative 80000H(Hex, Full- scale). In case of an ideal value of no input, outputs 00000H(@20bit). DC offset is
removed by internal HPF.
AK5352 samples the analog inputs at 3.072MHz with fs=48kHz. The digital filter rejects all noise between
26.5kHz and 3.0455MHz. However, the filter will not reject frequencies right around 3.072MHz ( and multiples
of 3.072MHz). Most audio signals do not have significant noise energy at 3.072MHz. Hence, a simple RC filter
is sufficient to attenuate any noise energy at 3.072MHz.
The reference voltage for A/D converter is supplied from the VREF pin at VA reference. In order to eliminate
the effects of high frequency noise on the VREF pin, a 10uF or less electrolytic capacitor and a 0.1uF ceramic
capacitor should be connected parallel between the VREF and the VA pins. No current should be driven from
the VREF pin.
The AK5352 accepts +5V supply voltage. Any voltage which exceeds the upper limit of (VA+)+0.3V and lower
limit of AGND-0.3V and any current beyond 10mA for the analog input pins(AINL±, AINR±) should be avoided.
Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals
at or beyond these limits.
Use caution specially in case of using ±15V in surrounding analog circuit.
„ Digital Connections
To minimize digital originated noise, connect the ADC digital outputs only to CMOS inputs. Logic families of
4000B, 74HC, 74AC, 74ACT and 74HCT series are suitable.
„ Multiple AK5352
In systems where multiple ADC's are required, care must be taken to insure the internal clocks are synchronized
between converters to make simultaneous sampling. In slave mode, synchronous sampling is achieved by supplying
the same MCLK and LRCK to all converters. In master mode, the same PD signal is supplied to each ADC. The PD
state is released at the first rising edge of MCLK after bringing PD into high. Hence, if the rising edge of PD and rising
edge of MCLK coincides together the sampling difference among the ADC's modulator would occur. The difference
could be 1/256fs in the sampling clock(64fs) of the modulator, typically 81ns at fs=48kHz.
0155-E-00
1997/1
- 16 -
ASAHI KASEI
[AK5352]
PACKAGE
z 24pin VSOP (Unit: mm)
„ Material & Lead finish
Package:
Lead-frame:
Lead-finish:
Epoxy
Copper
Soldering plate
0155-E-00
1997/1
- 17 -
ASAHI KASEI
[AK5352]
MARKING
Contents of AAXXXX
AA:
Lot#
XXXX: Date Code
0155-E-00
1997/1
- 18 -
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
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