NSC LMV602MMNOPB Low power general purpose, 2.7v operational amplifier Datasheet

LMV601, LMV602, LMV604
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
LMV601/LMV602/LMV604 1 MHz, Low Power General Purpose, 2.7V Operational Amplifiers
Check for Samples: LMV601, LMV602, LMV604
FEATURES
DESCRIPTION
•
The LMV601/LMV602/LMV604 are single, dual, and
quad low voltage, low power Operational Amplifiers.
They are designed specifically for low voltage general
purpose applications. Other important product
characteristics are low input bias current, rail-to-rail
output, and wide temperature range. The
LMV601/LMV602/LMV604 have 29nV Voltage Noise
at 10KHz, 1MHz GBW, 1.0V/μs Slew Rate, 0.25mV
Vos. The LMV601/2/4 operates from a single supply
voltage as low as 2.7V, while drawing 100uA (typ)
quiescent current. In shutdown mode the current can
be reduced to 45pA.
1
2
•
•
•
•
•
•
(Typical 2.7V Supply Values; Unless Otherwise
Noted)
Ensured 2.7V and 5V Specifications
Supply Current (Per Amplifier) 100μA
Gain Bandwidth Product 1.0MHz
Shutdown Current (LMV601) 45pA
Turn-On Time from Shutdown (LMV601) 5μs
Input Bias Current 20fA
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
The industrial-plus temperature range of −40°C to
125°C allows the LMV601/LMV602/LMV604 to
accommodate a broad range of extended
environment applications.
Cordless/Cellular Phones
Laptops
PDAs
PCMCIA/Audio
Portable/Battery-Powered Electronic
Equipment
Supply Current Monitoring
Battery Monitoring
Buffer
Filter
Driver
The LMV601 offers a shutdown pin that can be used
to disable the device. Once in shutdown mode, the
supply current is reduced to 45pA (typical).
The LMV601 is offered in the tiny 6-Pin SC70
package, the LMV602 in space saving 8-Pin VSSOP
and SOIC, and the LMV604 in 14-Pin TSSOP and
SOIC. These small package amplifiers offer an ideal
solution for applications requiring minimum PCB
footprint. Applications with area constrained PC board
requirements include portable and battery operated
electronics.
Sample and Hold Circuit
V
+
V
+
-
VIN
VOUT
+
+
SAMPL
E
CLOCK
C = 200pF
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
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Absolute Maximum Ratings (1) (2)
Machine Model
ESD Tolerance (3)
200V
Human Body Model
2000V
Differential Input Voltage
± Supply Voltage
Supply Voltage (V + -V −)
6.0V
Output Short Circuit to V
+
See (4)
Output Short Circuit to V
−
See (5)
−65°C to 150°C
Storage Temperature Range
Junction Temperature
(6)
Mounting Temperature
(1)
(2)
(3)
(4)
(5)
(6)
150°C
Infrared or Convection Reflow (20 sec.)
235°C
Wave Soldering Lead Temp. (10 sec.)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Shorting output to V+ will adversely affect reliability.
Shorting output to V-will adversely affect reliability.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
Supply Voltage
2.7V to 5.5V
−40°C to 125°C
Temperature Range
Thermal Resistance (θ JA)
(1)
2
6-Pin SC70
414°C/W
8-Pin SOIC
190°C/W
8-Pin VSSOP
235°C/W
14-Pin TSSOP
155°C/W
14-Pin SOIC
145°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
2.7V DC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = V+/2, VO = V+/2 and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
VOS
Typ (3)
Max (2)
LMV601
0.25
4
LMV602/LMV604
0.55
5
Parameter
Input Offset Voltage
Conditions
Min (2)
Units
mV
TCVOS
Input Offset Voltage Average
Drift
1.7
µV/°C
IB
Input Bias Current
0.02
pA
IOS
Input Offset Current
IS
Supply Current
6.6
Per Amplifier
Shutdown Mode, VSD = 0V
(LMV601)
fA
100
170
45pA
1μA
μA
CMRR
Common Mode Rejection Ratio
0V ≤ VCM ≤ 1.7V
0V ≤ VCM ≤ 1.6V
80
dB
PSRR
Power Supply Rejection Ratio
2.7V ≤ V+ ≤ 5V
82
dB
VCM
Input Common Mode Voltage
For CMRR ≥ 50dB
AV
Large Signal Voltage Gain
RL = 10kΩ to 1.35V
VO
Output Swing
RL = 10kΩ to 1.35V
0
Output Short Circuit Current
5.0
32
Sourcing
LMV604
24
Sinking
24
Turn-on Time from Shutdown
(LMV601)
VSD
Shutdown Pin Voltage Range
ON Mode (LMV601)
Shutdown Mode (LMV601)
(1)
(2)
(3)
V
dB
30
5.3
Sourcing
LMV601/LMV602
ton
1.7
113
30
IO
−0.2 to 1.9
(Range)
mV
mA
μs
5
1.7 to 2.7
2.4 to 2.7
0 to 1
0 to 0.8
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
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2.7V AC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 2.7V, V− = 0V, VCM = V+/2, VO = V+/2 and RL > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Min (2)
Conditions
Typ (3)
Max (2)
Units
(4)
1.0
V/μs
SR
Slew Rate
RL = 10kΩ,
GBW
Gain Bandwidth Product
RL = 100kΩ, CL = 200pF
1.0
MHz
Φm
Phase Margin
RL = 100kΩ
72
deg
Gm
Gain Margin
RL = 100kΩ
20
dB
en
Input-Referred Voltage Noise
f = 1kHz
40
nV/√Hz
in
Input-Referred Current Noise
f = 1kHz
0.001
pA/√Hz
THD
Total Harmonic Distortion
f = 1kHz, AV = +1
RL = 600Ω, VIN = 1VPP
0.017
%
(1)
(2)
(3)
(4)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Connected as voltage follower with 2VPP step input. Number specified is the slower of the positive and negative slew rates.
5V DC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VO = V+/2 and R L > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
VOS
Input Offset
Voltage
TCVOS
Typ (3)
Max (2)
LMV601
0.25
4
LMV602/LMV604
0.70
5
Parameter
Conditions
Min (2)
Units
mV
Input Offset
Voltage Average
Drift
1.9
µV/°C
IB
Input Bias Current
0.02
pA
IOS
Input Offset
Current
6.6
fA
IS
Supply Current
107
200
μA
Shutdown Mode,
VSD = 0V
(LMV601)
0.033
1
μA
86
dB
82
dB
Per Amplifier
CMRR
Common Mode
Rejection Ratio
0V ≤ VCM ≤ 4.0V
0V ≤ VCM ≤ 3.9V
PSRR
Power Supply
Rejection Ratio
2.7V ≤ V+ ≤ 5V
VCM
Input Common
Mode Voltage
For CMRR ≥
50dB
AV
Large Signal
Voltage Gain (4)
RL = 10kΩ to 2.5V
VO
Output Swing
RL = 10kΩ to 2.5V
0
(1)
(2)
(3)
(4)
4
Output Short
Circuit Current
4
116
7
30
IO
−0.2 to 4.2
(Range)
dB
30
7
Sourcing
113
Sinking
75
V
mV
mA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
RL is connected to mid-supply. The output voltage is GND + 0.2V ≤ VO ≤ V+ −0.2V
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
5V DC Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VO = V+/2 and R L > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
ton
Turn-on Time
from Shutdown
(LMV601)
VSD
Shutdown Pin
Voltage Range
ON Mode
(LMV601)
Shutdown Mode
(LMV601)
Min (2)
Typ (3)
Max (2)
5
Units
µs
3.1 to 5
4.5 to 5.0
0 to 1
0 to 0.8
V
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5V AC Electrical Characteristics (1)
Unless otherwise specified, all limits ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, VO = V+/2 and R L > 1MΩ.
Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
SR
Slew Rate
RL = 10kΩ,
GBW
Gain-Bandwidth Product
Φm
Phase Margin
Gm
Min (2)
Typ (3)
(4)
Max (2)
Units
1.0
V/µs
RL = 10kΩ, CL = 200pF
1.0
MHz
RL = 100kΩ
70
deg
Gain Margin
RL = 100kΩ
20
dB
en
Input-Referred Voltage Noise
f = 1kHz
39
nV/√Hz
in
Input-Referred Current Noise
f = 1kHz
0.001
pA/√Hz
THD
Total Harmonic Distortion
f = 1kHz, AV = +1
RL = 600Ω, VIN = 1VPP
0.012
%
(1)
(2)
(3)
(4)
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No assurance of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA.
All limits are ensured by testing or statistical analysis.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
Connected as voltage follower with 2VPP step input. Number specified is the slower of the positive and negative slew rates.
Connection Diagrams
1
6
2
5
+IN
+
V
SHDN
GND
3
-IN
4
OUT
Figure 1. 6-Pin SC70 – Top View
See Package Number DCK
Figure 2. 8-Pin VSSOP/SOIC – Top View
See Package Number DGK or D
Figure 3. 14-Pin TSSOP/SOIC Top View
See Package Number PW or D
6
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
Typical Performance Characteristics
Supply Current
vs.
Supply Voltage (LMV601)
Input Current
vs.
Temperature
150
1000
VS = 5V
100
130
125°C
INPUT CURRENT (pA)
SUPPLY CURRENT (PA)
140
85°C
120
110
100
90
80
25°C
10
1
.1
70
.01
-40°C
60
.001
-40 -20
50
2.5
3
3.5
4.5
4
SUPPLY VOLTAGE (V)
5
Figure 5.
Output Voltage Swing
vs.
Supply Voltage
Output Voltage Swing
vs.
Supply Voltage
7.0
RL = 10k:
RL = 2k:
6.5
OUTPUT VOLTAGE FROM
SUPPLY VOLTAGE (mV)
OUTPUT VOLTAGE FROM
SUPPLY VOLTAGE (mV)
32
30
NEGATIVE SWING
26
24
POSITIVE SWING
22
POSITIVE SWING
5.5
5.0
4.5
NEGATIVE SWING
4.0
3.0
3
3.5
4
4.5
SUPPLY VOLTAGE (V)
2.5
5
3.5
3
Figure 6.
Figure 7.
ISOURCE
vs.
VOUT
ISOURCE
vs.
VOUT
VS = 2.7V
5
4.5
4
SUPPLY VOLTAGE (V)
100
-40°C
25°C
VS = 5V
1
0
10
125°C
1
85°C
0.1
ISOURCE (mA)
ISOURCE (mA)
6.0
3.5
20
2.5
10
0
20 40 60 80 100 120 140
TEMPERATURE (°)
Figure 4.
34
28
0
-40°C
85°C
125°C
1
25°C
0.1
0.0
1
0.00
10.00
0.
0.01
1
10
1
1
+
OUTPUT VOLTAGE REFERENCED TO V (V)
0.01
0.001
0.01
0.1
10
1
+
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
ISINK
vs.
VOUT
100
100
-40°C
VS = 5V
-40°C
VS = 2.7V
ISINK
vs.
VOUT
10
10
25°C
ISINK (mA)
25°C
ISINK (mA)
1
0.1
125°C
125°C
1
85°C
0.1
0.01
85°C
0.001
0.001
0.01
0.1
1
0.01
0.001
10
0.01
0.1
OUTPUT VOLTAGE REFERENCED TO V (V)
Figure 10.
Figure 11.
VOS
vs.
VCM
VOS
vs.
VCM
3
3
VS = 2.7V
-40°C
VS = 5V
2.5
-40°C
2.5
25°C
25°C
2
2
VOS (mV)
VOS (mV)
10
1
-
-
OUTPUT VOLTAGE REFERENCED TO V (V)
85°C
1.5
125°C
85°C
1.5
1
1
0.5
0.5
125°C
0
-0.2
0.3
0.8
1.3
1.8
0
-0.2
2.3
0.5
1
VCM (V)
1.5
2.5
2
Figure 12.
Figure 13.
VIN
vs.
VOUT
VIN
vs.
VOUT
300
3
3.5 4
4.5
VCM (V)
300
VS = ±1.35V
200
INPUT VOLTAGE (PV)
INPUT VOLTAGE (PV)
200
100
0
RL = 10 k:
-100
RL = 10 k:
100
0
RL = 2 k:
-100
-200
-200
VS = ±2.5V
RL = 2 k:
-300
-1.5
-300
-1
-0.5
0
0.5
1
1.5
-3
Figure 14.
8
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-2
-1
0
1
2
3
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 15.
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Typical Performance Characteristics (continued)
CMRR
vs.
Frequency
80
VS =
5V
70
100 V = 5V, S
90 PSRR
VIN = VS/2
RL = 5k:
80
VS = 2.7V
40
30
RL = 5k:
VS = 2.7V,
+PSRR
70
PSRR (dB)
CMRR (dB)
60
50
PSRR
vs.
Frequency
60
50
VS = 5V,
+PSRR
40
30
20
20
10
10
0
0
100
10k
1k
100k
100
1M
VS = 2.7V, PSRR
10k
1k
Figure 16.
Figure 17.
Input Voltage Noise
vs.
frequency
Slew Rate
vs.
VSUPPLY
260
120
100
80
60
40
VS = 2.7V
RL = 10k:
VIN = 2VPP
1.2
1.1
RISING EDGE
1
0.9
FALLING EDGE
0.8
0.7
20
0
0.6
VS = 5V
0.5
10
1k
100
FREQUENCY (Hz)
10k
2.5
3
3.5
4
4.5
SUPPLY VOLTAGE (V)
Figure 18.
Figure 19.
Slew Rate
vs.
Temperature
Slew Rate
vs.
Temperature
1.2
RISING EDGE
1
0.8
FALLING EDGE
0.6
AV = +1
SLEW RATE (V/Ps)
1
SLEW RATE (V/Ps)
5
1.2
RISING EDGE
0.8
FALLING EDGE
0.6
0.4
RL = 10k:
0.2
10M
AV = +1
1.4
1.3
180
160
140
0.4
1M
1.5
VCM = VS/2
240
220
200
SLEW RATE (V/Ps)
INPUT VOLTAGE NOISE (nV/ Hz)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
AV = +1
RL = 10k:
VIN = 2VPP
0.2
VS = 2.7V
VIN = 2VPP
VS = 5V
0
0
-40 -20
0
20 40
60
80 100 120 140
-40 -20
TEMPERATURE (°)
Figure 20.
0
20 40
60
80 100 120 140
TEMPERATURE (°)
Figure 21.
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Typical Performance Characteristics (continued)
THD+N
vs.
Frequency
THD+N
vs.
VOUT
10
10
f = 10KHz
AV = +10
VS = 2.7V, AV = +10
VS = 2.7V, VO = 1VPP
1
THD+N (%)
THD+N (%)
1
RL = 600:
VS = 5V, VO = 2.5VPP
0.1
AV = +1
VS = 5V, AV = +10
0.1
0.01
VS = 5V, AV =
+1
VS = 2.7V, AV = +1
VS = 5V, VO = 1VPP
VS = 2.7V, VO = 1VPP
0.01
0.00
1
0.001
10
1
10k
100
1k
FREQUENCY (Hz)
100k
0.0
1
0.1
Figure 22.
Figure 23.
Open Loop Frequency Over Temperature
Open Loop Frequency Response
100
100
100
100
RL = 2k:
125°C
PHASE
80
10
1
VO (VPP)
80
PHASE
80
80
RL = 600:
60
RL = 100k:
GAIN
20
20
-40°C
0
0
GAIN (dB)
40
40
PHASE
(°)
40
40
GAIN
RL = 100k: 20
20
0
-20
-20
-40
-20
-20
RL = 2k:
25°C
VS = 5V
-40
-40
-40
RL = 2k:
VS = 2.7V
-60
10k
1k
100k
1M
FREQUENCY (Hz)
-60
10M
100k
1M
FREQUENCY (Hz)
Open Loop Frequency Response
Gain and Phase
vs.
CL
100
CL = 0
80
60
0
0
RL = 600:
-20
-20
RL = 2k:
-40
-40
VS = 5V
-60
10k
100k
1M
FREQUENCY (Hz)
-60
10M
GAIN (dB)
20
PHASE
(°)
RL = 100k:
20
40
40
CL = 100pF
GAIN
20
20
0
0
CL = 1000pF
-20
-40
-20
CL = 500pF
VS = 5V
RL = 600:
CL = 100pF
-60
1k
10k
Figure 26.
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60
CL = 500pF
40
GAIN
80
CL = 1000pF
60
RL = 100k:
40
PHASE
80
RL = 600:
60
10
0
100
RL = 2k:
PHASE
GAIN (dB)
10k
1k
Figure 25.
80
10
-60
10M
-60
Figure 24.
100
1k
0
RL = 600:
125°C
PHASE
(°)
GAIN (dB)
60
60
25°C
-40°C
PHASE
(°)
60
100k
1M
FREQUENCY (Hz)
-40
CL = 0
-60
10M
Figure 27.
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
Gain and Phase
vs.
CL
100
PHASE
Stability
vs.
Capacitive Load
VS = ±2.5V
3.5
CL = 1000pF
60
CL = 500pF
CL = 100pF
40
40
GAIN
20
20
CL = 0
0
0
CL = 1000pF
CL = 500pF
-20
-20
CL = 100pF
VS = 5V
-40
PHASE
(°)
60
CAPACITIVE LOAD (nF)
80
80
GAIN (dB)
4
100
CL = 0
AV = +1
RL = 2k:
3
VO = 100mVPP
2.5
2
1.5
1
0.5
-40
RL = 100k:
100k
1M
FREQUENCY (Hz)
-0.5 0
VO (V)
0.5
1
1.5
Stability
vs.
Capacitive Load
Non-Inverting Small Signal Pulse Response
INPUT SIGNAL
AV = +1
160
RL = 1M:
140
VO = 100mVPP
120
100
OUTPUT SIGNAL
CAPACITIVE LOAD (pF)
-1
Figure 29.
VS = ±2.5
80
60
40
20
0
-2.5 -2
-1.5
Figure 28.
200
180
-2
-1.5
-1
-0.5
0.5
0
1
(50 mV/div)
10k
1k
0
-2.5
-60
10M
-60
TA = 25°C
RL = 2k:
VS = ±2.5V
1.5
TIME (4 Ps/div)
VO (V)
Non-Inverting Large Signal Pulse Response
Non-Inverting Small Signal Pulse Response
RL = 2k:
VS = ±2.5V
OUTPUT SIGNAL
(50 mV/div)
TA = 25°C
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
Figure 31.
INPUT SIGNAL
Figure 30.
TA = 125°C
RL = 2k:
VS = ±2.5V
TIME (4 Ps/div)
TIME (4 Ps/div)
Figure 32.
Figure 33.
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Typical Performance Characteristics (continued)
OUTPUT SIGNAL
(1 V/div)
VS = ±2.5V
TA = -40°C
RL = 2k:
VS = ±2.5V
TIME (4 Ps/div)
Figure 34.
Figure 35.
Non-Inverting Large Signal Pulse Response
Inverting Small Signal Pulse Response
INPUT SIGNAL
OUTPUT SIGNAL
(50 mV/
div)
TIME (4 Ps/div)
TA = -40°C
RL = 2k:
VS = ±2.5V
(1 V/div)
OUTPUT SIGNAL
INPUT SIGNAL
RL = 2k:
TA = 25°C
RL = 2k:
VS = ±2.5V
TIME (4 Ps/div)
TIME (4 Ps/div)
Figure 36.
Figure 37.
Inverting Large Signal Pulse Response
Inverting Small Signal Pulse Response
(1 V/div)
INPUT SIGNAL
OUTPUT SIGNAL
(50 mV/
div)
INPUT SIGNAL
OUTPUT SIGNAL
Non-Inverting Small Signal Pulse Response
(50 mV/div)
TA = 125°C
INPUT SIGNAL
OUTPUT SIGNAL
INPUT SIGNAL
Non-Inverting Large Signal Pulse Response
TA = 25°C
RL = 2k:
VS = ±2.5V
TA = 125°C
RL = 2k:
VS = ±2.5V
TIME (4 Ps/div)
TIME (4 Ps/div)
Figure 38.
12
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Figure 39.
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LMV601, LMV602, LMV604
www.ti.com
SNOSC70B – APRIL 2012 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
RL = 2k:
VS = ±2.5V
TA = -40°C
RL = 2k:
VS = ±2.5V
TIME (4 Ps/div)
TIME (4 Ps/div)
Figure 40.
Figure 41.
Inverting Large Signal Pulse Response
Crosstalk Rejection
vs.
Frequency
200
VS = ±2.5V
CROSSTALK REJECTION (dB)
180
(1 V/div)
OUTPUT SIGNAL
Inverting Small Signal Pulse Response
INPUT SIGNAL
OUTPUT SIGNAL
(50 mV/
div)
(1 V/div)
TA =
125°C
INPUT SIGNAL
OUTPUT SIGNAL
INPUT SIGNAL
Inverting Large Signal Pulse Response
TA = -40°C
RL = 2k:
160
140
120
100
80
60
40
20
VS = ±2.5V
0
TIME (4 Ps/div)
100
Figure 42.
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 43.
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LMV601, LMV602, LMV604
SNOSC70B – APRIL 2012 – REVISED MARCH 2013
www.ti.com
APPLICATION SECTION
LMV601/LMV602/LMV604
The LMV601/LMV602/LMV604 family of amplifiers features low voltage, low power, and rail-to-rail output
operational amplifiers designed for low voltage portable applications. The family is designed using all CMOS
technology. This results in an ultra low input bias current. The LMV601 has a shutdown option, which can be
used in portable devices to increase battery life.
A simplified schematic of the LMV601/LMV602/LMV604 family of amplifiers is shown in Figure 44. The PMOS
input differential pair allows the input to include ground. The output of this differential pair is connected to the
Class AB turnaround stage. This Class AB turnaround has a lower quiescent current, compared to regular
turnaround stages. This results in lower offset, noise, and power dissipation, while slew rate equals that of a
conventional turnaround stage. The output of the Class AB turnaround stage provides gate voltage to the
complementary common-source transistors at the output stage. These transistors enable the device to have railto-rail output.
VDD
OUT
CLASS AB CONTROL
InP
InM
VEE
Figure 44. Simplified Schematic
CLASS AB TURNAROUND STAGE AMPLIFIER
This patented folded cascode stage has a combined class AB amplifier stage, which replaces the conventional
folded cascode stage. Therefore, the class AB folded cascode stage runs at a much lower quiescent current
compared to conventional folded cascode stages. This results in significantly smaller offset and noise
contributions. The reduced offset and noise contributions in turn reduce the offset voltage level and the voltage
noise level at the input of the LMV601/LMV602/LMV604. Also the lower quiescent current results in a high openloop gain for the amplifier. The lower quiescent current does not affect the slew rate of the amplifier nor its ability
to handle the total current swing coming from the input stage.
The input voltage noise of the device at low frequencies, below 1kHz, is slightly higher than devices with a BJT
input stage; However the PMOS input stage results in a much lower input bias current and the input voltage
noise drops at frequencies above 1kHz.
SAMPLE AND HOLD CIRCUIT
The lower input bias current of the LMV601 results in a very high input impedance. The output impedance when
the device is in shutdown mode is quite high. These high impedances, along with the ability of the shutdown pin
to be derived from a separate power source, make LMV601 a good choice for sample and hold circuits. The
sample clock should be connected to the shutdown pin of the amplifier to rapidly turn the device on or off.
14
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www.ti.com
SNOSC70B – APRIL 2012 – REVISED MARCH 2013
Figure 45 shows the schematic of a simple sample and hold circuit. When the sample clock is high the first
amplifier is in normal operation mode and the second amplifier acts as a buffer. The capacitor, which appears as
a load on the first amplifier, will be charging at this time. The voltage across the capacitor is that of the noninverting input of the first amplifier since it is connected as a voltage-follower. When the sample clock is low the
first amplifier is shut off, bringing the output impedance to a high value. The high impedance of this output, along
with the very high impedance on the input of the second amplifier, prevents the capacitor from discharging. There
is very little voltage droop while the first amplifier is in shutdown mode. The second amplifier, which is still in
normal operation mode and is connected as a voltage follower, also provides the voltage sampled on the
capacitor at its output.
V
+
V
+
-
-
VOUT
+
+
VIN
SAMPL
E
CLOCK
C = 200pF
Figure 45. Sample and Hold Circuit
SHUTDOWN FEATURE
The LMV601 is capable of being turned off in order to conserve power and increase battery life in portable
devices. Once in shutdown mode the supply current is drastically reduced, 1µA maximum, and the output will be
"tri-stated."
The device will be disabled when the shutdown pin voltage is pulled low. The shutdown pin should never be left
unconnected. Leaving the pin floating will result in an undefined operation mode and the device may oscillate
between shutdown and active modes.
VOUT
(1 V/div)
VSHDN
The LMV601 typically turns on 2.8µs after the shutdown voltage is pulled high. The device turns off in less than
400ns after shutdown voltage is pulled low. Figure 46 and Figure 47 show the turn-on and turn-off time of the
LMV601, respectively. In order to reduce the effect of the capacitance added to the circuit by the scope probe, in
the turn-off time circuit a resistive load of 600Ω is added. Figure 48 and Figure 49 show the test circuits used to
obtain the two plots.
VS = 5V
TIME (400 ns/div)
Figure 46. Turn-on Time
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LMV601, LMV602, LMV604
SNOSC70B – APRIL 2012 – REVISED MARCH 2013
www.ti.com
RL = 600:
VOUT
(1 V/div)
VSHDN
VS = 5V
TIME (1 Ps/div)
Figure 47. Turn-off Time
+
V
+
VOUT
SHDN
+
-
VIN = VS/2
Figure 48. Turn-on Time
V
+
+
VOUT
SHDN
RL = 600:
+
-
VIN = VS/2
Figure 49. Turn-off Time
LOW INPUT BIAS CURRENT
The LMV601/LMV602/LMV604 Amplifiers have a PMOS input stage. As a result, they will have a much lower
input bias current than devices with BJT input stages. This feature makes these devices ideal for sensor circuits.
A typical curve of the input bias current of the LMV601 is shown in Figure 50.
200
VS = 5V
TA = 25°C
INPUT BIAS (fA)
100
0
-100
-200
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
VCM (V)
Figure 50. Input Bias Current vs. VCM
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SNOSC70B – APRIL 2012 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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17
PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMV601MG/NOPB
ACTIVE
SC70
DCK
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AUA
LMV601MGX/NOPB
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AUA
LMV602MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV60
2MA
LMV602MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV60
2MA
LMV602MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AC9A
LMV602MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AC9A
LMV604MA/NOPB
ACTIVE
SOIC
D
14
55
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV604MA
LMV604MAX/NOPB
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV604MA
LMV604MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV604
MT
LMV604MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LMV604
MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
22-Mar-2013
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LMV601MG/NOPB
SC70
DCK
6
1000
178.0
LMV601MGX/NOPB
SC70
DCK
6
3000
LMV602MAX/NOPB
SOIC
D
8
2500
LMV602MM/NOPB
VSSOP
DGK
8
LMV602MMX/NOPB
VSSOP
DGK
B0
(mm)
K0
(mm)
P1
(mm)
8.4
2.25
2.45
1.2
4.0
178.0
8.4
2.25
2.45
1.2
330.0
12.4
6.5
5.4
2.0
1000
178.0
12.4
5.3
3.4
8
3500
330.0
12.4
5.3
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
1.4
8.0
12.0
Q1
3.4
1.4
8.0
12.0
Q1
LMV604MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
LMV604MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV601MG/NOPB
SC70
DCK
6
1000
210.0
185.0
35.0
LMV601MGX/NOPB
SC70
DCK
6
3000
210.0
185.0
35.0
LMV602MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LMV602MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV602MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV604MAX/NOPB
SOIC
D
14
2500
367.0
367.0
35.0
LMV604MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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