Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 LMX2492/LMX2492-Q1 14 GHz Low Noise Fractional N PLL with Ramp/Chirp Generation 1 Features 3 Description • • • • • • • • • • The LMX2492/92-Q1 is a low noise 14 GHz wideband delta-sigma fractional N PLL with ramp and chirp generation. It consists of a phase frequency detector, programmable charge pump, and high frequency input for the external VCO. The LMX2492/92-Q1 supports a broad and flexible class of ramping capabilities, including FSK, PSK, and configurable piecewise linear FM modulation profiles of up to 8 segments. It supports fine PLL resolution and fast ramp with up to a 200 MHz phase detector rate. The LMX2492/92-Q1 allows any of its registers to be read back. The LMX2492/92-Q1 can operate with a single 3.3 V supply. Moreover, supporting up to 5.25 V charge pump can eliminate the need of external amplifier, leading to a simpler solution with improved phase noise performance. 1 2 • • • • • • • -227 dBc/Hz Normalized PLL Noise 500 MHz - 14 GHz Wideband PLL 3.15 - 5.25 V Charge Pump PLL Supply Versatile Ramp / Chirp Generation 200 MHz Max Phase Detector Frequency FSK / PSK Modulation Pin Digital Lock Detect Single 3.3 V Supply Capability Automotive 125°C Q100 Grade 1 Qualification Non-Automotive (LMX2492) Option Applications Automotive FMCW Radar Military Radar Microwave Backhaul Test and Measurement Satellite Communications Wireless Infrastructure Sampling Clock for High Speed ADC/DAC Device Information PART NUMBER PACKAGE BODY SIZE (NOM) LMX2492-Q1RTW WQFN (24) 4.00 mm x 4.00 mm LMX2492RTW WQFN (24) 4.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic OSCin 2X R Divider (16 bit) 51 : Phase Comp GND/OSCin* 51 : Charge Pump CPout C2_LF C1_LF Vcp GND (x3) R2_LF CLK DATA LE MICROWIRE Interface 18 : Fin Fin* MOD 36 : 18 : To Circuit N Divider (18 bit) TRIG1 TRIG2 18 : Vcc (x5) CE MUX Modulation Generator 6' Compensation (24 bit) 68 : 51 : MUXout 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Absolute Maximum Ratings................................... 4 Storage Conditions.................................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information ................................................. 4 Electrical Characteristics .......................................... 5 Timing Requirements, Programming Interface (CLK, DATA, LE) .................................................................. 6 7.8 Typical Characteristics ............................................. 7 8 Detailed Description .............................................. 9 8.1 8.2 8.3 8.4 8.5 Overview ................................................................... 9 Functional Block Diagram ......................................... 9 Feature Description................................................... 9 Device Functional Modes........................................ 13 Programming........................................................... 14 8.6 8.7 8.8 8.9 8.10 8.11 9 Register Map........................................................... Register Field Descriptions ..................................... Lock Detect and Charge Pump Monitoring............. TRIG1,TRIG2,MOD, and MUXout Pins .................. Ramping Functions ............................................... Individual Ramp Controls ...................................... 14 18 21 22 24 26 Applications and Implementation ...................... 27 9.1 Application Information............................................ 27 9.2 Typical Applications ................................................ 27 10 Power Supply Recommendations ..................... 33 11 Layout................................................................... 34 11.1 Layout Guidelines ................................................. 34 11.2 Layout Example .................................................... 34 12 Device and Documentation Support ................. 35 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 35 35 35 35 35 35 35 13 Mechanical, Packaging, and Orderable Information ........................................................... 36 5 Revision History Changes from Revision A (June 2014) to Revision B Page • Changed Changed CLK, DATA, and LE to right Input/Output Format .................................................................................. 3 • Changed terminal to pin ........................................................................................................................................................ 3 • Changed Same specs, but new format tables for storage and ESD Ratings ....................................................................... 4 • Changed TYP to NOM ........................................................................................................................................................... 4 • Added Added comment for lower voltage operation. ............................................................................................................. 5 • Changed Fixed Diagram. A14 is hightest bit .......................................................................................................................... 6 • Added note in Applications and Implementation section ..................................................................................................... 27 Changes from Original (March 2014) to Revision A Page • Changed from 35 to 10........................................................................................................................................................... 6 • Changed from 10 to 4............................................................................................................................................................. 6 • Changed from 10 to 4............................................................................................................................................................. 6 • Changed from 25 to 10 .......................................................................................................................................................... 6 • Changed from 25 t o10........................................................................................................................................................... 6 Ö 2 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 6 Pin Configuration and Functions CPout Rset Vcp TRIG2 TRIG1 Vcc 24 Pin WQFN RTW Package (Top View) 24 23 22 21 20 19 GND 1 18 Vcc GND 2 17 MUXout GND 3 16 LE Pin 0 (Ground Substrate) Fin 4 Fin* 5 14 CLK Vcc 6 13 CE 8 9 10 11 12 Vcc OSCin GND/OSCin* GND MOD Vcc 7 15 DATA Pin Functions PIN NUMBER NAME I/O DESCRIPTION 0 DAP GND Die Attach Pad. Connect to PCB ground plane. 1 GND GND Ground for charge pump. 2,3 GND GND Ground for Fin Buffer 4,5 Fin Fin* Input Complimentary high frequency input pins. Should be AC coupled. If driving single-ended, impedance as seen from Fin and Fin* pins looking outwards from the part should be roughly the same. 6 Vcc Supply Power Supply for Fin Buffer 7 Vcc Supply Supply for On-chip LDOs 8 Vcc Supply Supply for OSCin Buffer 9 OSCin Input 10 GND/ OSCin* GND/Input GND Reference Frequency Input Complimentary input for OSCin. If not used, it is recommended to match the termination as seen from the OSCin terminal looking outwards. However, this may also be grounded as well. 11 GND 12 MOD Ground for OSCin Buffer 13 CE Input Chip Enable 14 CLK Input Serial Programming Clock. 15 DATA Input Serial Programming Data 16 LE Input Serial Programming Latch Enable 17 MUXout 18 Vcc Supply Supply for delta sigma engine. 19 Vcc Supply Supply for general circuitry. 20 TRIG1 Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics. 21 TRIG2 Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics. 22 Vcp Supply 23 Rset NC 24 CPout Output Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics. Input/Output Multiplexed Pin for Ramp Triggers, FSK/PSK Modulation, FastLock, Readback, and Diagnostics. Power Supply for the charge pump. No connect. Charge Pump Output Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 3 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Vcp Supply voltage for charge pump Vcc 5.5 V CPout Charge pump output pin -0.3 Vcp V Vcc All Vcc pins -0.3 3.6 V Others All other I/O pins -0.3 Vcc + 0.3 V TSolder Lead temperature (solder 4 seconds) 260 °C TJunction Junction temperature 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Storage Conditions applicable before the DMD is installed in the final product Tstg DMD storage temperature MSL Moisture sensitivity level MIN MAX UNIT -65 150 °C 3 n/a 7.3 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Vcc PLL supply voltage PARAMETER DEVICE 3.15 3.3 3.45 V Vcp Charge pump supply voltage Vcc 5.25 V TA Ambient temperature TJ Junction temperature LMX2492 -40 85 LMX2492-Q1 -40 125 LMX2492 -40 125 LMX2492-Q1 -40 135 °C °C 7.5 Thermal Information LMX2492 RTW (WQFN ) 24 PINS THERMAL METRIC (1) RθJA Junction-to-ambient thermal resistance 39.4 RθJC Junction-to-case thermal resistance 7.1 ψJB Junction-to-board characterization parameter 20 (1) 4 UNIT °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 7.6 Electrical Characteristics (3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C. -40°C ≤ TA ≤ 85 °C for the LMX2492 and -40°C ≤ TA ≤ 125 °C for the LMX2492-Q1 ; except as specified.) PARAMETER CONDITIONS All Vcc Pins Icc Current Consumption Vcp Pin IccPD fOSCin vOSCin Current Frequency for OSCin terminal Voltage for OSCin Pin (1) Fpd = 100 MHz 50 Fpd = 200 MHz 55 Kpd = 0.1 mA 2 Kpd = 1.6 mA 10 Kpd = 3.1 mA 19 Frequency for FinPin Power for Fin Pin fPD Phase Detector Frequency PN10kHz Normalized PLL 1/f Noise (3) ICPoutTRI Charge Pump Leakage Tristate Leakage OSC_DIFFR=0, Doubler Enabled 10 300 OSC_DIFFR=1, Doubler Disabled 10 1200 OSC_DIFFR=1, Doubler Enabled 10 600 LMX2492-Q1 Version Only Single Ended XO 30 MHz ≤ fOSCin ≤ 100 MHz 0.24 Vcc-0.5 All Other Cases 0.5 Vcc-0.5 500 14000 MHz -5 5 dBm 200 MHz Charge Pump Mismatch Normalized to 10 kHz offset for a 1 GHz carrier. (4) Charge Pump Current VCPout = Vcp / 2 (4) MHz Vpp -227 dBc/Hz -120 dBc/Hz VCPout = Vcp / 2 nA 5% 0.1 … CPG=31X (1) (2) (3) 600 10 CPG=1X ICPout mA 3 (3) PLL Figure of Merit UNIT 10 Single-Ended Operation PN1Hz MAX OSC_DIFFR=0, Doubler Disabled (2) pFin TYP 45 POWERDOWN fFin ICPoutMM MIN Fpd = 10 MHz mA 3.1 For optimal phase noise performance, a slew rate of at least 3 V/ns is recommended Tested to 13.5 GHz, Guaranteed to 14 GHz by characterization PLL Noise Metrics are measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as: PLL_Total = 10×log( 10PLL_Flat/10 + 10PLL_Flicker(Offset)/10) PLL_Flat = PN1Hz + 20×log(N) + 10×log(Fpd/1Hz) PLL_Flicker = PN10kHz - 10×log(Offset/10kHz) + 20×log(Fvco/1GHz) Charge pump mismatch varies as a function of charge pump voltage. Consult typical performance characteristics to see this variation. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 5 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ Vcc ≤ 3.45 V. Vcc ≤Vcp ≤5.25 V. Typical values are at Vcc = Vcp = 3.3 V, 25 °C. -40°C ≤ TA ≤ 85 °C for the LMX2492 and -40°C ≤ TA ≤ 125 °C for the LMX2492-Q1 ; except as specified.) PARAMETER CONDITIONS MIN TYP 0.8 x Vcc Vcc MAX UNIT LOGIC OUTPUT TERMINALS (MUXout,TRIG1,TRIG2,MOD) VOH Output High Voltage VOL Output Low Voltage V 0 0.2 x Vcc V V LOGIC INPUT TERMINALS (CE,CLK,DATA,LE,MUXout,TRIG1,TRIG2,MOD) VIH Input High Voltage 1.4 Vcc VIL Input Low Voltage 0 0.6 V IIH Input Leakage -5 5 uA TCELOW Chip enable Low Time 5 us TCEHIGH Chip enable High Time 5 us 1 7.7 Timing Requirements, Programming Interface (CLK, DATA, LE) MIN TCE Clock To LE Low Time TCS TCH NOM MAX UNIT 10 ns Data to Clock Setup Time 4 ns Data to Clock Hold Time 4 ns TCWH Clock Pulse Width High 10 ns TCWL Clock Pulse Width Low 10 ns TCES Enable to Clock Setup Time 10 ns TEWH Enable Pulse Width High 10 ns MSB DATA R/W LSB A14 A13 A12 A11 A0 D7 D1 D0 CLK tCES tCS tCH tCWH tCE tCWL LE tEWH Figure 1. Serial Data Input Timing There are several other considerations for programming: • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to an actual counter. • If no LE signal is given after the last data bit and the clock is kept toggling, then these bits will be read into the next lower register. This eliminates the need to send the address each time. • A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals • Timing specifications also apply to readback. Readback can be done through the MUXout, TRIG1, TRIG2, or MOD terminals. 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 5 5 4 4 Charge Pump Current (mA) Charge Pump Current (mA) 7.8 Typical Characteristics 3 2 1 0 ±1 ±2 ±3 Kpd = 8x Kpd = 16x Kpd = 31x ±4 ±5 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Charge Pump Voltage (V) 3.0 3 2 1 0 ±1 ±2 ±3 Kpd = 8x Kpd = 16x Kpd = 31x ±4 ±5 3.3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Charge Pump Voltage (V) C001 For a charge pump supply of 3.3 V, optimal performance is for a typical charge pump output voltage between 0.5 and 2.8 volts. Figure 2. Charge Pump Current for Vcp = 3.3 V 5.5 C002 For a charge pump supply voltage of 5 volts or higher, optimal performance is typically for a charge pump output voltage between 0.5 and 4.5 volts. Figure 3. Charge Pump Current for Vcp = 5.5 V 0 ±5 Power (dBm) ±10 ±15 ±20 ±25 ±30 ±35 ±40 0 2 4 6 8 10 12 14 16 Frequency (GHz) C001 Typical value of lowest power level as a function of frequency. Design to electrical specifications for input sensitivity, not typical performance graphs. Figure 4. Fin Input Sensitivity Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 7 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Typical Characteristics (continued) ±90 Theoretical 1/f Theoretical Flat Theoretical Model Phase Noise (dBc/Hz) ±95 Measurement ±100 ±105 ±110 ±115 ±120 1k 10k 100k 1M Offset (Hz) C001 This plot is for a phase detector of 100 MHz, 2 MHz loop bandwidth, and VCO at 9600 MHz. However, the plot shown is the divide by 2 port at 4800 MHz. The input was a 100 MHz Wenzel Oscillator. The model shows this phase noise has a figure of merit of -227 dBc/Hz and a normalized 1/f noise of -120.5 dBc/Hz. The charge pump supply was 5 V and the charge pump output voltage was 1.34 V. Figure 5. LMX2492/92-Q1 Phase Noise for Fpd =100 MHz, Fvco = 9600 MHz/2 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 8 Detailed Description 8.1 Overview The LMX2492/92-Q1 is a microwave PLL, consisting of a reference input and divider, high frequency input and divider, charge pump, ramp generator, and other digital logic. The Vcc power supply pins run at a nominal 3.3 volts, while the charge pump supply pin, Vcp, operates anywhere from Vcc to 5 volts. The device is designed to operate with an external loop filter and VCO. Modulation is achieved by manipulating the MASH engine. 8.2 Functional Block Diagram GND (x3) Vcc (x5) Vcp 2X OSCin R Divider (16 bit) GND/OSCin* Charge Pump Phase Comp Lock Detect Fin N Divider (18 bit) Fin* 4/5 Prescaler TRIG1 CE CLK DATA LE CPout 6' Compensation (24 bit) MICROWIRE Interface Modulation Generator MUX TRIG2 MOD MUXout 8.3 Feature Description 8.3.1 OSCin Input The reference can be applied in several ways. If using a differential input, this should be terminated differentially with a 100 ohm resistance and AC coupled to the OSCin and GND/OSCin* terminals. If driving this single-ended, then the GND/OSCin* terminal may be grounded, although better performance is attained by connecting the GND/OSCin* terminal through a series resistance and capacitance to ground to match the OSCin terminal impedance. 8.3.2 OSCin Doubler The OSCin doubler allows the input signal to the OSCin to be doubled in order to have higher phase detector frequencies. This works by clocking on both the rising and falling edges of the input signal, so it therefore requires a 50% input duty cycle. 8.3.3 R Divider The R counter is 16 bits divides the OSCin signal from 1 to 65535. If DIFF_R = 0, then any value can be chosen in this range. If DIFF_R=1, then the divide is restricted to 2,4,8, and 16, but allows for higher OSCin frequencies. 8.3.4 PLL N Divider The 16 bit N divider divides the signal at the Fin terminal down to the phase detector frequency. It contains a 4/5 prescaler that creates minimum divide restrictions, but allows the N value to increment in values of one. Modulator Order Minimum N Divide Integer Mode, 1st Order Modulator 16 2nd Order Modulator 17 3rd Order Modulator 19 4th Order Modulator 25 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 9 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.3.5 Fractional Circuitry The fractional circuitry controls the N divider with delta sigma modulation that supports a programmable first, second, third, and fourth order modulator. The fractional denominator is a fully programmable 24-bit denominator that can support any value from 1,2,..., 224, with the exception when the device is running one of the ramps, and in this case it is a fixed size of 224. 8.3.6 PLL Phase Detector and Charge Pump The phase detector compares the outputs of the R and N dividers and generates a correction voltage corresponding to the phase error. This voltage is converted to a correction current by the charge pump. The phase detector frequency, fPD, can be calculated as follows: fPD = fOSCin × OSC_2X / R. The charge pump supply voltage on this device, Vcp, can be either run at the Vcc voltage, or up to 5.25 volts in order to get higher tuning voltages to present to the VCO. 8.3.7 External Loop Filter The loop filter is external to the device and is application specific. Texas Instruments website has details on this at www.ti.com. 8.3.8 Fastlock and Cycle Slip Reduction The Fastlock™ and Cycle Slip Reduction features can be used to improved lock time. When the frequency is changed, a timeout counter can be used to engage these features for a prescribed number of phase detector cycles. During this time that the timeout counter is counting down, the device can be used to pull a terminal from high impedance to ground switch in an extra resistor (R2pLF), change the charge pump current (FL_CPG), or change the phase detector frequency. TRIG2 is recommended for switching the resistor with a setting of TRIG2_MUX = Fastlock (2) and TRIG2_PIN = Inverted/Open Drain (5). Charge Pump CPout C2_LF TRIG2 R2pLF C1_LF R2_LF Fastlock Control Parameter Normal Operation Fastlock Operation Charge Pump Gain CPG FL_CPG Device Pin (TRIG1, TRIG2, MOD, or MUXout) High Impedance Grounded The resistor and the charge pump current are changed simultaneously so that the phase margin remains the same while the loop bandwidth is by a factor of K as shown in the following table: 10 Parameter Symbol Calculation Charge Pump Gain in Fastlock FL_CPG Typically use the highest value. Loop Bandwidth Multiplier K K=sqrt(FL_CPG/CPG) External Resistor R2pLF R2 / (K-1) Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 Cycle slip reduction is another method that can also be used to speed up lock time by reducing cycle slipping. Cycle slipping typically occurs when the phase detector frequency exceeds about 100x the loop bandwidth of the PLL. Cycle slip reduction works in a different way than fastlock. To use this, the phase detector frequency is decreased while the charge pump current is simultaneously increased by the same factor. Although the loop bandwidth is unchanged, the ratio of the phase detector frequency to the loop bandwidth is, and this is helpful for cases when the phase detector frequency is high. Because cycle slip reduction changes the phase detector rate, it also impacts other things that are based on the phase detector rate, such as the fastlock timeout-counter and ramping controls. 8.3.9 Lock Detect and Charge Pump Voltage Monitor The LMX2492/92-Q1 offers two methods to determine if the PLL is in lock, charge pump voltage monitoring and digital lock detect. These features can be used individually or in conjunction to give a reliable indication of when the PLL is in lock. The output of this detection can be routed to the TRIG1, TRIG2, MOD, or MUXout terminals. 8.3.9.1 Charge Pump Voltage Monitor The charge pump voltage monitor allows the user to set low (CMP_THR_LOW) and high (CMP_THR_HIGH) thresholds for a comparator that monitors the charge pump output voltage. Vcp 3.3 V 5.0 V Threshold Suggested Level CPM_THR_LOW = (Vthresh + 0.08) / 0.085 6 for 0.5V limit CPM_THR_HIGH = (Vthresh - 0.96) / 0.044 42 for 2.8V limit CPM_THR_LOW = (Vthresh + 0.056) / 0.137 4 for 0.5V limit CPM_THR_HIGH = (Vthresh -1.23) / 0.071 46 for 4.5V limit 8.3.9.2 Digital Lock Detect Digital lock detect works by comparing the phase error as presented to the phase detector. If the phase error plus the delay as specified by the PFD_DLY bit is outside the tolerance as specified by DLD_TOL, then this comparison would be considered to be an error, otherwise passing. The DLD_ERR_CNT specifies how may errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT specifies how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets the count for the errors. The DLD_TOL value should be set to no more than half of a phase detector period plus the PFD_DLY value. The DLD_ERR_CNT and DLD_PASS_CNT values can be decreased to make the circuit more sensitive. If the circuit is too sensitive, then chattering can occur and the DLD_ERR_CNT, DLD_PASS_CNT, or DLD_TOL values should be increased. Note that if the OSCin signal goes away and there is no noise or self-oscillation at the OSCin pin, then it is possible for the digital lock detect to indicate a locked state when the PLL really is not in lock. If this is a concern, then digital lock detect can be combined with charge pump voltage monitor to detect this situation.. 8.3.10 FSK/PSK Modulation Two level FSK or PSK modulation can be created whenever a trigger event, as defined by the FSK_TRIG field is detected. This trigger can be defined as a transition on a terminal (TRIG1, TRIG2, MOD, or MUXout) or done purely in software. The RAMP_PM_EN bit defines the modulation to be either FSK or PSK and the FSK_DEV register determines the amount of the deviation. Remember that the FSK_DEV[32:0] field is programmed as the 2's complement of the actual desired FSK_DEV value. This modulation can be added to the modulation created from the ramping functions as well. RAMP_PM_EN Modulation Type Deviation 0 2 Level FSK Fpd × FSK_DEV / 224 1 2 Level PSK 360° × FSK_DEV / 224 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 11 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.3.11 Ramping Functions The LMX2492/92-Q1 supports a broad and flexible class of FMCW modulation formed by up to 8 linear ramps. When the ramping function is running, the denominator is fixed to a forced value of 224 = 16777216. The waveform always starts at RAMP0 when the LSB of the PLL_N (R16) is written to. After it is set up, it will start at the initial frequency and have piecewise linear frequency modulation that deviates from this initial frequency as specified by the modulation. Each of the eight ramps can be individually programmed. Various settings are as follows Ramp Characteristic Programming Field Name Description Ramp Length RAMPx_LEN RAMPx_DLY The user programs the length of the ramp in phase detector cycles. If RAMPx_DLY=1, then each count of RAMPx_LEN is actually two phase detector cycles. Ramp Slope RAMPx_LEN RAMPx_DLY RAMPx_INC The user does not directly program slope of the line, but rather this is done by defining how long the ramp is and how much the fractional numerator is increased per phase detector cycle. The value for RAMPx_INC is calculated by taking the total expected increase in the frequency, expressed in terms of how much the fractional numerator increases, and dividing it by RAMPx_LEN. The value programmed into RAMPx_INC is actually the two's complement of the desired mathematical value. Trigger for Next Ramp RAMPx_NEXT_TRIG The event that triggers the next ramp can be defined to be the ramp finishing or can wait for a trigger as defined by TRIG A, TRIG B, or TRIG C. Next Ramp RAMPx_NEXT This sets the ramp that follows. Waveforms are constructed by defining a chain ramp segments. To make the waveform repeat, make RAMPx_NEXT point to the first ramp in the pattern. Ramp Fastlock RAMPx_FL Ramp Flags RAMPx_FLAG This allows the ramp to use a different charge pump current or use Fastlock This allows the ramp to set a flag that can be routed to external terminals to trigger other devices. 8.3.11.1 Ramp Count If it is desired that the ramping waveform keep repeating, then all that is needed is to make the RAMPx_NEXT of the final ramp equal to the first ramp. This will run until the RAMP_EN bit is set to zero. If this is not desired, then one can use the RAMP_COUNT to specify how may times the specified pattern is to repeat. 8.3.11.2 Ramp Comparators and Ramp Limits The ramp comparators and ramp limits use programable thresholds to allow the device to detect whenever the modulated waveform frequency crosses a limit as set by the user. The difference between these is that comparators set a flag to alert the user while a ramp limits prevent the frequency from going beyond the prescribed threshold. In either case, these thresholds are expressed by programming the Extended_Fractional_Numerator. Extended_Fractional_Numerator = Fractional_Numerator + (N-N*) × 224 In the above, N is the PLL feedback value without ramping and N* is the instantaneous value during ramping. The actual value programmed is the 2's complement of Extended_Fractional_Numerator. Type Ramp Limits Ramp Comparators Programming Bit Threshold RAMP_LIMIT_LOW Lower Limit RAMP_LIMIT_HIGH Upper Limit RAMP_CMP0 RAMP_CMP1 For the ramp comparators, if the ramp is increasing and exceeds the value as specified by RAMP_CMPx, then the flag will go high, otherwise it is low. If the ramp is decreasing and goes below the value as specified by RAMP_CMPx, then the flag will go high, otherwise it will be low. 8.3.12 Power on Reset (POR) The power on reset circuitry sets all the registers to a default state when the device is powered up. This same reset can be done by programming SWRST=1. In the programming section, the power on reset state is given for all the programmable fields. 12 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 8.4 Device Functional Modes The two primary ways to use the LMX2492/92-Q1 are to run it to generate a set of frequencies 8.4.1 Continuous Frequency Generator In this mode, the LMX2492/92-Q1 generates a single frequency that only changes when the N divider is programmed to a new value. In this mode, the RAMP_EN bit is set to 0 and the ramping controls are not used. The fractional denominator can be programmed to any value from 1 to 16777216. In this kind of application, the PLL is tuned to different channels, but at each channel, the goal is to generate a stable fixed frequency. 8.4.1.1 Integer Mode Operation In integer mode operation, the VCO frequency needs to be an integer multiple of the phase detector frequency. This can be the case when the output frequency or frequencies are nicely related to the input frequency. As a rule of thumb, if this an be done with a phase detector of as high as the lesser of 10 MHz or the OSCin frequency, then this makes sense. To operate the device in integer mode, disable the fractional circuitry by programming the fractional order (FRAC_ORDER) , dithering (FRAC_DITH), and numerator (FRAC_NUM) to zero. 8.4.1.2 Fractional Mode Operation In fractional mode, the output frequency does not need to be an integer multiple of the phase detector frequency. This makes sense when the channel spacing is more narrow or the input and output frequencies are not nicely related. There are several programmable controls for this such as the modulator order, fractional dithering, fractional numerator, and fractional denominator. There are many trade-offs with choosing these, but here are some guidelines Parameter Field Name How to Choose Fractional Numerator and Denominator FRAC_NUM FRAC_DEN The first step is to find the fractional denominator. To do this, find the frequency that divides the phase detector frequency by the channel spacing. For instance, if the output ranges from 5000 to 5050 in 5 MHz steps and the phase detector is 100 MHz, then the fractional denominator is 100 MHz/5 = 20. So for a an output of 5015 MHz, the N divider would be 50 + 3/20. In this case, the fractional numerator is 3 and the fractional denominator is 20. Sometimes when dithering is used, it makes sense to express this as a larger equivalent fraction. Note that if ramping is active, the fractional denominator is forced to 224. Fractional Order FRAC_ORDER There are many trade-offs, but in general try either the 2nd or 3rd order modulator as starting points. The 3rd order modulator may give lower main spurs, but may generate others. Also if dithering is involved, it can generate phase noise. Dithering FRAC_DITH Dithering can reduce some fractional spurs, but add noise. Consult application note AN-1879 for more details on this. 8.4.2 Modulated Waveform Generator In this mode, the device can generate a broad class of frequency sweeping waveforms. The user can specify up to 8 linear segments in order to generate these waveforms. When the ramping function is running, the denominator is fixed to a forced value of 224 = 16777216 In addition to the ramping functions, there is also the capability to use a terminal to add phase or frequency modulation that can be done by itself or added on top of the waveforms created by the ramp generation functions. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 13 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.5 Programming 8.5.1 Loading Registers The device is programmed using several 24 bit registers. The first 16 bits of the register are the address, followed by the next 8 bits of data. The user has the option to pull the LE terminal high after this data, or keep sending data and it will apply this data to the next lower register. So instead of sending three registers of 24 bits each, one could send a single 40 bit register with the 16 bits of address and 24 bits of data. For that matter, the entire device could be programmed as a single register if desired. 8.6 Register Map Registers are programmed in REVERSE order from highest to lowest. Registers NOT shown in this table or marked as reserved can be written as all 0's unless otherwise stated. The POR value is the power on reset value that is assigned when the device is powered up or the SWRST bit is asserted. Table 1. Register Map Register 14 0 0 1 0x1 D7 D6 D5 D4 D3 D2 D1 D0 POR 0 0 0 1 1 0 0 0 0x18 Reserved 0 0 0 0 0x00 2 0x2 3-15 0x3 - 0xF Reserved 0 SWRST POWERDOWN[1:0] - 16 0x10 PLL_N[7:0] 0x64 17 0x11 18 0x12 19 0x13 FRAC_NUM[7:0] 0x00 20 0x14 FRAC_NUM[15:8] 0x00 21 0x15 FRAC_NUM[23:16] 0x00 22 0x16 FRAC_DEN[7:0] 0x00 23 0x17 FRAC_DEN[15:8] 0x00 24 0x18 FRAC_DEN[23:16] 0x00 25 0x19 PLL_R[7:0] 0x04 26 0x1A PLL_R[15:8] 0x00 27 0x1B 0 28 0x1C 0 29 0x1D 30 0x1E 0 CPM_ FLAGL CPM_THR_LOW[5:0] 0x0a 31 0x1F 0 CPM_ FLAGH CPM_THR_HIGH[5:0] 0x32 32 0x20 FL_TOC[7:0] 33 0x21 DLD_PASS_CNT[7:0] 34 0x22 35 0x23 36 0x24 TRIG1_MUX[4:0] TRIG1_PIN[2:0] 0x08 37 0x25 TRIG2_MUX[4:0] TRIG2_PIN[2:0] 0x10 38 0x26 MOD_MUX[4:0] MOD_PIN[2:0] 0x18 39 0x27 MUXout_MUX[4:0] MUXout_PIN[2:0] 0x38 40-57 0x28-0x39 PLL_N[15:8] 0 FRAC_ORDER[2:0] FL_CSR[1:0] 0 0x00 FRAC_DITHER[1:0] CPPOL FL_TOC[10:8] MOD_ MUX[5] Submit Documentation Feedback 1 PLL_N[17:16] PLL_R_ DIFF PFD_DLY[1:0] DLD_TOL[2:0] 0 OSC_2X TRIG2 _MUX[5] 0x00 0x08 CPG[4:0] 0x00 FL_CPG[4:0] 0x00 0x00 0x0f DLD_ERR_CNTR[4:0] MUXout _MUX[5] 0x00 TRIG1 _MUX[5] 0 Reserved 0x00 0 1 0x41 - Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 Register Map (continued) Table 1. Register Map (continued) Register 58 D7 D6 D5 D4 D3 D2 D1 D0 POR 0 RAMP_ PM_EN RAMP_ CLK RAMP_EN 0x00 0x3A RAMP_TRIG_A[3:0] 59 0x3B RAMP_TRIG_C[3:0] 60 0x3C RAMP_CMP0[7:0] 0x00 61 0x3D RAMP_CMP0[15:8] 0x00 62 0x3E RAMP_CMP0[23:16] 0x00 63 0x3F RAMP_CMP0[31:24] 0x00 64 0x40 RAMP_CMP0_EN[7:0] 0x00 65 0x41 RAMP_CMP1[7:0] 0x00 66 0x42 RAMP_CMP1[15:8] 0x00 67 0x43 RAMP_CMP1[23:16] 0x00 68 0x44 RAMP_CMP1[31:24] 0x00 69 0x45 RAMP_CMP1_EN[7:0] 70 0x46 RAMP_ LIMH[32] 71 0x47 FSK_DEV[7:0] 0x00 72 0x48 FSK_DEV[15:8] 0x00 73 0x49 FSK_DEV[23:16] 0x00 74 0x4A FSK_DEV[31:24] 0x00 75 0x4B RAMP_LIMIT_LOW[7:0] 0x00 76 0x4C RAMP_LIMIT_LOW[15:8] 0x00 77 0x4D RAMP_LIMIT_LOW[23:16] 0x00 78 0x4E RAMP_LIMIT_LOW[31:24] 0x00 79 0x4F RAMP_LIMIT_HIGH[7:0] 0xff 80 0x50 RAMP_LIMIT_HIGH[15:8] 0xff 81 0x51 RAMP_LIMIT_HIGH[23:16] 0xff 82 0x52 RAMP_LIMIT_HIGH[31:24] 0xff 83 0x53 RAMP_COUNT[7:0] 0x00 84 0x54 85 0x55 0 FSK_TRIG[1:0] RAMP_TRIG_INC[1:0] RAMP_TRIG_B[3:0] RAMP_ LIML[32] RAMP_ AUTO 0x00 0x00 FSK_ DEV[32] RAMP_ CMP1[32] RAMP_COUNT[12:8] Reserved Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 RAMP_ CMP0[32] 0x08 0x00 0x00 Submit Documentation Feedback 15 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Register Map (continued) Table 1. Register Map (continued) Register 86 0x56 87 88 D6 D5 D4 D3 D2 D1 D0 POR RAMP0_INC[7:0] 0x00 0x57 RAMP0_INC[15:8] 0x00 0x58 RAMP0_INC[23:16] 0x00 RAMP0_ DLY RAMP0_ FL 89 0x59 90 0x5A RAMP0_LEN[7:0] 91 0x5B RAMP0_LEN[15:8] 92 0x5C RAMP0_ NEXT_TRIG[1:0] 93 0x5D RAMP1_INC[7:0] 0x00 94 0x5E RAMP1_INC[15:8] 0x00 95 0x5F RAMP1_INC[23:16] 0x00 96 0x60 97 0x61 RAMP1_LEN[7:0] 98 0x62 RAMP1_LEN[15:8] 99 0x63 RAMP1_ NEXT_TRIG[1:0] 100 0x64 101 102 RAMP0_NEXT[2:0] RAMP1_ DLY RAMP1_ FL RAMP1_NEXT[2:0] RAMP0_INC[29:24] 0x00 0x00 0x00 RAMP0_ RST RAMP0_FLAG[1:0] RAMP1_INC[29:24] 0x00 0x00 0x00 0x00 RAMP1_ RST RAMP1_FLAG[1:0] 0x00 RAMP2_INC[7:0] 0x00 0x65 RAMP2_INC[15:8] 0x00 0x66 RAMP2_INC[23:16] 0x00 RAMP2 DLY RAMP2_ FL 103 0x67 104 0x68 RAMP2_LEN[7:0] 105 0x69 RAMP2_LEN[15:8] 0x6A RAMP2_ NEXT_TRIG[1:0] 106 RAMP2_NEXT[2:0] RAMP2_INC[29:24] 0x00 0x00 0x00 RAMP2_ RST RAMP2_FLAG[1:0] 0x00 107 0x6B RAMP3_INC[7:0] 0x00 108 0x6C RAMP3_INC[15:8] 0x00 109 0x6D RAMP3_INC[23:16] 0x00 RAMP3_ DLY RAMP3_ FL 110 0x6E 111 0x6F RAMP3_LEN[7:0] 112 0x70 RAMP3_LEN[15:8] 0x71 RAMP3_ NEXT_TRIG[1:0] 113 16 D7 RAMP3_NEXT[2:0] Submit Documentation Feedback RAMP3_INC[29:24] 0x00 0x00 0x00 RAMP3_ RST RAMP3_FLAG[1:0] 0x00 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 Register Map (continued) Table 1. Register Map (continued) Register 114 0x72 115 116 D7 D6 D5 D4 D3 D1 D0 POR 0x00 0x73 RAMP4_INC[15:8] 0x00 0x74 RAMP4_INC[23:16] 0x00 RAMP4_ DLY RAMP4_ FL 117 0x75 118 0x76 RAMP4_LEN[7:0] 119 0x77 RAMP4_LEN[15:8] 0x78 RAMP4_ NEXT_TRIG[1:0] 120 D2 RAMP4_INC[7:0] RAMP4_NEXT[2:0] RAMP4_INC[29:24] 0x00 0x00 0x00 RAMP4_ RST RAMP4_FLAG[1:0] 0x00 121 0x79 RAMP5_INC[7:0] 0x00 122 0x7A RAMP5_INC[15:8] 0x00 123 0x7B RAMP5_INC[23:16] 0x00 124 0x7C 125 0x7D RAMP5_LEN[7:0] 126 0x7E RAMP5_LEN[15:8] 127 0x7F RAMP5_ NEXT_TRIG[1:0] 128 0x80 129 130 RAMP5_ DLY RAMP5_ FL RAMP5_NEXT[2:0] RAMP5_INC[29:24] 0x00 0x00 0x00 RAMP5_ RST RAMP5_FLAG[1:0] 0x00 RAMP6_INC[7:0] 0x00 0x81 RAMP6_INC[15:8] 0x00 0x82 RAMP6_INC[23:16] 0x00 RAMP6_ DLY RAMP6_ FL 131 0x83 132 0x84 RAMP6_LEN[7:0] 133 0x85 RAMP6_LEN[15:8] 134 0x86 RAMP6_ NEXT_TRIG[1:0] 135 0x87 RAMP7_INC[7:0] 0x00 136 0x88 RAMP7_INC[15:8] 0x00 137 0x89 RAMP7_INC[23:16] 0x00 RAMP6_NEXT[2:0] RAMP7_ DLY RAMP7_ FL RAMP6_INC[29:24] 138 0x8A 139 0x8B RAMP7_LEN[7:0] 140 0x8C RAMP7_LEN[15:8] 141 0x8D RAMP7_ NEXT_TRIG[1:0] 142-32767 0x8E0x7fff RAMP7_NEXT[2:0] 0x00 0x00 0x00 RAMP6_ RST RAMP6_FLAG[1:0] RAMP7_INC[29:24] 0x00 0x00 0x00 0x00 RAMP7_ RST Reserved Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 RAMP7_FLAG[1:0] 0x00 0x00 Submit Documentation Feedback 17 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.7 Register Field Descriptions The following sections go through all the programmable fields and their states. Additional information is also available in the applications and feature descriptions sections as well. The POR column is the power on reset state that this field assumes if not programmed. 8.7.1 POWERDOWN and Reset Fields Table 2. POWERDOWN and Reset Fields Field POWERDOWN [1:0] SWRST 18 Location R2[1:0] R2[2] Submit Documentation Feedback POR 0 0 Description and States POWERDOWN Control Software Reset. Setting this bit sets all registers to their POR default values. Value POWERDOWN State 0 POWERDOWN, ignore CE 1 Power Up, ignore CE 2 Power State Defined by CE terminal state 3 Reserved Value Reset State 0 Normal Operation 1 Register Reset Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 8.7.2 Dividers and Fractional Controls Table 3. Dividers and Fractional Controls Field Location POR Description and States PLL_N [17:0] R18[1] to R16[0] 16 Feedback N counter Divide value. Minimum count is 16. Maximum is 262132. Writing of the register R16 begins any ramp execution when RAMP_EN=1. Value FRAC_ DITHER [1:0] FRAC_ ORDER [2:0] R18[3:2] R18[6:4] 0 Dither used by the fractional modulator 0 Fractional Modulator order Dither 0 Weak 1 Medium 2 Strong 3 Disabled Value Modulator Order 0 Integer Mode 1 1st Order Modulator 2 2nd Order Modulator 3 3rd Order Modulator 4 4th Order Modulator 5-7 Reserved FRAC_NUM [23:0] R21[7] to R19[0] 0 Fractional Numerator. This value should be less than or equal to the fractional denominator. FRAC_DEN [23:0] R24[7] to R22[0] 0 Fractional Denominator. If the RAMP_EN=1, this field is ignored and the denominator is fixed to 224. PLL_R [15:0] R26[7] to R25[0] 1 Reference Divider value. Selecting 1 will bypass counter. 0 Enables the Doubler before the Reference divider OSC_2X PLL_R _DIFF PFD_DLY [1:0] CPG [4:0] CPPOL R27[0] R27[2] R27[4:3] R28[4:0] R28[5] Enables the Differential R counter. This allows for higher OSCin frequencies, but restricts PLL_R to divides of 2,4,8 or 16. 0 Sets the charge pump minimum pulse width. This could potentially be a trade-off between fractional spurs and phase noise. Setting 1 is recommended for general use. 1 0 Charge pump gain Charge Pump Polarity Positive is for a positive slope VCO characteristic, negative otherwise. 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Value Doubler 0 Disabled 1 Enabled Value R Divider 0 Single-Ended 1 Differential Value Pulse Width 0 Reserved 1 860 ps 2 1200 ps 3 1500 ps Value Charge Pump State 0 Tri-State 1 100 uA 2 200 uA … … 31 3100 uA Value Charge Pump Polarity 0 Negative 1 Positive Submit Documentation Feedback 19 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.7.2.1 Speed Up Controls (Cycle Slip Reduction and Fastlock) Table 4. FastLock and Cycle Slip Reduction Field FL_ CSR [1:0] FL_ CPG [4:0] FL_ TOC [10:0] 20 Location R27[6:5] R29[4:0] R29[7:5] and R32[7:0] Submit Documentation Feedback POR 0 0 0 Description and States Cycle Slip Reduction (CSR) reduces the phase detector frequency by multiplying both the R and N counters by the CSR value while either the FastLock Timer is counting or the RAMPx_FL=1 and the part is ramping. Care must be taken that the R and N divides remain inside the range of the counters. Cycle slip reduction is generally not recommended during ramping. Charge pump gain only when Fast Lock Timer is counting down or a ramp is running with RAMPx_FL=1 Fast Lock Timer. This counter starts counting when the user writes the PLL_N(Register R16). During this time the FL_CPG gain is sent to the charge pump, and the FL_CSR shifts the R and N counters if enabled. When the counter terminates, the normal CPG is presented and the CSR undo’s the shifts to give a normal PFD frequency. Value CSR Value 0 Disabled 1 x2 2 x 4. 3 Reserved Value Fastlock Charge Pump Gain 0 Tri-State 1 100 uA 2 200 uA … … 31 3100 uA Value Fastlock Timer Value 0 Disabled 1 1 x 32 = 32 ... 2047 2047 x 32 = 65504 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 8.8 Lock Detect and Charge Pump Monitoring Table 5. Lock Detect and Charge Pump Monitor Field CPM_THR _LOW [5:0] CPM_FLAGL CPM_THR _HIGH [5:0] CPM_FLAGH Location R30[5:0] R30[6] R31[5:0] R31[6] POR 0x0A Description and States Charge pump voltage low threshold value. When the charge pump voltage is below this threshold, the LD goes low. This is a read only bit. Low indicates the charge pump voltage is below the minimum threshold. - 0x32 Charge pump voltage high threshold value. When the charge pump voltage is above this threshold, the LD goes low. This is a read only bit. Charge pump voltage high comparator reading. High indicates the charge pump voltage is above the maximum threshold. - Value Threshold 0 Lowest … … 63 Highest Value Flag Indication 0 Charge pump is below CPM_THR_LOW threshold 1 Charge pump is above CPM_THR_LOW threshold Value Threshold 0 Lowest … … 63 Highest Value Threshold 0 Charge pump is below CPM_THR_HIGH threshold 1 Charge pump is above CPM_THR_HIGH threshold DLD_ PASS_CNT [7:0] R33[7:0] 0xff Digital Lock Detect Filter amount. There must be at least DLD_PASS_CNT good edges and less than DLD_ERR edges before the DLD is considered in lock. Making this number smaller will speed the detection of lock, but also will allow a higher chance of DLD chatter. DLD_ ERR_CNT [4:0] R34[4:0] 0 Digital Lock Detect error count. This is the maximum number of errors greater than DLD_TOL that are allowed before DLD is de-asserted. Although the default is 0, the recommended value is 4. Value DLD _TOL [2:0] R34[7:5] Digital Lock detect edge window. If both N and R edges are within this window, it is considered a “good” edge. Edges that are farther apart in time are considered “error” edges. Window choice depends on phase detector frequency, charge pump minimum pulse width, fractional modulator order and the users desired margin. 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Window and Fpd Frequency 0 1 ns (Fpd > 130 MHz) 1 1.7 ns (80 MHz , Fpd ≤ 130 MHz) 2 3 ns (60 MHz , Fpd ≤ 80 MHz) 3 6 ns (45 MHz , Fpd ≤ 60 MHz) 4 10 ns (30 MHz < Fpd ≤ 45 MHz) 5 18 ns ( Fpd ≤ 30 MHz) 6 and 7 Reserved Submit Documentation Feedback 21 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.9 TRIG1,TRIG2,MOD, and MUXout Pins Table 6. TRIG1, TRIG2, MOD, and MUXout Terminal States Field TRIG1 _PIN [2:0] R36[2:0] POR R37[2:0] 0 MOD_ _PIN [2:0] R38[2:0] 0 R39[2:0] Submit Documentation Feedback Description and States 0 TRIG2 _PIN [2:0] MUXout_ _PIN [2:0] 22 Location This is the terminal drive state for the TRIG1, TRIG2, MOD, and MUXout Pins 0 Value Pin Drive State 0 TRISTATE (default) 1 Open Drain Output 2 Pullup / Pulldown Output 3 Reserved 4 GND 5 Inverted Open Drain Output 6 Inverted Pullup / Pulldown Output 7 Input Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 Table 7. TRIG1, TRIG2, MOD, and MUXout Selections Field Location POR Description and States Value TRIG1_MUX [5:0] TRIG2_MUX [5:0] MOD_MUX [5:0] MUXout_MUX [5:0] R36[7:3], R37.3 R36[7:3], R35.3 R37[7:3], R35.4 R38[7:3], R35.7 These fields control what signal is muxed to or from the TRIG1,TRIG2, MOD, and MUXout pins. Some of the abbreviations used are: COMP0, COMP1: Comparators 0 and 1 LD, DLD: Lock Detect, Digital Lock Detect CPM: Charge Pump Monitor CPG: Charge Pump Gain CPUP: Charge Pump Up Pulse CPDN: Charge Pump Down Pulse 1 2 3 7 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 MUX State 0 GND 1 Input TRIG1 2 Input TRIG2 3 Input MOD 4 Output TRIG1 after synchronizer 5 Output TRIG2 after synchronizer 6 Output MOD after synchronizer 7 Output Read back 8 Output CMP0 9 Output CMP1 10 Output LD (DLD good AND CPM good) 11 Output DLD 12 Output CPMON good 13 Output CPMON too High 14 Output CPMON too low 15 Output RAMP LIMIT EXCEEDED 16 Output R Divide/2 17 Output R Divide/4 18 Output N Divide/2 19 Output N Divide/4 20 Reserved 21 Reserved 22 Output CMP0RAMP 23 Output CMP1RAMP 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Output Faslock 29 Output CPG from RAMP 30 Output Flag0 from RAMP 31 Output Flag1 from RAMP 32 Output TRIGA 33 Output TRIGB 34 Output TRIGC 35 Output R Divide 36 Output CPUP 37 Output CPDN 38 Output RAMP_CNT Finished 39 to 63 Reserved Submit Documentation Feedback 23 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.10 Ramping Functions Table 8. Ramping Functions Field RAMP_EN RAMP_CLK RAMP_PM_EN RAMP_TRIGA [3:0] RAMP_TRIGB [3:0] RAMP_TRIGC [3:0] R58[0] R58[1] R58[2] R58[7:4] R59[3:0] R59[7:4] POR 0 0 0 0 Description and States Enables the RAMP functions. When this bit is set, the Fractional Denominator is fixed to 224. RAMP execution begins at RAMP0 upon the PLL_N[7:0] write. The Ramp should be set up before RAMP_EN is set. Value Ramp 0 Disabled 1 Enabled RAMP clock input source. The ramp can be clocked by either the phase detector clock or the MOD terminal based on this selection. Value Source 0 Phase Detector Phase modulation enable. Trigger A,B, and C Sources 1 MOD Terminal Value Modulation Type 0 Frequency Modulation 1 Phase Modulation Value Source 0 Never Triggers (default) 1 TRIG1 terminal rising edge 2 TRIG2 terminal rising edge 3 MOD terminal rising edge 4 DLD Rising Edge 5 CMP0 detected (level) 6 RAMPx_CPG Rising edge 7 RAMPx_FLAG0 Rising edge 8 Always Triggered (level) 9 TRIG1 terminal falling edge 10 TRIG2 terminal falling edge 11 MOD terminal falling edge 12 DLD Falling Edge 13 CMP1 detected (level) 14 RAMPx_CPG Falling edge 15 RAMPx_FLAG0 Falling edge RAMP_CMP0 [32:0] R70[0], R63[7] to R60[0] 0 Twos compliment of Ramp Comparator 0 value. Be aware of that the MSB is in Register R70. RAMP_CMP0_EN [7:0] R64[7:0] 0 Comparator 0 is active during each RAMP corresponding to the bit. Place a 1 for ramps it is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7 corresponds to R64[7] RAMP_CMP1 [32:0] R70[1], R68[7] to R65[0] 0 Twos compliment of Ramp Comparator 1 value. Be aware of that the MSB is in Register R70. RAMP_CMP1_EN [7:0] R69[7:0] 0 Comparator 1 is active during each RAMP corresponding to the bit. Place a 1 for ramps it is active in and 0 for ramps it should be ignored. RAMP0 corresponds to R64[0], RAMP7 corresponds to R64[7]. FSK_TRIG [1:0] FSK_DEV [32:0] 24 Location R76[4] to R75[3] R70[2], R74[7] to R71[0] Submit Documentation Feedback 0 0 Deviation trigger source. When this trigger source specified is active, the FSK_DEV value is applied. Value Trigger 0 Always Triggered 1 Trigger A 2 Trigger B 3 Trigger C Twos compliment of the deviation value for frequency modulation and phase modulation. This value should be written with 0 when not used. Be aware that the MSB is in Register R70. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 Ramping Functions (continued) Table 8. Ramping Functions (continued) Field Location POR Description and States RAMP_LIMIT_LOW [32:0] R70[3], R78[7] to 75[0] Twos compliment of the ramp lower limit that the ramp can not go below . The ramp limit 0x000 occurs before any deviation values are included. Care must be taken if the deviation is 00000 used and the ramp limit must be set appropriately. Be aware that the MSB is in Register R70. RAMP_LIMIT_HIGH [32:0] R70[4], R82[7] to 79.0[0] Twos compliment of the ramp higher limit that the ramp can not go above. The ramp limit 0xfffffff occurs before any deviation values are included. Care must be taken if the deviation is f used and the ramp limit must be set appropriately. Be aware that the MSB is in Register R70. RAMP_COUNT [12:0] R84[4] to R83[0] RAMP_AUTO RAMP_TRIG_INC [1:0] R84[5] R84[7:6] Number of RAMPs that will be executed before a trigger or ramp enable is brought down. Load zero if this feature is not used. Counter is automatically reset when RAMP_EN goes from 0 to 1. 0 Automatically clear RAMP_EN RAMP Count hits terminal count. 0 when Increment Trigger source for RAMP Counter. To disable ramp counter, load a count value of 0. 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Value Ramp 0 RAMP_EN unaffected by ramp counter (default) 1 RAMP_EN automatically brought low when ramp counter terminal counts Value Source 0 Increments occur on each ramp transition 1 Increment occurs on trigA 2 Increment occurs on trigB 3 Increment occurs on trigC Submit Documentation Feedback 25 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 8.11 Individual Ramp Controls These bits apply for all eight ramps. For the field names, x can be 0,1,2,3,4,5,6, or 7. Table 9. Individual Ramp Controls Field Location POR Description and States RAMPx _INC[29:0] Varies 0 Signed ramp increment. RAMPx _FL Varies 0 RAMPx _DLY RAMPx _LEN RAMPx _FLAG[1:0] RAMP0 _RST RAMPx_ NEXT _TRIG [1:0] RAMP0 _NEXT[2:0] 26 Varies Varies Varies Varies Varies Varies 0 0 0 0 0 This enables fastlock and cycle slip reduction for ramp x. During this ramp, each increment takes 2 PFD cycles per LEN clock instead of the normal 1 PFD cycle. Slows the ramp by a factor of 2. Value CPG 0 Disabled 1 Enabled Value Clocks 0 1 PFD clock per RAMP tick.(default) 1 2 PFD clocks per RAMP tick. Number of PFD clocks (if DLY is 0) to continue to increment RAMP. 1=>1 cycle, 2=>2 etc. Maximum of 65536 cycles. General purpose FLAGS sent out of RAMP. Forces a clear of the ramp accumulator. This is used to erase any accumulator creep that can occur depending on how the ramps are defined. Should be done at the start of a ramp pattern. Determines what event is necessary to cause the state machine to go to the next ramp. It can be set to when the RAMPx_LEN counter reaches zero or one of the events for Triggers A,B, or C. 0 Submit Documentation Feedback Value Flag 0 Both FLAG1 and FLAG0 are zero. (default) 1 FLAG0 is set, FLAG1 is clear 2 FLAG0 is clear, FLAG1 is set 3 Both FLAG0 and FLAG1 are set. Value Reset 0 Disabled 1 Enabled Value Operation 0 RAMPx_LEN 1 TRIG_A 2 TRIG_B 3 TRIG_C The next RAMP to execute when the length counter times out Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LMX2492/92-Q1 can be used in a broad class of applications such as generating a single frequency for a high frequency clock, generating a tunable range of frequencies, or generating swept waveforms that can be used in applications such as radar. 9.2 Typical Applications The following schematic is an example of hat could be used in a typical application. 3.3 or 5 V R3_LF 100 nF C2_LF C1_LF C3_LF 3.3 V R2_LF GND 4 19 Vcc 3 20 TRIG1 GND 21 TRIG2 2 22 Vcp GND 23 Rset 1 24 CPout 100 nF 3.3 V Vcc MUXOUT 18 17 100 nF 18 : LE 16 Fin DATA 15 5 Fin* CLK 14 6 Vcc CE 13 10 pF 68 : OSCin GND/OSCin* GND MOD 3.3 V 10 pF Vcc 36 : Vcc To Circuit 18 : 7 8 9 10 11 12 51 : 100 nF 3.3 V 3.3 V 18 : 100 nF 100 nF 68 : 18 : 9.2.1 Design Requirements For these examples, it will be assumed that there is a 100 MHz input signal and the output frequency is between 9400 and 9800 MHz with various modulated waveforms. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 27 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com Typical Applications (continued) Parameter Symbol Value Input Frequency OSCin 100 MHz Comments Phase Detector Frequency Fpd 100 MHz There are many possibilities, but this choice gives good performance and saves a little current (as shown in the electrical specifications). 9400 - 9800 MHz (Simple Chirp) VCO Frequency Fvco VCO Gain Kvco In the different examples, the VCO frequency is actually changing. However, the same loop filter 9500 - 9625 MHz (Complex Triggered design can be used for all three. Ramp 9400 - 9800 (Flattened Ramp) 200 MHz/V This parameter has nothing to do with the LMX2492/92-Q1, but is rather set by the external VCO choice. 9.2.2 Detailed Design Procedure The first step is to calculate the reference divider (PLL_R) and feedback divider (PLL_N) values as shown in the table that follows. Parameter Symbol and Calculations Value Comments Average VCO Frequency FvcoAvg = (FvcoMax + FvcoMin)/2 9600 MHz To design a loop filter, one designs for a fixed VCO value, although it is understood that the VCO will tune around. This typical value is usually chosen as the average VCO frequency. VCO Gain Kvco 200 MHz/V This parameter has nothing to do with the LMX2492/92-Q1, but is rather set by the external VCO choice. In this case, it was the RFMD1843 VCO. PLL Loop Bandwidth BW 380 kHz This bandwidth is very wide to allow the VCO frequency to be modulated. Charge Pump Gain CPG 3.1 mA Using the larger gain allows a wider loop bandwidth and gives good phase performance. R Divider PLL_R = OSCin / Fpd 1 This value is calculated from previous values. N Divider PLL_N = Fvco / Fpd 96 This value is calculated from previous values. Loop Filter Components C1_LF 68 pF C2_LF 3.9 nF C3_LF 150 pF R2_LF 390 ohm R3_LF 390 ohm These were calculated by TI design tools. Once a loop filter bandwidth is chosen, the external loop filter components of C1_LF, C2_LF, C3_LF, R2_LF, and R3_LF can be calculated with a tool such as the Clock Architect tool available at www.ti.com. It is also highly recommended to look at the EVM instructions. The CodeLoader software is an excellent starting point and example to see how to program this device. 28 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 9.2.3 Application Performance Plot - Sawtooth Waveform Example Using the above design, it can be programmed to generate a sawtooth waveform with the following paramters. Parameter Symbol Value Ramp Duration ΔT 100 uS VCO Frequency Fvco 9400 - 9800 MHz Range ΔF 9400 - 9800 MHz = 400 MHz Change tRAMP0t tRAMP0t tRAMP0t tRAMP0t Because we want the ramp length to be 100 us, this works out to 10,000 phase detector cycles which means that RAMP0_LEN=10000. To change 400 MHz, we know that each one of the 10000 steps is 40 kHz. Given the fractional denominator is 224 = 16777216 and the phase detector frequency is 100 MHz, this implies that the fractional numerator at the end of the ramp will be 6711. However, since this 6711 number is not exact (closer to 6718.8864), the ramp will creep if we do not reset it. Therefore, we set reset the ramp. After the ramp finishes, we want to start with the same ramp, so RAMP0_NEXT is RAMP0. The results of this analysis are in the table below: RAMP RAMP0_LEN RAMP0_INC RAMP0_NEXT RAMP0_RST RAMP0 ΔT × Fpd = 100 us / 100 MHz = 10000 (ΔF / Fpd) /RAMP0_LEN × 224 = (400/100)/10000 ×16777216 = 6711 0 1 The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually measured was from the divide by two output of the VCO and therefore the measured frequency was half of the actual frequency presented to the PLL. This ramping waveform does show some undershoot as the frequency rapidly returns from 9800 MHz ( 4900 MHz on the plot) to 9400 MHz (4700 MHz on the plot). This undershoot can be mitigated by adding additional ramps. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 29 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 9.2.4 Application Performance Plot - Flat Top Triangle Waveform Now consider pattern as shown below. The ramp is sometimes used because it can better account for Doppler Shift. The purpose for making the top and bottom portions flat is to help reduce the impact of the PLL overshooting and undershooting in order to make the sloped ramped portions more linear. Parameter Ramp Duration Range Symbol Value ΔT0 10 uS ΔT1 90 uS ΔT2 10 uS ΔT3 90 uS ΔF0 0 ΔF1 400 MHz ΔF2 0 ΔF3 -400 MHz tRAMP1t RAMP0 tRAMP1t RAMP2 RAMP0 RAMP RAMPx_LEN RAMPx_INC RAMP0 10 us/ 100 MHz =1000 0 RAMP2 RAMPx_NEXT RAMPx_RST 1 1 24 RAMP1 90 us / 100 MHz =9000 (ΔF / Fpd) /RAMP1_LEN × 2 = (400/100)/9000 ×16777216 = 7457 2 0 RAMP2 10 us/ 100 MHz =1000 0 3 0 90 us / 100 MHz =9000 (ΔF / Fpd) /RAMP1_LEN × 224 = (-400/100)/9000 ×16777216 = -7457 Program in 2's complement of 7457 = 230-7457 = 1073734367 0 0 RAMP3 30 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually measured was from the divide by two output of the VCO and therefore the measured frequency was half of the actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the overshoot and undersoot in the frequency. The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually measured was from the divide by two output of the VCO and therefore the measured frequency was half of the actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the overshoot and undersoot in the frequency. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 31 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 9.2.5 Applications Performance Plot -- Complex Triggered Ramp In this example, the modulation is not started until a trigger pulse from the MOD terminal goes high. Assume a phase detector frequency of 100 MHz and we RAMP1 to be 60 us and ramps 2,3,and 4 to be 12 us each. We set the next trigger for RAMP0 to be trigger A and define trigger A to be the MOD terminal. Then we configure as follows: MOD Frequency 9.800 GHz Increased Charge Pump Gain Increased Charge Pump Gain 9.800 GHz 9.400 GHz 9.725 GHz 9.600 GHz FLAG0 TRIG1 Output as Loop Filter Switch 1 FLAG1 TRIG2 Output as Loop Filter Switch 2 'T0 'T2 'T1 'T3 'T4 'T1 'T2 'T3 'T4 Figure 6. Complex Triggered Ramp Example RAMP RAMPx _LEN RAMPx_ INC RAMPx_FL RAMPx _NEXT RAMPx_FLAG RAMPx_ NEXT_TRIG RAMPx_RS T RAMP0 1 0 0 1 FLAG0 and FLAG1 TRIG A 1 RAMP1 6000 1073730639 0 2 FLAG0 and FLAG1 TOC Timeout 1 RAMP2 1200 27963 1 3 Disabled TOC Timeout 0 RAMP3 1200 17476 0 4 FLAG1 TOC Timeout 0 1 FLAG0 and FLAG1 TOC Timeout 0 RAMP4 32 1200 Submit Documentation Feedback 10486 0 Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 The actual measured waveform for this is shown in the following figure. Note that the frequency that was actually measured was from the divide by two output of the VCO and therefore the measured frequency was half of the actual frequency presented to the PLL. The flattened top and bottom of this triangle wave help mitigate the overshoot and undersoot in the frequency. Figure 7. Actual Measurement for Complex Triggered Ramp 10 Power Supply Recommendations For power supplies, it is recommended to place 100 nF close to each of the power supply pins. If fractional spurs are a large concern, using a ferrite bead to each of these power supply pins can reduce spurs to a small degree. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 33 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 11 Layout 11.1 Layout Guidelines For layout examples, the EVM instructions are the most comprehensive document. In general, the layout guidelines are similar to most other PLL devices. For the high frequency Fin pin, it is recommended to use 0402 components and match the trace width to these pad sizes. Also the same needs to be done on the Fin* pin. If layout is easier to route the signal to Fin* instead of Fin, then this is acceptable as well. 11.2 Layout Example 34 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 LMX2492, LMX2492-Q1 www.ti.com SNAS624B – MARCH 2014 – REVISED MAY 2015 12 Device and Documentation Support 12.1 Device Support 12.1.1 Development Support Texas Instruments has several software tools to aid in the development process including CodeLoder for programming, Clock Design Tool for Loop filter design and phase noise/spur simulation, and the Clock Architect. All these tools are available at www.ti.com. 12.2 Documentation Support 12.2.1 Related Documentation For the avid reader, the following resources are available at www.ti.com. Application Note 1879 -- Fractional N Frequency Synthesis PLL Performance, Simulation, and Design -- by Dean Banerjee 12.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 10. Related Links PARTS PRODUCT FOLDER SAMPLE and BUY TECHNICAL DOCUMENTS TOOLS and SOFTWARE SUPPORT and COMMUNITY LMX2492 Click here Click here Click here Click here Click here LMX2492-Q1 Click here Click here Click here Click here Click here 12.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 Submit Documentation Feedback 35 LMX2492, LMX2492-Q1 SNAS624B – MARCH 2014 – REVISED MAY 2015 www.ti.com 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 36 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: LMX2492 LMX2492-Q1 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMX2492QRTWRQ1 ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 X2492Q LMX2492QRTWTQ1 ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 X2492Q LMX2492RTWR ACTIVE WQFN RTW 24 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 X2492 LMX2492RTWT ACTIVE WQFN RTW 24 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 X2492 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 27-May-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LMX2492, LMX2492-Q1 : • Catalog: LMX2492 • Automotive: LMX2492-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMX2492QRTWRQ1 WQFN RTW 24 LMX2492QRTWTQ1 WQFN RTW LMX2492RTWR WQFN RTW LMX2492RTWT WQFN RTW SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 24 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-May-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMX2492QRTWRQ1 WQFN RTW 24 1000 213.0 191.0 55.0 LMX2492QRTWTQ1 WQFN RTW 24 250 213.0 191.0 55.0 LMX2492RTWR WQFN RTW 24 1000 213.0 191.0 55.0 LMX2492RTWT WQFN RTW 24 250 213.0 191.0 55.0 Pack Materials-Page 2 MECHANICAL DATA RTW0024A SQA24A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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