Maxim MAX5982BETE+ Ieee 802.3af/at-compliant, powered device interface Datasheet

19-5960; Rev 0; 6/11
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Features
The MAX5982A/MAX5982B/MAX5982C provide a complete interface for a powered device (PD) to comply with
the IEEE® 802.3af/at standard in a power-over-Ethernet
(PoE) system. The MAX5982A/MAX5982B/MAX5982C
provide the PD with a detection signature, classification signature, and an integrated isolation power switch
with inrush current control. During the inrush period,
the MAX5982A/MAX5982B/MAX5982C limit the current
to less than 182mA before switching to the higher current limit (1700mA to 2100mA) when the isolation power
MOSFET is fully enhanced. The devices feature an input
UVLO with wide hysteresis and long deglitch time to
compensate for twisted-pair cable resistive drop and to
assure glitch-free transition during power-on/-off conditions. The MAX5982A/MAX5982B/MAX5982C can withstand up to 100V at the input.
S Sleep Mode and Ultra-Low-Power Sleep
(MAX5982A/MAX5982B)
S IEEE 802.3af/at Compliant
S 2-Event Classification or an External Wall Adapter
Indicator Output
S Simplified Wall Adapter Interface
S PoE Classification 0–5
S 100V Input Absolute Maximum Rating
S Inrush Current Limit of 182mA Maximum
S Current Limit During Normal Operation Between
1700mA and 2100mA
S Current Limit and Foldback
S Legacy UVLO at 36V
S LED Driver with Programmable LED Current
(MAX5982A/MAX5982B)
S Overtemperature Protection
S Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN
The MAX5982A/MAX5982B/MAX5982C support a
2-Event classification method as specified in the IEEE
802.3at standard and provide a signal to indicate when
probed by a Type 2 power sourcing equipment (PSE).
The devices detect the presence of a wall adapter power
source connection and allow a smooth switchover from
the PoE power source to the wall power adapter.
The MAX5982A/MAX5982B/MAX5982C also provide a
power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. A sleep
mode feature in the MAX5982A/MAX5982B provides low
power consumption while supporting Maintain Power
Signature (MPS). An ultra-low-power sleep mode feature
in the MAX5982A/MAX5982B further reduces power
consumption while still supporting MPS. The MAX5982A/
MAX5982B also feature an LED driver that is automatically activated during sleep mode.
Applications
IEEE 802.3af/at Powered Devices
IP Phones, Wireless Access Nodes, IP Security
Cameras
WiMAXK Base Stations
Ordering Information appears at end of data sheet.
The MAX5982A/MAX5982B/MAX5982C are available in
a 16-pin, 5mm x 5mm, TQFN power package. These
devices are rated over the -40NC to +85NC extended
temperature range.
WiMAX is a trademark of WiMAX Forum.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5982A/MAX5982B/MAX5982C
General Description
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
ABSOLUTE MAXIMUM RATINGS
VDD to VSS...........................................................-0.3V to +100V
DET, RTN, WAD, PG, 2EC to VSS........................ -0.3V to +100V
CLS, SL, WK, ULP, LED to VSS................................-0.3V to +6V
Maximum Current on CLS (100ms maximum)..................100mA
Continuous Power Dissipation (TA = +70NC) (Note 1)
TQFN (derate 28.6mW/NC above +70NC)
Multilayer Board......................................................2285.7mW
Operating Temperature Range........................... -40NC to +85NC
Maximum Junction Temperature......................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s)............................... +300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
PACKAGE THERMAL CHARACTERISTICS(Note 2)
TQFN
Junction-to-Ambient Thermal Resistance (qJA)...........35°C/W
Junction-to-Case Thermal Resistance (BJC)...............2.7NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
FA
DETECTION MODE
Input Offset Current
Effective Differential Input
Resistance
IOFFSET
dR
VIN = 1.4V to 10.1V (Note 4)
VIN = 1.4V up to 10.1V with 1V step,
VDD = RTN = WAD = PG = 2EC (Note 5)
23.95
25.00
25.50
kI
VIN rising (Note 6)
22.0
22.8
23.6
V
CLASSIFICATION MODE
Classification Disable
Threshold
VTH,CLS
Classification Stability Time
Classification Current
0.2
ICLASS
VIN = 12.5V to
20.5V, VDD =
RTN = WAD =
PG = 2EC
ms
Class 0, RCLS = 615I
0
3.96
Class 1, RCLS = 117I
9.12
11.88
Class 2, RCLS = 66.5I
17.2
19.8
Class 3, RCLS = 43.7I
26.3
29.7
Class 4, RCLS = 30.9I
36.4
43.6
Class 5, RCLS = 21.3I
52.7
63.3
mA
TYPE 2 (802.3at) CLASSIFICATION MODE
Mark Event Threshold
VTHM
VIN falling
10.1
Hysteresis on Mark Event
Threshold
10.7
11.6
0.82
Mark Event Current
IMARK
VIN falling to enter mark event, 5.2V P VIN
P 10.1V
0.25
Reset Event Threshold
VTHR
VIN falling
2.8
3.8
2 _______________________________________________________________________________________
V
V
0.85
mA
5.2
V
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
60
V
0.25
0.55
mA
35.4
36.6
V
POWER MODE
VIN Supply Voltage Range
VIN Supply Current
IQ
Current through internal MOSFET = 0
VIN Turn-On Voltage
VON
VIN rising
34.3
VIN Turn-Off Voltage
VOFF
VIN falling
30
(Note 7)
4.2
VIN falling from 40V to 20V (Note 8)
30
120
tDELAY = minimum PG current pulse width
after entering into power mode
90
96
VIN Turn-On/-Off Hysteresis
VIN Deglitch Time
VHYST_UVLO
tOFF_DLY
Inrush to Operating Mode
Delay
tDELAY
Isolation Power MOSFET
On-Resistance
RON_ISO
IRTN = 950mA
RTN Leakage Current
IRTN_LKG
VRTN = 12.5V to 30V
V
V
Fs
102
ms
TJ = +25NC
0.1
0.2
TJ = +85NC
0.15
0.25
I
TJ = +125NC
0.2
10
FA
CURRENT LIMIT
Inrush Current Limit
Current Limit During Normal
Operation
Current Limit in Foldback
Condition
IINRUSH
ILIM
ILIM-FLDBK
Foldback Threshold
During initial turn-on period, VRTN = 1.5V
After inrush completed,
VRTN = 1V (Note 9)
90
135
182
mA
1700
1900
2100
mA
Both during inrush and after inrush
completed VRTN = 7.5V
VRTN (Note 10)
53
mA
6.5
7.0
7.5
V
8
9
10
V
LOGIC
WAD Detection Threshold
VWAD-REF
WAD Detection Threshold
Hysteresis
WAD Input Current
VWAD rising, VIN = 14V to 48V
(referenced to RTN)
VWAD falling, VRTN = 0V, VSS
unconnected
IWAD-LKG
0.35
VWAD = 10V (referenced to RTN)
2EC Sink Current
V2EC = 3.5V (referenced to RTN),
VSS disconnected
2EC Off-Leakage Current
V2EC = 48V
PG Sink Current
VRTN = 1.5V, VPG = 0.8V, during inrush
period
PG Off-Leakage Current
VPG = 60V
1
125
1.5
230
V
3.5
FA
2.25
mA
1
FA
375
FA
1
FA
3
V
0.85
V
SLEEP MODE (MAX5982A/MAX5982B)
WK and ULP Logic Threshold
VWK falling and VULP rising and falling
1.5
SL Logic Threshold
Falling
0.75
0.8
SL Current
RSL = 0I
RSL = 60.4kI, VLED = 3.5V
10
10.5
11.5
RSL = 30.2kI, VLED = 3.75V
19.5
20.9
22.5
LED Current Amplitude
VTH
ILED
RSL = 30.2kI, VLED = 4V
140
FA
mA
19
_______________________________________________________________________________________ 3
MAX5982A/MAX5982B/MAX5982C
ELECTRICAL CHARACTERISTICS (continued)
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at
TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
LED Current Programmable
Range
10
LED Current with Grounded SL
VSL = 0V
20.5
LED Current Frequency
fILED
Normal and ultra-low-power sleep modes
LED Current Duty Cycle
DILED
Normal and ultra-low-power sleep modes
VDD Current Amplitude
IVDD
Normal sleep mode, VLED = 3.5V
Internal Current Duty Cycle
TYP
DIVDD
24.5
MAX
UNITS
20
mA
28.5
mA
250
Hz
25
10
Normal and ultra-low-power sleep modes
11
%
12.2
mA
75
%
Internal Current Enable Time
tMPS
Ultra-low-power sleep mode
80
84
88
ms
Internal Current Disable Time
tMPDO
Ultra-low-power sleep mode
220
228
236
ms
tSL
Time VSL must remain below the SL logic
threshold to enter sleep and ultra-lowpower modes (MAX5982A)
5.4
6.0
6.6
s
TSD
TJ rising
+150
NC
TJ falling
30
NC
SL Delay Time
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
The input offset current is illustrated in Figure 1.
Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.
Classification current is turned off whenever the device is in power mode.
UVLO hysteresis is guaranteed by design, not production tested.
A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the
MAX5982A/MAX5982B/MAX5982C to exit power-on mode.
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an
overload condition across VDD and RTN.
Note
Note
Note
Note
Note
Note
3:
4:
5:
6:
7:
8:
IIN
dRi =
1V
(VINi + 1 - VINi)
=
(IINi + 1 - IINi) (IINi + 1 - IINi)
IOFFSET = IINi -
VINi
dRi
IINi + 1
dRi
IINi
IOFFSET
VINi
1V
VINi + 1
VIN
Figure 1. Effective Differential Input Resistance/Offset Current
4 _______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
TA = -40°C
25.0
24.5
0.1
TA = +25°C
TA = +85°C
MAX5982A toc03
25.5
5
4
3
2
TA = +85°C
1
0
-1
-2
TA = +25°C
-3
TA = -40°C
-4
-5
24.0
0
2
4
6
8
0
10
2
4
8
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
CLASS 5
IIN (mA)
4
8
10
2.0
TA = -40°C
CLASS 4
CLASS 3
VIN
5V/div
1.6
IIN
100mA/div
1.2
TA = +25°C
TA = +85°C
0.8
CLASS 2
20
CLASS 1
10
STEP INPUT APPLIED TO
VIN FROM 10V TO 12V
CLASS 0
0
0
5
10
15
20
25
30
VCLS
2V/div
0.4
0
0
100µs/div
10
20
VIN (V)
INRUSH CURRENT LIMIT
vs. RTN VOLTAGE
TA = +25°C
150
100
50
60
2.5
0.14
0.12
0.10
0.08
0.06
0.04
MAX5982A toc09
0.16
2.0
CURRENT LIMIT (A)
250
TA = +85°C
40
NORMAL OPERATION CURRENT LIMIT
vs. RTN VOLTAGE
MAX5982A toc08
TA = -40°C
INRUSH CURRENT LIMIT (A)
MAX5982A toc07
300
200
30
V2EC (V)
PG SINK CURRENT vs. PG VOLTAGE
IPG (µA)
6
2EC SINK CURRENT vs. 2EC VOLTAGE
MAX5982A toc05
50
30
2
VIN (V)
CLASSIFICATION SETTLING TIME
MAX5982A toc04
70
40
0
10
VIN (V)
VIN (V)
60
6
I2EC (mA)
0
MAX5982A toc06
0.2
IIN = IVDD + IDET
RDET = 25.4kI
RTN = 2EC = PG = WAD = VDD
INPUT OFFSET CURRENT (µA)
0.3
MAX5982A toc02
IIN = IVDD + IDET
RDET = 25.4kI
RTN = 2EC = PG = WAD = VDD
RSIGNATURE (kI)
IIN (mA)
26.0
MAX5982A toc01
0.5
0.4
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
SIGNATURE RESISTANCE
vs. INPUT VOLTAGE
DETECTION CURRENT
vs. INPUT VOLTAGE
1.5
1.0
0.5
0.02
0
0
50
0
10
20
30
VPG (V)
40
50
60
0
10
20
30
VRTN (V)
40
50
60
0
10
20
30
40
50
60
VRTN (V)
_______________________________________________________________________________________ 5
MAX5982A/MAX5982B/MAX5982C
Typical Operating Characteristics
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected; all
voltages are referenced to VSS.)
Typical Operating Characteristics (continued)
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected; all
voltages are referenced to VSS.)
INRUSH CONTROL WAVEFORM
WITH TYPE 2 CLASSIFICATION
INRUSH CONTROL WAVEFORM
WITH TYPE 2 CLASSIFICATION
MAX5982A toc10
MAX5982A toc11
VIN
50V/div
VIN
50V/div
V2EC
50V/div
VPG
50V/div
VRTN
50V/div
V2EC
50V/div
VRTN
50V/div
IRTN
100mA/div
IRTN
100mA/div
400µs/div
LED CURRENT vs. LED VOLTAGE
LED CURRENT vs. RSL
MAX5982A toc13
RSL = 30.2kI
20
MAX5982A toc12
20ms/div
25
25
22
15
ILED (mA)
ILED (mA)
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated Power MOSFET
RSL = 60.4kI
10
19
16
5
13
0
0
1
2
3
4
10
5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
VLED (V)
RSL (kI)
DRIVING LED WITH ULP IN
POWER MODE
SLEEP/ULTRA-LOW-POWER MODE
DELAY (MAX5982A)
MAX5982A toc15
MAX5982A toc14
VULP
2V/div
VSL
1V/div
ILED
5mA/div
ILED
5mA/div
10µs/div
1s/div
6 _______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
11
2EC
VDD
2
10
PG
DET
3
9
WAD
I.C.
4
N.C.
LED
N.C.
SL
N.C.
WK
N.C.
ULP
*EP
1
+
MAX5982C
*EP
5
6
7
8
5
6
7
12
CLS
11
2EC
10
PG
9
WAD
8
RTN
4
N.C.
13
RTN
I.C.
MAX5982A
MAX5982B
CLS
14
VSS
3
12
15
VSS
DET
+
16
RTN
2
13
RTN
VDD
14
VSS
1
15
VSS
N.C.
16
TOP VIEW
TQFN
TQFN
*CONNECT EP TO VSS.
Pin Description
PIN
NAME
FUNCTION
MAX5982A/
MAX5982B
MAX5982C
1
1, 13–16
N.C.
No Connection. Not internally connected.
2
2
VDD
Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS.
3
3
DET
Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD.
4
4
I.C.
Internally Connected. Leave unconnected.
5, 6
5, 6
VSS
Negative Supply Input. VSS connects to the source of the integrated isolation n-channel
power MOSFET.
7, 8
7, 8
RTN
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation
n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground as
shown in the Typical Application Circuit.
WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment
VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from
WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation
n-channel power MOSFET turns off and 2EC current sink turns on. Connect WAD directly
to RTN when the wall power adapter or other auxiliary power source is not used.
PG
Open-Drain, Power-Good Indicator Output. PG sinks 230FA to disable the downstream
DC-DC converter while turning on the hot-swap MOSFET switch. PG current sink is
disabled during detection, classification, and in the steady-state power mode. The PG
current sink is turned on to disable the downstream DC-DC converter when the device is
in sleep mode.
9
10
9
10
_______________________________________________________________________________________ 7
MAX5982A/MAX5982B/MAX5982C
Pin Configurations
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Pin Description (continued)
PIN
MAX5982A/
MAX5982B
MAX5982C
NAME
FUNCTION
11
11
2EC
2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is
enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by
a Type 2 PSE, the 2EC current sink is enabled after the isolation MOSFET is fully on
until VIN drops below the UVLO threshold. 2EC is latched when powered by a Type 2
PSE until VIN drops below the reset threshold. 2EC also asserts when a wall adapter
supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if
asserted by WAD. The 2EC current sink is turned off when the device is in sleep mode.
12
12
CLS
Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the
desired classification current. See the classification current specifications in the Electrical
Characteristics table to find the resistor value for a particular PD classification.
13
––
LED
LED Driver Output. During sleep mode, LED sources a periodic current (ILED) at 250Hz
with 25% duty cycle. The amplitude of ILED is set by RSL according to the formula ILED (in
A) = 645.75/(RSL + 1200).
14
––
SL
Sleep Mode Enable Input. In the MAX5982B, a falling edge on SL brings the device into
sleep mode (VSL must drop below 0.75V). In the MAX5982A, VSL must remain below
the threshold (0.75V) for a period of at least 6s after falling edge to bring the device into
sleep mode. An external resistor (RSL) connected between SL and VSS sets the LED
current (ILED).
15
––
WK
Wake Mode Enable Input. WK has an internal 2.5kI pullup resistor to the internal 5V
bias rail. A falling edge on WK brings the device out of sleep mode and into the normal
operating mode (wake mode).
Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kI pullup
resistor to the internal 5V bias rail. A falling edge on SL in the MAX5982B (and a 6s
period below the SL threshold in the MAX5982A) while ULP is asserted low enables
ultra-low-power sleep mode. When ultra-low-power sleep mode is enabled, the power
consumption of the device is reduced even lower than normal sleep mode to comply with
ultra-low-power sleep power requirements while still supporting MPS.
16
––
ULP
––
––
EP
Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally
connected to VSS through a resistive path and must be connected to VSS externally. To
optimize power dissipation, solder the exposed pad to a large copper power plane.
8 _______________________________________________________________________________________
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
VDD
VDD
EN
CLS
CLASSIFICATION
VDD
2EC
D
SET
Q
CLR
Q
D
SET
Q
CLR
Q
5V REGULATOR
1.5mA
VDD
5V
PG
46µA
DET
VON/VOFF
VDD
230µA
VDD
THERMAL
SHUTDOWN
WAD
R
S
Q
9V
tDELAY
ISWITCH
VSS
RTN
ISOLATION
SWITCH
K x ISWITCH
S
I0
1/K
I1
MUX
MAX5982A
MAX5982B
SL
5V
2.5kI
WK
LOGIC
LED
5V
50kI
ULP
_______________________________________________________________________________________ 9
MAX5982A/MAX5982B/MAX5982C
MAX5982A/MAX5982B Simplified Block Diagram
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
MAX5982C Simplified Block Diagram
VDD
VDD
EN
CLS
CLASSIFICATION
VDD
2EC
D
SET
Q
CLR
Q
D
SET
Q
CLR
Q
5V REGULATOR
1.5mA
VDD
5V
PG
46µA
DET
VON/VOFF
VDD
230µA
VDD
THERMAL
SHUTDOWN
tDELAY
R
S
WAD
Q
9V
VSS
ISWITCH
RTN
ISOLATION
SWITCH
K x ISWITCH
MAX5982C
S
I0
1/K
I1
MUX
10 �������������������������������������������������������������������������������������
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
2-EVENT
CLASSIFICATION
DETECTION
GND
2EC
VDD
RJ-45
AND
BRIDGE
RECTIFIER
DET
MAX5982A
MAX5982B
MAX5982C
1.5mA
DC-DC
CONVERTER
WAD
24V/48V
BATTERY
RCLS
IN-
VSS
-54V
ENABLE
2EC/WAD
CLS
SMAJ58A
GND
PG
RDET
24.9kI
68nF
IN+
WK
RTN
MAX5982A/MAX5982B ONLY
1kI
SL
ISOLATED SLEEP
MODE INPUT
ULP
-54V
LED
ISOLATED
ULTRA-LOW-POWER
SLEEP
-54V
-54V
______________________________________________________________________________________ 11
MAX5982A/MAX5982B/MAX5982C
Typical Operating Circuit
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Detailed Description
Operating Modes
Depending on the input voltage (VIN = VDD - VSS), the
MAX5982A/MAX5982B/MAX5982C operate in four different modes: PD detection, PD classification, mark event,
and PD power. The devices enter PD detection mode
when the input voltage is between 1.4V and 10.1V. The
device enters PD classification mode when the input
voltage is between 12.6V and 20V. The devices enter PD
power mode once the input voltage exceeds VON.
Detection Mode (1.4V ≤ VIN ≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on VIN in the 1.4V to 10.1V range
(1V step minimum) and then records the current measurements at the two points. The PSE then computes DV/DI
to ensure the presence of the 24.9kω signature resistor.
Connect the signature resistor (RDET) from VDD to DET for
proper signature detection. The MAX5982A/MAX5982B/
MAX5982C pull DET low in detection mode. DET goes
high impedance when the input voltage exceeds 12.5V.
In detection mode, most of the MAX5982A/MAX5982B/
MAX5982C internal circuitry is off and the offset current is
less than 10µA.
If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal
damage to the MAX5982A/MAX5982B/MAX5982C (see
the Typical Application Circuit). Since the PSE uses
a slope technique (DV/DI) to calculate the signature
resistance, the DC offset due to the protection diodes is
subtracted and does not affect the detection process.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD based
on the power consumption required by the PD. This allows
the PSE to efficiently manage power distribution. Class
0–5 is defined as shown in Table 1. (The IEEE 802.3af/at
standard defines only Class 0–4 and Class 5 for any special requirement.) An external resistor (RCLS) connected
from CLS to VSS sets the classification current.
The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5982A/MAX5982B/MAX5982C
exhibit a current characteristic with a value shown in
Table 1. The PSE uses the classification current information to classify the power requirement of the PD. The
classification current includes the current drawn by RCLS
and the supply current of the MAX5982A/MAX5982B/
MAX5982C so the total current drawn by the PD is within
the IEEE 802.3af/at standard figures. The classification
current is turned off whenever the device is in power mode.
2-Event Classification and Detection
During 2-Event classification, a Type 2 PSE probes PD
for classification twice. In the first classification event,
the PSE presents an input voltage between 12.6V and
20.5V and the MAX5982A/MAX5982B/MAX5982C present the programmed load ICLASS. The PSE then drops
the probing voltage below the mark event threshold of
10.1V and the MAX5982A/MAX5982B/MAX5982C present the mark current (IMARK). This sequence is repeated
one more time.
When the MAX5982A/MAX5982B/MAX5982C are powered by a Type 2 PSE, the 2-Event identification output
2EC asserts low after the internal isolation n-channel
MOSFET is fully turned on. 2EC current sink is turned
off when VDD goes below the UVLO threshold (VOFF)
and turns on when VDD goes above the UVLO threshold
(VON), unless VDD goes below VTHR to reset the latched
output of the Type 2 PSE detection flag.
Table 1. Setting Classification Current
IEEE 802.3at PD
CLASSIFICATION CURRENT
SPECIFICATION (mA)
MAXIMUM
POWER USED
BY PD
(W)
RCLS
(I)
0
0.44 to 12.95
615
12.6 to 20
1
0.44 to 3.94
117
12.6 to 20
2
3.84 to 6.49
66.5
12.6 to 20
17
20
16
21
3
6.49 to 12.95
43.7
12.6 to 20
26
30
25
31
4
12.95 to 25.5
30.9
12.6 to 20
36
44
35
45
5
> 25.5
21.3
12.6 to 20
54
64
51
68
CLASS
VIN*
(V)
CLASS CURRENT SEEN AT
VIN (mA)
MIN
MAX
MIN
0
4
0
5
9
12
8
13
*VIN is measured across the MAX5982A/MAX5982B/MAX5982C input VDD to VSS.
12 �������������������������������������������������������������������������������������
MAX
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Power Mode (Wake Mode)
The MAX5982A/MAX5982B/MAX5982C enter power
mode when VIN rises above the undervoltage-lockout threshold (VON). When VIN rises above VON, the
MAX5982A/MAX5982B/MAX5982C turn on the internal
n-channel isolation MOSFET to connect VSS to RTN with
inrush current limit internally set to 53mA when VRTN VSS > 7V and 135mA when VRTN - VSS < 7V. The isolation MOSFET is fully turned on when the voltage at RTN
is near VSS and the inrush current is reduced below the
inrush limit. Once the isolation MOSFET is fully turned
on, the MAX5982A/MAX5982B/MAX5982C change the
current limit to 1900mA (typ). The open-drain powergood output (PG) remains low for a minimum of tDELAY
until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush.
Undervoltage Lockout
The MAX5982A/MAX5982B/MAX5982C operate up to a
60V supply voltage with a turn-on UVLO threshold (VON)
at 35.4V and a turn-off UVLO threshold (VOFF) at 31V.
When the input voltage is above VON, the MAX5982A/
MAX5982B/MAX5982C enter power mode and the internal MOSFET is turned on. When the input voltage goes
below VOFF for more than tOFF_DLY, the MOSFET turns off.
Sleep and Ultra-Low-Power
Sleep Modes (MAX5982A/MAX5982B)
The MAX5982A/MAX5982B feature a sleep mode, which
pulls PG low while keeping the internal n-channel isolation MOSFET turned on. The PG output is used to disable downstream DC-DC converters reducing the power
consumption of the overall PD system in sleep mode. In
sleep mode, the LED driver output (LED) sources periodic current pulses. The LED current (ILED) is set by an
external resistor (RSL); see the Applications Information
section for more information. To enable sleep mode,
apply a falling edge to SL (MAX5982B) or hold SL low for
a minimum of 6 seconds after a falling edge.
An ultra-low-power sleep mode allows the MAX5982A/
MAX5982B to further reduce power consumption while
maintaining the power signature of the standard. The
ultra-low-power sleep enable input ULP is internally
held high with a 50kΩ pullup resistor to the internal 5V
bias of the MAX5982A/MAX5982B. To enable ultra-lowpower sleep sleep mode, set ULP to logic-low and apply
a falling edge to SL (MAX5982B) or hold SL low for a
minimum of 6s (MAX5982A). Apply a falling edge on the
wake-mode enable input (WK) to disable sleep or ultralow-power sleep mode and resume normal operation.
LED Driver (MAX5982A/MAX5982B)
The MAX5982A/MAX5982B drive an LED connected
from the output LED to VSS. During sleep mode/ultra-lowpower sleep mode, the LED is driven by current pulses
with the amplitude set by the resistor connected from SL
to VSS. The LED driver current amplitude is programmable from 10mA to 20mA using RSL according to the
following formula:
ILED =
645.75
(in amperes)
RSL + 1200
Power-Good Output
An open-drain output (PG) is used to allow disabling
downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS
for a period of tDELAY and until the internal isolation
MOSFET is fully turned on. The PG is also pulled low
during sleep mode and coming out of thermal shutdown.
Thermal-Shutdown Protection
The MAX5982A/MAX5982B/MAX5982C include thermal
protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +150NC,
the MAX5982A/MAX5982B/MAX5982C turn off the internal
power MOSFET, LED driver, and 2EC current sink. When
the junction temperature falls below +120NC, the devices
enter inrush mode and then return to power mode. Inrush
mode ensures the downstream DC-DC converter is turned
off as the internal power MOSFET is turned on.
Wall Power Adapter Detection and Operation
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD,
the MAX5982A/MAX5982B/MAX5982C feature wall
power adapter detection. The MAX5982A/MAX5982B/
MAX5982C give highest priority to the WAD and smoothly switch the power supply to WAD when it is detected.
Once the input voltage (VDD - VSS) exceeds the mark
event threshold, the MAX5982A/MAX5982B/MAX5982C
enable wall adapter detection. The wall power adapter is connected from WAD to RTN. The MAX5982A/
MAX5982B/MAX5982C detect the wall power adapter
when the voltage from WAD to RTN is greater than 9V.
When a wall power adapter is detected, the internal
n-channel isolation MOSFET turns off, 2EC current sink
turns on, and classification current is disabled if VIN is in
the classification range.
______________________________________________________________________________________ 13
MAX5982A/MAX5982B/MAX5982C
Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5982A/MAX5982B/
MAX5982C are powered by an external wall power
adapter. See the Wall Power Adapter Detection and
Operation section for more information.
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Applications Information
2) Use large SMT component pads for power dissipating devices such as the MAX5982A/MAX5982B/
MAX5982C and the external diodes.
Operation with 12V Adapter
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:
3) Use short and wide traces for high-power paths.
4) Place enough vias in the pad for the EP of the
MAX5982A/MAX5982B/MAX5982C so that heat generated inside can be effectively dissipated by the
PCB copper. The recommended spacing for the vias
is 1mm to 1.2mm pitch. The thermal vias should be
plated (1oz copper) and have a small barrel diameter
(0.3mm to 0.33mm).
1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5982A/MAX5982B/MAX5982C.
2-EVENT
CLASSIFICATION
(ASSERTED ON)
GND
VDD
RJ-45
AND
BRIDGE
RECTIFIER
DET
MAX5982A
MAX5982B
MAX5982C
I.5mA
DC-DC
CONVERTER
WAD
12V
BATTERY
RCLS
IN-
VSS
-54V
GND
ENABLE
2EC/WAD
CLS
SMAJ58A
IN+
PG
RDET
24.9kI
68nF
2EC
RTN
THIS CIRCUIT ACHIEVES
PROPER 2EC LOGIC WHEN
BATTERY IS < 12.5V
WALK MODE
INPUT
WK
MAX5982A/MAX5982B ONLY
1kI
SL
ISOLATED SLEEP
MODE INPUT
60.4kI
ULP
-54V
LED
ULTRA-LOW-POWER
SLEEP
-54V
-54V
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
14 �������������������������������������������������������������������������������������
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
ISOLATED 2-EVENT
CLASSIFICATION
OUTPUT
GND
GND
2EC
VDD
2EC/WAD
VAC
DET
68nF
CLS
SMAJ58A
VAC
WAD
MAX5982A
MAX5982B
MAX5982C
1.4mA
24/48V
BATTERY
43.7I
VSS
-54V
GND
CBULK
NT
RIN
D2
CIN
L2
RTN
RTN
D3
RDCLMP1
T1
NP
IN
PG
RTN
RTN
D1
L1
RTN
PG
PG
24.9kI
NS
RGATE2
RFB1
COUT1 COUT2 COUT3 COUT4 COUT5
RGATE1
N
N2
5i412DP
RFB2
EN
D4
RDCLMP2
N
DCLMP
CSS
SS
RDT
MAX5974C
MAX5974D
IN
N3
DT
CDITHER
RTN
N1
ROPTO3
CCLAMP
RGATE3
DITHER/
SYNC
NDRV
RCOMP2
U1
P
AUXDRV
RT
CCOMP1
N
RGATE4
RRT
ROPTO1
CCOMP2
N4
CAUX
RBIAS
18V
RFFB
RF
FFB
RTN
CF
FB
RG1
CINT
CS
RG2
RCOMP2
RTN
COMP
RTN
D5
CSSC
GND
PGND
RCSSC
RTN
ROPTO2
RTN
RTN
RAUX
RTN
U2
RTN
RCS
RTN
______________________________________________________________________________________ 15
MAX5982A/MAX5982B/MAX5982C
Typical Application Circuit
MAX5982A/MAX5982B/MAX5982C
IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
Ordering Information
PART
SLEEP/ULTRA-LOWPOWER MODE
6s FILTER DELAY ON SL
16 TQFN-EP*
Yes
Yes
16 TQFN-EP*
Yes
No
16 TQFN-EP*
No
––
TEMP RANGE
PIN-PACKAGE
MAX5982AETE+
-40NC to +85NC
MAX5982BETE+
-40NC to +85NC
MAX5982CETE+
-40NC to +85NC
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN-EP
T1655+4
21-0140
90-0121
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IEEE 802.3af/at-Compliant, Powered Device Interface
Controllers with Integrated 70W High-Power MOSFET
REVISION
NUMBER
REVISION
DATE
0
6/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©
2011 Maxim Integrated Products
17
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX5982A/MAX5982B/MAX5982C
Revision History