TI1 OPA4322AQPWQ1 Cmos operational amplifier with shutdown Datasheet

OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
20-MHz, Low-Noise, 1.8-V, RRI/O,
CMOS Operational Amplifier With Shutdown
Check for Samples: OPA322-Q1, OPA322S-Q1, OPA2322-Q1, OPA2322S-Q1, OPA4322-Q1, OPA4322S-Q1
FEATURES
DESCRIPTION
•
•
The OPA322-Q1 family consists of single, dual, and
quad-channel CMOS operational amplifiers featuring
low noise and rail-to-rail inputs/outputs optimized for
low-power, single-supply applications. Specified over
a wide supply range of 1.8 V to 5.5 V, and with a low
quiescent current of only 1.5 mA per channel, these
devices
are
well-suited
for
power-sensitive
applications.
1
23
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H3A
– Device CDM ESD Classification Level C5
Gain Bandwidth: 20 MHz
Low Noise: 8.5 nV/√Hz at 1 kHz
Slew Rate: 10 V/μs
Low THD+N: 0.0005%
Rail-to-Rail I/O
Offset Voltage: 2 mV (max)
Supply Voltage: 1.8 V to 5.5 V
Supply Current: 1.5 mA/ch
– Shutdown: 0.1 μA/ch
Unity-Gain Stable
Small Packages:
– SOT23, DFN, MSOP, TSSOP
APPLICATIONS
•
•
•
•
•
•
•
•
Automotive
Sensor Signal Conditioning
Consumer Audio
Multi-Pole Active Filters
Control-Loop Amplifiers
Communications
Security
Scanners
The combination of very low noise (8.5 nV/√Hz at
1 kHz), high gain-bandwidth (20 MHz), and fast slew
rate (10 V/μs) make the OPA322-Q1 family ideal for a
wide range of applications, including signal
conditioning and sensor amplification requiring high
gains. Featuring low THD+N, the OPA322-Q1 family
is also excellent for consumer audio applications,
particularly for single-supply systems.
The OPAx322S-Q1 models include a shutdown mode
allowing the amplifiers to switch from normal
operation to a standby current that is typically less
than 0.1 μA.
The OPA322-Q1 (single version) is available in
SOT23-5 and SOT23-6, whereas the OPA2322 (dual
version) comes in MSOP-8, MSOP-10, SO-8, and
DFN-8 packages. The quad versions OPA4322 come
in TSSOP-14 and TSSOP-16 packages. The
specification on all versions is for operation from
–40°C to 125°C.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FilterPro is a trademark of Texas Instruments Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VS = (V+) – (V–)
UNIT
6
V
(V–) – 0.5 to (V+) + 0.5
V
±10
mA
Output short-circuit current (3)
Continuous
mA
Operating temperature, TA
–40 to 125
°C
Storage temperature, Tstg
–65 to 150
°C
Junction temperature, TJ
150
°C
4
kV
1000
V
Signal input pins
ESD ratings
(1)
(2)
(3)
2
Voltage
(2)
OPA322-Q1, OPA322S-Q1, OPA2322-Q1,
OPA2322S-Q1, OPA4322-Q1, OPA4322S-Q1
Current (2)
Human-body model (HBM) AEC-Q100
Classification Level H3A
Charged-device model (CDM) AEC-Q100
Classification Level C5
Stresses above these ratings may cause permanent damage. Exposure to absolute-maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
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OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
THERMAL INFORMATION: OPA322-Q1
OPA322-Q1
THERMAL METRIC (1)
OPA322S-Q1
DBV
DBV
5 PINS
6 PINS
UNIT
θJA
Junction-to-ambient thermal resistance
219.3
177.5
°C/W
θJC(top)
Junction-to-case(top) thermal resistance
107.5
108.9
°C/W
θJB
Junction-to-board thermal resistance
57.5
27.4
°C/W
ψJT
Junction-to-top characterization parameter
7.4
13.3
°C/W
ψJB
Junction-to-board characterization parameter
56.9
26.9
°C/W
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Spacer
THERMAL INFORMATION: OPA2322-Q1
OPA2322-Q1
THERMAL METRIC (1)
OPA2322S-Q1
D
DRG
DGK
DGS
8 PINS
8 PINS
8 PINS
10 PINS
UNIT
θJA
Junction-to-ambient thermal resistance
122.6
50.6
174.8
171.5
°C/W
θJC(top)
Junction-to-case(top) thermal resistance
67.1
54.9
43.9
43.0
°C/W
θJB
Junction-to-board thermal resistance
64.0
25.2
95.0
91.4
°C/W
ψJT
Junction-to-top characterization parameter
13.2
0.6
2.0
1.9
°C/W
ψJB
Junction-to-board characterization parameter
63.4
25.3
93.5
89.9
°C/W
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
5.7
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Spacer
THERMAL INFORMATION: OPA4322-Q1
OPA4322-Q1
THERMAL METRIC (1)
OPA4322S-Q1
PW
PW
14 PINS
16 PINS
UNIT
θJA
Junction-to-ambient thermal resistance
109.8
105.9
°C/W
θJC(top)
Junction-to-case(top) thermal resistance
34.9
28.1
°C/W
θJB
Junction-to-board thermal resistance
52.5
51.1
°C/W
ψJT
Junction-to-top characterization parameter
2.2
0.8
°C/W
ψJB
Junction-to-board characterization parameter
51.8
50.4
°C/W
θJC(bottom)
Junction-to-case(bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2013, Texas Instruments Incorporated
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3
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C.
At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, VOUT = VS / 2, and SHDN_x = VS+, unless otherwise noted.
PARAMETER
TEST CONDITIONS
OPA322-Q1, OPA322S-Q1, OPA2322-Q1,
OPA2322S-Q1, OPA4322-Q1, OPA4322S-Q1
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input offset voltage
versus Temperature
versus Power supply
VOS
dVOS/dT
PSR
Over temperature
Channel separation
0.5
2
mV
VS = 5.5 V
1.8
6
μV/°C
VS = 1.8 V to 5.5 V
10
50
μV/V
VS = 1.8 V to 5.5 V
20
65
μV/V
At 1 kHz
130
dB
INPUT VOLTAGE
Common-mode voltage range
VCM
Common-mode rejection ratio
CMRR
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) + 0.1 V
Over temperature
90
(V+) + 0.1
100
V
dB
90
dB
INPUT BIAS CURRENT
Input bias current
IB
Over temperature
Input offset current
±10
pA
TA = –40°C to 85°C
±0.2
±50
pA
OPA322-Q1, OPA322S-Q1, TA = –40°C to
125°C
±800
pA
OPA2322, OPA2322S, TA = –40°C to 125°C
±600
pA
OPA4322, OPA4322S, TA = –40°C to 125°C
±400
pA
IOS
±0.2
Over temperature
±10
pA
TA = –40°C to 85°C
±50
pA
TA = –40°C to 125°C
±600
pA
NOISE
f = 0.1 Hz to 10 Hz
2.8
μVPP
f = 1 kHz
8.5
nV/√Hz
f = 10 kHz
7
nV/√Hz
f = 1 kHz
0.6
fA/√Hz
Differential
5
pF
Common-mode
4
pF
Input voltage noise
Input voltage noise density
en
Input current noise density
in
INPUT CAPACITANCE
OPEN-LOOP GAIN
Open-loop voltage gain
AOL
Phase margin
PM
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
100
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
94
VS = 5 V, CL = 50 pF
FREQUENCY RESPONSE
Gain bandwidth product
Slew rate
GBP
4
Degrees
Unity gain
20
MHz
G=1
10
V/μs
To 0.1%, 2-V step, G = 1
0.25
μs
0.32
μs
VIN × G > VS
100
ns
VO = 4 VPP, G = 1, f = 10 kHz, RL = 10 kΩ
0.0005
%
VO = 2 VPP, G = 1, f = 10 kHz, RL = 600 Ω
0.0011
%
Overload recovery time
(1)
47
To 0.01%, 2-V step, G = 1
tS
Total harmonic distortion +
noise (1)
dB
dB
VS = 5.0 V, CL = 50 pF
SR
Settling time
130
THD+N
Third-order filter; bandwidth = 80 kHz at –3 dB
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OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS: VS = 1.8 V to 5.5 V, or ±0.9 V to ±2.75 V (continued)
Boldface limits apply over the specified temperature range, TA = –40°C to 125°C.
At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, VOUT = VS / 2, and SHDN_x = VS+, unless otherwise noted.
PARAMETER
OPA322-Q1, OPA322S-Q1, OPA2322-Q1,
OPA2322S-Q1, OPA4322-Q1, OPA4322S-Q1
TEST CONDITIONS
MIN
UNIT
TYP
MAX
10
30
mV
40
mV
OUTPUT
Voltage output swing from
both rails
VO
Over temperature
RL = 10 kΩ
RL = 10 kΩ
Short-circuit current
ISC
Capacitive load drive
CL
Open-loop output resistance
RO
VS = 5.5 V
±65
mA
See Typical Characteristics
IO = 0 mA, f = 1 MHz
Ω
90
POWER SUPPLY
Specified voltage range
Quiescent current per amplifier
VS
IQ
1.8
OPA322-Q1, OPA322S-Q1
IO = 0 mA, VS = 5.5 V
Over temperature
IO = 0 mA, VS = 5.5 V
OPA2322-Q1, OPA2322S-Q1
IO = 0 mA, VS = 5.5 V
Over temperature
IO = 0 mA, VS = 5.5 V
OPA4322-Q1, OPA4322S-Q1
IO = 0 mA, VS = 5.5 V
Over temperature
1.6
1.5
1.4
IO = 0 mA, VS = 5.5 V
Power-on time
VS+ = 0 V to 5 V, to 90% IQ level
SHUTDOWN (2)
VS = 1.8 V to 5.5 V
Quiescent current, per amplifier
IQSD
All amplifiers disabled, SHDN = VS–
High voltage (enabled)
VIH
Amplifier enabled
Low voltage (disabled)
VIL
Amplifier disabled
0.1
Amplifier enable time (partial
shutdown) (3)
tON
Partial shutdown; G = 1, VOUT = 0.9 × VS / 2
SHDN pin input bias current (per pin)
mA
1.75
mA
1.85
mA
1.65
mA
1.75
mA
μs
0.5
(4)
(4)
µA
V
(V–) + 0.1
Full shutdown; G = 1, VOUT = 0.9 × VS / 2
tOFF
mA
2
(V+) - 0.1
tON
Amplifier disable time
V
1.9
28
Amplifier enable time (full
shutdown) (3)
(3)
5.5
IO = 0 mA, VS = 5.5 V
V
10
µs
6
µs
G = 1, VOUT = 0.1 × VS / 2
3
µs
VIH = 5 V
0.13
µA
VIL = 0 V
0.04
µA
TEMPERATURE
Specified range
–40
125
°C
Operating range
–40
150
°C
(2)
(3)
(4)
Ensured by design and characterization; not production tested.
The definition of isable time (tOFF) and enable time (tON) is the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
Full shutdown refers to the dual OPA2322S-Q1 having both channels A and B disabled (SHDN_A = SHDN_B = VS–) and the quad
OPA4322S-Q1 having all channels A to D disabled (SHDN_A/B = SHDN_C/D = VS–). Partial shutdown exercises only one SHDN pin; in
this mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
OUT
1
V-
2
+IN
3
DRG PACKAGE(1)(2)
DFN-8
(TOP VIEW)
V+
5
OUT A
4
1
-IN A
2
+IN A
3
V-
4
-IN
DBV PACKAGE
SOT23-6
(TOP VIEW)
8
V+
7
OUT B
6
-IN B
5
+IN B
Exposed
Thermal
Die Pad
on
Underside
PW PACKAGE
TSSOP-14
(TOP VIEW)
VOUT
1
6
V+
V-
2
5
SHDN
+IN
3
4
-IN
OUT A
DGS PACKAGE
MSOP-10
(TOP VIEW)
VOUT A
1
10 V+
-IN A
2
9
VOUT B
+IN A
3
8
-IN B
1
14 OUT D
A
D
13 -IN D
-IN A
2
+IN A
3
12 +IN D
V+
4
11 V-
+IN B
5
10 +IN C
-IN B
6
OUT B
7
B
C
9
-IN C
8
OUT C
A
B
V-
4
7
+IN B
SHDN A
5
6
SHDN B
PW PACKAGE
TSSOP-16
(TOP VIEW)
OUT A
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
6
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
(1)
Connect thermal pad to V–.
(2)
Pad size: 2 mm × 1.2 mm.
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8
V+
7
OUT B
6
-IN B
5
+IN B
1
16 OUT D
A
D
15 -IN D
-IN A
2
+IN A
3
14 +IN D
V+
4
13 V-
+IN B
5
12 +IN C
-IN B
6
OUT B
7
10 OUT C
SHDN A/B
8
9
B
C
11 -IN C
SHDN C/D
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OPEN-LOOP GAIN/PHASE versus FREQUENCY
125
-40
120
100
-60
115
80
-80
60
-100
40
-120
20
-140
-20
10
1
100
1k
10k
100k
1M
10M
Phase (°)
Gain
Phase
0
10 kW Load
Open-Loop Gain (dB)
RL = 10 kW, 50 pF
VS = ±2.5 V
120
Gain (dB)
OPEN-LOOP GAIN versus TEMPERATURE
-20
140
110
2 kW Load
105
100
95
-160
90
-180
100M
85
-50
-25
0
25
100
125
150
Figure 2.
INPUT BIAS CURRENT versus SUPPLY VOLTAGE
INPUT BIAS CURRENT versus COMMON-MODE VOLTAGE
6
0.8
5
4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2
1
0
-1
-2
-3
IB+
IBIOS
-5
-6
2.9
2.7
3
-4
IBIB+
-0.8
-3 -2.5 -2 -1.5 -1 -0.5 0
Supply Voltage (±V)
0.5
1
1.5
2
3
2.5
Common-Mode Voltage (V)
Figure 3.
Figure 4.
INPUT BIAS CURRENT versus TEMPERATURE
QUIESCENT CURRENT versus SUPPLY VOLTAGE
1.6
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
-100
IOS
IB+
IB-
IB
IOS
Quiescent Current (mA/Ch)
Input Bias Current (pA)
75
Figure 1.
1
-1
50
Temperature (°C)
Input Bias Current (pA)
Input Bias Current (pA)
Frequency (Hz)
1.55
1.5
1.45
1.4
+125°C
+85°C
1.35
+25°C
-40°C
1.3
-50
-25
0
25
50
75
Temperature (°C)
Figure 5.
Copyright © 2013, Texas Instruments Incorporated
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Supply Voltage (V)
Figure 6.
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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION HISTOGRAM
OFFSET VOLTAGE versus COMMON-MODE VOLTAGE
1
14
0.8
0.6
Offset Voltage (mV)
Number of Amplifiers (%)
12
10
8
6
4
0.4
0.2
0
-0.2
-0.4
-0.6
2
Representative Units
VS = ±2.75 V
-0.8
0
-3
1.5
1.1
1.3
0.9
0.5
0.7
0.1
0.3
-0.1
-0.3
-0.5
-0.7
-1.1
-0.9
-1.3
-1.5
-1
-2
0
-1
1
3
2
Common-Mode Voltage (V)
Offset Voltage (mV)
Figure 7.
Figure 8.
INPUT VOLTAGE NOISE SPECTRAL DENSITY versus
FREQUENCY
0.1 Hz TO 10 Hz INPUT VOLTAGE NOISE
6
VS = 1.8 V to 5.5 V
5
4
3
100
Voltage (mV)
Voltage Noise (nV/ÖHz)
1000
10
2
1
0
-1
-2
-3
1
-4
10
100
1k
10 k
1M
100 k
0
1
2
3
Frequency (Hz)
G = +10 V/V
-20
10 k
8
1M
9
10
20
G = +10 V/V
10 M
100 M
-20
10 k
G = +1 V/V
100 k
1M
Frequency (Hz)
Frequency (Hz)
Figure 11.
Figure 12.
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8
VS = +5.5 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
0
G = +1 V/V
100 k
40
Gain (dB)
Gain (dB)
20
0
7
CLOSED-LOOP GAIN versus FREQUENCY
60
VS = +1.8 V
RL = 10 kW
CL = 50 pF
G = +100 V/V
6
Figure 10.
CLOSED-LOOP GAIN versus FREQUENCY
40
5
Time (s)
Figure 9.
60
4
10 M
100 M
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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
www.ti.com
SLOS856A – JUNE 2013 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
MAXIMUM OUTPUT VOLTAGE versus FREQUENCY
OUTPUT VOLTAGE SWING versus OUTPUT CURRENT
6
3
5.5 VS
2
4
Output Voltage (V)
Output Voltage (VPP)
5
3.3 VS
3
2
1
-40°C
+25°C
+125°C
0
-1
1.8 VS
1
-2
RL = 10 kW
CL = 50 pF
VS = ±2.75 V
0
10 k
-3
100 k
10 M
1M
10
0
20
Frequency (Hz)
30
40
50
70
80
Figure 13.
Figure 14.
OPEN-LOOP OUTPUT IMPEDANCE versus FREQUENCY
SMALL-SIGNAL OVERSHOOT versus LOAD CAPACITANCE
1000
70
G = 1, VS = 1.8 V
VS = ±2.75 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
50
Overshoot (%)
Impedance (W)
60
Output Current (mA)
100
G = 10, VS = 5.5 V
40
30
20
10
0
10
1
10
100
1k
10 k
100 k
1M
10 M 100 M
500
0
1000
Frequency (Hz)
Figure 15.
0.01
Load = 600 W
0.001
Frequency = 10 kHz
VS = ±2.5 V
G = +1 V/V
Load = 10 kW
1
VIN (VPP)
Figure 17.
Copyright © 2013, Texas Instruments Incorporated
2500
3000
THD+N versus FREQUENCY
Total Harmonic Distortion and Noise (%)
Total Harmonic Distortion and Noise (%)
THD+N versus AMPLITUDE
0.1
2000
Figure 16.
0.1
0.0001
0.01
1500
Capacitive Load (pF)
10
0.1
Frequency = 10 kHz
VIN = 2 VPP
VS = ±2.5 V
G = +1 V/V
0.01
Load = 600 W
0.001
Load = 10 kW
0.0001
10
100
1k
10 k
100 k
Frequency (Hz)
Figure 18.
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9
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
CHANNEL SEPARATION versus FREQUENCY (for Dual)
0
Frequency = 10 kHz
VIN = 4 VPP
VS = ±2.5 V
G = +1 V/V
VS = ±2.75 V
-20
Channel Separation (dB)
Total Harmonic Distortion and Noise (%)
THD+N versus FREQUENCY
0.1
0.01
Load = 600 W
0.001
-60
-80
-100
-120
Load = 10 kW
0.0001
-40
-140
10
100
1k
1k
100 k
10 k
10 k
1M
Frequency (Hz)
Figure 19.
Figure 20.
SLEW RATE versus SUPPLY VOLTAGE
10 M
100 M
SMALL-SIGNAL STEP RESPONSE
12
0.1
CL = 50 pF
Gain = +1
VS = ±2.75 V
VIN = 100 mVPP
0.075
11.5
0.05
11
Voltage (V)
Slew Rate (V/ms)
100 k
Frequency (Hz)
Rise
10.5
Fall
10
0.025
0
-0.025
-0.05
9.5
VOUT
VIN
-0.075
9
1.6
2
2.4
2.8
3.2
3.6
4
4.4
4.8
5.2
-0.1
-0.8
5.6
-0.4
0
0.4
Supply Voltage (V)
Figure 21.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE versus TIME
1.5
0.075
VIN
Gain = -1
VS = ±2.75 V
VIN = 100 mVPP
Voltage (V)
Voltage (V)
Gain = +1
VS = ±2.75 V
VIN = 2 VPP
1
0.05
0
1.6
1.2
Figure 22.
0.1
0.025
0.8
Time (ms)
-0.025
0.5
VOUT
0
-0.5
-0.05
-0.1
-1.6
-1.2
-0.8
-0.4
Time (ms)
Figure 23.
10
-1
VOUT
VIN
-0.075
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0
0.4
0.8
-1.5
-0.4
0
0.4
0.8
1.2
1.6
Time (ms)
Figure 24.
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Product Folder Links: OPA322-Q1 OPA322S-Q1 OPA2322-Q1 OPA2322S-Q1 OPA4322-Q1 OPA4322S-Q1
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
TYPICAL CHARACTERISTICS (continued)
At TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ, unless otherwise noted.
CMRR AND PSRR versus FREQUENCY
TURN-OFF TRANSIENT
3
Shutdown Signal
Output Signal
2.4
100
1.8
1.2
80
Voltage (V)
Common-Mode Rejection Ratio,
Power-Supply Rejection Ratio (dB)
120
60
40
0.6
0
−0.6
−1.2
−1.8
20
PSRR
CMRR
−2.4
−3
0
1k
100
10k
100k
1M
0
2
4
6
8
Frequency (Hz)
Figure 25.
2.4
1.8
Voltage (V)
Voltage (V)
1.2
0.6
0
−0.6
−1.2
−1.8
Shutdown Signal
Output Signal
−2.4
2
4
6
8
16
18
20
G000
TURN-ON AND TURN-OFF TRANSIENT 5.5V
(High Supply)
TURN-ON TRANSIENT
0
14
Figure 26.
3
−3
10
12
Time (µs)
10
12
Time (µs)
14
16
18
20
G000
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
−5
Shutdown Signal
Output Signal
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
Figure 27.
Figure 28.
TURN-ON AND TURN-OFF TRANSIENT 1.8V
(Low Supply)
2
1.5
Voltage (V)
1
0.5
0
−0.5
−1
Shutdown Signal
Output Signal
−1.5
−2
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
G000
Figure 29.
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11
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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APPLICATION INFORMATION
OPERATING VOLTAGE
The OPA322-Q1 family of operational amplifiers are unity-gain stable and can operate on a single-supply voltage
(1.8 V to 5.5 V), or a split-supply voltage (±0.9 V to ±2.75 V), making them highly versatile and easy to use. The
power-supply pins should have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). The specifications
of these amplifiers fully apply from 1.8 V to 5.5 V and over the extended temperature range of –40°C to 125°C.
Parameters that can exhibit variance with regard to operating voltage or temperature are presented in the Typical
Characteristics.
INPUT AND ESD PROTECTION
The OPA322-Q1 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as
the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are
inherently current-limited to less than 10 mA; therefore, there is no need for a limiting resistor. Figure 30 shows
how one may add a series input resistor (RS) to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input; keep the value minimal in noise-sensitive applications.
V+
IOVERLOAD
10 mA, Max
VOUT
OPA322-Q1
VIN
RS
Figure 30. Input Current Protection
PHASE REVERSAL
The design of the OPA322-Q1 operational amplifiers is for immunity to phase reversal when the input pins
exceed the supply voltages, therefore providing further in-system stability and predictability. Figure 31 shows the
input voltage exceeding the supply voltage without any phase reversal.
4
VIN
VS = ±2.5 V
3
Voltage (V)
2
VOUT
1
0
-1
-2
-3
-4
-500
-250
0
250
500
750
1000
Time (ms)
Figure 31. No Phase Reversal
12
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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with high-impedance feedback networks, it may be necessary to add a
feedback capacitor across the feedback resistor, RF, as shown in Figure 32. This capacitor compensates for the
zero created by the feedback network impedance and the OPA322-Q1 input capacitance (and any parasitic
layout capacitance). The effect becomes more significant with higher-impedance networks.
CF
RIN
RF
VIN
V+
CIN
RIN ´ CIN = RF ´ CF
OPA322-Q1
VOUT
CL
CIN
NOTE: Where CIN is equal to the OPA322-Q1 input capacitance (approximately 9 pF) plus any parasitic layout capacitance.
Figure 32. Feedback Capacitor Improves Dynamic Performance
TI suggests the use of a variable capacitor for the feedback capacitor, because input capacitance may vary
between operational amplifiers and layout capacitance is difficult to determine. For the circuit shown in Figure 32,
choose the value of the variable feedback capacitor so that the input resistance times the input capacitance of
the OPA322-Q1 (typically 9 pF) plus the estimated parasitic layout capacitance equals the feedback capacitor
times the feedback resistor:
RIN × CIN = RF × CF
where:
CIN is equal to the OPA322-Q1 input capacitance (sum of differential and common-mode) plus the layout
capacitance.
Adjust the capacitor value until optimum performance is obtained.
EMI SUSCEPTIBILITY AND INPUT FILTERING
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
device, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This
shift is a result of signal rectification associated with the internal semiconductor junctions. Although EMI can
affect all operational amplifier pin functions, the input pins are likely to be the most susceptible. The OPA322-Q1
operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to
EMI. The input filter proviede both common-mode and differential-mode filtering. The filter design is for a cutoff
frequency of approximately 580 MHz (–3 dB), with a rolloff of 20 dB per decade.
OUTPUT IMPEDANCE
The open-loop output impedance of the OPA322-Q1 common-source output stage is approximately 90 Ω.
Connecting the operational amplifier with feedback significantly reduces this value by the loop gain. For each
decade rise in the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold
increase in effective output impedance. While the OPA322-Q1 output impedance remains very flat over a wide
frequency range, at higher frequencies the output impedance rises as the open-loop gain of the operational
amplifier drops. However, at these frequencies the output also becomes capacitive as a result of parasitic
capacitance. This characteristic, in turn, prevents the output impedance from becoming too high, which can
cause stability problems when driving large capacitive loads. As mentioned previously, the OPA322-Q1 has
excellent capacitive load-drive capability for an operational amplifier with its bandwidth.
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13
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
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CAPACITIVE LOAD AND STABILITY
The OPA322-Q1 design is for use in applications where driving a capacitive load is required. As with all
operational amplifiers, there may be specific instances where the OPA322-Q1 can become unstable. The
particular operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to
consider when establishing whether an amplifier is stable in operation. An operational amplifier in the unity-gain
(1 V/V) buffer configuration and driving a capacitive load exhibits a greater tendency to become unstable than an
amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output
resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the
phase margin increases as the capacitive loading increases. When operating in the unity-gain configuration, the
OPA322-Q1 remains stable with a pure capacitive load up to approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (CL > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains, as shown in Figure 33. One technique
for increasing the capacitive load-drive capability of the amplifier operating in unity gain is to insert a small
resistor (RS), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 34.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is the creation of a voltage divider with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider, however, may be insignificant. For
instance, with a load resistance, RL = 10 kΩ and RS = 20 Ω, the gain error is only about 0.2%. However, when RL
is decreased to 600 Ω, which the OPA322-Q1 is able to drive, the error increases to 7.5%.
70
G = 1, VS = 1.8 V
60
G = 1, VS = 5.5 V
G = 10, VS = 1.8 V
Overshoot (%)
50
G = 10, VS = 5.5 V
40
30
20
10
0
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 33. Small-Signal Overshoot versus Capacitive Load (100-mVPP Output Step)
V+
RS
VOUT
OPA322-Q1
VIN
10 W to
20 W
RL
CL
Figure 34. Improving Capacitive Load Drive
14
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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
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SLOS856A – JUNE 2013 – REVISED JUNE 2013
OVERLOAD RECOVERY TIME
Overload recovery time is the time required for the output of the amplifier to come out of saturation and recover
to the linear region. Overload recovery is particularly important in applications with a requirement for smallsignals amplification in the presence of large transients. Figure 35 and Figure 36 show the positive and negative
overload recovery times of the OPA322-Q1, respectively. In both cases, the time elapsed before the OPA322-Q1
comes out of saturation is less than 100 ns. In addition, the symmetry between the positive and negative
recovery times allows excellent signal rectification without distortion of the output signal.
3
Output
0.5
Input
2
0
1.5
-0.5
Voltage (V)
Voltage (V)
1
VS = ±2.75 V
G = -10
2.5
1
0.5
0
-1
-1.5
-2
Input
Output
-0.5
VS = ±2.75 V
G = -10
-2.5
-1
9.75
10
10.25
10.5
10.75
Time (250 ns/div)
Figure 35. Positive Recovery Time
11
-3
9.75
10
10.25
10.5
10.75
11
Time (250 ns/div)
Figure 36. Negative Recovery Time
SHUTDOWN FUNCTION
The reference for the SHDN (enable) pin function of the OPAx322S-Q1 is to the negative supply voltage of the
operational amplifier. A logic-level high enables the operational amplifier. The definition of a valid logic high is
voltage [(V+) – 0.1 V], up to (V+), applied to the SHDN pin. The definition of a valid logic low is [(V–) + 0.1 V],
down to (V–), applied to the enable pin. The maximum allowed voltage applied to SHDN is 5.5 V with respect to
the negative supply, independent of the positive supply voltage. Drive this pin or connect it either to a valid high
or low voltage; do not leave it as an open circuit.
The logic input is a high-impedance CMOS input. Control of dual operational amplifier versions is independent,
and that of quad operational amplifier versions is in pairs with logic inputs. For battery-operated applications, use
of this feature may greatly reduce the average current and extend battery life. The enable time is 10 µs for full
shutdown of all channels; disable time is 3 μs. When disabled, the output assumes a high-impedance state. This
architecture allows the OPAx322S-Q1 to operate as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases with
increased load resistance. Ensuring shutdown (disable) within a specific shutdown time requires the specified 10kΩ load to mid-supply (VS / 2). Using the OPAx322S-Q1 without a load significantly increases the resulting turnoff time.
GENERAL LAYOUT GUIDELINES
The OPA322-Q1 is a wideband amplifier. To realize the full operational performance of the device, follow good
high-frequency printed circuit board (PCB) layout practices. Connect the bypass capacitors between each supply
pin and ground as close to the device as possible. Design the bypass capacitor traces for minimum inductance.
LEADLESS DFN PACKAGE
The OPA2322-Q1 uses the DFN style package (also known as SON), which is a QFN with contacts on only two
sides of the package bottom. This leadless package maximizes PCB space and offers enhanced thermal and
electrical characteristics through an exposed pad. One of the primary advantages of the DFN package is its low
height (0,8 mm).
DFN packages are physically small, and have a smaller routing area. Additionally, they offer improved thermal
performance, reduced electrical parasitics, and a pinout scheme that is consistent with other commonly-used
packages (such as SO and MSOP). The absence of external leads also eliminates bent-lead issues.
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15
OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
SLOS856A – JUNE 2013 – REVISED JUNE 2013
www.ti.com
Standard PCB-assembly techniques allow for easy mounting of the DFN package. See the application reports,
QFN/SON PCB Attachment (SLUA271) and Quad Flatpack No-Lead Logic Packages (SCBA017), both available
for download at www.ti.com. Connect the exposed leadframe die pad on the bottom of the DFN package to
the most-negative potential (V–). The dimension of the exposed thermal die pad is 2 mm ×
1,2 mm and is centered.
APPLICATION EXAMPLES
ACTIVE FILTER
The OPA322-Q1 is well-suited for active filter applications that require a wide-bandwidth, fast-slew-rate, lownoise, single-supply operational amplifier. Figure 37 shows a 500-kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The component selection provides a maximally-flat Butterworth response.
Beyond the cutoff frequency, rolloff is –40 dB/decade. The Butterworth response is ideal for applications that
require predictable gain characteristics, such as the anti-aliasing filter used in front of an ADC.
One point to observe when considering the MFB filter is its inverted output, relative to the input. If this inversion
is not required, or not desired, a one can achieve a noninverting output through one of these options:
1. Adding an inverting amplifier
2. Adding an additional second-order MFB stage
3. Using a noninverting filter topology, such as the Sallen-Key (shown in Figure 38).
One can quickly accomplish MFB and Sallen-Key, low-pass and high-pass filter synthesis using TI’s FilterPro™
program. This software is available as a free download at www.ti.com.
R3
549 W
C2
150 pF
R1
549 W
R2
1.24 kW
V+
VIN
VOUT
OPA322-Q1
C1
1 nF
V-
Figure 37. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V+
1.8 kW
19.5 kW
150 kW
VIN = 1 VRMS
3.3 nF
47 pF OPA322-Q1
VOUT
V-
Figure 38. OPA322-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
16
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OPA322-Q1, OPA322S-Q1
OPA2322-Q1, OPA2322S-Q1
OPA4322-Q1, OPA4322S-Q1
www.ti.com
SLOS856A – JUNE 2013 – REVISED JUNE 2013
REVISION HISTORY
Changes from Original (June 2013) to Revision A
Page
•
Changed from Product Preview to Production Data ............................................................................................................. 1
•
Removed ordering information table ..................................................................................................................................... 2
•
Changed input bias current max over temp limit from ±400 to ±600 .................................................................................... 4
•
Changed input offset current max over temp limit from ±400 to ±600 ................................................................................. 4
•
Changed max voltage output swing from both rails from 20 to 30. ...................................................................................... 5
•
Changed max over temperature limit from 30 to 40. ............................................................................................................ 5
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17
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
Device Marking
(4/5)
OPA2322AQDGKRQ1
ACTIVE
VSSOP
DGK
8
OPA4322AQPWQ1
PREVIEW
TSSOP
PW
14
90
TBD
Call TI
Call TI
-40 to 125
OPA4322AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
OVDQ
4322AQ1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2322-Q1, OPA4322-Q1 :
• Catalog: OPA2322, OPA4322
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Mar-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2322AQDGKRQ1
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA4322AQPWRQ1
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Mar-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2322AQDGKRQ1
VSSOP
OPA4322AQPWRQ1
TSSOP
DGK
8
2500
366.0
364.0
50.0
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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