CY7C1011G Automotive 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Features Functional Description CY7C1011G is a high-performance CMOS fast static RAM automotive part with embedded ECC. This device has a single Chip Enable (CE) input, and is accessed by asserting it LOW. ■ High speed ❐ tAA = 10 ns ■ Temperature range ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C ■ Embedded error-correcting code (ECC) for single-bit error correction[1] ■ Low active and standby current ❐ Active current, ICC = 40-mA typical (Automotive-E) ❐ Standby current, ISB2 = 6-mA typical (Automotive-E) ■ Operating voltage range: 2.2 V to 3.6 V ■ 1.0-V data retention ■ TTL compatible inputs and outputs ■ Available in Pb-free 48-ball VFBGA and 44-pin TSOP II packages To perform data writes, assert the Write Enable (WE) input LOW, and provide the data on the device data pins (I/O0 through I/O15) and address pins (A0 through A16) pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. You can access read data on the I/O lines (I/O0 through I/O15). To perform byte access, assert the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE LOW), or when the control signals are deasserted (OE, BLE, BHE). Logic Block Diagram – CY7C1011G MEMORY ARRAY ECC DECODER INPUT BUFFER SENSE AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER ECC ENCODER I/O0‐I/O7 I/O8‐I/O15 A10 A11 A12 A13 A14 A15 A16 COLUMN DECODER BHE WE OE CE BLE Note 1. This device does not support automatic write-back on error detection. Cypress Semiconductor Corporation Document Number: 001-95423 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 23, 2015 CY7C1011G Automotive Contents Pin Configurations ........................................................... 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 001-95423 Rev. *B Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 2 of 17 CY7C1011G Automotive Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1.2 mm) pinout[2] 1 2 BLE OE I/O 8 3 4 5 6 A0 A1 A2 NC A BHE A3 A4 CE I/O 0 B I/O 9 I/O 10 A5 A6 I/O 1 I/O 2 C VSS I/O 11 NC A7 I/O 3 VCC D VCC I/O 12 NC A 16 I/O 4 VSS E I/O 14 I/O 13 A 14 A 15 I/O 5 I/O 6 F I/O 15 NC A 12 A 13 WE I/O 7 G NC A8 A9 A 10 A 11 NC H Figure 2. 44-pin TSOP II pinout [2] A4 A3 A2 A1 A0 /CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 /WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 44-pin TSOP II 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 /OE /BHE /BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC Product Portfolio Power Dissipation Product CY7C1011G30 Range Automotive -E Automotive -A VCC Range (V) 2.2 V–3.6 V Speed (ns) 10 Operating ICC, (mA) f = fmax Standby, ISB2 (mA) Typ[3] Max Typ[3] Max 40 50 6 14 38 45 6 8 Notes 2. NC pins are not connected internally to the die. 3. Typical values are included for reference only and are not guaranteed or tested. Document Number: 001-95423 Rev. *B Page 3 of 17 CY7C1011G Automotive DC input voltage[4] .............................. –0.3 V to VCC + 0.3 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Supply voltage on VCC relative to GND[4] .....................–0.5 V to Vcc +0.3 V DC voltage applied to outputs in HI-Z State[4] ......................................–0.3 V to Vcc +0.3 V Current into outputs (in low state) ............................... 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Grade Ambient Temperature VCC Automotive-E –40 C to +125 C 2.2 V to 3.6 V Automotive-A –40 C to +85 C 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 10 ns (Automotive-A) 10 ns (Automotive-E) Unit Min Typ Max Min Typ Max 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – – 2 – – 2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – – 2.2 – – 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 – – 0.4 2.2 V to 2.7 V – 2 – VCC + 0.3[4] 2 – VCC + 0.3[4] 2.7 V to 3.6 V – 2 – VCC + 0.3[4] 2 – VCC + 0.3[4] 2.2 V to 2.7 V – –0.3[4] – 0.6 –0.3[4] – 0.6 – –0.3[4] – 0.8 –0.3[4] – 0.8 –1 – +1 –5 – +5 A –1 – +1 –5 – +5 A – 38 45 – 40 50 mA – – 15 – – 24 mA – 6 8 – 6 14 mA 2.7 V to 3.6 V IIX Input leakage current GND < VIN < VCC IOZ Output leakage current GND < VOUT < VCC, Output disabled ICC Operating supply current VCC = 3.6 V, IOUT = 0 mA, CMOS levels ISB1 Automatic CE power down current – TTL inputs VCC = 3.6 V, CE > VIH, f = fMAX = 1/tRC VIN > VIH or VIN < VIL, V V V V f = fMAX ISB2 Automatic CE power down current – CMOS inputs VCC = 3.6 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 Note 4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 2 ns. Document Number: 001-95423 Rev. *B Page 4 of 17 CY7C1011G Automotive Capacitance Parameter [5] Description CIN Input capacitance COUT I/O capacitance Test Conditions All Packages Unit 10 pF 10 pF TA = 25 C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [5] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA 44-pin TSOPII Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 30.68 66.82 C/W 14.83 15.97 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [6] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 Output 30 pF* * Including jig and scope (b) All Input Pulses VHIGH GND R2 5 pF* (a) * Capacitive load consists of all components of the test environment R1 90% 90% 10% 10% Rise Time: > 1 V/ns (c) Parameters 3.0 V Unit R1 317 R2 351 VTH 1.5 V VHIGH 3 V Fall Time: > 1 V/ns Notes 5. Tested initially and after any design or process change that may affect these parameters. 6. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization. Document Number: 001-95423 Rev. *B Page 5 of 17 CY7C1011G Automotive Data Retention Characteristics Over the Operating Range Parameter Description Conditions Automotive-A Automotive-E Min Max Min Max Unit VDR VCC for data retention – 1 – 1 – V ICCDR Data retention current VCC = 1.2 V, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V – 8 – 14 mA tCDR[7] Chip deselect to data re– tention time 0 – 0 – ns tR[7, 8] Operation recovery time VCC > 2.2 V 10 – 10 – ns Data Retention Waveform Figure 4. Data Retention Waveform[8] VCC VCC(min) DATA RETENTION MODE VDR = 1 V tCDR VCC(min) tR CE Notes 7. These parameters are guaranteed by design. 8. Full-device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. Document Number: 001-95423 Rev. *B Page 6 of 17 CY7C1011G Automotive AC Switching Characteristics Over the Operating Range Parameter [9] Description 10 ns (Automotive-A/ Automotive-E) Min Unit Max Read Cycle tRC Read cycle time 10 – ns tAA Address to data – 10 ns tOHA Data 3 – ns – 10 ns [9] tACE CE LOW to data tDOE OE LOW to data – 4.5 ns tLZOE OE LOW to low impedance [10, 11] 0 – ns – 5 ns 3 – ns – 5 ns 0 – ns – 10 ns – 4.5 ns 0 – ns – 6 ns 10 – ns tHZOE tLZCE OE HIGH to HI-Z [10, 11] CE LOW to low impedance [9, 10, 11] tHZCE CE HIGH to HI-Z tPU CE LOW to power up [9, 11] tPD CE HIGH to power down tDBE Byte enable to data valid Byte enable to low tHZBE Byte disable to HI-Z[11] tWC [9, 11] impedance[11] tLZBE Write Cycle [9, 10, 11] [12, 13] Write cycle time [9] tSCE CE LOW to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 5 – ns tHD Data hold from write end 0 – ns 3 – ns – 5 ns 7 – ns tLZWE WE HIGH to low impedance [10, 11] tHZWE WE LOW to HI-Z tBW Byte Enable to write end [10, 11] Notes 9. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 3 on page 5, unless specified otherwise. 10. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 5. Transition is measured 200 mV from steady state voltage. 11. These parameters are guaranteed by design and are not tested. 12. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 13. The minimum write cycle pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE. Document Number: 001-95423 Rev. *B Page 7 of 17 CY7C1011G Automotive Switching Waveforms Figure 5. Read Cycle No. 1 of CY7C1011G (Address Transition Controlled) [14, 15] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [15] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATA OUT VALID HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU ISB Notes 14. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 15. WE is HIGH for read cycle. Document Number: 001-95423 Rev. *B Page 8 of 17 CY7C1011G Automotive Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [16, 17, 18] ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE/ BLE OE tHZOE tHD tSD DATA I/O DATAIN VALID Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [16, 17, 18, 19] tWC ADDRESS tSCE CE tBW BHE/ BLE tSA tAW tHA tPWE WE t LZWE t HZWE DATA I/O tSD tHD DATAIN VALID Notes 16. Address valid prior to or coincident with CE LOW transition. 17. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 19. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. Document Number: 001-95423 Rev. *B Page 9 of 17 CY7C1011G Automotive Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (BLE or BHE Controlled) [20, 21] tWC ADDRESS tSCE CE tAW tSA tHA tBW BHE/ BLE tPWE WE t HZWE tHD tSD DATA I/O t LZWE DATA IN VALID Figure 10. Write Cycle No. 4 (WE Controlled) [20, 21, 22] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O Note 23 DATA IN VALID tHZOE Notes 20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 22. Data I/O is high impedance if OE = VIH. 23. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-95423 Rev. *B Page 10 of 17 CY7C1011G Automotive Truth Table CE OE WE BLE BHE H X X X X HI-Z HI-Z Power-down Standby (ISB) L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out HI-Z Read lower bits only Active (ICC) L L H H L HI-Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in HI-Z Write lower bits only Active (ICC) L X L H L HI-Z Data in Write upper bits only Active (ICC) L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC) I/O0–I/O7 Document Number: 001-95423 Rev. *B I/O8–I/O15 Mode Power Page 11 of 17 CY7C1011G Automotive Ordering Information Speed (ns) 10 Voltage Range Ordering Code Package Diagram Package Type (All Pb-free) Operating Range CY7C1011G30-10BAJXE 2.2 V–3.6 V 001-85259 48-ball VFBGA Automotive-E CY7C1011G30-10ZSXE 2.2 V–3.6 V 51-85087 44-pin TSOP II Automotive-E CY7C1011G30-10ZSXA 2.2 V–3.6 V 51-85087 44-pin TSOP II Automotive-A Ordering Code Definitions CY 7 C 1 04 1 G XX - 10 XX J X X Temperature Range: X = E or A E = Automotive-E, A = Automotive-A Pb-free J = JEDEC Compliant (only for BGA package) Package Type: XX = BA or ZS BA = 48-ball VFBGA; ZS = 44-pin TSOP II Speed: 10 ns Voltage Range: 30 = 2.2 V–3.6 V Revision Code “G”: Process Technology – 65 nm Data width: 1 = × 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-95423 Rev. *B Page 12 of 17 CY7C1011G Automotive Package Diagrams Figure 11. 48-ball VFBGA (6 × 8 × 1.2 mm) BA48M/BK48M (0.35 mm Ball Diameter) Package Outline, 001-85259 001-85259 *A Document Number: 001-95423 Rev. *B Page 13 of 17 CY7C1011G Automotive Package Diagrams (continued) Figure 12. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 001-95423 Rev. *B Page 14 of 17 CY7C1011G Automotive Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degrees Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-95423 Rev. *B Symbol Unit of Measure Page 15 of 17 CY7C1011G Automotive Document History Page Document Title: CY7C1011G Automotive, 2-Mbit (128K words × 16 bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-95423 Rev. ECN No. Orig. of Change Submission Date *A 4998910 NILE 11/02/2015 Changed status from Preliminary to Final. *B 5024020 NILE 11/23/2015 Updated Ordering Information: Updated part numbers. Document Number: 001-95423 Rev. *B Description of Change Page 16 of 17 CY7C1011G Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-95423 Rev. *B Revised November 23, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 17 of 17