Product Folder Sample & Buy Support & Community Tools & Software Technical Documents DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 DLP9000 Family of 0.9 WQXGA Type A DMDs 1 Features 2 Applications • • 1 • • • High Resolution 2560×1600 (WQXGA) Array – > 4 Million Micromirrors – 7.56-µm Micromirror Pitch – 0.9-Inch Micromirror Array Diagonal – ±12° Micromirror Tilt Angle (Relative to Flat State) – Designed for Corner Illumination – Integrated Micromirror Driver Circuitry – Two High Speed Options DLP9000X With a Single DLPC910 Digital Controller – 480 MHz Input Data Clock Rate – Up to 61 Giga-Bits Per Second (with Continuous Streaming Input Data) – Up to 14989 Hz (1-Bit Binary Patterns) – Up to 1873 Hz (8-Bit Gray Patterns With Illumination Modulation) DLP9000 with Dual DLPC900 Digital Controllers – 400 MHz Input Data Clock Rate – Up to 38 Giga-Bits per Second (With Up to 400 Pre-Stored Binary Patterns) – Up to 9523 Hz (1-Bit Binary Patterns) – Up to 1031 Hz (8-Bit Gray Patterns PreLoaded With Illumination Modulation), External Input Up to 360 Hz Designed for Use With Broad Wavelength Range – 400 nm to 700 nm – Window Transmission 95% (Single Pass, Through Two Window Surfaces) – Micromirror Reflectivity 88% – Array Diffraction Efficiency 86% – Array Fill Factor 92% • • Industrial – Machine Vision and Quality Control – 3D Printing – Direct Imaging Lithography – Laser Marking and Repair Medical – Ophthalmology – 3D Scanners for Limb and Skin Measurement – Hyper-Spectral Imaging – Hyper-Spectral Scanning Displays – 3D Imaging Microscopes – Intelligent and Adaptive Lighting 3 Description Featuring over 4 million micromirrors, the high resolution DLP9000 and DLP9000X digital micromirror devices (DMDs) are spatial light modulators (SLMs) that modulate the amplitude, direction, and/or phase of incoming light. This advanced light control technology has numerous applications in the industrial, medical, and consumer markets. The streaming nature of the DLP9000X and its DLPC910 controller enable very high speed continuous data streaming for lithographic applications. Both DMDs enable large build sizes and fine resolution for 3D printing applications. The high resolution provides the direct benefit of scanning larger objects for 3D machine vision applications. Device Information(1) PART NUMBER PACKAGE DLP9000 BODY SIZE (NOM) 42.20 mm x 42.20 mm x 7.00 mm CLGA (355) DLP9000X (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE Typical DLP9000X Application Illumination Driver LVDS Interface Row and Block Signals Status Signals JTAG(3:0) LVD Interface DLPC910 RESET Signals Red,Green,Blue PWM HSYNC, VSYNC 24-bit RGB Data USB I2C Illumination Sensor Control Signals Typical DLP9000 Application PCLK, DE FAN DLPC900 Flash OSC PGM(4:0) I2C SCP SCP DMD DATA CTRL_RSTZ I2C OSC 50 MHz LED0 LED1 DMD CTL, DATA DLP9000XFLS SCP Interface DLPR910 LED Driver LED Strobes DLP9000FLS VLED0 VLED1 24-bit RGB Data DLPC900 LED0 LED1 Flash Power Management Voltage Supplies 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Description (continued)......................................... 4 Pin Configuration and Functions ......................... 4 Specifications....................................................... 11 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Absolute Maximum Ratings .................................... 11 Storage Conditions.................................................. 12 ESD Ratings............................................................ 12 Recommended Operating Conditions..................... 12 Thermal Information ................................................ 14 Electrical Characteristics......................................... 14 Timing Requirements .............................................. 16 Capacitance at Recommended Operating Conditions ................................................................ 21 7.9 Typical Characteristics ............................................ 21 7.10 System Mounting Interface Loads ........................ 22 7.11 Micromirror Array Physical Characteristics .......... 22 7.12 Micromirror Array Optical Characteristics ............. 24 7.13 Optical and System Image Quality........................ 25 7.14 Window Characteristics......................................... 25 7.15 Chipset Component Usage Specification ............. 25 8 9 9.3 9.4 9.5 9.6 9.7 Feature Description................................................. Device Functional Modes........................................ Window Characteristics and Optics ....................... Micromirror Array Temperature Calculation............ Micromirror Landed-On/Landed-Off Duty Cycle ..... 29 32 32 33 34 10 Application and Implementation........................ 37 10.1 Application Information.......................................... 37 10.2 Typical Applications .............................................. 37 11 Power Supply Requirements ............................. 40 11.1 11.2 11.3 11.4 DMD DMD DMD DMD Power Supply Requirements ...................... 40 Power Supply Power-Up Procedure ........... 40 Mirror Park Sequence Requirements .......... 41 Power Supply Power-Down Procedure ...... 41 12 Layout................................................................... 44 12.1 Layout Guidelines ................................................. 44 12.2 Layout Example .................................................... 46 13 Device and Documentation Support ................. 50 13.1 13.2 13.3 13.4 13.5 13.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 50 51 51 52 52 52 Parameter Measurement Information ................ 26 Detailed Description ............................................ 27 14 Mechanical, Packaging, and Orderable Information ........................................................... 52 9.1 Overview ................................................................. 27 9.2 Functional Block Diagram ....................................... 28 14.1 Thermal Characteristics ........................................ 52 14.2 Package Thermal Resistance ............................... 52 14.3 Case Temperature ................................................ 52 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2015) to Revision B Page • Separated TCASE into TARRAY and TWINDOW. Changed TGRADIENT to TDELTA. Reduce DCLK_A,B,C,D for DLP9000 in Absolute Maximum Ratings. ............................................................................................................................. 11 • Separated Tstg into Tdmd and RH in Storage Conditions. .................................................................................................. 12 • Changed TDMD to TARRAY and TGRADIENT to TDELTA, added short term operational, and updated temperature values in Recommended Operating Conditions. .................................................................................................................. 13 • Added the four modes of operation. ..................................................................................................................................... 21 • Removed the column showing the pixel data rate and added the pattern mode pattern rates............................................ 21 • Updated CL2w constant in Micromirror Array Temperature Calculation. ............................................................................. 33 • Added recommended idle mode operation for maximizing mirror useful life. ...................................................................... 34 • Updated Micromirror Derating Curve.................................................................................................................................... 34 • Added mirror park sequence requirements. ......................................................................................................................... 41 • Updated device nomenclature and markings. ...................................................................................................................... 51 Changes from Original (September 2014) to Revision A Page • Updated title .......................................................................................................................................................................... 1 • Updated Features, Description, and Device Information to include DLP9000XFLS DMD..................................................... 1 • Added DLP9000XFLS application diagram. ........................................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 • Updated Absolute Maximum Ratings to include DLP9000XFLS absolute maximum ratings. ............................................. 11 • Updated Recommended Operating Conditions to include DLP9000XFLS recommended operating conditions................. 12 • Updated Electrical Characteristics to include DLP9000XFLS electrical characteristics....................................................... 14 • Updated Electrical Characteristics to include DLP9000XFLS electrical characteristics....................................................... 15 • Updated Timing Requirements to include DLP9000XFLS timing requirements................................................................... 16 • Updated Typical Characteristics tables to have pixel data rates and patttern rates for both the DLP9000FLS and the DLP9000XFLS...................................................................................................................................................................... 21 • Updated Device Functional Modes section to include DLP9000X functional description. ................................................... 32 • Updated Application and Implementations section to include typical application for the DLP9000XFLS. ........................... 37 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 3 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 5 Description (continued) Reliable function and operation of the DLP9000 family requires that each DMD be used in conjunction with its specific digital controller. The DLP9000X must be driven by a single DLPC910 Controller and the DLP9000 must be driven by two DLPC900 Controllers. These dedicated chipsets provide robust, high resolution, high speed system solutions. 6 Pin Configuration and Functions FLS Package Connector Terminals 355-Pin CLGA Bottom View 4 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Pin Functions PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) D_AN(0) H10 Input LVDS DDR Differential Data, Negative 737 D_AN(1) G3 Input LVDS DDR Differential Data, Negative 737 D_AN(2) G9 Input LVDS DDR Differential Data, Negative 737 D_AN(3) F4 Input LVDS DDR Differential Data, Negative 738 D_AN(4) F10 Input LVDS DDR Differential Data, Negative 739 D_AN(5) E3 Input LVDS DDR Differential Data, Negative 739 D_AN(6) E9 Input LVDS DDR Differential Data, Negative 737 D_AN(7) D2 Input LVDS DDR Differential Data, Negative 737 D_AN(8) J5 Input LVDS DDR Differential Data, Negative 739 D_AN(9) C9 Input LVDS DDR Differential Data, Negative 736 D_AN(10) F14 Input LVDS DDR Differential Data, Negative 743 D_AN(11) B8 Input LVDS DDR Differential Data, Negative 737 D_AN(12) G15 Input LVDS DDR Differential Data, Negative 739 D_AN(13) B14 Input LVDS DDR Differential Data, Negative 740 D_AN(14) H16 Input LVDS DDR Differential Data, Negative 737 D_AN(15) D16 Input LVDS DDR Differential Data, Negative 737 D_AP(0) H8 Input LVDS DDR Differential Data, Positive 737 D_AP(1) G5 Input LVDS DDR Differential Data, Positive 738 D_AP(2) G11 Input LVDS DDR Differential Data, Positive 737 D_AP(3) F2 Input LVDS DDR Differential Data, Positive 736 D_AP(4) F8 Input LVDS DDR Differential Data, Positive 739 D_AP(5) E5 Input LVDS DDR Differential Data, Positive 738 D_AP(6) E11 Input LVDS DDR Differential Data, Positive 737 D_AP(7) D4 Input LVDS DDR Differential Data, Positive 737 D_AP(8) J3 Input LVDS DDR Differential Data, Positive 739 D_AP(9) C11 Input LVDS DDR Differential Data, Positive 737 D_AP(10) F16 Input LVDS DDR Differential Data, Positive 741 D_AP(11) B10 Input LVDS DDR Differential Data, Positive 737 D_AP(12) H14 Input LVDS DDR Differential Data, Positive 739 D_AP(13) B16 Input LVDS DDR Differential Data, Positive 739 D_AP(14) G17 Input LVDS DDR Differential Data, Positive 737 D_AP(15) D14 Input LVDS DDR Differential Data, Positive 737 D_BN(0) AD8 Input LVDS DDR Differential Data, Negative 739 D_BN(1) AE3 Input LVDS DDR Differential Data, Negative 737 D_BN(2) AF8 Input LVDS DDR Differential Data, Negative 736 D_BN(3) AF2 Input LVDS DDR Differential Data, Negative 739 D_BN(4) AG5 Input LVDS DDR Differential Data, Negative 737 D_BN(5) AH8 Input LVDS DDR Differential Data, Negative 737 D_BN(6) AG9 Input LVDS DDR Differential Data, Negative 737 D_BN(7) AH2 Input LVDS DDR Differential Data, Negative 739 NAME DESCRIPTION TRACE (mils) (4) DATA BUS A DATA BUS B (1) (2) (3) (4) The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. DDR = Double Data Rate. SDR = Single Data Rate. Refer to the Timing Requirements regarding specifications and relationships. Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions regarding differential termination specification. Dielectric Constant for the DMD Type A ceramic package is approximately 9.6. For the package trace lengths shown: Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns. Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 5 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Pin Functions (continued) PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) D_BN(8) AL9 Input LVDS DDR Differential Data, Negative 737 D_BN(9) AJ11 Input LVDS DDR Differential Data, Negative 738 D_BN(10) AF14 Input LVDS DDR Differential Data, Negative 736 D_BN(11) AE11 Input LVDS DDR Differential Data, Negative 737 D_BN(12) AH16 Input LVDS DDR Differential Data, Negative 740 D_BN(13) AD14 Input LVDS DDR Differential Data, Negative 737 D_BN(14) AG17 Input LVDS DDR Differential Data, Negative 738 D_BN(15) AD16 Input LVDS DDR Differential Data, Negative 738 D_BP(0) AD10 Input LVDS DDR Differential Data, Positive 738 D_BP(1) AE5 Input LVDS DDR Differential Data, Positive 737 D_BP(2) AF10 Input LVDS DDR Differential Data, Positive 737 D_BP(3) AF4 Input LVDS DDR Differential Data, Positive 738 D_BP(4) AG3 Input LVDS DDR Differential Data, Positive 737 D_BP(5) AH10 Input LVDS DDR Differential Data, Positive 737 D_BP(6) AG11 Input LVDS DDR Differential Data, Positive 737 D_BP(7) AH4 Input LVDS DDR Differential Data, Positive 740 D_BP(8) AL11 Input LVDS DDR Differential Data, Positive 736 D_BP(9) AJ9 Input LVDS DDR Differential Data, Positive 739 D_BP(10) AF16 Input LVDS DDR Differential Data, Positive 737 D_BP(11) AE9 Input LVDS DDR Differential Data, Positive 737 D_BP(12) AH14 Input LVDS DDR Differential Data, Positive 737 D_BP(13) AE15 Input LVDS DDR Differential Data, Positive 737 D_BP(14) AG15 Input LVDS DDR Differential Data, Positive 740 D_BP(15) AE17 Input LVDS DDR Differential Data, Positive 739 D_CN(0) C15 Input LVDS DDR Differential Data, Negative 737 D_CN(1) E15 Input LVDS DDR Differential Data, Negative 737 D_CN(2) A17 Input LVDS DDR Differential Data, Negative 736 D_CN(3) F20 Input LVDS DDR Differential Data, Negative 737 D_CN(4) B20 Input LVDS DDR Differential Data, Negative 738 D_CN(5) G21 Input LVDS DDR Differential Data, Negative 737 D_CN(6) D22 Input LVDS DDR Differential Data, Negative 737 D_CN(7) E23 Input LVDS DDR Differential Data, Negative 737 D_CN(8) B26 Input LVDS DDR Differential Data, Negative 739 D_CN(9) F28 Input LVDS DDR Differential Data, Negative 737 D_CN(10) C27 Input LVDS DDR Differential Data, Negative 737 D_CN(11) J29 Input LVDS DDR Differential Data, Negative 737 D_CN(12) D26 Input LVDS DDR Differential Data, Negative 737 D_CN(13) H26 Input LVDS DDR Differential Data, Negative 739 D_CN(14) E29 Input LVDS DDR Differential Data, Negative 736 D_CN(15) G29 Input LVDS DDR Differential Data, Negative 737 D_CP(0) C17 Input LVDS DDR Differential Data, Positive 738 D_CP(1) E17 Input LVDS DDR Differential Data, Positive 737 D_CP(2) A15 Input LVDS DDR Differential Data, Positive 735 D_CP(3) F22 Input LVDS DDR Differential Data, Positive 737 D_CP(4) B22 Input LVDS DDR Differential Data, Positive 737 D_CP(5) H20 Input LVDS DDR Differential Data, Positive 737 D_CP(6) D20 Input LVDS DDR Differential Data, Positive 737 D_CP(7) E21 Input LVDS DDR Differential Data, Positive 737 D_CP(8) B28 Input LVDS DDR Differential Data, Positive 739 NAME DESCRIPTION TRACE (mils) (4) DATA BUS C 6 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Pin Functions (continued) PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) D_CP(9) F26 Input LVDS DDR Differential Data, Positive 735 D_CP(10) C29 Input LVDS DDR Differential Data, Positive 737 D_CP(11) J27 Input LVDS DDR Differential Data, Positive 737 D_CP(12) D28 Input LVDS DDR Differential Data, Positive 736 D_CP(13) H28 Input LVDS DDR Differential Data, Positive 739 D_CP(14) E27 Input LVDS DDR Differential Data, Positive 736 D_CP(15) G27 Input LVDS DDR Differential Data, Positive 737 D_DN(0) AJ15 Input LVDS DDR Differential Data, Negative 737 D_DN(1) AC27 Input LVDS DDR Differential Data, Negative 737 D_DN(2) AK16 Input LVDS DDR Differential Data, Negative 738 D_DN(3) AE29 Input LVDS DDR Differential Data, Negative 738 D_DN(4) AE21 Input LVDS DDR Differential Data, Negative 737 D_DN(5) AF20 Input LVDS DDR Differential Data, Negative 738 D_DN(6) AL15 Input LVDS DDR Differential Data, Negative 737 D_DN(7) AG29 Input LVDS DDR Differential Data, Negative 738 D_DN(8) AD22 Input LVDS DDR Differential Data, Negative 739 D_DN(9) AG21 Input LVDS DDR Differential Data, Negative 738 D_DN(10) AJ23 Input LVDS DDR Differential Data, Negative 736 D_DN(11) AJ29 Input LVDS DDR Differential Data, Negative 737 D_DN(12) AF28 Input LVDS DDR Differential Data, Negative 737 D_DN(13) AK22 Input LVDS DDR Differential Data, Negative 741 D_DN(14) AD28 Input LVDS DDR Differential Data, Negative 739 D_DN(15) AK28 Input LVDS DDR Differential Data, Negative 739 D_DP(0) AJ17 Input LVDS DDR Differential Data, Positive 737 D_DP(1) AC29 Input LVDS DDR Differential Data, Positive 737 D_DP(2) AK14 Input LVDS DDR Differential Data, Positive 738 D_DP(3) AE27 Input LVDS DDR Differential Data, Positive 737 D_DP(4) AD20 Input LVDS DDR Differential Data, Positive 737 D_DP(5) AF22 Input LVDS DDR Differential Data, Positive 738 D_DP(6) AL17 Input LVDS DDR Differential Data, Positive 737 D_DP(7) AG27 Input LVDS DDR Differential Data, Positive 738 D_DP(8) AE23 Input LVDS DDR Differential Data, Positive 739 D_DP(9) AG23 Input LVDS DDR Differential Data, Positive 738 D_DP(10) AJ21 Input LVDS DDR Differential Data, Positive 736 D_DP(11) AJ27 Input LVDS DDR Differential Data, Positive 737 D_DP(12) AF26 Input LVDS DDR Differential Data, Positive 737 D_DP(13) AK20 Input LVDS DDR Differential Data, Positive 740 D_DP(14) AD26 Input LVDS DDR Differential Data, Positive 739 D_DP(15) AK26 Input LVDS DDR Differential Data, Positive 739 SCTRL_AN D8 Input LVDS DDR Differential Serial Control, Negative 736 SCTRL_BN AK8 Input LVDS DDR Differential Serial Control, Negative 739 SCTRL_CN G23 Input LVDS DDR Differential Serial Control, Negative 737 SCTRL_DN AH28 Input LVDS DDR Differential Serial Control, Negative 739 SCTRL_AP D10 Input LVDS DDR Differential Serial Control, Positive 736 SCTRL_BP AK10 Input LVDS DDR Differential Serial Control, Positive 739 SCTRL_CP H22 Input LVDS DDR Differential Serial Control, Positive 739 SCTRL_DP AH26 Input LVDS DDR Differential Serial Control, Positive 739 NAME DESCRIPTION TRACE (mils) (4) DATA BUS D SERIAL CONTROL Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 7 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Pin Functions (continued) PIN (1) NO. TYPE (I/O/P) SIGNAL DCLK_AN H2 Input LVDS Differential Clock, Negative 740 DCLK_BN AJ5 Input LVDS Differential Clock, Negative 740 DCLK_CN C23 Input LVDS Differential Clock, Negative 736 DCLK_DN AH22 Input LVDS Differential Clock, Negative 736 DCLK_AP H4 Input LVDS Differential Clock, Positive 740 DCLK_BP AJ3 Input LVDS Differential Clock, Positive 740 DCLK_CP C21 Input LVDS Differential Clock, Positive 736 DCLK_DP AH20 Input LVDS Differential Clock, Positive 738 NAME DATA RATE (2) INTERNAL TERM (3) DESCRIPTION TRACE (mils) (4) CLOCKS SERIAL COMMUNICATIONS PORT (SCP) SCP_DO AC3 Output LVCMOS SDR SCP_DI AD2 Input LVCMOS SDR SCP_CLK AE1 Input SCP_ENZ AD4 Serial Communications Port Output Pull-Down Serial Communications Port Data Input LVCMOS Pull-Down Serial Communications Port Clock Input LVCMOS Pull-Down Active-low Serial Communications Port Enable MICROMIRROR RESET CONTROL RESET_ADDR(0) H12 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(1) C5 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(2) B6 Input LVCMOS Pull-Down Reset Driver Address Select RESET_ADDR(3) A19 Input LVCMOS Pull-Down Reset Driver Address Select RESET_MODE(0) J1 Input LVCMOS Pull-Down Reset Driver Mode Select RESET_MODE(1) G1 Input LVCMOS Pull-Down Reset Driver Mode Select RESET_SEL(0) AK4 Input LVCMOS Pull-Down Reset Driver Level Select RESET_SEL(1) AL13 Input LVCMOS Pull-Down Reset Driver Level Select H6 Input LVCMOS Pull-Down Reset Address, Mode, & Level latched on rising-edge RESET_STROBE ENABLES AND INTERRUPTS PWRDNZ B4 Input LVCMOS RESET_OEZ AK24 Input LVCMOS Pull-Down Active-low output enable for DMD reset driver circuits RESETZ AL19 Input LVCMOS Pull-Down Active-low sets Reset circuits in known VOFFSET state C3 Output LVCMOS RESET_IRQZ Active-low Device Reset Active-low, output interrupt to ASIC VOLTAGE REGULATOR MONITORING PG_BIAS J19 Input LVCMOS Pull-Up Active-low fault from external VBIAS regulator PG_OFFSET A13 Input LVCMOS Pull-Up Active-low fault from external VOFFSET regulator AC19 Input LVCMOS Pull-Up Active-low fault from external VRESET regulator EN_BIAS J15 Output LVCMOS Active-high enable for external VBIAS regulator EN_OFFSET H30 Output LVCMOS Active-high enable for external VOFFSET regulator EN_RESET J17 Output LVCMOS Active-high enable for external VRESET regulator PG_RESET LEAVE PIN UNCONNECTED MBRST(0) L5 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(1) M28 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(2) P4 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(3) P30 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(4) L3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(5) P28 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(6) P2 Output Analog Pull-Down For proper DMD operation, do not connect 8 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Pin Functions (continued) PIN (1) NAME NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) MBRST(7) T28 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(8) M4 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(9) L29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(10) T4 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(11) N29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(12) N3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(13) L27 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(14) R3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(15) V28 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(16) V4 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(17) R29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(18) Y4 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(19) AA27 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(20) W3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(21) W27 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(22) AA3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(23) W29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(24) U5 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(25) U29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(26) Y2 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(27) AA29 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(28) U3 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(29) Y30 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(30) AA5 Output Analog Pull-Down For proper DMD operation, do not connect MBRST(31) R27 Output Analog Pull-Down For proper DMD operation, do not connect DESCRIPTION TRACE (mils) (4) LEAVE PIN UNCONNECTED RESERVED_PFE J11 Input LVCMOS Pull-Down For proper DMD operation, do not connect RESERVED_TM AC7 Input LVCMOS Pull-Down For proper DMD operation, do not connect RESERVED_XI0 AC25 Input LVCMOS Pull-Down For proper DMD operation, do not connect RESERVED_XI1 AC23 Input LVCMOS Pull-Down For proper DMD operation, do not connect RESERVED_XI2 J23 Input LVCMOS Pull-Down For proper DMD operation, do not connect RESERVED_TP0 AC9 Input Analog For proper DMD operation, do not connect RESERVED_TP1 AC11 Input Analog For proper DMD operation, do not connect RESERVED_TP2 AC13 Input Analog For proper DMD operation, do not connect LEAVE PIN UNCONNECTED RESERVED_BA AC15 Output LVCMOS For proper DMD operation, do not connect RESERVED_BB J13 Output LVCMOS For proper DMD operation, do not connect RESERVED_BC AC21 Output LVCMOS For proper DMD operation, do not connect RESERVED_BD J21 Output LVCMOS For proper DMD operation, do not connect RESERVED_TS AC17 Output LVCMOS For proper DMD operation, do not connect LEAVE PIN UNCONNECTED NO CONNECT J7 For proper DMD operation, do not connect NO CONNECT J9 For proper DMD operation, do not connect NO CONNECT J25 For proper DMD operation, do not connect Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 9 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Pin Functions PIN NO. TYPE (I/O/P) SIGNAL A3, A9, A5, A11, A7, B2 Power Analog Supply voltage for positive Bias level of Micromirror reset signal. L1, N1, R1 Power Analog Supply voltage for HVCMOS logic. U1, W1 Power Analog Supply voltage for stepped high voltage at Micromirror address electrodes. AC1, AA1 Power Analog Supply voltage for Offset level of MBRST(31:0). L31, N31, R31, U31, W31, AA31 Power Analog Supply voltage for negative Reset level of Micromirror reset signal. VCC A21, A23, A25, A27, A29, C1, C31, E31, G31, J31, K2, AC31, AE31, AG1, AG31, AJ31, AK2, AK30, AL3, AL5, AL7, AL21, AL23, AL25, AL27 Power Analog Supply voltage for LVCMOS core logic. Supply voltage for normal high level at Micromirror address electrodes. VCCI H18, H24, M6, M26, P6, P26, T6, T26, V6, V26, Y6, Y26, AD6, AD12, AD18, AD24 Power Analog Supply voltage for LVDS receivers. VSS A1, B12, B18, B24, B30, C7, C13, C19, C25, D6, D12, D18, D24, D30, E1, E7, E13, E19, E25, F6, F12, F18, F24, F30, G7, G13, G19, G25, K4, K6, K26, K28, K30, M2, M30, N5, N27, R5, T2, T30, U27, V2, V30, W5, Y28, AB2, AB4, AB6, AB26, AB28, AB30, AC5, AD30, AE7, AE13, AE19, AE25, AF6, AF12, AF18, AF24, AF30, AG7, AG13, AG19, AG25, AH6, AH12, AH18, AH24, AH30, AJ1, AJ7, AJ13, AJ19, AJ25, AK6, AK12, AK18, AL29 Power Analog Device Ground. Common return for all power. NAME (1) VBIAS VOFFSET VRESET (1) 10 DESCRIPTION The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT –0.5 4 V –0.5 4 V –0.5 9 V SUPPLY VOLTAGES VCC Supply voltage for LVCMOS core logic (2) (2) VCCI Supply voltage for LVDS receivers VOFFSET Supply voltage for HVCMOS and micromirror electrode (2) (3) VBIAS Supply voltage for micromirror electrode (2) VRESET Supply voltage for micromirror electrode (2) | VCC – VCCI | Supply voltage delta (absolute value) (4) 0.3 V Supply voltage delta (absolute value) (5) 8.75 V –0.5 VCC + 0.3 V –0.5 VCCI + 0.3 V 700 mV 7 mA | VBIAS – VOFFSET | –0.5 17 V –11 0.5 V INPUT VOLTAGES Input voltage for all other LVCMOS input pins Input voltage for all other LVDS input pins | VID | Input differential voltage (absolute value) IID Input differential current (2) (2) (6) (7) (7) CLOCKS DLP9000 ƒclock DLP9000X Clock frequency for LVDS interface, DCLK_A 440 Clock frequency for LVDS interface, DCLK_B 440 Clock frequency for LVDS interface, DCLK_C 440 Clock frequency for LVDS interface, DCLK_D 440 Clock frequency for LVDS interface, DCLK_A 500 Clock frequency for LVDS interface, DCLK_B 500 Clock frequency for LVDS interface, DCLK_C 500 Clock frequency for LVDS interface, DCLK_D 500 MHz ENVIRONMENTAL TARRAY TWINDOW Array temperature: operational (8) (9) 0 90 (9) -40 90 0 70 Window temperature: non–operational -40 90 Array temperature: non–operational Window temperature: operational |TDELTA| Absolute termperature delta between the window test points and the ceramic test point TP1 (10) RH Relative Humidity, operating and non–operating 10 ºC ºC ºC 95% (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above Recommended Operating Conditions for extended periods may affect device reliability. (2) All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected. (3) VOFFSET supply transients must fall within specified voltages. (4) To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. (5) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information. (6) This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential. (7) LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. (8) Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential temperature, or illumination power density may affect device reliability. (9) The highest temperature of the active array as calculated by the Micromirror Array Temperature Calculation using ceramic test point 1 (TP1) in Figure 15. (10) Temperature delta is the highest difference between the ceramic test point TP1 and window test points TP2 and TP3 in Figure 15. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 11 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 7.2 Storage Conditions applicable before the DMD is installed in the final product MIN TDMD DMD storage temperature RH Relative Humidity, (non-condensing) -40 MAX UNIT 80 °C 95% 7.3 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) VALUE UNIT ±2000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN SUPPLY VOLTAGES VCC VCCI VOFFSET VBIAS VRESET NOM MAX UNIT (1) (2) DLP9000 Supply voltage for LVCMOS core logic 3.0 3.3 3.6 DLP9000X Supply voltage for LVCMOS core logic 3.3 3.45 3.6 DLP9000 Supply voltage for LVDS receivers 3.0 3.3 3.6 DLP9000X Supply voltage for LVDS receivers 3.3 3.45 3.6 8.25 8.5 8.75 V 15.5 16 16.5 V –9.5 –10 –10.5 V (3) Supply voltage for HVCMOS and micromirror electrodes Supply voltage for micromirror electrodes V V |VCCI–VCC| Supply voltage delta (absolute value) (4) 0.3 V |VBIAS–VO FFSET| (5) 8.75 V VCC + 0.3 V Supply voltage delta (absolute value) LVCMOS PINS (6) VIH High level Input voltage VIL Low level Input voltage 1.7 IOH High level output current at VOH = 2.4 V IOL Low level output current at VOL = 0.4 V TPWRDNZ PWRDNZ pulse width (6) – 0.3 (7) 2.5 0.7 V –20 mA 15 mA 10 ns SCP INTERFACE (8) ƒclock SCP clock frequency tSCP_SKEW Time between valid SCPDI and rising edge of SCPCLK tSCP_DELAY Time between valid SCPDO and rising edge of SCPCLK tSCP_BYTE_INT Time between consecutive bytes (9) –800 (9) 500 kHz 800 ns 700 ns 1 µs 30 ns ERVAL tSCP_NEG_ENZ Time between falling edge of SCPENZ and the first rising edge of SCPCLK tSCP_PW_ENZ SCPENZ inactive pulse width (high level) 1 tSCP_OUT_EN Time required for SCP output buffer to recover after SCPENZ (from tri-state) ƒclock SCP circuit clock oscillator frequency (10) 9.6 µs 1.5 ns 11.1 MHz (1) (2) (3) (4) (5) Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected. All voltages are referenced to common ground VSS. VOFFSET supply transients must fall within specified max voltages. To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply Requirements for additional information. (6) Tester Conditions for VIH and VIL: Frequency = 60 MHz. Maximum Rise Time = 2.5 ns at (20% to 80%) Frequency = 60 MHz. Maximum Fall Time = 2.5 ns at (80% to 20%) (7) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the SCPDO output pin. (8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK. (9) Refer to Figure 1. (10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required. 12 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT LVDS INTERFACE ƒclock DLP9000 Clock frequency DCLK DLP9000X Clock frequency DCLK 400 (11) 400 (12) |VID| Input differential voltage (absolute value) VCM Common mode VLVDS LVDS voltage tLVDS_RSTZ Time required for LVDS receivers to recover from PWRDNZ ZIN Internal differential termination resistance 95 ZLINE Line differential impedance (PWB/trace) 90 ENVIRONMENTAL (13) DLP9000X (12) 0 DLP9000X mV 10 ns 105 Ω 110 Ω Array temperature, Short–term operational 0 Array temperature, Long–term operational (14) (15) (16) 10 Array temperature, Short–term operational (14) (15) (18) 0 10 10 70 10 40 Window Temperature test points TP2 and TP3, Long-term operational (16) ILLVIS Illumination RH Relative Humidity (non-condensing) TARRAY 100 mV (14) (15) (18) Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1 (20) (13) mV 2000 (14) (15) (16) |TDELTA| ENVIRONMENTAL 600 Array temperature, Long–term operational Window Temperature test points TP2 and TP3, Long-term operational (16) DLP9000 TWINDOW 400 1200 For Illumination Source Between 420 nm and 700 nm DLP9000 TARRAY 100 (12) MHz 480 10 40 to 65 (17) 40 (19) 10 °C °C 10 Thermally Limited (21) °C mW/cm2 95% For Illumination Source Between 400 nm and 420 nm Array temperature, Long–term operational (14) (15) (16) 20 30 Array temperature, Short–term operational (14) (15) (18) 0 20 °C TWINDOW Window Temperature test points TP2 and TP3, Long-term operational (16) 30 °C |TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1 (20) 10 °C ILLVIS Illumination 10 W/cm2 RH Relative Humidity (non-condensing) ENVIRONMENTAL (13) DLP9000 TARRAY 95% For Illumination Source <400 nm and >700 nm DLP9000X Array temperature, Long–term operational (14) (15) (16) Array temperature, Short–term operational (14) (15) (18) 0 Array temperature, Long–term operational (14) (15) (16) 10 Array temperature, Short–term operational (14) (15) (18) 0 10 40 to 65 (17) 40 (19) 10 °C 10 (11) The DLP9000X, coupled with the DLPC910, is designed for operation at 2 specific DCLK frequencies only - 400 MHz or 480 MHz. 480 MHz operation is only allowed at the specific environmental operating conditions as shown in this table. (12) Refer to Figure 2, Figure 3, and Figure 4. (13) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. (14) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 15 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation. (15) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime. (16) Long-term is defined as the usable life of the device. (17) Per Figure 16, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle. (18) Array and Window temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours. (19) For the DLP9000X, Figure 16 does not apply and the maximum temperature is as specified in table. (20) Temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in Figure 15. (21) Refer to Thermal Information and Micromirror Array Temperature Calculation. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 13 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Recommended Operating Conditions (continued) over operating free-air temperature range (unless otherwise noted) MIN Window Temperature test points TP2 and TP3, Long-term operational (16) DLP9000 TWINDOW DLP9000X Window Temperature test points TP2 and TP3, Long-term operational (16) NOM MAX 10 70 10 40 UNIT °C |TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1 (20) ILLUV Illumination, wavelength < 400 nm 0.68 mW/cm2 ILLIR Illumination, wavelength > 700 nm 10 mW/cm2 RH Relative Humidity (non-condensing) 10 °C 95% 7.5 Thermal Information DLP9000 THERMAL METRIC (1) FLS (CLGA) UNIT 355 PINS RθJA (1) Thermal resistance, active area to test point 1 (TP1) (max) 0.5 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. 7.6 Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH High-level output voltage VCC = 3 V, IOH = –20 mA VOL Low level output voltage VCC = 3.6, IOL = 15 mA (2) (3) IIH High–level input current IlL Low level input current VCC = 3.6 V, VI = 0 IOZ High–impedance output current VCC = 3.6 V (1) MIN TYP MAX 2.4 VCC = 3.6 V, VI = VCC UNIT V 0.4 V 250 µA –250 µA 10 µA CURRENT ICC Supply current (4) ICCI IOFFSET Supply current IBIAS (5) IRESET DLP9000 VCC = 3.6 V, DCLK=400 MHz 1600 DLP9000X VCC = 3.6V, DCLK=480 MHz 1850 DLP9000 VCCI = 3.6 V, DCLK=400 MHz 985 DLP9000X VCCI = 3.6, DCLK=480 MHz 1100 VOFFSET = 8.75 V 25 VBIAS = 16.5 V 14 VRESET = –10.5 V ITOTAL Supply current mA mA 11 DLP9000 Total Sum 2634 DLP9000X Total Sum 3000 mA POWER (1) (2) (3) (4) (5) 14 All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected. Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins. LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and Functions to determine pull-up or pull-down configuration used. To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Electrical Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS PCC PCCI Supply power dissipation (1) MIN TYP MAX DLP9000 VCC = 3.6 V 5760 DLP9000X VCC = 3.6 V 6660 DLP9000 VCCI = 3.6 V 3546 DLP9000X VCCI = 3.6 V 3960 UNIT mW mW POFFSET VOFFSET = 8.75 V 219 mW PBIAS VBIAS = 16.5 V 231 mW PRESET VRESET = –10.5 V 115 mW PTOTAL Supply power dissipation (6) DLP9000 Total Sum, DCLK = 400 MHz 9871 DLP9000X Total Sum, DCLK = 480 MHz 11185 mW CAPACITANCE CI CO (6) Input capacitance ƒ = 1 MHz 10 pF Output capacitance ƒ = 1 MHz 10 pF Reset group capacitance MBRST(31:0) ƒ = 1 MHz; 2560 × 50 micromirrors 290 pF 230 Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination source. See the Micromirror Array Temperature Calculation. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 15 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 7.7 Timing Requirements over Recommended Operating Conditions (unless otherwise noted) (1) MIN SCP INTERFACE NOM MAX UNIT (2) tr Rise time 20% to 80% 200 ns tƒ Fall time 80% to 20% 200 ns LVDS INTERFACE (2) tr Rise time 20% to 80% 100 400 ps tƒ Fall time 80% to 20% 100 400 ps LVDS CLOCKS (3) DLP9000 tc Cycle time DLP9000X DLP9000 tw Pulse duration DLP9000X LVDS INTERFACE tsu tsu DCLK_D, 50% to 50% 2.5 DCLK_A, 50% to 50% 2.083 DCLK_B, 50% to 50% 2.083 DCLK_C, 50% to 50% 2.083 DCLK_D, 50% to 50% 2.083 DCLK_A, 50% to 50% 1.19 1.25 DCLK_B, 50% to 50% 1.19 1.25 DCLK_C, 50% to 50% 1.19 1.25 DCLK_D, 50% to 50% 1.19 1.25 DCLK_A, 50% to 50% 1.031 1.042 DCLK_B, 50% to 50% 1.031 1.042 DCLK_C, 50% to 50% 1.031 1.042 DCLK_D, 50% to 50% 1.031 1.042 Setup time Setup time 0.2 0.2 D_C(15:0) before rising or falling edge of DCLK_C 0.2 D_D(15:0) before rising or falling edge of DCLK_D 0.2 SCTRL_A before rising or falling edge of DCLK_A 0.2 SCTRL_B before rising or falling edge of DCLK_B 0.2 SCTRL_C before rising or falling edge of DCLK_C 0.2 SCTRL_D before rising or falling edge of DCLK_D 0.2 Hold time Hold time DLP9000X 16 2.5 D_B(15:0) before rising or falling edge of DCLK_B DLP9000 (1) (2) (3) 2.5 DCLK_C, 50% to 50% D_A(15:0) before rising or falling edge of DCLK_A DLP9000X th 2.5 DCLK_B, 50% to 50% ns ns (3) DLP9000 th DCLK_A, 50% to 50% D_A(15:0) after rising or falling edge of DCLK_A 0.5 D_B(15:0) after rising or falling edge of DCLK_B 0.5 D_C(15:0) after rising or falling edge of DCLK_C 0.5 D_D(15:0) after rising or falling edge of DCLK_D 0.5 D_A(15:0) after rising or falling edge of DCLK_A 0.4 D_B(15:0) after rising or falling edge of DCLK_B 0.4 D_C(15:0) after rising or falling edge of DCLK_C 0.4 D_D(15:0) after rising or falling edge of DCLK_D 0.4 SCTRL_A after rising or falling edge of DCLK_A 0.5 SCTRL_B after rising or falling edge of DCLK_B 0.5 SCTRL_C after rising or falling edge of DCLK_C 0.5 SCTRL_D after rising or falling edge of DCLK_D 0.5 SCTRL_A after rising or falling edge of DCLK_A 0.4 SCTRL_B after rising or falling edge of DCLK_B 0.4 SCTRL_C after rising or falling edge of DCLK_C 0.4 SCTRL_D after rising or falling edge of DCLK_D 0.4 ns ns ns ns Refer to Pin Configuration and Functions for pin details. Refer to Figure 5. Refer to Figure 6. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Timing Requirements (continued) over Recommended Operating Conditions (unless otherwise noted) (1) MIN LVDS INTERFACE DLP9000 Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0) Channel B relative to Channel A tskew NOM MAX UNIT –1.25 1.25 ns -1.04 1.04 ns –1.25 1.25 ns -1.04 1.04 ns (3) DLP9000 Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0) DLP9000X Channel A includes the following LVDS pairs: DCLK_AP and DCLK_AN SCTRL_AP and SCTRL_AN D_AP(15:0) and D_AN(15:0) DLP9000X Channel B includes the following LVDS pairs: DCLK_BP and DCLK_BN SCTRL_BP and SCTRL_BN D_BP(15:0) and D_BN(15:0) Skew time DLP9000 Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0) Channel D relative to Channel C DLP9000 Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0) DLP9000X Channel C includes the following LVDS pairs: DCLK_CP and DCLK_CN SCTRL_CP and SCTRL_CN D_CP(15:0) and D_CN(15:0) DLP9000X Channel D includes the following LVDS pairs: DCLK_DP and DCLK_DN SCTRL_DP and SCTRL_DN D_DP(15:0) and D_DN(15:0) tc SCPCLK fclock = 1 / tc 50% 50% tSCP_SKEW SCPDI 50% tSCP_DELAY SCPD0 50% Not to scale. Refer to SCP Interface section of the Recommended Operating Conditions table. Figure 1. SCP Timing Parameters Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 17 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com (VIP + VIN) / 2 DCLK_P , SCTRL_P , D_P(0:?) LVDS Receiver VID VIP DCLK_N , SCTRL_N , D_N(0:?) VCM VIN Refer to LVDS Interface section of the Recommended Operating Conditions table. Refer to Pin Configuration and Functions for list of LVDS pins. Figure 2. LVDS Voltage Definitions (References) VLVDS max = VCM max + | 1/2 * VID max | VCM VID VLVDS min = VCM min ± | 1/2 * VID max | Not to scale. Refer to LVDS Interface section of the Recommended Operating Conditions table. Figure 3. LVDS Voltage Parameters DCLK_P , SCTRL_P , D_P(0:?) ESD Internal Termination LVDS Receiver DCLK_N , SCTRL_N , D_N(0:?) ESD Refer to LVDS Interface section of the Recommended Operating Conditions table. Refer to Pin Configuration and Functions for list of LVDS pins. Figure 4. LVDS Equivalent Input Circuit 18 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 LVDS Interface SCP Interface 1.0 * VCC 1.0 * VID VCM 0.0 * VCC 0.0 * VID tr tf tr tf Not to scale. Refer to the Timing Requirements table Refer to Pin Configuration and Functions for a list of LVDS pins and SCP pins.. Figure 5. Rise Time and Fall Time Not to scale. Refer to LVDS INTERFACE section in the Timing Requirements table. Figure 6. Timing Requirement Parameter Definitions Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 19 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Not to scale. Refer to LVDS INTERFACE section in the Timing Requirements table. Figure 7. LVDS Interface Channel Skew Definition 20 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 7.8 Capacitance at Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT CI Input capacitance ƒ = 1 MHz 10 pF CO Output capacitance ƒ = 1 MHz 10 pF CIM MBRST(31:0) input capacitance f = 1 MHz. All inputs interconnected. 290 pF 230 7.9 Typical Characteristics When the DLP9000 DMD is controlled by two DLPC900 controllers, these digital controllers offer four modes of operation. 1. Video Mode 2. Video Pattern Mode 3. Pre-Stored Pattern Mode 4. Pattern On-The-Fly Mode In video mode, the video source is displayed on the DMD at the rate of the incoming video source. In modes 2, 3, and 4, the pattern rates depend on the bit depth as shown in Table 1. When the DLP9000X DMD is controlled by the DLPC910 controller, the digital controller offers streaming 1-bit binary patterns to the DMD at speeds greater than 61 Gigabits per second (Gbps). The patterns are streamed from a customer designed applications processor into the DLPC910 input LVDS data interface. Table 2 shows the pattern rates for the different DMD Reset Modes. Table 1. DLPC900 with DLP9000 Pattern Rate versus Bit Depth BIT DEPTH VIDEO PATTERN MODE (Hz) PRE-STORED or PATTERN ONTHE-FLY MODE (Hz) 1 2880 9523 2 1440 3289 3 960 2638 4 720 1364 5 480 823 6 480 672 7 360 500 8 247 247 Table 2. DLPC910 with DLP9000X Pattern Rates versus Reset Mode RESET MODE (1) MAX PATTERN RATE (Hz) Global 53.42 13043 (4) Single 56.46 13783 (5) Dual 59.89 14624 (5) 14989 (5) Quad (1) (2) (3) (4) (5) MAX PIXEL DATA RATE (Gbps) (2) 61.39 (3) Refer to the DLPC910 data sheet in Related Documentation for a description of the reset modes. Pixel data rates are based on continuous streaming. Increasing exposure periods may be necessary for a desired application but may decrease pattern rate. Global reset mode allows for continuous or pulsed illumination source. This reset mode typically requires pulsed illumination such as a laser or LED. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 21 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 7.10 System Mounting Interface Loads PARAMETER MIN NOM Thermal interface area (See Figure 8) Maximum system mounting interface load to be applied to the: Electrical interface area Datum A interface area (1) MAX UNIT 35 lbs 300 lbs 160 lbs Thermal Interface Area Electrical Interface Area Other Area Datum ‘A’ Areas Figure 8. System Mounting Interface Loads 7.11 Micromirror Array Physical Characteristics M Number of active columns N Number of active rows P Micromirror (pixel) pitch (1) (1) 22 See Figure 9 Micromirror active array width M×P Micromirror active array height N×P Micromirror active border Pond of micromirror (POM) Micromirror total area P2 x M x N (converted to cm) (1) VALUE UNIT 2560 micromirrors 1600 micromirrors 7.56 µm 19.3536 mm 12.096 mm 14 micromirrors/ side 2.341 cm2 Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum A area (300 + 35 – Datum A). The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 0 1 2 3 M±4 M±3 M±2 M±1 www.ti.com 0 1 2 3 DMD Active Array NxP M x N Micromirrors N±4 N±3 N±2 N±1 MxP P Border micromirrors omitted for clarity. Details omitted for clarity. P Not to scale. P P Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications. Figure 9. Micromirror Array Physical Characteristics Figure 10. DMD Micromirror Active Area Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 23 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 7.12 Micromirror Array Optical Characteristics Refer to Optical Interface and System Image Quality for important information. PARAMETER α Micromirror tilt angle β Micromirror tilt angle tolerance TEST CONDITIONS DMD landed state Micromirror tilt direction MAX –1 (5) (6) Micromirror crossover time NOM 12 (1) (2) (3) (4) (5) See Figure 11 Number of out-of-specification micromirrors MIN (1) 44 45 Adjacent micromirrors (7) (8) (9) Typical performance ° 46 ° 10 2.5 DMD efficiency within the wavelength range 400 nm to 420 nm ° 1 0 Non-adjacent micromirrors (10) 68% DMD photopic efficiency within the wavelength range 420 nm to 700 nm (10) 66% UNIT micromirrors μs (1) (2) (3) (4) Measured relative to the plane formed by the overall micromirror array. Additional variation exists between the micromirror array and the package datums. Represents the landed tilt angle variation relative to the nominal landed tilt angle. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. (5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations, or system contrast variations. (6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State direction. A binary value of 0 results in a micromirror landing in the OFF State direction. (7) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the specified Micromirror Switching Time. (8) Micromirror crossover time is primarily a function of the natural response time of the micromirrors. (9) Performance as measured at the start of life. (10) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency. M±4 M±3 M±2 M±1 illumination 0 1 2 3 Not To Scale 0 1 2 3 On-State Tilt Direction 45° Off-State Tilt Direction N±4 N±3 N±2 N±1 Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications. Figure 11. Micromirror Landed Orientation and Tilt 24 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 7.13 Optical and System Image Quality Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in a) through c) below: a. Numerical Aperture and Stray Light Control. The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur. b. Pupil Match. TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within two degrees of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. c. Illumination Overfill. Overfill light illuminating the area outside the active array can create artifacts from the mechanical features that surround the active array and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere outside the active array more than 20 pixels from the edge of the active array on all sides. Depending on the particular system’s optical architecture and assembly tolerances, this amount of overfill light on the outside of the active array may still cause artifacts to still be visible. NOTE TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED ABOVE. 7.14 Window Characteristics PARAMETER (1) TEST CONDITIONS Window material designation Corning 7056 Window refractive index at wavelength 589 nm Window aperture See Illumination overfill Refer to Illumination Overfill Window transmittance, single–pass through both surfaces and glass (3) (1) (2) (3) MIN TYP MAX UNIT 1.487 (2) At wavelength 405 nm. Applies to 0° and 24° AOI only. 95% Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI. 97% Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI. 97% Refer to Window Characteristics and Optics for more information. For details regarding the size and location of the window aperture, refer to the package mechanical characteristics listed in the Mechanical ICD in the Mechanical, Packaging, and Orderable Information section. Refer to the TI application report DLPA031, Wavelength Transmittance Considerations for DMD Window. 7.15 Chipset Component Usage Specification The DMD is a component of one or more DLP® chipsets. Reliable function and operation of the DMD requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DMD. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 25 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 8 Parameter Measurement Information The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 12 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation section. Device Pin Output Under Test Tester Channel CLOAD Figure 12. Test Load Circuit 26 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 9 Detailed Description 9.1 Overview The DMD is a 0.9 inch diagonal spatial light modulator which consists of an array of highly reflective aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 9. The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR). The DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram. The positive or negative deflection angle of the micromirrors can be individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST). Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror Array Optical Characteristics. The micromirrors are electrically tied to the micromirror reset signals (MBRST) and the micromirror array is divided into reset groups. Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative (–) tilt angle state corresponds to an 'off' pixel. Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration and Functions for more information on micromirror reset control. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 27 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 9.2 Functional Block Diagram Channel A Interface DCLK_C SCTRL_C DATA_C Channel C Interface Column Read & Write Control Bit Lines Control EN_REG VBIAS VRESET VOFFSET VCCI VCC VSS MBRST DATA_A SCTRL_A DCLK_A Not to Scale. Details Omitted for Clarity. See Accompanying Notes in this Section. (0,0) Word Lines Word Lines Row Voltage Generators Row Micromirror Array Voltages Voltages Voltage Generators Bit Lines (M-1, N-1) Column Read & Write Control Channel D Interface DCLK_D SCTRL_D DATA_D VBIAS VRESET VOFFSET VCCI VCC VSS MBRST DATA_B SCTRL_B DCLK_B Channel B Interface RESET_CTRL SCP Control For pin details on Channels A, B, C, and D, refer to Pin Configuration and Functions and LVDS Interface section of Timing Requirements. 28 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 9.3 Feature Description The DMD consists of 4096000 highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors) organized in a two-dimensional orthogonal pixel array. Refer to Figure 9 and Figure 13. Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to Micromirror Array Optical Characteristics and Figure 14. The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package, as shown in Figure 13. Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the CMOS memory cell data update. Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror switching to a – α position. Updating the angular position of the micromirror array consists of two steps. First, update the contents of the CMOS memory. Second, apply a micromirror reset (also referred as Mirror Clocking Pulse) to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror reset pulses are generated internally by the DMD, with application of the pulses being coordinated by the DLPC900 or the DLPC910 digital controller. For more information, refer to the TI application report DLPA008, DMD101: Introduction to Digital Micromirror Device (DMD) Technology. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 29 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Feature Description (continued) Incident Illumination Package Pin A1 Corner Details Omitted For Clarity. Not To Scale. DMD Micromirror Array 0 (Border micromirrors eliminated for clarity) M±1 Active Micromirror Array 0 N±1 Micromirror Hinge-Axis Orientation Micromirror Pitch P (um) 45° P (um) P (um) ³2Q-6WDWH´ Tilt Direction ³2II-6WDWH´ Tilt Direction P (um) Refer to Micromirror Array Physical Characteristics , Figure 9, and Figure 11. Figure 13. Micromirror Array, Pitch, Hinge Axis Orientation 30 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Feature Description (continued) g n t -L i de n ci tio In ina m u Ill Details Omitted For Clarity. ht Not To Scale. Pa th Package Pin A1 Corner DMD Incident Illumination Two ³2Q-6WDWH´ Micromirrors nt t Path ide Inc n-Ligh atio min Illu nt t Path ide Inc n-Ligh tio ina m Illu Projected-Light Path Two ³2II-6WDWH´ Micromirrors For Reference gh Li eat th t S a ff- P O a±b t Flat-State ( ³SDUNHG´ ) Micromirror Position -a ± b Silicon Substrate ³2Q-6WDWH´ Micromirror Silicon Substrate ³2II-6WDWH´ Micromirror Micromirror States: On, Off, Flat Figure 14. Micromirror States: On, Off, Flat Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 31 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 9.4 Device Functional Modes 9.4.1 DLP9000 The DLP9000 DMD is controlled by two DLPC900 digital controllers. The digital controller operates in two different modes. The first is video mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are downloaded over USB or pre-stored in flash memory, and then streamed to the DMD. The resulting DMD pattern rate depends on which mode and bit-depth is selected. For more information, refer to the DLPC900 data sheet listed under Related Documentation. 9.4.2 DLP9000X The DLP9000X DMD is controlled by one DLPC910 digital controller. The digital controller offers high speed streaming mode where 1-bit binary patterns are accepted at the LVDS interface input, and then streamed to the DMD. To ensure reliable operation, the DLP9000X must always be used with the DLPC910. For more information, refer to the DLPC910 data sheet listed under Related Documentation. 9.5 Window Characteristics and Optics NOTE TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 9.5.1 Optical Interface and System Image Quality TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections. 9.5.2 Numerical Aperture and Stray Light Control The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur. 9.5.3 Pupil Match TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 9.5.4 Illumination Overfill The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable. 32 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 9.6 Micromirror Array Temperature Calculation Figure 15. DMD Thermal Test Points Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations: TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) QARRAY = QELECTRICAL + QILLUMINATION QILLUMINATION = (CL2W × SL) (1) (2) (3) Where: TARRAY = Computed micromirror array temperature (°C) TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 15 RARRAY–TO–CERAMIC = DMD package thermal resistance from micromirror array to outside ceramic (°C/W) specified in Thermal Information QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W) QELECTRICAL = DMD electrical power dissipation (W), specified in Electrical Characteristics CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below SL = Measured ANSI screen lumens (lm) Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. Absorbed optical power from the illumination source is variable and depends on the operating state of the micromirrors and the intensity of the light source. Equations shown above produce a total projection efficiency through the projection lens from DMD to the screen of 87%. The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00274 W/lm. Sample Calculation for typical projection application: TCERAMIC = 55°C, assumed system measurement; refer to Recommended Operating Conditions regarding specific limits. SL = 2000 lm QELECTRICAL = 9.87W for the DLP9000 (refer to the power specifications in Electrical Characteristics) CL2W = 0.00274 W/lm Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 33 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Micromirror Array Temperature Calculation (continued) QARRAY = 9.87 W + (0.00274 W/lm × 2000 lm) = 15.35 W TARRAY = 55°C + (15.35 W × 0.5 ºC/W) = 62.68°C 9.7 Micromirror Landed-On/Landed-Off Duty Cycle 9.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state. As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time. Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored. Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages) always add to 100. 9.7.2 Landed Duty Cycle and Useful Life of the DMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life. Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical. Individual DMD mirror duty cycles vary by application as well as the mirror location on the DMD within any specific application. DMD mirror useful life are maximized when every individual mirror within a DMD approaches 50/50 (or 1/1) duty cycle. Therefore, for the DLPC900 and DLP9000 chipset, it is recommended that DMD Idle Mode be enabled as often as possible. Examples are whenever the system is idle, the illumination is disabled, between sequential pattern exposures (if possible), or when the exposure pattern sequence is stopped for any reason. This software mode provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states. Refer to the DLPC900 Programmer’s Guide DLPU018 for a description of the DMD Idle Mode command. For the DLPC910 and DLP9000X chipset, it is recommended the controlling applications processor provide a 50/50 pattern sequence to the DLPC910 for display on the DLP9000X as often as possible, similar to the above examples stated for the DLPC900. The pattern provides a 50/50 duty cycle across the entire DMD mirror array, where the mirrors are continuously flipped between the on and off states. 9.7.3 Landed Duty Cycle and Operational DMD Temperature Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life. This is quantified in the de-rating curve shown in Figure 16. The importance of this curve is that: • All points along this curve represent the same usable life. • All points above this curve represent lower usable life (and the further away from the curve, the lower the usable life). • All points below this curve represent higher usable life (and the further away from the curve, the higher the usable life). In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle. 34 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Max Recommended DMD Temperature ± Operational ( 0C) Micromirror Landed-On/Landed-Off Duty Cycle (continued) 80 70 60 50 40 30 0/100 100/0 5/95 95/5 10/90 15/85 90/10 85/15 20/80 25/75 80/20 75/25 30/70 35/65 40/60 45/55 50/50 70/30 65/35 6040 55/45 Micromirror Landed Duty Cycle Figure 16. Max Recommended DMD Temperature – Derating Curve 9.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel. For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle. Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 3. Table 3. Grayscale Value and Landed Duty Cycle GRAYSCALE VALUE LANDED DUTY CYCLE 0% 0/100 10% 10/90 20% 20/80 30% 30/70 40% 40/60 50% 50/50 60% 60/40 70% 70/30 80% 80/20 90% 90/10 100% 100/0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 35 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point. During a given period of time, the landed duty cycle of a given pixel can be calculated as follows: Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% × Blue_Scale_Value) Where: Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red, Green, and Blue are displayed (respectively) to achieve the desired white point. For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green, blue color intensities would be as shown in Table 4. Table 4. Example Landed Duty Cycle for Full-Color 36 RED CYCLE PERCENTAGE 50% GREEN CYCLE PERCENTAGE 20% BLUE CYCLE PERCENTAGE 30% RED SCALE VALUE GREEN SCALE VALUE BLUE SCALE VALUE 0% 0% 0% 0/100 100% 0% 0% 50/50 0% 100% 0% 20/80 0% 0% 100% 30/70 12% 0% 0% 6/94 0% 35% 0% 7/93 0% 0% 60% 18/82 100% 100% 0% 70/30 LANDED DUTY CYCLE 0% 100% 100% 50/50 100% 0% 100% 80/20 12% 35% 0% 13/87 0% 35% 60% 25/75 12% 0% 60% 24/76 100% 100% 100% 100/0 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information The DLP9000 DMD is controlled by two DLPC900 controllers. This chipset offers two modes of operation. The first is video mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are pre-stored in flash memory and then streamed to the DMD. The allowed DMD pattern rate depends on which mode and bit-depth is selected. The DLP9000X DMD is controlled by the DLPC910 controller, where the DLPC910 is configured by the program content in the DLPR910. This chipset offers streaming 1-bit binary patterns to the DMD at speeds greater than 61 Gigabits per second (Gbps). The patterns are streamed from an customer designed processor into the DLPC910 LVDS input data interface. Both the DLP9000 and the DLP9000X provide solutions for many varied applications including structured light, 3-D printing, video projection, and high speed lithography. The DMD is a spatial light modulator, which reflects incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data being used. 10.2 Typical Applications 10.2.1 Typical Application using DLP9000 A typical embedded system application using two DLPC900 controllers and a DLP9000 DMD is shown in Figure 17. In this configuration, the DLPC900 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or processor. The 24-bit parallel data must be split between a left half and a right half, each half between the two controllers. The external processor must format each half to consist of 1280x1600 plus any horizontal and vertical blanking at half the pixel clock rate. This system configuration supports still and motion video as well as sequential pattern modes. For more information, refer to the DLPC900 digital controller data sheet listed under Related Documentation. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 37 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Typical Applications (continued) I2C I2C_SCL0, I2C_SDA0 LED EN[2:0] LED PWM[2:0] P1_A,P2_A[9:0] P1_B,P2_B[9:0] P1_C,P2_C[9:0] DLPC900 Master Processor P1A_CLK, P1_DATEN P1_VSYNC, P1_HSYNC TRIG_OUT[1:0] TRIG_IN[1:0] Camera Crystal MOSC P1_A,P2_A[9:0] P1_B,P2_B[9:0] P1_C,P2_C[9:0] FPGA HDMI Digital Receiver DP HDMI DISPLAYPORT P1A_CLK, P1_DATEN P1_VSYNC, P1_HSYNC LED Status DMD_A,B[15:0] DMD Control DMD SSP DLP9000FLS Power VCC Management PWRGOOD POSENSE SYNC SSP TDO[1:0],TRST,TCK RMS[1:0],RTCK FAN POWER RAILS MOSC JTAG PWM LEDs I2C_SCL1 I2C_SDA1 I2C 12V DC IN POWER RAILS DLPC900 Slave HEARTBEAT FAULT_STATUS PWRGOOD POSENSE DMD_A,B[15:0] Flex USB_DN,DP LED Status LED Driver USB GUI RAM HEARTBEAT FAULT_STATUS PM_ADDR[22:0],WE DATA[15:0],OE,CS Flex Parallel Flash Host PM_ADDR[22:0],WE DATA[15:0],OE,CS Parallel Flash Figure 17. DLP9000 Typical Application Schematic 10.2.1.1 Design Requirements Detailed design requirements are located in the DLPC900 or the DLPC910 digital controller data sheets. Refer to the data sheets listed under Related Documentation. 10.2.1.2 Detailed Design Procedure Reference Design material exists for systems using either the DLP9000 or the DLP9000X DMD with their respective Controllers. This reference material includes reference board schematics, PCB layouts, and Bills of Materials. Layout guidelines for boards utilizing these controllers and DMDs can be found in the respective DLPC900 or DLPC910 Controller data sheets. For more information, please refer to the individual controller data sheets listed under Related Documentation. 10.2.2 Typical Application Using DLP9000X Direct-write digital imaging is regularly used in high-end lithography printing. This mask-less technology offers a continuous run of printing by changing the digitally created patterns without stopping the imaging head. Figure 18 shows a system where a DLPC910 digital controller is coupled with the DLP9000X DMD. This system offers an ideal back-end imager that takes in digital images at 2560 x 1600 in resolution to achieve speeds of more than 61 Gbps. For more information, refer to the DLPC910 digital controller data sheet listed under Related Documentation. 38 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Typical Applications (continued) Illumination Driver Illumination Sensor LVDS Interface DCLKIN(A,B,C,D),DVALID(A,B,C,D),DIN(A,B,C,D)[15:]) Row and Block Signals USER Interface ROWMD(1:0),ROWAD(10:0),BLKMD(1:0),BLKAD(3:0),RST2BLKZ Control Signals DOUT(A,B,C,D)[15:0] COMP_DATA,NS_FLIP,WDT_ENBLZ,PWR_FLOAT Connectivity USB Ethernet DCLKOUT (A,B,C,D) APPS SCTRL(A,B,C,D) Status Signals FPGA RESET_ADDR(3:0) RST_ACTIVE,INIT_ACTIVE,ECP2_FINISHED DLPC910 RESET_MODE(1:0) RESET_SEL(1:0) JTAG(3:0) DLP9000XFLS RESET_STRB RESET_OEZ Volatile And Non-volatile Storage DLPR910 PGM(4:0) RESET_IRQZ SCP BUS(3:0) CTRL_RSTZ RESETZ I2C VLED0 OSC 50 MHz VLED1 Power Management Figure 18. DLP9000X Typical Application Schematic Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 39 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 11 Power Supply Requirements 11.1 DMD Power Supply Requirements The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC900 or DLPC910 Controllers within their associated reference designs. CAUTION For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and powerdown operations. VSS must also be connected. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 19. 11.2 DMD Power Supply Power-Up Procedure • • • • • 40 During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start after VOFFSET. During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates requirements during power-up are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 19. During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at operating voltages listed in Recommended Operating Conditions. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 11.3 DMD Mirror Park Sequence Requirements 11.3.1 DLP9000 For correct power down operation of the DLP9000 DMD, the following power down procedure must be executed. Prior to an anticipated power removal, the controlling applications processor must command the DLPC900 to enter Standby mode by using the Power Mode command and then wait for a minimum of 20 ms to allow the DLPC900 to complete the power down procedure. This procedure will assure the mirrors are in a flat state. Following this procedure, the power can be safely removed. In the event of an unanticipated power loss, the power management system must detect the input power loss, command the DLPC900 to enter Standby mode by using the Power Mode command, and then maintain all operating power levels of the DLPC900 and the DLP9000 DMD for a minimum of 20 ms to allow the DLPC900 to complete the power down procedure. Following this procedure, the power can be allowed to fall below safe operating levels. Refer to the DLPC900 datasheet for more details on power down requirements. In both anticipated power down and unanticipated power loss, the DLPC900 is commanded over the USB/I2C interface, and then the DLPC900 loads the correct power down sequence to the DMD. Communicating over the USB/I2C and loading the power down sequence accounts for most of the 20 ms. Compared to the DLPC910, the controlling processor only needs to assert the PWR_FLOAT pin and wait for a minimum of 500 µs. The controlling applications processor can resume normal operations by commanding the DLPC900 to enter Normal mode. See Power Mode command in the DLPC900 Programmer’s Guide DLPU018 for a description of this command. 11.3.2 DLP9000X For correct power down operation of the DLP9000X DMD, the following power down procedure must be executed. Prior to an anticipated power removal, assert PWR_FLOAT to the DLPC910 for a minimum of 500 μs to allow the DLPC910 to complete the power down procedure. This procedure will assure the DMD mirrors are in a flat state. Following this procedure, the power can be safely removed. In the event of an unanticipated power loss, the power management system must detect the input power loss, assert PWR_FLOAT to the DLPC910, and maintain all operating power levels of the DLPC910 and the DLP9000X DMD for a minimum of 500 μs to allow the DLPC910 to complete the power down procedure. Refer to the DLPC910 datasheet for more details on power down requirements. To restart after assertion of PWR_FLOAT without removing power, the DLPC910 must be reset by setting CTRL_RSTZ low (logic 0) for 50 ms, and then back to high (logic 1), or power to the DLPC910 must be cycled. 11.4 DMD Power Supply Power-Down Procedure • • • • • During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the specified limit of ground. Refer to Table 5. During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET. During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed in Absolute Maximum Ratings, in Recommended Operating Conditions, and in Figure 19. During power-down, LVCMOS input pins must be less than specified in Recommended Operating Conditions. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 41 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com DMD Power Supply Power-Down Procedure (continued) EN_BIAS, EN_OFFSET, and EN_RESET are disabled by DLP controller software or PWRDNZ signal control Note 3 VBIAS, VOFFSET, and VRESET are disabled by DLP controller software Mirror Park Sequence RESET_OEZ VSS ¸¸ Power Off VCC / VCCI Note 6 VSS VCC / VCCI PWRDNZ ¸¸ VSS VCC VCCI VCC / VCCI VSS EN_BIAS EN_OFFSET EN_RESET VSS VCC / VCCI VBIAS VSS ¸¸ VSS ¸¸ ¸¸ Note 3 VSS VBIAS VBIAS VBIAS < Specification Note 1 Note 1 VSS ¨9 < Specification ¨9 < Specification VOFFSET ¸¸ Note 4 VSS VOFFSET VOFFSET VOFFSET < Specification Note 4 VSS VSS Note 5 VSS Refer to specifications listed in Recommended Operating Conditions. Waveforms are not to scale. Details are omitted for clarity. VRESET < Specification Note 4 VSS VRESET VRESET > Specification VRESET ¸¸ VRESET VCC LVCMOS Inputs ¸¸ VSS VSS Note 2 LVDS Inputs Note 2 ¸¸ VSS VSS Figure 19. DMD Power Supply Sequencing Requirements 42 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 DMD Power Supply Power-Down Procedure (continued) 1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. 2. During power-up, the LVDS signals are less than the input differential voltage (VID) maximum specified in Recommended Operating Conditions. During power-down, LVDS signals are less than the high level input voltage (VIH) maximum specified in Recommended Operating Conditions. 3. When system power is interrupted, the DLPC900 and the DLPC910 controllers initiate a hardware powerdown that activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to disable VBIAS, VOFFSET, and VRESET, respectively. 4. Refer to Table 5. 5. Figure not to scale. Details have been omitted for clarity. Refer to Recommended Operating Conditions. 6. Refer to DMD Mirror Park Sequence Requirements for details on powering down the DMD. Table 5. DMD Power-Down Sequence Requirements PARAMETER MIN VBIAS VOFFSET Supply voltage level during power–down sequence VRESET –4.0 MAX V 4.0 V 0.5 V Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 UNIT 4.0 43 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 12 Layout 12.1 Layout Guidelines Each chipset provides a solution for many applications including structured light and video projection. This section provides layout guidelines for the DMD. 12.1.1 General PCB Recommendations The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches ±10%, using a dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent. Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity. Refer to the digital controller data sheets listed under Related Documentation regarding DMD Interface Considerations. High-speed interface waveform quality and timing on the digital controllers (that is, the LVDS DMD interface) is dependent on the following factors: • Total length of the interconnect system • Spacing between traces • Characteristic impedance • Etch losses • How well matched the lengths are across the interface Thus, ensuring positive timing margin requires attention to many factors. As an example, DMD interface system timing margin can be calculated as follows: • Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation) • Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation) The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise. Both the DLPC910 and the DLPC900 I/O timing parameters can be found in their respective data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy to determine. In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these recommendations should be confirmed with PCB signal integrity analysis or lab measurements. 12.1.2 Power Planes Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by 0.2". Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes should be connected together with a minimum distance between connections of 0.5". Extra vias are not required if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and signal vias should be inside the perimeter ring of ground vias. Power and Ground pins of each component shall be connected to the power and ground planes with one via for each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”). Unused or spare device pins that are connected to power or ground may be connected together with a single via to power or ground. Ground plane slots are NOT allowed. Route VOFFSET, VBIAS, and VRESET as a wide trace >20 mils (wider if space allows) with 20 mils spacing. 44 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Layout Guidelines (continued) 12.1.3 LVDS Signals The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation such that constant differential impedance (as in section Board Stack and Impedance Requirements) is maintained throughout the length. Avoid sharp turns and layer switching while keeping lengths to a minimum. The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair. 12.1.4 Critical Signals The critical signals on the board must be hand routed in the order specified below. In case of length matching requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB. Table 6. Timing Critical Signals GROUP SIGNAL 1 D_AP(0:15), D_AN(0:15), DCLK_AP, DCLK_AN, SCTRL_AN, SCTRL_AP, D_BP(0:15), D_BN(0:15), DCLK_BP, DCLK_BN, SCTRL_BN, SCTRL_BP, D_CP(0:15), D_CN(0:15), DCLK_CP, DCLK_CN, SCTRL_CN, SCTRL_CP, D_DP(0:15), D_DN(0:15), DCLK_DP, DCLK_DN, SCTRL_DN, SCTRL_DP. 2 RESET_ADDR_(0:3), RESET_MODE_(0:1), RESET_OEZ, RESET_SEL_(0:1) RESET_STROBE, RESET_IRQZ. 3 SCP_CLK, SCP_DO, SCP_DI, SCP_DMD_CSZ. 4 Others CONSTRAINTS ROUTING LAYERS Internal signal layers. Avoid layer switching when routing these signals. Refer to Table 7 and Table 8 Internal signal layers. Top and bottom as required. Any No matching/length requirement Any 12.1.5 Flex Connector Plating Plate all the pad area on top layer of flex connection with a minimum of 35 and maximum 50 micro-inches of electrolytic hard gold over a minimum of 150 micro-inches of electrolytic nickel. 12.1.6 Device Placement Unless otherwise specified, all major components should be placed on top layer. Small components such as ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are side by side as much as possible and place the smaller value capacitor closer to the device. 12.1.7 Device Orientation It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented with the “+” terminal the same direction and likewise for the vertically oriented ones. 12.1.8 Fiducials Fiducials for automatic component insertion should be placed on the board according to the following guidelines or on recommendation from manufacturer: • Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB. • Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing <0.05"). • Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad). Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 45 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 12.2 Layout Example 12.2.1 Board Stack and Impedance Requirements Refer to Figure 20 regarding guidance on the parameters. PCB design: Configuration: Asymmetric dual stripline Etch thickness (T): 1.0-oz copper (1.2 mil) Flex etch thickness (T): 0.5-oz copper (0.6 mil) Single-ended signal impedance: 50 Ω (±10%) Differential signal impedance: 100 Ω (±10%) PCB stack-up: Reference plane 1 is assumed to be a ground plane for proper return path. Reference plane 2 is assumed to be the I/O power plane or ground. 46 Dielectric material with a low Loss-Tangent, for example: Hitachi 679gs or equivalent. (Er): 3.8 (nominal) Signal trace distance to reference plane 1 (H1): 5.0 mil (nominal) Signal trace distance to reference plane 2 (H2): 34.2 mil (nominal) Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Layout Example (continued) Figure 20. PCB Stack Geometries Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 47 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com Layout Example (continued) Table 7. General PCB Routing (Applies to All Corresponding PCB Signals) PARAMETER Line width (W) APPLICATION SINGLE-ENDED SIGNALS DIFFERENTIAL PAIRS UNIT Escape routing in ball field 4 .4 (0.1) 4 .3 (0.1) mil (mm) PCB etch data or control 7 (0.18) 4.25 (0.11) mil (mm) PCB etch clocks 7 (0.18) 4.25 (0.11) mil (mm) PCB etch data or control N/A 5.75 (1) –0.15 mil (mm) PCB etch clocks N/A 5.75 (1) –0.15 mil (mm) PCB etch data or control N/A 20 (0.51) mil (mm) PCB etch clocks N/A 20 (0.51) mil (mm) Escape routing in ball field 4 (0.1) 4 (0.1) mil (mm) PCB etch data or control 10 (0.25) 20 (0.51) mil (mm) PCB etch clocks 20 (0.51) 20 (0.51) mil (mm) Total data N/A 10 –0.25 mil (mm) Total data N/A 10 –0.25 mil (mm) Differential signal pair spacing (S) Minimum differential pair-to-pair spacing (S) Minimum line spacing to other signals (S) Maximum differential pair P-to-N length mismatch (1) Spacing may vary to maintain differential impedance requirements Table 8. DMD Interface Specific Routing SIGNAL GROUP LENGTH MATCHING INTERFACE SIGNAL GROUP REFERENCE SIGNAL MAX MISMATCH UNIT DMD (LVDS) SCTRL_AN / SCTRL_AP D_AP(15:0)/ D_AN(15:0) DCKA_P/ DCKA_N ± 50 (± 1.3) mil (mm) DMD (LVDS) SCTRL_BN/ SCTRL_BP D_BP(15:0)/ D_BN(15:0) DCKB_P/ DCKB_N ± 50 (± 1.3) mil (mm) DMD (LVDS) SCTRL_CN/ SCTRL_CP D_CP(15:0)/ D_CN(15:0) DCK_CP/ DCK_CN ± 50 (± 1.3) mil (mm) DMD (LVDS) SCTRL_DN/ SCTRL_DP D_DP(15:0)/ D_DN(15:0) DCK_CP/ DCK_CN ± 50 (± 1.3) mil (mm) Number of layer changes: • Single-ended signals: Minimize • Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair should not change layers. Table 9. DMD Signal Routing Length BUS DMD (LVDS) (1) 48 (1) MIN MAX UNIT 50 375 mm Max signal routing length includes escape routing. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 Stubs: Stubs should be avoided. Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω internally. Connector (DMD-LVDS interface bus only): High-speed connectors that meet the following requirements should be used: • Differential crosstalk: <5% • Differential impedance: 75 to 125 Ω Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers shall have the predominant traces routed orthogonal to each other. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 49 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 13 Device and Documentation Support 13.1 Device Support 13.1.1 Device Handling All external signals on the DMD are protected from damage by electrostatic discharge, and are tested in accordance with JESD22-A114-B electrostatic discharge (ESD) sensitivity testing human body model (HBM). Table 10. DMD ESD Protection Limits PACKAGE TERMINAL TYPE VOLTAGE (MAXIMUM) UNIT Input 2000 V Output 2000 V VCC 2000 V VCCI 2000 V VOFFSET 2000 V VBIAS 2000 V VRESET 2000 V All MBRST 2000 V All CMOS devices require proper Electrostatic Discharge (ESD) handling procedures. Refer to drawing 2504641 DMD Handling Specification, for precautions to protect the DMD from ESD and to protect the DMD’s glass and electrical contacts. Refer to drawing 2504640 DMD Glass Cleaning Procedure, for correct and consistent methods for cleaning the glass of the DMD, in such a way that the anti-reflective coatings on the glass surface are not damaged. 13.1.2 Device Nomenclature Figure 21 provides a legend for reading the complete device name for any DLP device. Table 11. Package-Specific Information PACKAGE TYPE ALTERNATE NAME FLS LCCC DLP9000 _ _ FLS Package Type Revision Speed Grade Blank = Standard Speed X = High Speed Device Descriptor Figure 21. Device Nomenclature 50 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 DLP9000 www.ti.com DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 13.1.3 Device Markings The device marking will include both human-readable information and a 2-dimensional matrix code. The humanreadable information is described in Figure 22. The 2-dimensional matrix code is an alpha-numeric character string that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias voltage bin letter. TI Internal Numbering 2 Dimensional Matrix Code (DMD Part Number and Serial Number) DMD Part Number YYYYYYY DLP9000_ _ FLS GHXXXXX LLLLLLM LLLLLL Part 2 of Serial Number (7 characters) Part 1 of Serial Number (7 characters) TI Internal Numbering Figure 22. DMD Markings 13.2 Documentation Support 13.2.1 Related Documentation The following documents contain additional information related to the use of the DLP9000 family of devices: • DLPC900 Digital Controller Data Sheet (DLPS037) • DLPC900 Software Programmer's Guide (DLPU018) • DLPC910 Digital Controller Data Sheet (DLPS064) • DLPR910 Configuration PROM Data Sheet (DLPS065) 13.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 51 DLP9000 DLPS036B – SEPTEMBER 2014 – REVISED OCTOBER 2016 www.ti.com 13.4 Trademarks E2E is a trademark of Texas Instruments. DLP is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 13.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 13.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 14.1 Thermal Characteristics Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array and the temperature gradient between any two points on or within the package. Refer to Absolute Maximum Ratings and Recommended Operating Conditions regarding applicable temperature limits. 14.2 Package Thermal Resistance The DMD is designed to conduct the absorbed and dissipated heat back to the series FLS package where it can be removed by an appropriate thermal management system. The thermal management system must be capable of maintaining the package within the specified operational temperatures at the thermal test point locations (refer to Figure 15 or Micromirror Array Temperature Calculation). The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions can include light energy absorbed by the window aperture, electrical power dissipation of the array, and parasitic heating. For the thermal resistance, refer to Thermal Information. 14.3 Case Temperature The temperature of the DMD case can be measured directly. For consistency, a thermal test point location is defined as shown in Figure 15 and Micromirror Array Temperature Calculation. 52 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: DLP9000 PACKAGE OPTION ADDENDUM www.ti.com 2-Nov-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) DLP9000BFLS ACTIVE CLGA FLS 355 1 TBD Call TI Call TI DLP9000FLS ACTIVE CLGA FLS 355 1 Green (RoHS & no Sb/Br) W NIPDAU N / A for Pkg Type DLP9000XBFLS PREVIEW CLGA FLS 355 1 TBD Call TI Call TI DLP9000XFLS ACTIVE CLGA FLS 355 1 Green (RoHS & no Sb/Br) W NIPDAU N / A for Pkg Type Op Temp (°C) Device Marking (4/5) 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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