LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 LP3883 3A Fast-Response Ultra Low Dropout Linear Regulators Check for Samples: LP3883 FEATURES DESCRIPTION • • • • • • • • The LP3883 is a high-current, fast-response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. 1 2 Ultra Low Dropout Voltage (210 mV @ 3A typ) Low Ground Pin Current Load Regulation of 0.04%/A 60 nA Typical Quiescent Current in Shutdown 1.5% Output Accuracy (25°C) TO-220, DDPAK/TO-263 Packages Over Temperature/over Current Protection −40°C to +125°C Junction Temperature Range APPLICATIONS • • • • • • • DSP Power Supplies Server Core and I/O Supplies Linear Power Supplies for PC Add-in-Cards Set-Top Box Power Supplies Microprocessor Power Supplies High Efficiency Linear Power Supplies SMPS Post-Regulators The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in TO-220 and DDPAK/TO-263 packages. Dropout Voltage: 210 mV (typ) @ 3A load current. Ground Pin Current: 3 mA (typ) at full load. Shutdown Current: 60 nA (typ) when S/D pin is low. Precision Output Voltage: 1.5% room temperature accuracy. Typical Application Circuit At least 4.7 µF of input and output capacitance is required for stability. Connection Diagram Figure 1. TO-220, Top View See NDH0005D Package Figure 2. DDPAK/TO-263, Top View See KTT0005B Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2002–2013, Texas Instruments Incorporated LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com Block Diagram These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) −65°C to +150°C Storage Temperature Range Lead Temp. (Soldering, 5 seconds) ESD Rating 260°C Human Body Model (3) Machine Model (4) Power Dissipation (5) 2 kV 200V Internally Limited VIN Supply Voltage (Survival) −0.3V to +6V VBIAS Supply Voltage (Survival) −0.3V to +7V −0.3V to +7V Shutdown Input Voltage (Survival) IOUT (Survival) Internally Limited −0.3V to +6V Output Voltage (Survival) −40°C to +150°C Junction Temperature (1) (2) (3) (4) (5) Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications, see Electrical Characteristics. Specifications do not apply when operating the device outside of its rated operating conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin. The machine model is a 220 pF capacitor discharged directly into each pin. The machine model ESD rating of pin 5 is 100V. At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220 devices is 65°C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4°C/W can be assumed. θJ-A for DDPAK/TO-263 devices is approximately 40°C/W if soldered down to a copper plane which is at least 1.5 square inches in area. If power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. OPERATING RATINGS VIN Supply Voltage (VOUT + VDO) to 5.5V Shutdown Input Voltage 0 to +6V IOUT 3A −40°C to +125°C Operating Junction Temperature Range VBIAS Supply Voltage 2 4.5V to 6V Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = COUT = 4.7 µF, VS/D = VBIAS. Symbol VO Parameter Conditions Output Voltage Tolerance 10 mA < IL < 3A VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 6V Typical (1) MIN (2) MAX (2) 1.198 1.234 1.186 1.246 1.478 1.522 1.455 1.545 1.773 1.827 1.746 1.854 Units 1.216 1.5 V 1.8 (3) ΔVO/ΔVIN Output Voltage Line Regulation VO(NOM) + 1V ≤ VIN ≤ 5.5V 0.01 %/V ΔVO/ΔIL Output Voltage Load Regulation (4) 10 mA < IL < 3A 0.04 0.06 %/A VDO Dropout Voltage (5) IL = 3A 210 270 420 mV IQ(VIN) Quiescent Current Drawn from VIN Supply 10 mA < IL < 3A 3 7 8 mA 0.03 1 30 µA 1 2 3 mA VS/D ≤ 0.3V 0.03 1 30 µA VOUT = 0V 6 VS/D ≤ 0.3V IQ(VBIAS) ISC Quiescent Current Drawn from VBIAS Supply Short-Circuit Current 10 mA < IL < 3A A Shutdown Input VSDT Output Turn-off Threshold Output = ON 0.7 Output = OFF 0.7 Td (OFF) Turn-OFF Delay RLOAD X COUT << Td (OFF) 20 Td (ON) Turn-ON Delay RLOAD X COUT << Td (ON) 15 IS/D S/D Input Current VS/D =1.3V 1 VS/D ≤ 0.3V −1 VIN = VOUT +1V, f = 120 Hz 80 VIN = VOUT + 1V, f = 1 kHz 65 VBIAS = VOUT + 3V, f = 120 Hz 70 VBIAS = VOUT + 3V, f = 1 kHz 65 1.3 V 0.3 µs µA AC Parameters PSRR (VIN) Ripple Rejection for VIN Input Voltage PSRR (VBIAS) Ripple Rejection for VBIAS Voltage en (1) (2) (3) (4) (5) Output Noise Density f = 120 Hz Output Noise Voltage VOUT = 1.8V BW = 10 Hz − 100 kHz 150 BW = 300 Hz − 300 kHz 90 1 dB µV/root−H z µV (rms) Typical numbers represent the most likely parametric norm for 25°C operation. Limits are ensured through testing, statistical correlation, or design. Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load. Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 3 LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. 4 Dropout vs IL IGND vs VSD Figure 3. Figure 4. VOUT vs Temperature DC Load Regulation Figure 5. Figure 6. Line Regulation vs VIN Line Regulation vs VBIAS Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. IBIAS vs IL IBIAS vs VBIAS Figure 9. Figure 10. IGND vs VSD Noise Measurement Figure 11. Figure 12. VOUTStartup Waveform VOUTStartup Waveform Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 5 LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. 6 VOUTStartup Waveform Line Regulation vs VBIAS Figure 15. Figure 16. Line Regulation vs VBIAS VIN PSRR Figure 17. Figure 18. VIN PSRR VBIAS PSRR Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. Load Transient Response (Both Oscon 10µF/3A) Load Transient Response (Both Oscon 100µF/3A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 3A/DIV ILOAD 3A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 21. Figure 22. Load Transient Response (Both POSCAP 100µF/3A) Load Transient Response (SANYO 150µF/3A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 3A/DIV ILOAD 3A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 23. Figure 24. Load Transient Response (Tantalum 10µF/3A) Load Transient Response (Tantalum 100µF/3A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 3A/DIV ILOAD 3A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 25. Figure 26. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 7 LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: TA = 25°C, COUT = 4.7µF, Cin = 4.7µF, S/D pin is tied to VBIAS, VIN = 2.2V, VOUT = 1.8V. Load Transient Response (Both Oscon 10µF/1A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV Load Transient Response (Both Oscon 100µF/1A) ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 27. Figure 28. Load Transient Response (Both POSCAP 100µF/1A) Load Transient Response (SANYO 150µF/1A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 29. Figure 30. Load Transient Response (Tantalum 10µF/1A) Load Transient Response (Tantalum 100µF/1A) VOUT 100mV/DIV MAGNITUDE MAGNITUDE VOUT 100mV/DIV ILOAD 1A/DIV ILOAD 1A/DIV TIME (50Ps/DIV) TIME (50Ps/DIV) Figure 31. 8 Figure 32. Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 APPLICATION HINTS EXTERNAL CAPACITORS To assure regulator stability, input and output capacitors are required as shown in the Typical Application Circuit. OUTPUT CAPACITOR At least 4.7µF of output capacitance is required for stability (the amount of capacitance can be increased without limit). The output capacitor must be located less than 1 cm from the output pin of the IC and returned to a clean analog ground. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" range as shown in the graph below over the full operating temperature range for stable operation. 10 COUT ESR (:) 1.0 COUT = 4.7PF STABLE REGION 0.1 COUT = 100PF .01 .001 0 1 2 3 LOAD CURRENT (A) Figure 33. Minimum ESR vs Output Load Current Tantalum capacitors are recommended for the output as their ESR is ideally suited to the part's requirements and the ESR is very stable over temperature. Aluminum electrolytics are not recommended because their ESR increases very rapidly at temperatures below 10C. Aluminum caps can only be used in applications where lower temperature operation is not required. A second problem with Al caps is that many have ESR's which are only specified at low frequencies. The typical loop bandwidth of a linear regulator is a few hundred kHz to several MHz. If an Al cap is used for the output cap, it must be one whose ESR is specified at a frequency of 100 kHz or more. Because the ESR of ceramic capacitors is only a few milli Ohms, they are not suitable for use as output capacitors on LP388X devices. The regulator output can tolerate ceramic capacitance totaling up to 15% of the amount of Tantalum capacitance connected from the output to ground. OUTPUT "BYPASS" CAPACITORS Many designers place small value "bypass" capacitors at various circuit points to reduce noise. Ceramic capacitors in the value range of about 1000pF to 0.1µF placed directly on the output of a PNP or P-FET LDO regulator can cause a loss of phase margin which can result in oscillations, even when a Tantalum output capacitor is in parallel with it. This is not unique to Texas Instruments LDO regulators, it is true of any P-type LDO regulator. The reason for this is that PNP or P-FET regulators have a higher output impedance (compared to an NPN regulator), which results in a pole-zero pair being formed by every different capacitor connected to the output. The zero frequency is approximately: Fz = 1 / (2 X π X ESR X C) where • • ESR is the equivalent series resistance of the capacitor C is the value of capacitance (1) Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 9 LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 www.ti.com The pole frequency is: Fp = 1 / (2 X π X RL X C) where • RL is the load resistance connected to the regulator output (2) To understand why a small capacitor can reduce phase margin: assume a typical LDO with a bandwidth of 1MHz, which is delivering 0.5A of current from a 2.5V output (which means RL is 5 Ohms). We then place a .047 µF capacitor on the output. This creates a pole whose frequency is: Fp = 1 / (2 X π X 5 X .047 X 10E-6) = 677 kHz (3) This pole would add close to 60 degrees of phase lag at the crossover (unity gain) frequency of 1 MHz, which would almost certainly make this regulator oscillate. Depending on the load current, output voltage, and bandwidth, there are usually values of small capacitors which can seriously reduce phase margin. If the capacitors are ceramic, they tend to oscillate more easily because they have very little internal inductance to damp it out. If bypass capacitors are used, it is best to place them near the load and use trace inductance to "decouple" them from the regulator output. INPUT CAPACITOR The input capacitor must be at least 4.7 µF, but can be increased without limit. It's purpose is to provide a low source impedance for the regulator input. Ceramic capacitors work best for this, but Tantalums are also very good. There is no ESR limitation on the input capacitor (the lower, the better). Aluminum electrolytics can be used, but their ESR increase very quickly at cold temperatures. They are not recommended for any application where temperatures go below about 10°C. BIAS CAPACITOR The 0.1µF capacitor on the bias line can be any good quality capacitor (ceramic is recommended). BIAS VOLTAGE The bias voltage is an external voltage rail required to get gate drive for the N-FET pass transistor. Bias voltage must be in the range of 4.5 - 6V to assure proper operation of the part. UNDER VOLTAGE LOCKOUT The bias voltage is monitored by a circuit which prevents the regulator output from turning on if the bias voltage is below approximately 4V. SHUTDOWN OPERATION Pulling down the shutdown (S/D) pin will turn-off the regulator. Pin S/D must be actively terminated through a pull-up resistor (10 kΩ to 100 kΩ) for a proper operation. If this pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator), the pull-up resistor is not required. This pin must be tied to Vin if not used. POWER DISSIPATION/HEATSINKING A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = (VIN−VOUT)IOUT+ (VIN)IGND where • IGND is the operating ground current of the device (4) The maximum allowable temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax− TAmax (5) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: 10 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 θJA = TRmax / PD (6) These parts are available in TO-220 and DDPAK/TO-263 packages. The thermal resistance depends on amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 60 °C/W for TO-220 package and ≥ 60 °C/W for DDPAK/TO-263 package no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required. HEATSINKING TO-220 PACKAGE The thermal resistance of a TO220 package can be reduced by attaching it to a heat sink or a copper plane on a PC board. If a copper plane is to be used, the values of θJA will be same as shown in next section for TO263 package. The heatsink to be used in the application should have a heatsink to ambient thermal resistance, θHA≤ θJA − θCH − θJC. (7) In this equation, θCH is the thermal resistance from the case to the surface of the heat sink and θJC is the thermal resistance from the junction to the surface of the case. θJC is about 3°C/W for a TO220 package. The value for θCH depends on method of attachment, insulator, etc. θCH varies between 1.5°C/W to 2.5°C/W. If the exact value is unknown, 2°C/W can be assumed. HEATSINKING DDPAK/TO-263 PACKAGE The DDPAK/TO-263 package uses the copper plane on the PCB as a heatsink. The tab of these packages are soldered to the copper plane for heat sinking. The graph below shows a curve for the θJA of DDPAK/TO-263 package for different copper area sizes, using a typical PCB with 1 ounce copper and no solder mask over the copper area for heat sinking. Figure 34. θJA vs Copper (1 Ounce) Area for DDPAK/TO-263 package As shown in the graph below, increasing the copper area beyond 1 square inch produces very little improvement. The minimum value for θJA for the DDPAK/TO-263 package mounted to a PCB is 32°C/W. Figure 35 shows the maximum allowable power dissipation for DDPAK/TO-263 packages for different ambient temperatures, assuming θJA is 35°C/W and the maximum junction temperature is 125°C. Figure 35. Maximum power dissipation vs ambient temperature for DDPAK/TO-263 package Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 11 LP3883 SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 12 www.ti.com Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 LP3883 www.ti.com SNVS223F – NOVEMBER 2002 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2002–2013, Texas Instruments Incorporated Product Folder Links: LP3883 13 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LP3883ES-1.2 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3883ES -1.2 LP3883ES-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES -1.2 LP3883ES-1.5 NRND DDPAK/ TO-263 KTT 5 45 TBD Call TI Call TI -40 to 125 LP3883ES -1.5 LP3883ES-1.5/NOPB ACTIVE DDPAK/ TO-263 KTT 5 45 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES -1.5 LP3883ESX-1.2 NRND DDPAK/ TO-263 KTT 5 500 TBD Call TI Call TI -40 to 125 LP3883ES -1.2 LP3883ESX-1.2/NOPB ACTIVE DDPAK/ TO-263 KTT 5 500 Pb-Free (RoHS Exempt) CU SN Level-3-245C-168 HR -40 to 125 LP3883ES -1.2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LP3883ESX-1.2 DDPAK/ TO-263 KTT 5 500 330.0 24.4 LP3883ESX-1.2/NOPB DDPAK/ TO-263 KTT 5 500 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.75 14.85 5.0 16.0 24.0 Q2 10.75 14.85 5.0 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP3883ESX-1.2 DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 LP3883ESX-1.2/NOPB DDPAK/TO-263 KTT 5 500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA KTT0005B TS5B (Rev D) BOTTOM SIDE OF PACKAGE www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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