LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 LM5110 Dual 5A Compound Gate Driver with Negative Output Voltage Capability Check for Samples: LM5110 FEATURES PACKAGE • • • 1 2 • • • • • • • • • • • • Independently Drives Two N-Channel MOSFETs Compound CMOS and Bipolar Outputs Reduce Output Current Variation 5A sink/3A Source Current Capability Two Channels can be Connected in Parallel to Double the Drive Current Independent Inputs (TTL Compatible) Fast Propagation Times (25 ns Typical) Fast Rise and Fall Times (14 ns/12 ns Rise/Fall with 2 nF Load) Dedicated Input Ground Pin (IN_REF) for Split Supply or Single Supply Operation Outputs Swing from VCC to VEE which can be Negative Relative to Input Ground Available in Dual Non-inverting, Dual Inverting and Combination Configurations Shutdown Input Provides Low Power Mode Supply Rail Under-voltage Lockout Protection Pin-out Compatible with Industry Standard Gate Drivers TYPICAL APPLICATIONS • • • • Synchronous Rectifier Gate Drivers Switch-mode Power Supply Gate Driver Solenoid and Motor Drivers Power Level Shifter SOIC-8 WSON-10 (4 mm x 4 mm) DESCRIPTION The LM5110 Dual Gate Driver replaces industry standard gate drivers with improved peak output current and efficiency. Each “compound” output driver stage includes MOS and bipolar transistors operating in parallel that together sink more than 5A peak from capacitive loads. Combining the unique characteristics of MOS and bipolar devices reduces drive current variation with voltage and temperature. Separate input and output ground pins provide Negative Drive Capability allowing the user to drive MOSFET gates with positive and negative VGS voltages. The gate driver control inputs are referenced to a dedicated input ground (IN_REF). The gate driver outputs swing from VCC to the output ground VEE which can be negative with respect to IN_REF. The ability to hold MOSFET gates off with a negative VGS voltage reduces losses when driving low threshold voltage MOSFETs often used as synchronous rectifiers. When driving with conventional positive only gate voltage, the IN_REF and VEE pins are connected together and referenced to a common ground. Under-voltage lockout protection and a shutdown input pin are also provided. The drivers can be operated in parallel with inputs and outputs connected to double the drive current capability. This device is available in the SOIC-8 and the thermally-enhanced WSON-10 packages. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated LM5110 SNVS255A – MAY 2004 – REVISED MAY 2004 www.ti.com Pin Configurations IN_REF 1 8 2 7 IN_A SHDN IN_REF IN_A VEE 6 VCC IN_B 4 IN_B 5 10 2 9 3 8 4 7 5 6 SHDN OUT A OUT A VEE 3 1 Figure 1. SOIC-8 OUT_B NC NC OUT_B VCC Figure 2. WSON-10 NC - NOT CONNECTED Block Diagram VCC UVLO 18µA IN_REF SHDN OUT_A IN_A LEVEL SHIFT VEE VCC IN_B OUT_B LEVEL SHIFT IN_REF VEE Figure 3. Block Diagram of LM5110 2 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 Typical Application VOUT VIN +10V +5V LM5110-1 VCC LM5110-1 VCC LM5025 CONTROLLER OUT_A IN_A IN_B OUT_B OUT_B IN_REF IN_REF OUT_B FB VEE VEE IN_B IN_A OUT_A OUT_A VEE VEE -3V Single Supply & Paralleled Inputs and Outputs Dual Supply utilizing negative Output voltage Drive Figure 4. Simplified Power Converter Using Synchronous Rectifiers with Negative Off Gate Voltage PIN DESCRIPTION Pin Description Name Description Application Information SOIC-8 WSON-10 1 1 IN_REF Ground reference for control inputs Connect to VEE for standard positive only output voltage swing. Connect to system logic ground reference for positive and negative output voltage swing. 2 2 IN_A ‘A’ side control input TTL compatible thresholds. 3 3 VEE Power ground of the driver outputs Connect to either power ground or a negative gate drive supply. 4 4 IN_B ‘B’ side control input TTL compatible thresholds. 5 7 OUT_B Output for the ‘B’ side driver. Capable of sourcing 3A and sinking 5A. Voltage swing of this output is from VCC to VEE. 6 8 VCC Positive supply Locally decouple to VEE and IN_REF. 7 9 OUT_A. Output for the ‘A’ side driver. Capable of sourcing 3A and sinking 5A. Voltage swing of this output is from VCC to VEE . 8 10 nSHDN Shutdown input pin Pull below 1.5V to activate low power shutdown mode. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 3 LM5110 SNVS255A – MAY 2004 – REVISED MAY 2004 www.ti.com Configuration Table Part Number “A” Output Configuration “B” Output Configuration Package LM5110-1M Non-Inverting Non-Inverting SOIC- 8 LM5110-2M Inverting Inverting SOIC- 8 LM5110-3M Inverting Non-Inverting SOIC- 8 LM5110-1SD Non-Inverting Non-Inverting WSON-10 LM5110-2SD Inverting Inverting WSON-10 LM5110-3SD Inverting Non-Inverting WSON-10 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VCC to VEE −0.3V to 15V VCC to IN_REF −0.3V to 15V IN to IN_REF, nSHDN to IN_REF −0.3V to 15V −0.3V to 5V IN_REF to VEE −55°C to +150°C Storage Temperature Range, TSTG Maximum Junction Temperature, TJ(max) +150°C Operating Junction Temperature +125°C ESD Rating (1) 2kV Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. (2) Electrical Characteristics TJ = −40°C to +125°C, VCC = 12V, VEE = IN_REF = 0V, nSHDN = VCC, No Load on OUT_A or OUT_B, unless otherwise specified. Symbol Parameter VCC Operating Range Conditions VCC−IN_REF and VCC−VEE VCCR VCC Under Voltage Lockout (rising) VCC−IN_REF VCCH VCC Under Voltage Lockout Hysteresis ICC VCC Supply Current (ICC) ICCSD VCC Shutdown Current (ICC) Min Typ 3.5 2.3 2.9 Max Units 14 V 3.5 V 230 mV IN_A = IN_B = 0V (5110-1) 1 2 IN_A = IN_B = VCC (5110-2) 1 2 IN_A = VCC, IN_B = 0V (5110-3) 1 2 nSHDN = 0V 18 25 µA 1.75 2.2 V mA CONTROL INPUTS VIH Logic High VIL Logic Low HYS Input Hysteresis IIL Input Current Low IN_A=IN_B=VCC (5110-1-2-3) −1 0.1 1 IIH Input Current High IN_A=IN_B=VCC (5110-1) 10 18 25 IN_A=IN_B=VCC (5110-2) −1 0.1 1 IN_A=VCC (5110-3) -1 0.1 1 IN_B=VCC (5110-3) 10 18 25 −18 −25 0.8 1.35 V 400 mV µA SHUTDOWN INPUT ISD 4 Pull-up Current nSHDN = 0 V Submit Documentation Feedback µA Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 Electrical Characteristics (continued) TJ = −40°C to +125°C, VCC = 12V, VEE = IN_REF = 0V, nSHDN = VCC, No Load on OUT_A or OUT_B, unless otherwise specified. Symbol Parameter VSDR Shutdown Threshold VSDH Shutdown Hysteresis Conditions nSHDN rising Min Typ Max Units 0.8 1.5 2.2 V 165 mV OUTPUT DRIVERS ROH Output Resistance High IOUT = −10 mA 30 50 Ω ROL Output Resistance Low IOUT = + 10 mA 1.4 2.5 Ω ISource Peak Source Current OUTA/OUTB = VCC/2, 200 ns Pulsed Current 3 A ISink Peak Sink Current OUTA/OUTB = VCC/2, 200 ns Pulsed Current 5 A SWITCHING CHARACTERISTICS td1 Propagation Delay Time Low to High, IN rising (IN to OUT) CLOAD = 2 nF, see Figure 6 25 40 ns td2 Propagation Delay Time High to Low, IN falling (IN to OUT) CLOAD = 2 nF, see Figure 6 25 40 ns tr Rise Time CLOAD = 2.0 nF, see Figure 6 14 25 ns tf Fall Time CLOAD = 2 nF, see Figure 6 12 25 ns TJ = 150°C 500 LATCHUP PROTECTION AEC - Q100, Method 004 mA Timing Waveforms 50% 50% INPUT INPUT OUTPUT 50% 50% tD1 tD2 tD1 tD2 90% 90% OUTPUT 10% 10% tf tr tr tf (b) (a) Figure 5. Inverting Timing Waveforms Figure 6. Non-Inverting Timing Waveforms Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 5 LM5110 SNVS255A – MAY 2004 – REVISED MAY 2004 www.ti.com Typical Performance Characteristics Supply Current vs Frequency Supply Current vs Capacitive Load 100 1000 TA = 25°C 10 VCC = 12V SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VCC = 15V VCC = 10V VCC = 5V 1 f = 500kHz 100 10 f = 100kHz 1 TA = 25°C f = 10kHz CL = 2200pF 0.1 1 10 100 0.1 100 1000 10k 1k CAPACITIVE LOAD (pF) FREQUENCY (kHz) Figure 7. Figure 8. Rise and Fall Time vs Supply Voltage Rise and Fall Time vs Temperature 20 20 TA = 25°C VCC = 12V CL = 2200pF CL = 2200pF 18 18 16 16 TIME (ns) TIME (ns) tr tr 14 14 tf tf 12 12 10 10 5 6 4 7 8 9 10 11 12 13 14 15 16 -75 -50 -25 0 SUPPLY VOLTAGE (V) 25 50 75 100 125 150 175 TEMPERATURE (°C) Figure 9. Figure 10. Rise and Fall Time vs Capacitive Load Delay Time vs Supply Voltage 50 32.5 TA = 25°C TA = 25°C VCC = 12V CL = 2200pF 30 40 TIME (ns) TIME (ns) 27.5 30 tr 20 tf 22.5 tD1 10 20 0 17.5 100 1k CAPACITIVE LOAD (pF) 10k 4 6 8 10 12 14 16 SUPPLY VOLTAGE (V) Figure 11. 6 tD2 25 Figure 12. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 Typical Performance Characteristics (continued) Delay Time vs Temperature RDSON vs Supply Voltage 32.5 3.25 VCC = 12V CL = 2200pF IOUT = 10mA 2.75 tD2 ROH ROL (:) TIME (ns) 27.5 55 25 tD1 45 2.25 1.75 35 ROH (:) 30 65 TA = 25°C ROL 22.5 1.25 20 25 15 0.75 17.5 -75 -50 -25 0 0 25 50 75 100 125 150 175 3 6 9 12 15 18 SUPPLY VOLTAGE (V) TEMPERATURE (°C) Figure 13. Figure 14. UVLO Thresholds and Hysteresis vs Temperature 0.450 VCCR 2.800 2.500 VCCF 0.390 0.330 2.200 0.270 VCCH 1.900 1.600 -75 -50 -25 0 HYSTERESIS (V) UVLO THRESHOLDS (V) 3.100 0.210 0.150 25 50 75 100 125 150 175 TEMPERATURE (°C) Figure 15. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 7 LM5110 SNVS255A – MAY 2004 – REVISED MAY 2004 www.ti.com DETAILED OPERATING DESCRIPTION LM5110 dual gate driver consists of two independent and identical driver channels with TTL compatible logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. The bipolar device provides high peak current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power ground potential at the VEE pin. The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The negative supply of the input buffer is connected to the input ground pin IN_REF. An internal level shifting circuit connects the logic input buffers to the totem pole output drivers. The level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. When driving MOSFET gates from a single positive supply, the IN_REF and VEE pins are both connected to the power ground. The LM5110 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver applications. Pin 1 (IN_REF) on the LM5110 is a no-connect on standard driver IC's. Connecting pin 1 to pin 3 (VEE) on the printed circuit board accommodates the pin-out of both the LM5110 and competitive drivers. The isolated input/output grounds provide the capability to drive the MOSFET to a negative VGS voltage for a more robust and reliable off state. In split supply configuration, the IN_REF pin is connected to the ground of the controller which drives the LM5110 inputs. The VEE pin is connected to a negative bias supply that can range from the IN-REF as much as 14V below the VCC gate drive supply. The maximum recommended voltage difference between VCC and IN_REF or between VCC and VEE is 14V. The minimum voltage difference between VCC and IN_REF is 3.5V. Enhancement mode MOSFETs do not inherently require a negative bias on the gate to turn off the FET. However, certain applications may benefit from the capability of negative VGS voltage during turn-off including: 1. when the gate voltages cannot be held safely below the threshold voltage due to transients or coupling in the printed circuit board. 2. when driving low threshold MOSFETs at high junction temperatures 3. when high switching speeds produce capacitive gate-drain current that lifts the internal gate potential of the MOSFET The two driver channels of the LM5110 are designed as identical cells. Transistor matching inherent to integrated circuit manufacturing ensures that the ac and dc performance of the channels are nearly identical. Closely matched propagation delays allow the dual driver to be operated as a single driver if inputs and output pins are connected. The drive current capability in parallel operation is 2X the drive of either channel. Small differences in switching speed between the driver channels will produce a transient current (shoot-through) in the output stage when two output pins are connected to drive a single load. The efficiency loss for parallel operation has been characterized at various loads, supply voltages and operating frequencies. The power dissipation in the LM5110 increases by less than 1% relative to the dual driver configuration when operated as a single driver with inputs and outputs connected. An Under-voltage lockout (UVLO) circuit is included in the LM5110, which senses the voltage difference between VCC and the input ground pin, IN_REF. When the VCC to IN_REF voltage difference falls below 2.7V both driver channels are disabled. The driver will resume normal operation when the VCC to IN_REF differential voltage exceeds approximately 2.9V. UVLO hysteresis prevents chattering during brown-out conditions. The Shutdown pin (nSHDN) is a TTL compatible logic input provided to enable/disable both driver channels. When nSHDN is in the logic low state, the LM5110 is switched to a low power standby mode with total supply current less than 25 µA. This function can be effectively used for start-up, thermal overload, or short circuit fault protection. It is recommended that this pin be connected to VCC when the shutdown function is not being used. The shutdown pin has an internal 18μA current source pull-up to VCC. The input pins of non-inverting drivers have an internal 18μA current source pull-down to IN-REF. The input pins of inverting driver channels have neither pull-up nor pull-down current sources. The LM5110 is available in dual non-inverting (-1), dual inverting (-2) and the combination inverting plus noninverting (-3) configurations. All three configurations are offered in the SOIC-8 and WSON-10 plastic packages. 8 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 Layout Considerations Attention must be given to board layout when using LM5110. Some important considerations include: 1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support high peak currents being drawn from VCC during turn-on of the MOSFET. 2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground avoiding inductive loops. The two paths for returning current to ground are a) between LM5110 IN-REF pin and the ground of the circuit that controls the driver inputs, b) between LM5110 VEE pin and the source of the power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the LM5110. A good method is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface. 3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the LM5110. 4. The LM5110 SOIC footprint is compatible with other industry standard drivers. Simply connect IN_REF pin of the LM5110 to VEE (pin 1 to pin 3) to operate the LM5110 in a standard single supply configuration. 5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either IN_REF or VCC to avoid spurious output signals. If the shutdown feature is not used, the nSHDN pin should be connected to VCC to avoid erratic behavior that would result if system noise were coupled into a floating ’nSHDN’ pin. Thermal Performance INTRODUCTION The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC components in worst case operating conditions. The junction temperature is estimated based on the power dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board and environment. The θJA is not a given constant for the package and depends on the printed circuit board design and the operating environment. DRIVE POWER REQUIREMENT CALCULATIONS IN LM5110 The LM5110 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to switch the MOSFET gate very quickly for operation at high frequencies. VGATE VHIGH Q1 RG VTRIG CIN Q2 The schematic above shows a conceptual diagram of the LM5110 output and MOSFET load. Q1 and Q2 are the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge QG in coloumbs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 9 LM5110 SNVS255A – MAY 2004 – REVISED MAY 2004 www.ti.com Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is approximated by PDRIVER = VGATE x QG x FSW where • FSW = switching frequency of the MOSFET As an example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V. The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching frequency of 300 kHz and VGATE of 12V is equal to PDRIVER = 12V x 30 nC x 300 kHz = 0.108W. If both channels of the LM5110 are operating at equal frequency with equivalent loads, the total losses will be twice as this value which is 0.216W. In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. When either output of the LM5110 changes state, current will flow from VCC to VEE for a very brief interval of time through the output totem-pole N and P channel MOSFETs. The final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and Under-voltage lockout sections. Characterization of the LM5110 provides accurate estimates of the transient and quiescent power dissipation components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8 mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power. Therefore the total power dissipation PD = 0.216 + 0.008 + 0.012 = 0.236W. We know that the junction temperature is given by TJ = PD x θJA + TA Or the rise in temperature is given by TRISE = TJ − TA = PD x θJA For SOIC-8 package θJA is estimated as 170°C/W for the conditions of natural convection. Therefore TRISE is equal to TRISE = 0.236 x 170 = 40.1°C For WSON-10 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. This substantially decreases the junction to ambient thermal resistance (θJA). θJA as low as 40°C/W is achievable with the WSON10 package. The resulting TRISE for the dual driver example above is thereby reduced to just 9.5 degrees. CONTINUOUS CURRENT RATING OF LM5110 The LM5110 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring continuous load current (resistive or inductive loads), package power dissipation, limits the LM5110 current capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be calculated as ISINK (MAX) := TJ(MAX) - TA TJA · RDS (ON) where • RDS(on) is the on resistance of lower MOSFET in the output stage of LM5110 Consider TJ(max) of 125°C and θJA of 170°C/W for an SO-8 package under the condition of natural convection and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the LM5110 output at TJ(max) is 2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents. Similarly, the maximum continuous source current can be calculated as 10 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 LM5110 www.ti.com SNVS255A – MAY 2004 – REVISED MAY 2004 TJ(MAX) - TA ISOURCE (MAX) := TJA · VDIODE where • VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to be about 1.1V at TJ(max) of 125°C Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA. Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Product Folder Links: LM5110 11 PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM5110-1M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -1M LM5110-1MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -1M LM5110-1SD NRND WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5110-1 LM5110-1SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 5110-1 LM5110-1SDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110-1 LM5110-2M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -2M LM5110-2MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -2M LM5110-2SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 5110-2 LM5110-3M/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -3M LM5110-3MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110 -3M LM5110-3SD NRND WSON DPR 10 1000 TBD Call TI Call TI -40 to 125 5110-3 LM5110-3SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110-3 LM5110-3SDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5110-3 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 26-Dec-2014 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5110-1MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5110-1SD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5110-1SD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LM5110-1SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5110-2MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5110-2SD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1 LM5110-3MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5110-3SD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5110-3SD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5110-3SDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Mar-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5110-1MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5110-1SD WSON DPR 10 1000 210.0 185.0 35.0 LM5110-1SD/NOPB WSON DPR 10 1000 203.0 203.0 35.0 LM5110-1SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5110-2MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5110-2SD/NOPB WSON DPR 10 1000 203.0 203.0 35.0 LM5110-3MX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5110-3SD WSON DPR 10 1000 210.0 185.0 35.0 LM5110-3SD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5110-3SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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