Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 OPAx197 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Operational Amplifiers 1 Features 3 Description • • • • • • • • • • • • • • The OPAx197 family (OPA197, OPA2197, and OPA4197) is a new generation of 36-V operational amplifiers. 1 Low Offset Voltage: ±250 µV (max) Low Offset Voltage Drift: ±2.5 µV/°C (max) Low Noise: 5.5 nV/√Hz at 1 kHz High Common-Mode Rejection: 120 dB (min) Low Bias Current: ±5 pA (typ) Rail-to-Rail Input and Output Wide Bandwidth: 10-MHz GBW High Slew Rate: 20 V/µs Low Quiescent Current: 1 mA per Amplifier (typ) Wide Supply: ±2.25 V to ±18 V, +4.5 V to +36 V EMI- and RFI-Filtered Inputs Differential Input Voltage Range to Supply Rail High Capacitive Load Drive Capability: 1 nF Industry Standard Packages: – Single in SOIC-8, SOT-5, and VSSOP-8 – Dual in SOIC-8 and VSSOP-8 – Quad in SOIC-14 and TSSOP-14 These devices offer outstanding dc precision and ac performance, including rail-to-rail input/output, low offset (±25 µV, typ), low offset drift (±0.25 µV/°C, typ), and 10-MHz bandwidth. Unique features such as differential input-voltage range to the supply rail, high output current (±65 mA), high capacitive load drive of up to 1 nF, and high slew rate (20 V/µs) make the OPA197 a robust, highperformance operational amplifier for high-voltage, industrial applications. The OPA197 family of op amps is available in standard packages and is specified from –40°C to +125°C. Device Information(1) PART NUMBER OPA197 2 Applications • • • • • • • Multiplexed Data-Acquisition Systems Test and Measurement Equipment High-Resolution ADC Driver Amplifiers SAR ADC Reference Buffers Programmable Logic Controllers High-Side and Low-Side Current Sensing High Precision Comparators OPA2197 OPA4197 PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.90 mm SOT (5) 2.90 mm × 1.60 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (8) 4.90 mm × 3.90 mm VSSOP (8) 3.00 mm × 3.00 mm SOIC (14) 8.65 mm x 3.90 mm TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the package option addendum at the end of the data sheet. OPA197 in a High-Voltage, Multiplexed, Data-Acquisition System Analog Inputs REF3140 Bridge Sensor OPA197 Gain Gain RC Filter RC Filter OPA625 Reference Driver + Thermocouple 4:2 HV MUX + OPA197 + Antialiasing Filter REF P ADS8864 VIN Current Sensing M Gain Optical Sensor VIN OPA197 Gain High-Voltage Multiplexed Input High-Voltage Level Translation VCM 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA. OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 6.7 Absolute Maximum Ratings ..................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information: OPA197 .................................. 6 Thermal Information: OPA2197 ................................ 6 Thermal Information: OPA4197 ................................ 6 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) ................................................................... 7 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)............................................................... 9 6.9 Typical Characteristics ............................................ 11 7 Detailed Description ............................................ 19 7.1 Overview ................................................................. 19 7.2 Functional Block Diagram ....................................... 19 7.3 Feature Description................................................. 20 7.4 Device Functional Modes........................................ 26 8 Application and Implementation ........................ 27 8.1 Application Information............................................ 27 8.2 Typical Applications ................................................ 27 9 Power-Supply Recommendations...................... 31 10 Layout................................................................... 31 10.1 Layout Guidelines ................................................. 31 10.2 Layout Example .................................................... 32 11 Device and Documentation Support ................. 33 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 33 33 33 34 34 34 34 34 12 Mechanical, Packaging, and Orderable Information ........................................................... 34 4 Revision History Changes from Original (January 2016) to Revision A • 2 Page Added OPA2197 and OPA4197 CDM values to ESD Ratings table...................................................................................... 5 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 5 Pin Configuration and Functions D and DGK Packages: OPA197 8-Pin SOIC and VSSOP Top View NC 1 8 NC -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC DBV Package: OPA197 5-Pin SOT Top View OUT 1 V- 2 +IN 3 5 4 V+ -IN D and DGK Packages: OPA2197 8-Pin SOIC and VSSOP Top View OUT A 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B D and PW Packages: OPA4197 14-Pin SOIC and TSSOP Top View OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 3 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com Pin Functions: OPA197 PIN OPA197 NAME +IN I/O D (SOIC), DGK (VSSOP) DBV (SOT) 3 3 DESCRIPTION I Noninverting input Inverting input –IN 2 4 I NC 1, 5, 8 — — No internal connection (can be left floating) OUT 6 1 O Output V+ 7 5 — Positive (highest) power supply V– 4 2 — Negative (lowest) power supply Pin Functions: OPA2197 and OPA4197 PIN OPA2197 OPA4197 D (SOIC), DGK (VSSOP) D (SOIC), PW (TSSOP) +IN A 3 3 I Noninverting input, channel A +IN B 5 5 I Noninverting input, channel B +IN C — 10 I Noninverting input, channel C +IN D — 12 I Noninverting input, channel D –IN A 2 2 I Inverting input, channel A –IN B 6 6 I Inverting input, channel B –IN C — 9 I Inverting input,,channel C –IN D — 13 I Inverting input, channel D OUT A 1 1 O Output, channel A OUT B 7 7 O Output, channel B OUT C — 8 O Output, channel C OUT D — 14 O Output, channel D V+ 8 4 — Positive (highest) power supply V– 4 11 — Negative (lowest) power supply NAME 4 I/O DESCRIPTION Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 6 Specifications 6.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VS = (V+) – (V–) Signal input pins ±20 Single supply 40 Common-mode Voltage MAX Dual supply (V–) – 0.5 ±10 mA Continuous Operating, TA –55 150 Junction, TJ 150 Storage, Tstg (2) V (V+) – (V–) + 0.2 Current (1) V (V+) + 0.5 Differential Output short circuit (2) Temperature UNIT –65 °C 150 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Short-circuit to ground, one amplifier per package. 6.2 ESD Ratings VALUE UNIT ALL DEVICES V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 V Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±750 V Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500 V MAX UNIT OPA197 V(ESD) OPA2197 V(ESD) OPA4197 V(ESD) (1) (2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Supply voltage, VS = (V+) – (V–) Dual supply Single supply Operating temperature, TA NOM ±2.25 ±18 4.5 36 –40 125 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 V °C 5 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 6.4 Thermal Information: OPA197 OPA197 THERMAL METRIC (1) D (SOIC) DBV (SOT) DGK (VSSOP) 8 PINS 5 PINS 8 PINS UNIT 180.4 °C/W RθJA Junction-to-ambient thermal resistance 115.8 158.8 RθJC(top) Junction-to-case(top) thermal resistance 60.1 60.7 67.9 °C/W RθJB Junction-to-board thermal resistance 56.4 44.8 102.1 °C/W ψJT Junction-to-top characterization parameter 12.8 1.6 10.4 °C/W ψJB Junction-to-board characterization parameter 55.9 4.2 100.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.5 Thermal Information: OPA2197 OPA2197 THERMAL METRIC (1) D (SOIC) DGK (VSSOP) 8 PINS 8 PINS UNIT RθJA Junction-to-ambient thermal resistance 107.9 158 °C/W RθJC(top) Junction-to-case(top) thermal resistance 53.9 48.6 °C/W RθJB Junction-to-board thermal resistance 48.9 78.7 °C/W ψJT Junction-to-top characterization parameter 6.6 3.9 °C/W ψJB Junction-to-board characterization parameter 48.3 77.3 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. 6.6 Thermal Information: OPA4197 OPA4197 THERMAL METRIC (1) D (SOIC) PW (TSSOP) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 86.4 92.6 °C/W RθJC(top) Junction-to-case(top) thermal resistance 46.3 27.5 °C/W RθJB Junction-to-board thermal resistance 41.0 33.6 °C/W ψJT Junction-to-top characterization parameter 11.3 1.9 °C/W ψJB Junction-to-board characterization parameter 40.7 33.1 °C/W RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 6.7 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE VS = ±18 V VOS Input offset voltage VCM = (V+) – 1.5 V dVOS/dT Input offset voltage drift PSRR Power-supply rejection ratio VS = ±18 V, VCM = (V+) – 3 V VS = ±18 V, VCM = (V+) – 1.5 V ±25 ±250 TA = 0°C to 85°C ±30 ±350 TA = –40°C to +125°C ±50 ±400 ±10 ±250 TA = 0°C to 85°C ±25 ±350 TA = –40°C to +125°C ±50 ±500 ±0.5 ±2.5 ±0.8 ±4.5 ±1 ±3 µV/V ±5 ±20 pA ±5 nA ±20 pA ±2 nA TA = –40°C to +125°C TA = –40°C to +125°C µV µV/°C INPUT BIAS CURRENT IB IOS Input bias current Input offset current TA = –40°C to +125°C ±2 TA = –40°C to +125°C NOISE En Input voltage noise en Input voltage noise density (V–) – 0.1 V < VCM < (V+) – 3 V f = 0.1 Hz to 10 Hz 1.30 (V+) – 1.5 V < VCM < (V+) + 0.1 V f = 0.1 Hz to 10 Hz 4 (V–) – 0.1 V < VCM < (V+) – 3 V (V+) – 1.5 V < VCM < (V+) + 0.1 V in Input current noise density f = 100 Hz µVPP 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz nV/√Hz 12.5 f = 1 kHz 1.5 fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 3 V CMRR Common-mode rejection ratio VS = ±18 V, (V+) – 1.5 V < VCM < (V+) TA = –40°C to +125°C TA = –40°C to +125°C (V+) + 0.1 120 140 110 126 100 120 80 100 VS = ±18 V, (V+) – 3 V < VCM < (V+) – 1.5 V V dB See Typical Characteristics INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 1 || 6.4 MΩ || pF 1013Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = ±18 V, (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ VS = ±18 V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ TA = –40°C to +125°C TA = –40°C to +125°C 120 134 110 126 120 143 110 134 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 dB 7 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate VS = ± 18 V, G = 1, 10-V step To 0.01% ts Settling time To 0.001% tOR Overload recovery time VIN × G = VS THD+N Total harmonic distortion + noise G = 1, f = 1 kHz, VO = 3.5 VRMS 10 MHz 20 V/µs V S = ±18 V, G = 1, 10-V step 1.4 V S = ±18 V, G = 1, 5-V step 0.9 V S = ±18 V, G = 1, 10-V step 2.1 V S = ±18 V, G = 1, 5-V step µs 1.8 200 ns 0.00008% OUTPUT No load Positive rail Voltage output swing from rail VO Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 25 95 125 RLOAD = 2 kΩ 430 500 5 25 RLOAD = 10 kΩ 95 125 RLOAD = 2 kΩ 430 500 No load Negative rail ISC 5 RLOAD = 10 kΩ VS = ±18 V ±65 mV mA See Typical Characteristics f = 1 MHz, IO = 0 A, See Figure 26 375 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 1 TA = –40°C to +125°C, IO = 0 A 1.3 1.5 mA TEMPERATURE Thermal protection (1) (1) 8 140 °C For a detailed description of thermal protection, see the Thermal Protection section. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 6.8 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX ±5 ±250 ±8 ±350 ±10 ±400 UNIT OFFSET VOLTAGE VS = ±2.25 V, VCM = (V+) – 3 V TA = 0°C to 85°C TA = –40°C to +125°C VOS Input offset voltage (V+) – 3.5 V < VCM < (V+) – 1.5 V VS = ±3 V, VCM = (V+) – 1.5 V dVOS/dT Input offset voltage drift PSRR Power-supply rejection ratio VS = ±2.25 V, VCM = (V+) – 3 V VS = ±2.25 V, VCM = (V+) – 1.5 V µV See Common-Mode Voltage Range section ±10 ±250 TA = 0°C to 85°C ±25 ±350 TA = –40°C to +125°C ±50 ±500 ±0.5 ±2.5 ±0.8 ±4.5 TA = –40°C to +125°C TA = –40°C to +125°C, VCM = VS / 2 – 0.75 V ±2 µV µV/°C µV/V INPUT BIAS CURRENT IB IOS Input bias current Input offset current ±5 TA = –40°C to +125°C ±2 TA = –40°C to +125°C ±20 pA ±5 nA ±20 pA ±2 nA NOISE En Input voltage noise (V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz (V–) – 0.1 V < VCM < (V+) – 3 V en Input voltage noise density (V+) – 1.5 V < VCM < (V+) + 0.1 V in 1.30 (V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz Input current noise density µVPP 4 f = 100 Hz 10.5 f = 1 kHz 5.5 f = 100 Hz 32 f = 1 kHz 12.5 f = 1 kHz 1.5 nV/√Hz fA/√Hz INPUT VOLTAGE VCM Common-mode voltage range (V–) – 0.1 VS = ±2.25 V, (V–) – 0.1 V < VCM < (V+) – 3 V CMRR Common-mode rejection ratio VS = ±2.25 V, (V+) – 1.5 V < VCM < (V+) TA = –40°C to +125°C TA = –40°C to +125°C (V+) + 0.1 90 110 88 104 94 120 77 100 VS = ±2.25 V, (V+) – 3 V < VCM < (V+) – 1.5 V V dB See Typical Characteristics INPUT IMPEDANCE ZID Differential ZIC Common-mode 100 || 1.6 1 || 6.4 MΩ || pF 1013Ω || pF OPEN-LOOP GAIN AOL Open-loop voltage gain VS = ±2.25 V, (V–) + 0.6 V < VO < (V+) – 0.6 V, RLOAD = 2 kΩ VS = ±2.25 V, (V–) + 0.3 V < VO < (V+) – 0.3 V, RLOAD = 10 kΩ TA = –40°C to +125°C TA = –40°C to +125°C 104 126 100 114 104 134 100 120 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 dB 9 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued) at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FREQUENCY RESPONSE GBW Unity gain bandwidth SR Slew rate G = 1, 1-V step ts Settling time To 0.01% tOR Overload recovery time VIN× G = VS VS = ±3 V, G = 1, 5-V step 10 MHz 20 V/µs 1 µs 200 ns OUTPUT No load Positive rail Voltage output swing from rail VO Short-circuit current CLOAD Capacitive load drive ZO Open-loop output impedance 25 95 125 RLOAD = 2 kΩ 430 500 5 25 RLOAD = 10 kΩ 95 125 RLOAD = 2 kΩ 430 500 No load Negative rail ISC 5 RLOAD = 10 kΩ VS = ±2.25 V ±65 mV mA See Typical Characteristics f = 1 MHz, IO = 0 A, see Figure 26 375 Ω POWER SUPPLY IQ Quiescent current per amplifier IO = 0 A 1 TA = –40°C to +125°C 1.3 1.5 mA TEMPERATURE Thermal protection (1) (1) 10 140 °C For a detailed description of thermal protection, see the Thermal Protection section. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 6.9 Typical Characteristics Table 1. Table of Graphs DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1, Figure 2, Figure 3 Offset Voltage Drift Distribution Figure 4 Offset Voltage vs Temperature Figure 5 Offset Voltage vs Common-Mode Voltage Figure 6, Figure 7, Figure 8 Offset Voltage vs Power Supply Figure 9 Open-Loop Gain and Phase vs Frequency Figure 10 Closed-Loop Gain and Phase vs Frequency Figure 11 Input Bias Current vs Common-Mode Voltage Figure 12 Input Bias Current vs Temperature Figure 13 Output Voltage Swing vs Output Current (maximum supply) Figure 14, Figure 15 CMRR and PSRR vs Frequency Figure 16 CMRR vs Temperature Figure 17 PSRR vs Temperature Figure 18 0.1-Hz to 10-Hz Noise Figure 19 Input Voltage Noise Spectral Density vs Frequency Figure 20 THD+N Ratio vs Frequency Figure 21 THD+N vs Output Amplitude Figure 22 Quiescent Current vs Supply Voltage Figure 23 Quiescent Current vs Temperature Figure 24 Open Loop Gain vs Temperature Figure 25 Open Loop Output Impedance vs Frequency Figure 26 Small Signal Overshoot vs Capacitive Load (100-mV output step) Figure 27, Figure 28 No Phase Reversal Figure 29 Positive Overload Recovery Figure 30 Negative Overload Recovery Figure 31 Small-Signal Step Response (100 mV) Figure 32, Figure 33 Large-Signal Step Response Figure 34 Settling Time Figure 35, Figure 36, , Short-Circuit Current vs Temperature Figure 37 Maximum Output Voltage vs Frequency Figure 38 Propagation Delay Rising Edge Figure 39 Propagation Delay Falling Edge Figure 40 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 11 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 500 35 30 25 Amplifiers (%) Number of Amplifiers 400 300 200 20 15 10 100 5 0 -100 -80 -60 -40 -20 0 20 40 Input Offset Voltage (PV) 60 80 0 -60 -50 -40 -30 -20 -10 0 10 20 30 Input Offset Voltage (PV) 100 40 50 60 4770 production units Figure 1. Offset Voltage Production Distribution at 25°C Figure 2. Offset Voltage Production Distribution at 125°C 35 15 30 12 Amplifiers (%) Amplifiers (%) 25 20 15 9 6 10 3 5 0 -200 -150 -100 -50 0 50 100 Input Offset Voltage (PV) 150 0 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 Input Offset Voltage Drift (PV/qC) 200 Figure 4. Offset Voltage Drift Distribution from –40°C to +125°C 150 75 100 50 Input Offset Voltage (PV) Input Offset Voltage ( V) Figure 3. Offset Voltage Production Distribution at –40°C 50 0 ±50 ±100 25 0 -25 -50 ±150 ±75 ±50 ±25 0 25 50 75 100 125 Temperature (ƒC) 150 -75 -20 -15 -10 C001 15 20 6 typical units 9 typical units Figure 5. Offset Voltage vs Temperature 12 -5 0 5 10 Common-Mode Voltage (V) Figure 6. Offset Voltage vs Common-Mode Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 100 200 75 150 Input Offset Voltage (PV) 50 25 0 -25 -50 100 50 0 -50 -100 -150 -75 -100 13 14 15 16 17 Common-Mode Voltage (V) 18 -200 -2.5 19 -2 -1.5 6 typical units 2 2.5 Figure 8. Offset Voltage vs Common-Mode Voltage 100 140 75 120 280 Open Loop Gain Phase 240 50 100 200 80 160 60 120 40 80 20 40 0 0 Open Loop Gain (db) Input Offset Voltage (PV) 1.5 6 typical units Figure 7. Offset Voltage vs Common-Mode Voltage 25 0 -25 -50 -75 -100 0 2 4 6 8 10 12 14 Power-Supply Voltage (V) 16 18 20 -20 1 10 100 6 typical units 1k 10k 100k Frequency (Hz) 1M 10M -40 100M CLOAD = 15 pF Figure 9. Offset Voltage vs Power Supply Figure 10. Open-Loop Gain and Phase vs Frequency 1000 60 G = 100 V/V G = +1 V/V G = 10 V/V G = -1 V/V 40 20 0 800 Input Bias Current (pA) Closed Loop Gain (db) -1 -0.5 0 0.5 1 Common-Mode Voltage (V) Phase (q) Input Offset Voltage (PV) at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 600 400 200 0 ±200 ±400 ±600 ±800 -20 1k 10k 100k 1M Frequency (Hz) 10M 50M Figure 11. Closed-Loop Gain and Phase vs Frequency ±1000 ±20.0 ±15.0 ±10.0 ±5.0 0.0 5.0 10.0 15.0 VCM (V) 20.0 C001 Figure 12. Input Bias Current vs Common-Mode Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 13 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 3000 (V-) + 5 +125°C (V-) + 4 2000 Output Voltage (V) Input Bias Current (pA) IBIB+ IOS 1000 +85°C (V-) + 3 (V-) + 2 -40°C 25°C (V-) + 1 0 (V-) (V-) - 1 -1000 -75 -50 -25 0 25 50 Temperature (qC) 75 100 0 125 40 50 60 70 80 C001 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) 160.0 (V+) Output Voltage (V) 30 Figure 14. Output Voltage Swing from Negative Power Supply vs Output Current (Maximum Supply) (V+) + 1 (V+) - 1 25°C (V+) - 2 -40°C +125°C (V+) - 3 (V+) - 4 +85°C 140.0 120.0 100.0 80.0 60.0 +PSRR 40.0 CMRR 20.0 -PSRR 0.0 (V+) - 5 0 10 20 30 40 50 60 70 Output Current (mA) 1 80 10 100 1k 10k 100k Frequency (Hz) C001 1M C012 Figure 16. CMRR and PSRR vs Frequency Figure 15. Output Voltage Swing from Positive Power Supply vs Output Current (Maximum Supply) 10 1 Power-Supply Rejection Ratio (µV/V) Common-Mode Rejection Ratio (µV/V) 20 Output Current (mA) Figure 13. Input Bias Current vs Temperature 8 6 4 VS = ±2.25 V 2 0 ±2 VS = ±18 V ±4 ±6 ±8 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 ±10 ±75 ±50 ±25 0 25 50 75 100 Temperature (ƒC) Figure 17. CMRR vs Temperature 14 10 125 150 ±75 ±50 ±25 0 25 50 75 100 Temperature (ƒC) C001 125 150 C001 Figure 18. PSRR vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 400 nV/div Voltage Noise Density (nV/—Hz) 1000 VCM = 0 V (P-Channel) VCM = V+ - 100 mV (N-Channel) 500 300 200 100 50 30 20 10 5 3 2 1 100m 1 10 Time (1 s/div) 100 1k Frequency (Hz) 10k 100k Peak-to-peak noise = VRMS × 6.6 = 1.30 VPP Figure 19. 0.1-Hz to 10-Hz Noise Figure 20. Input Voltage Noise Spectral Density vs Frequency 1 G = 1 V/V, RL = 10 k: G = 1 V/V, RL = 2 k: G = 1 V/V, RL = 2 k: G = 1 V/V, RL = 10 k: 0.01 0.001 0.0001 1E-5 10 100 1k Frequency (Hz) 10k Total Harmonic Distortion + Noise (%) Total Harmonic Distortion + Noise (%) 0.1 G = 1 V/V, RL = 10 k: G = 1 V/V, RL = 2 k: 0.1 0.01 0.001 0.0001 1E-5 0.01 100k G = 1 V/V, RL = 2 k: G = 1 V/V, RL = 10 k: 0.1 1 Output Amplitude (VRMS) VOUT = 3.5 VRMS, BW = 80 kHz 10 20 f = 1 kHz, BW = 80 kHz Figure 21. THD+N Ratio vs Frequency Figure 22. THD+N vs Output Amplitude 1.2 1.2 Quiescent Current (mA) Quiescent Current (mA) VS = r2.25 V VS = r18 V 1.1 1 0.9 0.8 0 4 8 12 16 20 24 Supply Voltage (V) 28 32 36 Figure 23. Quiescent Current vs Supply Voltage 1.1 1 0.9 0.8 -50 -25 0 25 50 Temperature (qC) 75 100 125 Figure 24. Quiescent Current vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 15 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 3 10k VS = r2.25 V VS = r18 V Output Impedance ( ) 2 AOL (PV/V) 1 0 -1 1k 100 -2 10 -3 -50 0 -25 0 25 50 Temperature (qC) 75 100 45 40 Overshoot (%) Overshoot (%) 1k 10k 1M 10M C016 25 20 15 35 30 25 20 10 15 5 10 30 40 50 70 100 200 300 500 700 1000 Capacitive Load (pF) RISO = 0 : RISO = 25 : RISO = 50 : 5 20 2000 30 40 50 70 100 200 300 500 700 1000 Capacitive Load (pF) G = –1 V/V 2000 G = 1 V/V Figure 27. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Figure 28. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step) Output Input Voltage (5 V/div) Voltage (5 V/div) Output Input Time (200 ns/div) Time (200 Ps/div) VS = ±18 V, input = ±18.5 VPP Figure 29. No Phase Reversal 16 100k 50 RISO = 0 : RISO = 25 : RISO = 50 : 30 0 20 100 Figure 26. Open-Loop Output Impedance vs Frequency 45 35 10 Frequency (Hz) Figure 25. Open-Loop Gain vs Temperature 40 1 125 G = –10 V/V Figure 30. Positive Overload Recovery Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) Voltage (5 V/div) Output (50 mV/Div) Output Input Time (200 ns/div) Time (200 ns/Div) G = –10 V/V G = 1 V/V Figure 32. Small-Signal Step Response Output (2.5 V/Div) Output (50 mV/Div) Figure 31. Negative Overload Recovery Time (150 ns/Div) Time (300 ns/Div) G = –1 V/V G = 1 V/V Figure 34. Large-Signal Step Response Output Voltage Delta from Final Value (mV) Output Voltage Delta from Final Value (mV) Figure 33. Small-Signal Step Response 4 3 2 1 0 -1 -2 -3 -4 0 0.2 0.4 0.6 0.8 1 1.2 Time (Ps) 1.4 1.6 1.8 G = 1, 0.01% settling = ±1 mV, step applied at t = 0 Figure 35. Settling Time (10-V Positive Step) 2 4 3 2 1 0 -1 -2 -3 -4 0 0.2 0.4 0.6 0.8 1 1.2 Time (Ps) 1.4 1.6 1.8 2 G = 1, 0.01% settling = ±500 µV, step applied at t = 0 Figure 36. Settling Time (5-V Positive Step) Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 17 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted) 100 30 Maximum output voltage without slew-rate induced distortion. VS = ±15 V 25 80 Output Voltage (VPP) Short-Circuit Current (mA) Sinking current Sourcing current 60 40 20 20 15 VS = ±5 V 10 VS = ±2.25 V 5 0 -75 0 -50 -25 0 25 50 75 Temperature (qC) 100 125 150 10k 100k 1M 10M Frequency (Hz) Figure 37. Short-Circuit Current vs Temperature C033 Figure 38. Maximum Output Voltage vs Frequency Output Voltage (1 V/div) Output Voltage (5 V/div) Overdrive = 100 mV tpLH = 0.97 s VOUT Voltage VOUT Voltage tpLH = 1.1 s Overdrive = 100 mV Time (200 ns/div) Time (200 ns/div) C025 Figure 39. Propagation Delay Rising Edge 18 C026 Figure 40. Propagation Delay Falling Edge Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 7 Detailed Description 7.1 Overview The OPAx197 uses a patented two-temperature trim architecture to achieve a very low offset voltage of 250 µV (max) and low voltage offset drift of 0.75 µV/°C (max) over the full specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for high-impedance industrial sensors, filters, and high-voltage data acquisition. 7.2 Functional Block Diagram OPAx197 NCH Input Stage +IN 36-V Differential Front End Slew Boost High Capacitive Load Compensation Output Stage OUT -IN PCH Input Stage t Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 19 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 7.3 Feature Description 7.3.1 Input Protection Circuitry The OPAx197 uses a unique input architecture to eliminate the need for input protection diodes, but still provides robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure 41 can be activated by fast transient step responses and can introduce signal distortion and settling time delays because of alternate current paths, as shown in Figure 42. For low-gain circuits, these fast-ramping input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended settling time, as shown in Figure 43. V+ V+ +IN +IN OUT OPAx197 36 V OUT ~0.7 V -IN -IN V OPAx197 Provides Full 36-V Differential Input Range V Conventional Input Protection Limits Differential Input Range Figure 41. OPA197 Input Protection Does Not Limit Differential Input Capability Vn = +10 V RFILT +10 V 1 Ron_mux Sn 1 D 2 ~±9.3 V +10 V CFILT CS CD Vn+1 = ±10 V RFILT ±10 V Vin± 2 Ron_mux Sn+1 ~0.7 V CS CFILT Vout Idiode_transient ±10 V Input Low Pass Filter Vin+ Buffer Amplifier Simplified Mux Model Figure 42. Back-to-Back Diodes Create Settling Issues Output Delta from Final Value (mV) 100 Op amp with standard input diodes OPA197 50 0 0.1% settling = r10 mV -50 -100 0 6 12 18 24 30 36 Time (Ps) 42 48 54 60 Figure 43. OPA197 Protection Circuit Maintains Fast-Settling Transient Response 20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 Feature Description (continued) The OPAx197 family of operational amplifiers provides a true high-impedance differential input capability for highvoltage applications. This patented input protection architecture does not introduce additional signal distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input applications. The OPA197 can tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up to 36 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals such as multiplexed data-acquisition systems, as shown in Figure 53. 7.3.2 EMI Rejection The OPAx197 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx197 benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 44 shows the results of this testing on the OPA197. Table 2 shows the EMIRR IN+ values for the OPA197 at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can also be found in the application report EMI Rejection Ratio of Operational Amplifiers, SBOA128, available for download from www.ti.com. 160.0 140.0 PRF = -10 dBm VSUPPLY = ±18 V VCM = 0 V EMIRR IN+ (dB) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 10M 100M 1G Frequency (Hz) 10G C017 Figure 44. EMIRR Testing Table 2. OPA197 EMIRR IN+ For Frequencies of Interest FREQUENCY APPLICATION OR ALLOCATION EMIRR IN+ 400 MHz Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications 44.1 dB 900 MHz Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications 52.8 dB 1.8 GHz GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) 61.0 dB 2.4 GHz 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) 69.5 dB 3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB 5.0 GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) 105.5 dB Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 21 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 7.3.3 Phase Reversal Protection The OPAx197 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The OPAx197 is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 45. Voltage (5 V/div) Output Input Time (200 Ps/div) Figure 45. No Phase Reversal 7.3.4 Thermal Protection The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the OPAx197 is 150°C. Exceeding this temperature causes damage to the device. The OPAx197 has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 46 shows an application example for the OPA197 that has significant self heating (159°C) because of its power dissipation (0.81 W). Thermal calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 46 depicts how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL. VOUT 3 V TA = 65°C PD = 0.81W JA = 116°C/W TJ = 116°C/W × 0.81W + 65°C TJ = 159°C (expected) +30 V 0V Normal Operation Output High-Z 150°C IOUT = 30 mA + ± RL 100 Ÿ VIN 3V + 3V ± Temperature OPAx197 140ºC Figure 46. Thermal Protection 7.3.5 Capacitive Load and Stability The OPAx197 features a patented output stage capable of driving large capacitive loads, and in a unity-gain configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 47 and Figure 48. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation. 22 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 45 50 RISO = 0 : RISO = 25 : RISO = 50 : 40 40 30 Overshoot (%) Overshoot (%) 35 25 20 15 35 30 25 20 10 15 5 10 0 20 RISO = 0 : RISO = 25 : RISO = 50 : 45 30 40 50 70 100 200 300 500 700 1000 Capacitive Load (pF) 5 20 2000 Figure 47. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step, G = –1 V/V) 30 40 50 70 100 200 300 500 700 1000 Capacitive Load (pF) 2000 Figure 48. Small-Signal Overshoot vs Capacitive Load (100-mV Output Step, G = 1 V/V) For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10-Ω to 20-Ω) resistor, RISO, in series with the output, as shown in Figure 49. This resistor significantly reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load in parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the OPA197 well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 49 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin, and results using the OPA197 are summarized in Table 3. For additional information on techniques to optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation, and test results. +Vs Vout Riso + Vin Cload + ± -Vs Figure 49. Extending Capacitive Load Drive with the OPA197 Table 3. OPA197 Capacitive Load Drive Solution Using Isolation Resistor Comparison of Calculated and Measured Results PARAMETER VALUE Capacitive Load 100 pF 1000 pF 0.01 µF 0.1 µF 1 µF Phase Margin 45° 60° 45° 60° 45° 60° 45° 60° 45° 60° RISO (Ω) 47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7 Measured Overshoot (%) 23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6 Calculated PM 45.1° 58.1° 45.8° 59.7° 46.1° 60.1° 45.2° 60.2° 47.2° 60.2° For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files, simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using an Isolation Resistor . Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 23 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 7.3.6 Common-Mode Voltage Range The OPAx197 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 50. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded compared to operation outside this region. V+ IS1 ±IN PCH1 PCH2 NCH4 NCH3 +IN FUSE BANK TRIM TRIM V± Figure 50. Rail-to-Rail Input Stage To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when possible. The OPAx197 uses a precision trim for both the N-channel and P-channel regions. This technique enables significantly lower levels of offset than previous-generation devices, causing variance in the transition region of the input stages to appear exaggerated relative to offset over the full common-mode voltage range, as shown in Figure 51. Transition Region N-Channel Region P-Channel Region 200 200 100 100 Input Offset Voltage ( V) Input Offset Voltage ( V) P-Channel Region 0 ±100 OPAx197 Input Offset Voltage vs Vcm ±200 Transition Region N-Channel Region 0 ±100 ±200 Input Offset Voltage vs Vcm without a precision trimmed Input ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 ±300 ±15.0 ±14.0 « 11.0 12.0 13.0 Common-Mode Voltage (V) 14.0 15.0 Figure 51. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers 24 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 7.3.7 Electrical Overstress Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. See Figure 52 for an illustration of the ESD circuits contained in the OPAx197 (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation. TVS ± + RF +VS VDD R1 RS IN± 100 Ÿ IN+ 100 Ÿ OPAx197 ± + Power-Supply ESD Cell + ID RL ± VIN VSS ± + ±VS TVS Figure 52. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 25 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level. Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events. 7.3.8 Overload Recovery Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the OPAx197 is approximately 200 ns. 7.4 Device Functional Modes The OPAx197 has a single functional mode and is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power supply voltage for the OPAx197 is 36 V (±18 V). 26 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The OPAx197 family offers outstanding dc precision and ac performance. These devices operate up to 36-V supply rails and offer true rail-to-rail input/output, ultralow offset voltage and offset voltage drift, as well as 10-MHz bandwidth and high capacitive load drive. These features make the OPAx197 a robust, highperformance operational amplifier for high-voltage industrial applications. 8.2 Typical Applications 8.2.1 16-Bit Precision Multiplexed Data-Acquisition System Figure 53 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in industrial applications that require low distortion and a high-voltage differential input. The circuit uses the ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This application example explains the process for optimizing the precision, high-voltage, front-end drive circuit using the OPA197 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864. 1 2 Very Low Output Impedance Input-Filter Bandwidth 3 High-Impedance Inputs No Differential Input Clamps Fast Settling-Time Requirements Attenuate High-Voltage Input Signal Fast-Settling Time Requirements Stability of the Input Driver Attenuate ADC Kickback Noise VREF Output: Value and Accuracy Low Temp and Long-Term Drift Voltage Reference CH0+ ±20-V, 10-kHz Sine Wave 4 + RC Filter Buffer RC Filter OPA197 Reference Driver + CH0- Gain Network OPA197 Gain Network + OPA197 4:2 Mux REFP + CH3+ ±20-V, 10-kHz Sine Wave + OPA140 Gain Network OPA197 VINP + Antialiasing Filter OPA197 SAR ADC + VINM OPA197 n High-Voltage Multiplexed Input CONV Gain Network CH3- 16 Bits 400 kSPS High-Voltage Level Translation VCM REF3240 Voltage Divider OPA350 VCM Generation Circuit Counter n Shmidtt Trigger Delay Digital Counter For Multiplexer 5 Fast logic transition Figure 53. OPA197 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High-Voltage Inputs With Lowest Distortion Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 27 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com Typical Applications (continued) 8.2.1.1 Design Requirements The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input. The design requirements for this block design are: • System Supply Voltage: ±15 V • ADC Supply Voltage: 3.3 V • ADC Sampling Rate: 400 kSPS • ADC Reference Voltage (REFP): 4.096 V • System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency (fIN) of 10 kHz are applied to each differential input of the mux. 8.2.1.2 Detailed Design Procedure The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for highest system linearity and fast settling. The overall system block diagram is shown in Figure 53. The circuit is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit resolution and lowest distortion system. The diagram includes the most important specifications for each individual analog block. This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding helps in the decision of an appropriate input filter and selection of a mux to meet the system settling requirements. The next important step is the design of the attenuating analog front end (AFE) used to level translate the high-voltage input signal to a low-voltage ADC input while maintaining the amplifier stability. The next step is to design a digital interface to switch the mux input channels with minimum delay. The final design challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage with low offset, drift, and noise contributions. 8.2.1.3 Application Curve Integral Nonlinearity Error (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –20 –15 –10 –5 0 5 10 15 20 ADC Differential Input (V) Figure 54. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for High Voltage Inputs with Lowest Distortion. 28 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 8.2.2 Slew Rate Limit for Input Protection In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages. By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high output current and slew rate of the OPAx197 make the device an optimal amplifier to achieve slew rate control for both dual- and single-supply systems.Figure 55 shows the OPA197 in a slew-rate limit design. Op Amp Gain Stage Slew Rate Limiter C1 470 nF R1 1.69 NŸ VEE VEE R2 1.6 0Ÿ + VIN - OPA197 + V+ OPA197 + V+ VOUT VCC RL 10 NŸ VCC Figure 55. Slew Rate Limiter Uses One Op Amp For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 29 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 8.2.3 Precision Reference Buffer The OPAx197 features high output current drive capability and low input offset voltage, making the device an excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-µF ceramic capacitor shown in Figure 56, RISO, a 37.4-Ω isolation resistor, provides separation of two feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output, VOUT. Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz, while still providing a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability components: RF, RFx, CF, and RISO. RF 1 NŸ RFx 10 NŸ CF 39 nF RISO 37.4 Ÿ ± OPA197 + V+ VOUT CL 10 µF VREF 2.5 V VCC Figure 56. Precision Reference Buffer 30 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 9 Power-Supply Recommendations The OPAx197 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. CAUTION Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings. Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout section. 10 Layout 10.1 Layout Guidelines For best operational performance of the device, use good PCB layout practices, including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds paying attention to the flow of the ground current. For more detailed information refer to Circuit Board Layout Techniques, SLOA089. • In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace. • Place the external components as close to the device as possible. As shown in Figure 57, keeping RF and RG close to the inverting input minimizes parasitic capacitance. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. • Cleaning the PCB following board assembly is recommended for best performance. • Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 31 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 10.2 Layout Example + VIN VOUT RG RF (Schematic Representation) Place components close to device and Run the input traces to each other to as far away from reduce parasitic the supply lines errors as possible VS+ RF NC NC GND ±IN V+ VIN +IN OUT V± NC RG Use low-ESR, ceramic bypass capacitor GND VS± GND Use low-ESR, ceramic bypass capacitor VOUT Ground (GND) plane on another layer Figure 57. Operational Amplifier Board Layout for Noninverting Configuration 32 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 OPA197, OPA2197, OPA4197 www.ti.com SBOS737A – JANUARY 2016 – REVISED JULY 2016 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 TINA-TI™ (Free Software Download) TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities. Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool. NOTE These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder. 11.1.1.2 TI Precision Designs The OPA197 is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits. 11.2 Documentation Support 11.2.1 Related Documentation Circuit Board Layout Techniques, SLOA089. Op Amps for Everyone, SLOD006. 11.3 Related Links Table 4 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY OPA197 Click here Click here Click here Click here Click here OPA2197 Click here Click here Click here Click here Click here OPA4197 Click here Click here Click here Click here Click here Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 33 OPA197, OPA2197, OPA4197 SBOS737A – JANUARY 2016 – REVISED JULY 2016 www.ti.com 11.4 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.5 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.6 Trademarks E2E is a trademark of Texas Instruments. TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc. Bluetooth is a registered trademark of Bluetooth SIG, Inc. TINA, DesignSoft are trademarks of DesignSoft, Inc. All other trademarks are the property of their respective owners. 11.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.8 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 34 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: OPA197 OPA2197 OPA4197 PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) OPA197ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197 OPA197IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV OPA197IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 12MV OPA197IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST OPA197IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 12ST OPA197IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA197 OPA2197ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2197 OPA2197IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV OPA2197IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 4HV OPA2197IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 2197 OPA4197ID PREVIEW SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197 OPA4197IDR PREVIEW SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 OPA4197 OPA4197IPW PREVIEW TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 OPA4197 OPA4197IPWR PREVIEW TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 OPA4197 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2016 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ OPA197IDBVR SOT-23 3000 180.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.4 3.23 3.17 1.37 4.0 W Pin1 (mm) Quadrant 8.0 Q3 OPA197IDBVT SOT-23 DBV 5 250 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 OPA197IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA197IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA197IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA2197IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2197IDGKT VSSOP DGK 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1 OPA2197IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Aug-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA197IDBVR SOT-23 DBV 5 3000 223.0 270.0 35.0 OPA197IDBVT SOT-23 DBV 5 250 223.0 270.0 35.0 OPA197IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 OPA197IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 OPA197IDR SOIC D 8 2500 367.0 367.0 35.0 OPA2197IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 OPA2197IDGKT VSSOP DGK 8 250 223.0 270.0 35.0 OPA2197IDR SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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