The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. CONTINUITY OF SPECIFICATIONS There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. Future revisions will occur when appropriate, and changes will be noted in a document history page. CONTINUITY OF ORDERING PART NUMBERS Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. FOR MORE INFORMATION Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products and services. OUR CUSTOMERS Cypress is for true innovators – in companies both large and small. Our customers are smart, aggressive, out-of-the-box thinkers who design and develop game-changing products that revolutionize their industries or create new industries with products and solutions that nobody ever thought of before. ABOUT CYPRESS Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to www.cypress.com. Cypress Semiconductor Corporation Document Number: 002-15051 Rev. *I 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Revised July 1, 2016 Preliminary Data Sheet BCM43455 Single-Chip 5G WiFi IEEE 802.11ac MAC/Baseband/ Radio with Integrated Bluetooth 4.1 and FM Receiver GE NE R AL DE S C RI PT ION The Broadcom® BCM43455 single-chip device provides the highest level of integration for a mobile or handheld wireless system with integrated singlestream IEEE 802.11ac MAC/baseband/radio, Bluetooth 4.1,and FM receiver. In IEEE 802.11ac mode, the WLAN operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates of up to 433.3 Mbps. All rates specified in the IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers and receive low-noise amplifiers. Optional external PAs and LNAs are also supported. The WLAN section supports the following host interface options: an SDIO v3.0 interface that can operate in 4b or 1b mode, a high-speed 4-wire UART, and a PCIe Gen1 (3.0 compliant) interface. The Bluetooth section supports a high-speed 4-wire UART interface. Using advanced design techniques and process technology to reduce active and idle power, the BCM43455 is designed to address the needs of mobile devices that require minimal power consumption and compact size. It includes a power management unit which simplifies the system power topology and allows for direct operation from a mobile platform battery while maximizing battery life. The BCM43455 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external radios (such as LTE cellular and GPS) is provided via an external interface. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. Figure 1: Functional Block Diagram VIO WLAN Host I/F WL_REG_ON PCIe UART SDIO External Coexistence I/F COEX BT_REG_ON Bluetooth Host I/F FM Rx Host I/F VBAT 5 GHz WLAN Tx 5 GHz WLAN Rx 2.4 GHz WLAN Tx 2.4 GHz WLAN/BT Rx Bluetooth Tx FEM or T/R Switch FEM or Optional T/R Switch CBF BCM43455 UART I2 S PCM BT_DEV_WAKE BT_HOST_WAKE FM Rx FM I/F FM Audio Out I2 S 43455-DS109-R 5300 California Avenue • Irvine, CA 92617 • Phone: 949-926-5000 • Fax: 949-926-5203 November 5, 2015 BCM43455 Preliminary Data Sheet Revision History F E A T U RE S IEEE 802.11x Key Features • IEEE 802.11ac compliant. • • • • • • • • • • • • • • Support for TurboQAM® (MCS0–MCS8 86 Mbps and MCS0–MCS9 96 Mbps) HT20, 20 MHz channel bandwidth. Single-stream spatial multiplexing up to 433.3 Mbps data rate. Supports 20, 40, and 80 MHz channels with optional SGI (256 QAM modulation). Full IEEE 802.11a/b/g/n legacy compatibility with enhanced performance. Supports explicit IEEE 802.11ac transmit beamforming. TX and RX low-density parity check (LDPC) support for improved range and power efficiency. On-chip power amplifiers and low-noise amplifiers for both bands. Support for optional front-end modules (FEM) with external PAs and LNAs. Supports optional integrated T/R switch for 2.4 GHz band. Supports RF front-end architecture with a single dual-band antenna shared between Bluetooth and WLAN for lowest system cost. Shared Bluetooth and WLAN receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both Bluetooth and WLAN. Internal fractional-n PLL allows support for a wide range of reference clock frequencies. Supports IEEE 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as LTE or GPS. Supports standard SDIO v3.0 (including DDR50 mode at 50 MHz and SDR104 mode at 208 MHz, 4-bit and 1-bit) interfaces. Broadcom® November 5, 2015 • 43455-DS109-R Bluetooth Key Features • Complies with Bluetooth Core Specification Version 4.1 with provisions for supporting future specifications. • Bluetooth Class 1 or Class 2 transmitter operation. • Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. • Adaptive frequency hopping (AFH) for reducing radio frequency interference. • Interface support, host controller interface (HCI) using a high-speed UART interface and PCM for audio data. • FM unit supports HCI for communication. • FM receiver: 65 MHz to 108 MHz FM bands; supports the European radio data systems (RDS) and the North American radio broadcast data system (RBDS) standards. • Low power consumption improves battery life of handheld devices. • Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. • Automatic frequency detection for standard crystal and TCXO values. General Features • Supports battery voltage range from 3.0V to 5.25V supplies with internal switching regulator. • Programmable dynamic power management • 6 Kbit OTP for storing board parameters. • GPIOs: 15 • 140-ball WLBGA package (4.47 mm × 5.27 mm, 0.4 mm pitch). • BROADCOM CONFIDENTIAL Page 2 F E A T U RE S IEEE 802.11x Key Features (Cont.) • Backward compatible with SDIO v2.0 host interfaces. • PCIe mode complies with PCI Express base specification revision 3.0 compliant Gen1 interface for ×1 lane and power management base specification. • Integrated ARMCR4 processor with tightly coupled memory for complete WLAN subsystem functionality and minimizing the need to wake-up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to field upgrade with future features. On-chip memory includes 800 KB SRAM and 704 KB ROM. • General Features (Cont.) • Security: – WPA and WPA2 (Personal) support for powerful encryption and authentication – AES and TKIP in hardware for faster data encryption and IEEE 802.11i compatibility – Reference WLAN subsystem provides Cisco Compatible Extensions (CCX, CCX 2.0, CCX 3.0, and CCX 4.0) – Reference WLAN subsystem provides Wi-Fi Protected Setup (WPS) • Worldwide regulatory support: Global products supported with worldwide homologated design. OneDriver™ software architecture for easy migration from existing embedded WLAN and Bluetooth devices as well as future devices. Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2015 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom®, the pulse logo, Connecting everything®, the Connecting everything logo, OneDriver™, SmartAudio®, and TurboQAM® are among the trademarks of Broadcom Corporation and/or its affiliates in the United States, certain other countries and/or the EU. Any other trademarks or trade names mentioned are the property of their respective owners. This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. BROADCOM PROVIDES THIS DATA SHEET “AS-IS,” WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. BCM43455 Preliminary Data Sheet Revision History Revision History Revision Date Change Description 43455-DS109-R 11/05/15 Updated: • Table 17: “WLBGA Pin List by Pin Number,” on page 81. • Table 18: “WLBGA Pin List by Pin Name,” on page 83. • Table 19: “Signal Descriptions,” on page 85. 43455-DS108-R 09/25/15 43455-DS107-R 07/29/15 43455-DS106-R 07/09/15 43455-DS105-R 04/06/15 Updated: • Figure 55: “140-Ball WLBGA Package Mechanical Information,” on page 24: nominal height (A) is 0.55 mm. Updated: • Figure 56: “140-Balls WLBGA Keep-out Areas for PCB Layout —Top View with Balls Facing Down,” on page 169 Updated: • Table 22: “WLBGA Signal Descriptions,” on page 97. • Table 26: “I/O States,” on page 106. • Table 37: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 125. • Table 39: “WLAN 5 GHz Receiver Performance Specifications,” on page 130. • Figure 56: “140-Balls WLBGA Keep-out Areas for PCB Layout—Top View with Balls Facing Down,” on page 168. Updated: • Table 36: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 122. • Table 38: “WLAN 5 GHz Transmitter Performance Specifications,” on page 128. Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 4 BCM43455 Preliminary Data Sheet Revision History Revision Date Change Description 43455-DS104-R 03/31/15 Updated: • “JTAG/SWD Interface” on page 73. • Table 22: “WLBGA Signal Descriptions,” on page 97: WLAN GPIO interface and JTAG interface. • Table 29: “ESD Specifications,” on page 110. • Table 31: “Bluetooth Receiver RF Specifications,” on page 113. • Table 32: “Bluetooth Transmitter RF Specifications,” on page 116. • Table 33: “Local Oscillator Performance,” on page 118. • Table 34: “BLE RF Specifications,” on page 118. • Table 36: “2.4 GHz Band General RF Specifications,” on page 125. • Table 37: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 125. • Table 38: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 129. • Table 40: “WLAN 5 GHz Transmitter Performance Specifications,” on page 135. • “Transmitter Spurious Emissions Specifications” on page 137. • Section 18: “Internal Regulator Electrical Specifications,” on page 141. • Table 53: “2.4 GHz Mode WLAN Power Consumption,” on page 147. • Table 54: “5 GHz Mode WLAN Power Consumption,” on page 148. • Table 55: “Bluetooth and BLE Current Consumption,” on page 149. Added: • “SWD Timing” on page 161. Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 5 BCM43455 Preliminary Data Sheet Revision History Revision Date Change Description 43455-DS103-R 02/04/15 Updated: • “External Coexistence Interface” on page 72. • Table 31: “Bluetooth Receiver RF Specifications,” on page 113. • Table 32: “Bluetooth Transmitter RF Specifications,” on page 116. • Table 33: “Local Oscillator Performance,” on page 118. • Table 34: “BLE RF Specifications,” on page 118. • Table 35: “FM Receiver Specifications,” on page 119. • Table 37: “WLAN 2.4 GHz Receiver Performance Specifications,” on page 125. • Table 38: “WLAN 2.4 GHz Transmitter Performance Specifications,” on page 128. • Table 39: “WLAN 5 GHz Receiver Performance Specifications,” on page 129. • Table 40: “WLAN 5 GHz Transmitter Performance Specifications,” on page 133. • Table 42: “2.4 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications,” on page 135. • Table 43: “5 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications,” on page 136. • Table 44: “5 GHz Band, 40 MHz Channel Spacing TX Spurious Emissions Specifications,” on page 137. • Table 45: “5 GHz Band, 80 MHz Channel Spacing TX Spurious Emissions Specifications,” on page 138. • Table 46: “2G and 5G General Receiver Spurious Emissions,” on page 139. • Table 53: “2.4 GHz Mode WLAN Power Consumption,” on page 146. • Table 54: “5 GHz Mode WLAN Power Consumption,” on page 147. 43455-DS102-R 11/20/14 Updated: • Table 26: “ESD Specifications,” on page 104. 43455-DS101-R 11/06/14 43455-DS100-R 10/27/14 Updated: • Figure 3: “Typical Power Topology (Page 1 of 2),” on page 22 and Figure 4: “Typical Power Topology (Page 2 of 2),” on page 23. • Figure 38: “Port Locations for Bluetooth Testing,” on page 109. • Figure 39: “Port Locations for WLAN Testing,” on page 121. Initial release. Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 6 BCM43455 Preliminary Data Sheet Table of Contents Table of Contents About This Document ................................................................................................................................ 17 Purpose and Audience .......................................................................................................................... 17 Acronyms and Abbreviations................................................................................................................. 17 Document Conventions ......................................................................................................................... 17 References ............................................................................................................................................ 17 Technical Support ...................................................................................................................................... 18 Section 1: BCM43455 Overview ....................................................................................... 19 Overview...................................................................................................................................................... 19 Standards Compliance............................................................................................................................... 21 Mobile Phone Usage Model ....................................................................................................................... 22 Section 2: Power Supplies and Power Management ..................................................... 23 Power Supply Topology............................................................................................................................. 23 BCM43455 PMU Features .......................................................................................................................... 23 WLAN Power Management ........................................................................................................................ 26 PMU Sequencing ........................................................................................................................................ 26 Power-Off Shutdown .................................................................................................................................. 27 Power-Up/Power-Down/Reset Circuits..................................................................................................... 28 Section 3: Frequency References.................................................................................... 29 Crystal Interface and Clock Generation ................................................................................................... 29 External Frequency Reference.................................................................................................................. 30 Frequency Selection .................................................................................................................................. 32 External 32.768 kHz Low-Power Oscillator .............................................................................................. 33 Section 4: Bluetooth and FM Subsystem Overview....................................................... 34 Features....................................................................................................................................................... 34 Bluetooth Radio.......................................................................................................................................... 36 Transmit ................................................................................................................................................ 36 Digital Modulator ................................................................................................................................... 36 Digital Demodulator and Bit Synchronizer............................................................................................. 36 Power Amplifier ..................................................................................................................................... 36 Receiver ................................................................................................................................................ 37 Digital Demodulator and Bit Synchronizer............................................................................................. 37 Receiver Signal Strength Indicator........................................................................................................ 37 Local Oscillator Generation ................................................................................................................... 37 Calibration ............................................................................................................................................. 37 Section 5: Bluetooth Baseband Core .............................................................................. 38 Bluetooth 4.0 Features............................................................................................................................... 38 Broadcom® November 5, 2015 • 43455-DS109-R Page 7 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Table of Contents Bluetooth 4.1 Features............................................................................................................................... 39 Bluetooth Low Energy ............................................................................................................................... 39 Link Control Layer...................................................................................................................................... 39 Test Mode Support ..................................................................................................................................... 40 Bluetooth Power Management Unit .......................................................................................................... 40 RF Power Management ........................................................................................................................ 40 Host Controller Power Management ..................................................................................................... 40 BBC Power Management...................................................................................................................... 43 Wideband Speech.......................................................................................................................... 43 Packet Loss Concealment ............................................................................................................. 43 Audio Rate-Matching Algorithms.................................................................................................... 44 Codec Encoding............................................................................................................................. 44 Multiple Simultaneous A2DP Audio Stream................................................................................... 44 FM Over Bluetooth ................................................................................................................................ 44 Burst Buffer Operation ................................................................................................................... 44 Adaptive Frequency Hopping.................................................................................................................... 45 Advanced Bluetooth/WLAN Coexistence................................................................................................. 45 Fast Connection (Interlaced Page and Inquiry Scans) ........................................................................... 45 Section 6: Microprocessor and Memory Unit for Bluetooth.......................................... 46 RAM, ROM, and Patch Memory ................................................................................................................. 46 Reset............................................................................................................................................................ 46 Section 7: Bluetooth Peripheral Transport Unit ............................................................. 47 SPI Interface................................................................................................................................................ 47 SPI/UART Transport Detection.................................................................................................................. 47 PCM Interface.............................................................................................................................................. 48 Slot Mapping ......................................................................................................................................... 48 Frame Synchronization ......................................................................................................................... 48 Data Formatting..................................................................................................................................... 48 Wideband Speech Support ................................................................................................................... 49 Multiplexed Bluetooth Over PCM .......................................................................................................... 49 Burst PCM Mode ................................................................................................................................... 49 PCM Interface Timing............................................................................................................................ 50 Short Frame Sync, Master Mode ................................................................................................... 50 Short Frame Sync, Slave Mode ..................................................................................................... 51 Long Frame Sync, Master Mode.................................................................................................... 52 Long Frame Sync, Slave Mode...................................................................................................... 53 Short Frame Sync, Burst Mode...................................................................................................... 54 Long Frame Sync, Burst Mode ...................................................................................................... 55 Broadcom® November 5, 2015 • 43455-DS109-R Page 8 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Table of Contents UART Interface............................................................................................................................................ 56 I2S Interface................................................................................................................................................. 57 I2S Timing.............................................................................................................................................. 58 Section 8: FM Receiver Subsystem ................................................................................. 60 FM Radio ..................................................................................................................................................... 60 Digital FM Audio Interfaces ....................................................................................................................... 60 FM Over Bluetooth ..................................................................................................................................... 60 eSCO............................................................................................................................................................ 60 Wideband Speech Link .............................................................................................................................. 61 A2DP ............................................................................................................................................................ 61 Autotune and Search Algorithms ............................................................................................................. 61 Audio Features ........................................................................................................................................... 62 RDS/RBDS................................................................................................................................................... 64 Section 9: WLAN Global Functions ................................................................................. 65 WLAN CPU and Memory Subsystem........................................................................................................ 65 One-Time Programmable Memory ............................................................................................................ 65 GPIO Interface............................................................................................................................................. 65 External Coexistence Interface ................................................................................................................. 66 UART Interface............................................................................................................................................ 67 JTAG/SWD Interface................................................................................................................................... 67 Section 10: WLAN Host Interfaces................................................................................... 68 SDIO v3.0..................................................................................................................................................... 68 SDIO Pins.............................................................................................................................................. 69 PCI Express Interface................................................................................................................................. 70 Transaction Layer Interface................................................................................................................... 71 Data Link Layer ..................................................................................................................................... 71 Physical Layer ....................................................................................................................................... 71 Logical Subblock ................................................................................................................................... 71 Scrambler/Descrambler......................................................................................................................... 71 8B/10B Encoder/Decoder...................................................................................................................... 72 Elastic FIFO........................................................................................................................................... 72 Electrical Subblock ................................................................................................................................ 72 Configuration Space.............................................................................................................................. 72 Section 11: Wireless LAN MAC and PHY ........................................................................ 73 IEEE 802.11ac MAC .................................................................................................................................... 73 PSM....................................................................................................................................................... 74 WEP ...................................................................................................................................................... 75 TXE ....................................................................................................................................................... 75 Broadcom® November 5, 2015 • 43455-DS109-R Page 9 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Table of Contents RXE ....................................................................................................................................................... 75 IFS......................................................................................................................................................... 75 TSF........................................................................................................................................................ 76 NAV ....................................................................................................................................................... 76 MAC-PHY Interface............................................................................................................................... 76 IEEE 802.11ac PHY ..................................................................................................................................... 76 Section 12: WLAN Radio Subsystem ............................................................................. 78 Receiver Path.............................................................................................................................................. 78 Transmit Path.............................................................................................................................................. 78 Calibration................................................................................................................................................... 78 Section 13: Ball Map and Pin Descriptions..................................................................... 80 Ball Map....................................................................................................................................................... 80 Pin List by Pin Number .............................................................................................................................. 81 Pin List by Pin Name .................................................................................................................................. 83 Pin Descriptions ......................................................................................................................................... 85 WLAN GPIO Signals and Strapping Options ........................................................................................... 91 Multiplexed Bluetooth GPIO Signals ..................................................................................................... 92 I/O States ..................................................................................................................................................... 94 Section 14: DC Characteristics ........................................................................................ 97 Absolute Maximum Ratings ...................................................................................................................... 97 Environmental Ratings .............................................................................................................................. 98 Electrostatic Discharge Specifications .................................................................................................... 98 Recommended Operating Conditions and DC Characteristics ............................................................. 99 Section 15: Bluetooth RF Specifications ...................................................................... 100 Section 16: FM Receiver Specifications........................................................................ 107 Section 17: WLAN RF Specifications ............................................................................ 112 Introduction............................................................................................................................................... 112 2.4 GHz Band General RF Specifications............................................................................................... 113 WLAN 2.4 GHz Receiver Performance Specifications .......................................................................... 113 WLAN 2.4 GHz Transmitter Performance Specifications ..................................................................... 117 WLAN 5 GHz Receiver Performance Specifications ............................................................................. 118 WLAN 5 GHz Transmitter Performance Specifications ........................................................................ 124 General Spurious Emissions Specifications ......................................................................................... 125 Transmitter Spurious Emissions Specifications .................................................................................. 125 2.4 GHz Band Spurious Emissions .............................................................................................. 126 20 MHz Channel Spacing .................................................................................................... 126 5 GHz Band Spurious Emissions ................................................................................................. 127 Broadcom® November 5, 2015 • 43455-DS109-R Page 10 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Table of Contents 20 MHz Channel Spacing .................................................................................................... 127 40 MHz Channel Spacing .................................................................................................... 128 80 MHz Channel Spacing .................................................................................................... 129 Receiver Spurious Emissions Specifications ...................................................................................... 129 Section 18: Internal Regulator Electrical Specifications ............................................. 130 Core Buck Switching Regulator.............................................................................................................. 130 3.3V LDO (LDO3P3) .................................................................................................................................. 131 2.5V LDO (BTLDO2P5) ............................................................................................................................. 132 CLDO ......................................................................................................................................................... 133 LNLDO ....................................................................................................................................................... 134 PCIe LDO ................................................................................................................................................... 135 Section 19: System Power Consumption...................................................................... 136 WLAN Current Consumption................................................................................................................... 136 2.4 GHz Mode ..................................................................................................................................... 136 5 GHz Mode ........................................................................................................................................ 137 Bluetooth Current Consumption............................................................................................................. 138 Section 20: Interface Timing and AC Characteristics .................................................. 139 SDIO Timing .............................................................................................................................................. 139 SDIO Default Mode Timing ................................................................................................................. 139 SDIO High-Speed Mode Timing.......................................................................................................... 141 SDIO Bus Timing Specifications in SDR Modes ................................................................................. 142 Clock Timing ................................................................................................................................ 142 Card Input Timing......................................................................................................................... 143 Card Output Timing...................................................................................................................... 144 SDIO Bus Timing Specifications in DDR50 Mode............................................................................... 146 Data Timing.................................................................................................................................. 147 PCI Express Interface Parameters .......................................................................................................... 148 JTAG Timing ............................................................................................................................................. 150 SWD Timing .............................................................................................................................................. 150 Section 21: Power-Up Sequence and Timing ............................................................... 151 Sequencing of Reset and Regulator Control Signals ........................................................................... 151 Description of Control Signals ............................................................................................................. 151 Control Signal Timing Diagrams.......................................................................................................... 152 Section 22: Package Information ................................................................................... 154 Package Thermal Characteristics ........................................................................................................... 154 Junction Temperature Estimation and PSIJT Versus THETAJC ........................................................... 154 Environmental Characteristics................................................................................................................ 154 Broadcom® November 5, 2015 • 43455-DS109-R Page 11 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Table of Contents Section 23: Mechanical Information .............................................................................. 155 Section 24: Ordering Information .................................................................................. 157 Broadcom® November 5, 2015 • 43455-DS109-R Page 12 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet List of Figures List of Figures Figure 1: Functional Block Diagram................................................................................................................... 1 Figure 2: BCM43455 Block Diagram ............................................................................................................... 20 Figure 3: Typical Power Topology (Page 1 of 2).............................................................................................. 24 Figure 4: Typical Power Topology (Page 2 of 2).............................................................................................. 25 Figure 5: Recommended Oscillator Configuration ........................................................................................... 29 Figure 6: Recommended Circuit to Use With an External Reference Clock .................................................... 30 Figure 7: Startup Signaling Sequence Prior to Software Download ................................................................ 42 Figure 8: CVSD Decoder Output Waveform Without PLC ............................................................................... 44 Figure 9: CVSD Decoder Output Waveform After Applying PLC..................................................................... 44 Figure 10: Functional Multiplex Data Diagram................................................................................................. 49 Figure 11: PCM Timing Diagram (Short Frame Sync, Master Mode) .............................................................. 50 Figure 12: PCM Timing Diagram (Short Frame Sync, Slave Mode) ................................................................ 51 Figure 13: PCM Timing Diagram (Long Frame Sync, Master Mode)............................................................... 52 Figure 14: PCM Timing Diagram (Long Frame Sync, Slave Mode)................................................................. 53 Figure 15: PCM Burst Mode Timing (Receive Only, Short Frame Sync) ......................................................... 54 Figure 16: PCM Burst Mode Timing (Receive Only, Long Frame Sync) ......................................................... 55 Figure 17: UART Timing .................................................................................................................................. 57 Figure 18: I2S Transmitter Timing .................................................................................................................... 59 Figure 19: I2S Receiver Timing........................................................................................................................ 59 Figure 20: Audio SNR for Blend, Switch, and FME Modes.............................................................................. 62 Figure 21: Stereo Separation for Blend, Switch, and FME Modes .................................................................. 63 Figure 22: Example Soft Mute Characteristic .................................................................................................. 63 Figure 23: Broadcom GCI or BT-SIG WCI-2 LTE Coexistence Interface ........................................................ 66 Figure 24: 3-Wire LTE Coexistence Interface.................................................................................................. 66 Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode) ........................................................................ 69 Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode) ........................................................................ 69 Figure 27: PCI Express Layer Model ............................................................................................................... 70 Figure 28: WLAN MAC Architecture ................................................................................................................ 73 Figure 29: WLAN PHY Block Diagram............................................................................................................. 77 Figure 30: Radio Functional Block Diagram .................................................................................................... 79 Figure 31: 140-Ball WLBGA Map—Bottom View (Balls Facing Up) ............................................................... 80 Figure 32: Port Locations for Bluetooth Testing............................................................................................. 100 Figure 33: Port Locations for WLAN Testing ................................................................................................. 112 Figure 34: SDIO Bus Timing (Default Mode) ................................................................................................. 139 Figure 35: SDIO Bus Timing (High-Speed Mode).......................................................................................... 141 Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 13 BCM43455 Preliminary Data Sheet List of Figures Figure 36: SDIO Clock Timing (SDR Modes) ................................................................................................ 142 Figure 37: SDIO Bus Input Timing (SDR Modes) .......................................................................................... 143 Figure 38: SDIO Bus Output Timing (SDR Modes up to 100 MHz) ............................................................... 144 Figure 39: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz)..................................................... 144 Figure 40: ∆tOP Consideration for Variable Data Window (SDR 104 Mode) ................................................ 145 Figure 41: SDIO Clock Timing (DDR50 Mode) .............................................................................................. 146 Figure 42: SDIO Data Timing (DDR50 Mode) ............................................................................................... 147 Figure 43: SWD Read and Write Timing........................................................................................................ 150 Figure 44: WLAN = ON, Bluetooth = ON ....................................................................................................... 152 Figure 45: WLAN = OFF, Bluetooth = OFF.................................................................................................... 152 Figure 46: WLAN = ON, Bluetooth = OFF ..................................................................................................... 153 Figure 47: WLAN = OFF, Bluetooth = ON ..................................................................................................... 153 Figure 48: 140-Ball WLBGA Package Mechanical Information ..................................................................... 155 Figure 49: 140-Balls WLBGA Keep-out Areas for PCB Layout—Top View with Balls Facing Down ............ 156 Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 14 BCM43455 Preliminary Data Sheet List of Tables List of Tables Table 1: Power-Up/Power-Down/Reset Control Signals.................................................................................. 28 Table 2: Crystal Oscillator and External Clock—Requirements and Performance ......................................... 30 Table 3: External 32.768 kHz Sleep Clock Specifications ............................................................................... 33 Table 4: Power Control Pin Description ........................................................................................................... 41 Table 5: SPI-to-UART Signal Mapping ............................................................................................................ 47 Table 6: PCM Interface Timing Specifications (Short Frame Sync, Master Mode).......................................... 50 Table 7: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)............................................ 51 Table 8: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) .......................................... 52 Table 9: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) ............................................ 53 Table 10: PCM Burst Mode (Receive Only, Short Frame Sync) ...................................................................... 54 Table 11: PCM Burst Mode (Receive Only, Long Frame Sync) ...................................................................... 55 Table 12: Example of Common Baud Rates.................................................................................................... 56 Table 13: UART Timing Specifications ............................................................................................................ 57 Table 14: Timing for I2S Transmitters and Receivers ...................................................................................... 58 Table 15: 3-Wire External Coexistence Interface ............................................................................................ 66 Table 16: SDIO Pin Description ....................................................................................................................... 69 Table 17: WLBGA Pin List by Pin Number ...................................................................................................... 81 Table 18: WLBGA Pin List by Pin Name.......................................................................................................... 83 Table 19: Signal Descriptions .......................................................................................................................... 85 Table 20: Strapping Options ............................................................................................................................ 91 Table 21: GPIO Multiplexing Matrix ................................................................................................................. 92 Table 22: Multiplexed GPIO Signals ................................................................................................................ 93 Table 23: I/O States ......................................................................................................................................... 94 Table 24: Absolute Maximum Ratings ............................................................................................................. 97 Table 25: Environmental Ratings ..................................................................................................................... 98 Table 26: ESD Specifications .......................................................................................................................... 98 Table 27: Recommended Operating Conditions and DC Characteristics ........................................................ 99 Table 28: Bluetooth Receiver RF Specifications............................................................................................ 101 Table 29: Bluetooth Transmitter RF Specifications....................................................................................... 104 Table 30: Local Oscillator Performance......................................................................................................... 106 Table 31: BLE RF Specifications ................................................................................................................... 106 Table 32: FM Receiver Specifications ........................................................................................................... 107 Table 33: 2.4 GHz Band General RF Specifications...................................................................................... 113 Table 34: WLAN 2.4 GHz Receiver Performance Specifications .................................................................. 113 Table 35: WLAN 2.4 GHz Transmitter Performance Specifications .............................................................. 117 Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 15 BCM43455 Preliminary Data Sheet List of Tables Table 36: WLAN 5 GHz Receiver Performance Specifications ..................................................................... 118 Table 37: WLAN 5 GHz Transmitter Performance Specifications ................................................................. 124 Table 38: Recommended Spectrum Analyzer Settings ................................................................................. 125 Table 39: 2.4 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications ........................ 126 Table 40: 5 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications ........................... 127 Table 41: 5 GHz Band, 40 MHz Channel Spacing TX Spurious Emissions Specifications ........................... 128 Table 42: 5 GHz Band, 80 MHz Channel Spacing TX Spurious Emissions Specifications ........................... 129 Table 43: 2G and 5G General Receiver Spurious Emissions ........................................................................ 129 Table 44: Core Buck Switching Regulator (CBUCK) Specifications .............................................................. 130 Table 45: LDO3P3 Specifications .................................................................................................................. 131 Table 46: BTLDO2P5 Specifications ............................................................................................................. 132 Table 47: CLDO Specifications ...................................................................................................................... 133 Table 48: LNLDO Specifications .................................................................................................................... 134 Table 49: PCIe LDO Specifications ............................................................................................................... 135 Table 50: 2.4 GHz Mode WLAN Power Consumption ................................................................................... 136 Table 51: 5 GHz Mode WLAN Power Consumption ...................................................................................... 137 Table 52: Bluetooth and BLE Current Consumption...................................................................................... 138 Table 53: SDIO Bus Timing Parameters (Default Mode)............................................................................... 139 Table 54: SDIO Bus Timing Parameters (High-Speed Mode)....................................................................... 141 Table 55: SDIO Bus Clock Timing Parameters (SDR Modes) ....................................................................... 142 Table 56: SDIO Bus Input Timing Parameters (SDR Modes) ........................................................................ 143 Table 57: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz)............................................. 144 Table 58: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) .................................. 145 Table 59: SDIO Bus Clock Timing Parameters (DDR50 Mode) .................................................................... 146 Table 60: SDIO Bus Timing Parameters (DDR50 Mode) .............................................................................. 147 Table 61: PCI Express Interface Parameters ................................................................................................ 148 Table 62: JTAG Timing Characteristics ......................................................................................................... 150 Table 63: SWD Read and Write Timing Parameters ..................................................................................... 150 Table 64: Package Thermal Characteristics .................................................................................................. 154 Table 65: Part Ordering Information .............................................................................................................. 157 Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 16 BCM43455 Preliminary Data Sheet About This Document About This Document Purpose and Audience This data sheet provides details on the functional, operational, and electrical characteristics for the Broadcom® BCM43455. It is intended for hardware design, application, and OEM engineers. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: http://www.broadcom.com/press/glossary.php. Document Conventions The following conventions may be used in this document: Convention Description Bold User input and actions: for example, type exit, click OK, press ALT+C Monospace Code: #include <iostream> HTML: <td rowspan = 3> Command line commands and parameters: wl [-l] <command> <> Placeholders for required elements: enter your <username> or wl <command> [] Indicates optional command-line parameters: wl [-l] Indicates bit and byte ranges (inclusive): [0:3] or [7:0] References The references in this section may be used in conjunction with this document. Note: Broadcom provides customer access to technical documentation and software through its Customer Support Portal (CSP) and Downloads & Support site (see Technical Support). For Broadcom documents, replace the “xx” in the document number with the largest number available in the repository to ensure that you have the most current version of the document. Document (or Item) Name Number Source [1] Bluetooth MWS Coexistence 2-wire Transport Interface – Specification [2] PCI Bus Local Bus Specification, Revision 2.3 – www.pcisig.com [3] PCIe Base Specification Version 1.1 – www.pcisig.com Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL www.bluetooth.com Page 17 BCM43455 Preliminary Data Sheet Technical Support Technical Support Broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates through its customer support portal (https://support.broadcom.com). For a CSP account, contact your Sales or Engineering support representative. In addition, Broadcom provides other product support through its Downloads & Support site (http://www.broadcom.com/support/). Broadcom® November 5, 2015 • 43455-DS109-R BROADCOM CONFIDENTIAL Page 18 BCM43455 Preliminary Data Sheet BCM43455 Overview Section 1: BCM43455 Overview Overview The Broadcom BCM43455 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.1 a/b/g/n/ac MAC/baseband/radio, Bluetooth 4.1 + EDR (enhanced data rate), and FM receiver. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. Comprehensive power management circuitry and software ensure the system can meet the needs of highly mobile devices that require minimal power consumption and reliable operation. Figure 2 on page 20 shows the interconnect of all the major physical blocks in the BCM43455 and their associated external interfaces, which are described in greater detail in the following sections. Broadcom® November 5, 2015 • 43455-DS109-R Page 19 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Overview Figure 2: BCM43455 Block Diagram SECI UART and GCI GPIOs GCI UART Port Control BT_HOST_WAKE BT_DEV_WAKE UART USB 1.1 PCM I2S Other GPIOs RAM ROM VBAT TCM RAM 800 KB ROM 704 KB PCM ARMCM3 ARMCR4 USB AHB Bus Matrix WLAN Master Slave DMA JTAG Master GPIO Timers WD Pause WLAN BT Access SDIOD AXI2ANB AHB2AXI SDIO 3.0 PCIE Chip Common (OTP) RX/TX PCIE AXI2APB BLE LCU AHB2APB PMU WLAN RAM Sharing I2S Registers WL_REG_ON BT_REG_ON WL_HOST_WAKE UART WL_DEV_WKAE JTAG Other GPIOs WLAN NIC-301 AXI Backplane BTFM APU BlueRF GCI Coex I/F DOT11MAC (D11) Shared LNA Control and Other Coex I/F 1×1 IEEE 802.11ac PHY (Rev. 4) RF Switch Controls Modem FM Analog Audio FM RX 32 kHz External LPO BT RF 2.4 GHz/5 GHz TINY Radio CLB XTAL BT PA 5 GHz PA Driver Shared 2.4 LNA LNA LNA 5 GHz PA L L 2.4 GHz PA WLAN: 5 GHz: iPA, iLNA, eLG, eTR 2 GHz: iPA, iLNA, eLG, iTR BT: Shared LNA, iTR eTR Diplexer Broadcom® November 5, 2015 • 43455-DS109-R Page 20 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Standards Compliance Standards Compliance The BCM43455 supports the following standards: • Bluetooth 2.1 + EDR • Bluetooth 3.0 • Bluetooth 4.1 (Bluetooth Low Energy) • IEEE 802.11ac single-stream mandatory and optional requirements for 20, 40, and 80 MHz channels • IEEE 802.11n (Handheld Device Class, Section 11) • IEEE 802.11a • IEEE 802.11b • IEEE 802.11g • IEEE 802.11d • IEEE 802.11h • IEEE 802.11i • Security: – WEP – WPA Personal – WPA2 Personal – WMM – WMM-PS (U-APSD) – WMM-SA – AES (hardware accelerator) – TKIP (hardware accelerator) – CKIP (software support) • Proprietary protocols: – CCXv2 – CCXv3 – CCXv4 – CCXv5 – WFAEC • IEEE 802.15.2 Coexistence Compliance (on-silicon solution compliant with IEEE 3-wire requirements) The BCM43455 supports the following future drafts/standards: • IEEE 802.11r (fast roaming between APs) • IEEE 802.11w (secure management frames) Broadcom® November 5, 2015 • 43455-DS109-R Page 21 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet • Mobile Phone Usage Model IEEE 802.11 Extensions: – IEEE 802.11e QoS Enhancements (as per the WMM specification is already supported) – IEEE 802.11h 5 GHz Extensions – IEEE 802.11i MAC Enhancements – IEEE 802.11k Radio Resource Measurement Mobile Phone Usage Model The BCM43455 incorporates a number of unique features to simplify integration into mobile phone platforms. Its flexible PCM and UART interfaces enable it to transparently connect with the existing circuits. In addition, the TCXO and LPO inputs allow the use of existing handset features to further minimize the size, power, and cost of the complete system. • The PCM interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. • The UART interface supports hardware flow control with tight integration to power control sideband signaling to support the lowest power operation. • The crystal oscillator interface accommodates any of the typical reference frequencies used by cell phones. • FM digital interfaces can use either I2S or PCM. • The highly linear design of the radio transceiver ensures that the device has the lowest spurious emissions output regardless of the state of operation. It has been fully characterized in the global cellular bands. • The transceiver design has excellent blocking and intermodulation performance in the presence of a cellular transmission (LTE, GSM, GPRS, CDMA, WCDMA, or iDEN). The BCM43455 is designed to directly interface with new and existing handset designs. Broadcom® November 5, 2015 • 43455-DS109-R Page 22 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Power Supplies and Power Management Section 2: Power Supplies and Power Management Power Supply Topology One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the BCM43455. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth, and WLAN functions in embedded designs. A single VBAT (3.0V to 5.25V DC max.) and VIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the BCM43455. Two control signals, BT_REG_ON and WL_REG_ON, are used to power-up the regulators and take the respective section out of reset. The CBUCK CLDO and LNLDO power-up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO may be turned off/on based on the dynamic demands of the digital baseband. The BCM43455 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, the LPLDO1 (which is the low-power linear regulator that is supplied by the system VIO supply) provides the BCM43455 with all required voltage, further reducing leakage currents. BCM43455 PMU Features • VBAT to 1.35Vout (170 mA nominal, 600 mA maximum) Core-Buck (CBUCK) switching regulator • VBAT to 3.3Vout (200 mA nominal, 450 mA–850 mA maximum) LDO3P3 • VBAT to 2.5Vout (15 mA nominal, 70 mA maximum) BTLDO2P5 • 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO • 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep-sleep • 1.35V to 1.2Vout (35 mA nominal, 55 mA maximum) LDO for PCIE • Additional internal LDOs (not externally accessible) • PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. Broadcom® November 5, 2015 • 43455-DS109-R Page 23 BROADCOM CONFIDENTIAL BCM43455 PMU Features BCM43455 Preliminary Data Sheet Figure 3 and Figure 4 on page 25 show the regulators and a typical power topology. Figure 3: Typical Power Topology (Page 1 of 2) WL RF - BCM43455 Shaded areas are internal to the device. Internal LNLDO 80 mA 1.2V Internal LNLDO 10 mA 1.2V Internal VCOLDO 80 mA 1.2V Internal LNLDO 80 mA 1.2V Internal LNLDO 10 mA 1.2V XTAL LDO 30 mA 1.2V TX MIXER and PA (not all versions) WL RF - LOGEN WL RF – LNA WL RF – AFE and TIA WL RF – TX WL RF – ADC REF WL RF – XTAL VBAT 2.2 µH 0806 CORE BUCK WL_REG_ON BT_REG_ON REGULATOR CBUCK Max 600 mA Avg 170 mA 1.35V LPLDO1 3 mA 1.1V LNLDO 100 mA 0603 4.7 µF 0402 GND VDDIO 1 µF 0402 1.2V WL RF – RFPLL PFD and MMD BT RF 2.2 µF 0402 0.1 µF 0201 PCIe LDO Max 55 mA Avg 35 mA (bypass/off in deepsleep) 1.2V PCIE PLL, RXTX 0.47 µF 0201 WL BBPLL/DFLL WLAN/BT/CLB/Top, Always ON CLDO Max 200 mA Avg 80 mA (bypass in deep sleep) 1.3V- 1.2V- 0.95V (AVS) WL OTP WL PHY 4.7 µF 0402 WL Subcore WL VDDM (SRAMs + AOS) BT VDDM BT Digital Power switch No power switch Broadcom® November 5, 2015 • 43455-DS109-R Page 24 BROADCOM CONFIDENTIAL BCM43455 PMU Features BCM43455 Preliminary Data Sheet Figure 4: Typical Power Topology (Page 2 of 2) BCM43455 Shaded areas are internal to the device. BTLDO2P5 Max 70 mA Avg 15 mA 2.5V BT CLASS 1 PA 2.2 µF 0402 10 pF 0201 WL RF – PA (2.4 GHz, 5 GHz) VBAT LDO3P3 Spike 800 mA Max 450 mA Avg 200 mA WL RF – PAD (2.4 GHz, 5 GHz) 3.3V VDDIO_RF 4.7 µF 0402 WL OTP 3.3V 2.5V Internal LNLDO 10 mA 2.5V Internal LNLDO 25 mA 2.5V Internal LNLDO 8 mA 2.5V WL RF – RX, TX, NMOS miniPMU LDOs 2.5V WL RF – VCO 2.5V Power switch No power switch WL RF – CP No dedicated power switch, but internal power-down modes and block-specific power switches. Broadcom® November 5, 2015 • 43455-DS109-R Page 25 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN Power Management WLAN Power Management The BCM43455 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43455 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the BCM43455 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the BCM43455 into various power management states appropriate to the current environment and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, freerunning counters (running at 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. The BCM43455 WLAN power states are described as follows: • Active mode— All WLAN blocks in the BCM43455 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. • Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the BCM43455 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator or TCXO) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake-up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. • Deep-sleep mode—Most of the chip including both analog and digital domains and most of the regulators are powered off. Logic states in the digital core are saved and preserved into a retention memory in the always-ON domain before the digital core is powered off. Upon a wake-up event triggered by the PMU timers, an external interrupt or a host resume through the PCIe bus, logic states in the digital core are restored to their pre-deep-sleep settings to avoid lengthy HW reinitialization. • Power-down mode—The BCM43455 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. PMU Sequencing The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. Resource requests may derive from several sources: clock requests from cores, the minimum resources defined in the ResourceMin register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. Broadcom® November 5, 2015 • 43455-DS109-R Page 26 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Power-Off Shutdown Each resource is in one of four states: • enabled • disabled • transition_on • transition_off The timer contains 0 when the resource is enabled or disabled and a non-zero value in the transition states. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. During each clock cycle, the PMU sequencer performs the following actions: • Computes the required resource set based on requests and the resource dependency table. • Decrements all timers whose values are non zero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. • Compares the request with the current resource status and determines which resources must be enabled or disabled. • Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered up dependents. • Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. Power-Off Shutdown The BCM43455 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the BCM43455 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the BCM43455 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. During a low-power shutdown state, provided VDDIO remains applied to the BCM43455, all outputs are tristated, and most inputs signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the BCM43455 to be fully integrated in an embedded device and take full advantage of the lowest power-savings modes. When the BCM43455 is powered on from this state, it is the same as a normal power-up and the device does not retain any information about its state from before it was powered down. Broadcom® November 5, 2015 • 43455-DS109-R Page 27 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Power-Up/Power-Down/Reset Circuits Power-Up/Power-Down/Reset Circuits The BCM43455 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 21: “Power-Up Sequence and Timing,” on page 151. Table 1: Power-Up/Power-Down/Reset Control Signals Signal Description WL_REG_ON This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM43455 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal BCM43455 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has an internal 200 k pull-down resistor that is enabled by default. It can be disabled through programming. Broadcom® November 5, 2015 • 43455-DS109-R Page 28 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Frequency References S e c t i o n 3 : F re q u e n c y R e f e r e n c e s An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference may be used. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. Crystal Interface and Clock Generation The BCM43455 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator including all external components is shown in Figure 5. Consult the reference schematics for the latest configuration. Figure 5: Recommended Oscillator Configuration C WRF_XTAL_XOP 27 pF 37.4 MHz C x ohms WRF_XTAL_XON 27 pF Note: A reference schematic is available for further details. Contact your Broadcom FAE. A fractional-N synthesizer in the BCM43455 generates the radio frequencies, clocks, and data/packet timing, enabling it to operate using a wide selection of frequency references. The recommended default frequency reference is a 37.4 MHz crystal. The signal characteristics for the crystal interface are listed in Table 2 on page 30. Note: Although the fractional-N synthesizer can support alternative reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Broadcom for further details. Broadcom® November 5, 2015 • 43455-DS109-R Page 29 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet External Frequency Reference External Frequency Reference As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the Phase Noise requirements listed in Table 2. If used, the external clock should be connected to the WRF_XTAL_XOP pin through an external 1000 pF coupling capacitor, as shown in Figure 6. The internal clock buffer connected to this pin will be turned OFF when the BCM43455 goes into sleep mode. When the clock buffer turns ON and OFF there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin. Figure 6: Recommended Circuit to Use With an External Reference Clock 1000 pF Reference Clock WRF_XTAL_XOP NC WRF_XTAL_XON Table 2: Crystal Oscillator and External Clock—Requirements and Performance Crystala External Frequency Referenceb c Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Units Frequency 2.4G and 5G bands, IEEE 802.11ac operation 35 – 52 – 52 – MHz Frequency 5G Band, IEEE 802.11n operation only 19 – 52 35 – 52 MHz 2.4G band IEEE 802.11n Between 19 MHz and 52 MHz d, e operation, and both bands legacy IEEE 802.11a/b/g operation only Frequency tolerance Without trimming over the lifetime of the equipment, including temperaturef –20 – 20 –20 – 20 ppm Crystal load capacitance – – 16 – – – – pF ESR – – – 60 – – – Ω Drive level External crystal must be able to tolerate this drive level. 200 – – – – – μW Input impedance Resistive (WRF_XTAL_XOP) Capacitive WRF_XTAL_XOP Input low level DC-coupled digital signal – – – 30k 100k – Ω – – 7.5 – – 7.5 pF – – – 0 – 0.2 V Broadcom® November 5, 2015 • 43455-DS109-R Page 30 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet External Frequency Reference Table 2: Crystal Oscillator and External Clock—Requirements and Performance (Cont.) Crystala External Frequency Referenceb c Parameter Conditions/Notes Min. Typ. Max. Min. Typ. Max. Units WRF_XTAL_XOP Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_XOP input voltage (see Figure 6 on page 30) IEEE 802.11a/b/g operation only – – – 400 – 1200 mVp-p WRF_XTAL_XOP input voltage (see Figure 6 on page 30) IEEE 802.11n/ac AC-coupled analog input – – – 1 – – Vp-p Duty cycle 37.4 MHz clock – – – 40 50 60 % Phase (IEEE 802.11b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Phase Noiseg (IEEE 802.11a) 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz Phase Noiseg (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Phase Noiseg (IEEE 802.11n, 5 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz Phase Noiseg (IEEE 802.11ac, 5 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –148 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –155 dBc/Hz Noiseg a. (Crystal) Use WRF_XTAL_XON and WRF_XTAL_XOP. b. See “External Frequency Reference” on page 30 for alternative connection methods. c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto-detected frequency using the LPO clock. e. The frequency step size is approximately 80 Hz resolution. f. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. g. Assumes that external clock has a flat phase noise response above 100 kHz. Broadcom® November 5, 2015 • 43455-DS109-R Page 31 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Frequency Selection Frequency Selection Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard handset reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, 38.4, and 52 MHz, but also other frequencies in this range, with approximately 80 Hz resolution. The BCM43455 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency. Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. Contact Broadcom for further details. The reference frequency for the BCM43455 may be set in the following ways: • Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. • Auto-detect any of the standard handset reference frequencies using an external LPO clock. For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard frequencies commonly used, the BCM43455 automatically detects the reference frequency and programs itself to the correct reference frequency. In order for auto frequency detection to work correctly, the BCM43455 must have a valid and stable 32.768 kHz LPO clock that meets the requirements listed in Table 3 on page 33 and is present during power-on reset. Broadcom® November 5, 2015 • 43455-DS109-R Page 32 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet External 32.768 kHz Low-Power Oscillator External 32.768 kHz Low-Power Oscillator The BCM43455 uses a secondary low frequency clock for low-power-mode timing. Either the internal lowprecision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake-up earlier to avoid missing beacons. Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 3. Table 3: External 32.768 kHz Sleep Clock Specifications Parameter LPO Clock Units Nominal input frequency 32.768 kHz Frequency accuracy ±200 ppm Duty cycle 30–70 % Input signal amplitude 200–3300 mV, p-p Signal type Square-wave or sine-wave – >100k <5 Ω pF <10,000 ppm Input impedancea Clock jitter (during initial start-up) a. When power is applied or switched off. Broadcom® November 5, 2015 • 43455-DS109-R Page 33 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth and FM Subsystem Overview Section 4: Bluetooth and FM Subsystem Overview The BCM43455 is a Bluetooth 4.1 + EDR-compliant, baseband processor with 2.4 GHz transceiver with an integrated FM/RDS/RBDS receiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus FM radio solution. The BCM43455 is the optimal solution for any Bluetooth voice and/or data application that also requires an FM radio receiver. The Bluetooth subsystem presents a standard host controller interface (HCI) via a high-speed UART and PCM for audio. The FM subsystem supports the HCI control interface, analog output, as well as I2S and PCM interfaces. The BCM43455 incorporates all Bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume. The BCM43455 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. It provides full radio compatibility to operate simultaneously with GPS, WLAN, and cellular radios. The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability. Features Primary BCM43455 Bluetooth features include: • Supports key features of upcoming Bluetooth standards • Fully supports Bluetooth Core Specification version 4.1 + EDR features: – Adaptive frequency hopping (AFH) – Quality of service (QoS) – Extended synchronous connections (eSCO)—voice connections – Fast connect (interlaced page and inquiry scans) – Secure simple pairing (SSP) – Sniff subrating (SSR) – Encryption pause resume (EPR) – Extended inquiry response (EIR) – Link supervision timeout (LST) • UART baud rates up to 4 Mbps • Supports all Bluetooth 4.1 + HS packet types • Supports maximum Bluetooth data rates over HCI UART • Multipoint operation with up to seven active slaves – Maximum of seven simultaneous active ACL links – Maximum of three simultaneous active SCO and eSCO connections with scatternet support Broadcom® November 5, 2015 • 43455-DS109-R Page 34 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Features • Trigger Broadcom fast connect (TBFC) • Narrowband and wideband packet loss concealment • Scatternet operation with up to four active piconets with background scan and support for scatter mode • High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see “Host Controller Power Management” on page 40) • Channel quality driven data rate and packet type selection • Standard Bluetooth test modes • Extended radio and production test mode features • Full support for power savings modes – Bluetooth clock request – Bluetooth standard sniff – Deep-sleep modes and software regulator shutdown • Supports a low-power crystal, which can be used during power save mode for better timing accuracy. Major FM radio features include: • 65 MHz to 108 MHz FM bands supported (US, Europe, and Japan) • FM subsystem control using the Bluetooth HCI interface • FM subsystem operates from reference clock inputs. • Improved audio interface capabilities with full-featured bidirectional PCM and I2S • I2S can be master or slave. FM receiver-specific features include: • Excellent FM radio performance with 1 μV sensitivity for 26 dB (S + N) ÷ N • Signal-dependent stereo/mono blending • Signal dependent soft mute • Auto search and tuning modes • Audio silence detection • RSSI, IF frequency, status indicators • RDS and RBDS demodulator and decoder with filter and buffering functions • Automatic frequency jump Broadcom® November 5, 2015 • 43455-DS109-R Page 35 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Radio Bluetooth Radio The BCM43455 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality of service. Transmit The BCM43455 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible to the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide Bluetooth class 1 or class 2 operation. Digital Modulator The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and 8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit-synchronization algorithm. Power Amplifier The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. Broadcom® November 5, 2015 • 43455-DS109-R Page 36 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Radio Receiver The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the BCM43455 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. Digital Demodulator and Bit Synchronizer The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. Receiver Signal Strength Indicator The radio portion of the BCM43455 provides a receiver signal strength indicator (RSSI) signal to the baseband, so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. Local Oscillator Generation A local oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The BCM43455 uses an internal RF and IF loop filter. Calibration The BCM43455 radio transceiver features an automated calibration scheme that is fully self contained in the radio. No user interaction is required during normal operation or during manufacturing to provide the optimal performance. Calibration optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment. Broadcom® November 5, 2015 • 43455-DS109-R Page 37 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Baseband Core Section 5: Bluetooth Baseband Core The Bluetooth Baseband Core (BBC) implements all of the time critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air: • Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. • Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. Bluetooth 4.0 Features The BBC supports all Bluetooth 4.0 features, with the following benefits: • Dual-mode Bluetooth Low Energy (BT and BLE operation) • Extended Inquiry Response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode. • Encryption Pause Resume (EPR): Enables the use of Bluetooth technology in a much more secure environment. • Sniff Subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. • Secure Simple Pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required. • Link Supervision Time Out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link time-out supervision. • QoS enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements. Broadcom® November 5, 2015 • 43455-DS109-R Page 38 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth 4.1 Features Bluetooth 4.1 Features The BBC supports all Bluetooth 4.1 features, with the following benefits: • Dual-mode classic Bluetooth and classic low energy (BT and BLE) operation • Low-energy physical layer • Low-energy link layer • Enhancements to HCI for low energy • Low-energy direct test mode • 128 AES-CCM secure connection for both BT and BLE Note: The BCM43455 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. Bluetooth Low Energy The BCM43455 supports the Bluetooth Low Energy operating mode. Link Control Layer The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth Link Controller. • Major states: – Standby – Connection • Substates: – Page – Page Scan – Inquiry – Inquiry Scan – Sniff Broadcom® November 5, 2015 • 43455-DS109-R Page 39 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Test Mode Support Test Mode Support The BCM43455 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. In addition to the standard Bluetooth Test Mode, the BCM43455 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include: • Fixed frequency carrier wave (unmodulated) transmission – Simplifies some type-approval measurements (Japan) – Aids in transmitter performance analysis • Fixed frequency constant receiver mode – Receiver output directed to I/O pin – Allows for direct BER measurements using standard RF test equipment – Facilitates spurious emissions testing for receive mode • Fixed frequency constant transmission – 8-bit fixed pattern or PRBS-9 – Enables modulated signal measurements with standard RF test equipment Bluetooth Power Management Unit The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the BCM43455 are: • RF Power Management • Host Controller Power Management • “BBC Power Management” on page 43 • “FM Over Bluetooth” on page 44 RF Power Management The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly. Host Controller Power Management When running in UART mode, the BCM43455 may be configured so that dedicated signals are used for power management hand-shaking between the BCM43455 and the host. The basic power saving functions supported by those hand-shaking signals include the standard Bluetooth defined power savings modes and standby modes of operation. Table 4 on page 41 describes the power-control handshake signals used with the UART interface. Broadcom® November 5, 2015 • 43455-DS109-R Page 40 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Power Management Unit Note: Pad function Control Register is set to 0 for these pins. See “DC Characteristics” on page 97 for more details. Table 4: Power Control Pin Description Signal Mapped to Pin Type Description BT_DEV_WAKE BT_GPIO_0 I Bluetooth device wake-up: Signal from the host to the BCM43455 indicating that the host requires attention. • Asserted: The Bluetooth device must wake-up or remain awake. • Deasserted: The Bluetooth device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. BT_HOST_WAKE BT_GPIO_1 O Host wake-up. Signal from the BCM43455 to the host indicating that the BCM43455 requires attention. • Asserted: host device must wake-up or remain awake. • Deasserted: host device may sleep when sleep criteria are met. The polarity of this signal is software configurable and can be asserted high or low. BT_CLK_REQ BT_CLK_REQ_OUT WL_CLK_REQ_OUT O The BCM43455 asserts BT_CLK_REQ when Bluetooth or WLAN wants the host to turn on the reference clock. The BT_CLK_REQ polarity is active-high. Add an external 100 kΩ pull-down resistor to ensure the signal is deasserted when the BCM43455 powers up or resets when VDDIO is present. Broadcom® November 5, 2015 • 43455-DS109-R Page 41 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Power Management Unit Figure 7 shows the startup signaling sequence prior to software download. Figure 7: Startup Signaling Sequence Prior to Software Download LPO Host IOs unconfigured VDDIO Host IOs configured T1 HostResetX BT_DEV_WAKE T2 BTH IOs unconfigured BTH IOs configured BT_REG_ON T3 BT_HOST_WAKE BT_UART_CTS_N Host side drives this line low BT_UART_RTS_N T4 CLK_REQ_OUT T5 BTH device drives this line low indicating transport is ready Driven Pulled Notes : T1 is the time for Host to settle it’s IOs after a reset. T2 is the time for Host to drive BT_REG_ON high after the Host IOs are configured. T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has elapsed. T4 is the time for BTH device to drive BT_UART_RTS_N low after the Host drives BT_UART_CTS_N low. This assumes the BTH device has already completed initialization. T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for designs that use an external reference clock source from the Host. This pin is irrelevant for Crystal reference clock based designs where the BTH device generates it’s own reference clock from an external crystal connected to it’s oscillator circuit. Timing diagram assumes VBAT is present. Broadcom® November 5, 2015 • 43455-DS109-R Page 42 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Power Management Unit BBC Power Management The following are low-power operations for the BBC: • Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets. • Bluetooth-specified low-power connection modes: sniff, hold, and park. While in these modes, the BCM43455 runs on the low-power oscillator and wakes up after a predefined time period. • A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. When the BCM43455 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the BCM43455 to effectively be off while keeping the I/O pins powered so they do not draw extra current from any other devices connected to the I/O. During the low-power shutdown state, provided VDDIO remains applied to the BCM43455, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the BCM43455 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. Two BCM43455 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the BCM43455 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. Wideband Speech The BCM43455 provides support for wideband speech (WBS) using on-chip Broadcom SmartAudio® technology. The BCM43455 can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 Kbps rate) transferred over the PCM bus. Packet Loss Concealment Packet Loss Concealment (PLC) improves apparent audio quality for systems with marginal link performance. Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several ways: • Fill in zeros. • Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets). • Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). These techniques cause distortion and popping in the audio stream. The BCM43455 uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality. Figure 8 and Figure 9 on page 44 show audio waveforms with and without Packet Loss Concealment. Broadcom PLC/BEC algorithms also support wideband speech. Broadcom® November 5, 2015 • 43455-DS109-R Page 43 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Power Management Unit Figure 8: CVSD Decoder Output Waveform Without PLC Packet Loss Causes Ramp-down Figure 9: CVSD Decoder Output Waveform After Applying PLC Audio Rate-Matching Algorithms The BCM43455 has an enhanced rate-matching algorithm that uses interpolation algorithms to reduce audio stream jitter that may be present when the rate of audio data coming from the host is not the same as the Bluetooth audio data rates. Codec Encoding The BCM43455 can support SBC and mSBC encoding and decoding for wideband speech. Multiple Simultaneous A2DP Audio Stream The BCM43455 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend. FM Over Bluetooth FM Over Bluetooth enables the BCM43455 to stream data from FM over Bluetooth without requiring the host to be awake. This can significantly extend battery life for usage cases where someone is listening to FM radio on a Bluetooth headset. Burst Buffer Operation The BCM43455 has a data buffer that can buffer data being sent over the HCI and audio transports, then send the data at an increased rate. This mode of operation allows the host to sleep for the maximum amount of time, dramatically reducing system current consumption. Broadcom® November 5, 2015 • 43455-DS109-R Page 44 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Adaptive Frequency Hopping Adaptive Frequency Hopping The BCM43455 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map. Advanced Bluetooth/WLAN Coexistence The BCM43455 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo. Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also supported. The BCM43455 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception. The BCM43455 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement. The BCM43455 also supports Transmit Power Control on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including nonWLAN 2.4 GHz interference). The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information. Fast Connection (Interlaced Page and Inquiry Scans) The BCM43455 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures. Broadcom® November 5, 2015 • 43455-DS109-R Page 45 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Microprocessor and Memory Unit for Bluetooth Section 6: Microprocessor and Memory Unit for Bluetooth The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICERT debug and JTAG interface units. It runs software from the link control (LC) layer, up to the host controller interface (HCI). The ARM core is paired with a memory unit that contains 845 KB of ROM memory for program storage and boot ROM, 270 KB of RAM for data scratchpad and patch RAM code. The internal ROM allows for flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory. External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or features additions. These patches may be downloaded from the host to the BCM43455 through the UART transports. The mechanism for downloading via UART is identical to the proven interface of the BCM4329 and BCM4330 devices. RAM, ROM, and Patch Memory The BCM43455 Bluetooth core has 270 KB of internal RAM which is mapped between general purpose scratch pad memory and patch memory and 845 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory capability enables the addition of code changes for purposes of feature additions and bug fixes to the ROM memory. Reset The BCM43455 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes High. If BT_REG_ON is low, then the POR circuit is held in reset. Broadcom® November 5, 2015 • 43455-DS109-R Page 46 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth Peripheral Transport Unit Section 7: Bluetooth Peripheral Transport Unit SPI Interface The BCM43455 supports a slave SPI HCI transport with an input clock range of up to 16 MHz. Higher clock rates can be possible. The physical interface between the SPI master and the BCM43455 consists of the four SPI signals (SPI_CSB, SPI_CLK, SPI_SI, and SPI_SO) and one interrupt signal (SPI_INT). The SPI signals are muxed onto the UART signals (see Table 5). The BCM43455 can be configured to accept active-low or activehigh polarity on the SPI_CSB chip select signal. It can also be configured to drive an active-low or active-high SPI_INT interrupt signal. Bit ordering on the SPI_SI and SPI_SO data lines can be configured as either littleendian or big-endian. Additionally, proprietary sleep mode and half-duplex handshaking is implemented between the SPI master and the BCM43455. The SPI_INT is required to negotiate the start of a transaction. The SPI interface does not require flow control in the middle of a payload. The FIFO is large enough to handle the largest packet size. Only the SPI master can stop the flow of bytes on the data lines, since it controls SPI_CSB and SPI_CLK. Flow control should be implemented in the higher layer protocols. Table 5: SPI-to-UART Signal Mapping SPI Signals UART Signals SPI_CLK BT_UART_CTS_N SPI_CSB BT_UART_RTS_N SPI_MISO BT_UART_RXD SPI_MOSI BT_UART_TXD SPI_INT BT_HOST_WAKE SPI/UART Transport Detection The BT_HOST_WAKE (BT_GPIO1) pin is also used for BT transport detection. The transport detection occurs during the power-up sequence. It selects either UART or SPI transport operation based on the following pin state: • If the BT_HOST_WAKE (BT_GPIO1) pin is pulled low by an external pull-down during power-up, it selects the SPI transport interface. • If the BT_HOST_WAKE (BT_GPIO1) pin is not pulled low externally during power-up, then the default internal pull-up is detected as a high and it selects the UART transport interface. Broadcom® November 5, 2015 • 43455-DS109-R Page 47 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface PCM Interface The BCM43455 supports two independent PCM interfaces that share the pins with the I2S interfaces. The PCM Interface on the BCM43455 can connect to linear PCM Codec devices in master or slave mode. In master mode, the BCM43455 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the BCM43455. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. Slot Mapping The BCM43455 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. Frame Synchronization The BCM43455 supports both short- and long-frame synchronization in both master and slave modes. In shortframe synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Data Formatting The BCM43455 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the BCM43455 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. Broadcom® November 5, 2015 • 43455-DS109-R Page 48 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Wideband Speech Support When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16-bit samples, resulting in a 64 Kbps bit rate. The BCM43455 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 Kbps rate) is transferred over the PCM bus. Multiplexed Bluetooth Over PCM Bluetooth supports multiple audio streams within the Bluetooth channel and both 16 kHz and 8 kHz streams can be multiplexed. This mode of operation is only supported when the Bluetooth host is the master. Figure 10 shows the operation of the multiplexed transport with three simultaneous SCO connections. To accommodate additional SCO channels, the transport clock speed is increased. To change between modes of operation, the transport must be halted and restarted in the new configuration. Figure 10: Functional Multiplex Data Diagram 1 frame BT SCO 1 Rx BT SCO 2 Rx BT SCO 3 Rx BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx PCM_OUT PCM_IN PCM_SYNC CLK PCM_CLK 16 bits per SCO frame Each SCO channel duplicates the data 6 times. Each WBS frame duplicates the data 3 times per frame Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. Broadcom® November 5, 2015 • 43455-DS109-R Page 49 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface PCM Interface Timing Short Frame Sync, Master Mode Figure 11: PCM Timing Diagram (Short Frame Sync, Master Mode) 1 2 3 PC M _B C LK 4 P C M _SY N C 8 H IG H IM PED AN C E PC M _O U T 5 7 6 PC M_IN Table 6: PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 12 2 PCM bit clock LOW 41 – – ns 3 PCM bit clock HIGH 41 – – ns 4 PCM_SYNC delay 0 – 25 ns 5 PCM_OUT delay 0 – 25 ns 6 PCM_IN setup 8 – – ns 7 PCM_IN hold 8 – – ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns Broadcom® November 5, 2015 • 43455-DS109-R MHz Page 50 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Short Frame Sync, Slave Mode Figure 12: PCM Timing Diagram (Short Frame Sync, Slave Mode) 1 2 3 PCM_BCLK 4 5 PCM_SYNC 9 PCM_OUT HIGH IMPEDANCE 6 8 7 PCM_IN Table 7: PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 12 MHz 2 PCM bit clock LOW 41 – – ns 3 PCM bit clock HIGH 41 – – ns 4 PCM_SYNC setup 8 – – ns 5 PCM_SYNC hold 8 – – ns 6 PCM_OUT delay 0 – 25 ns 7 PCM_IN setup 8 – – ns 8 PCM_IN hold 8 – – ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns Broadcom® November 5, 2015 • 43455-DS109-R Page 51 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Long Frame Sync, Master Mode Figure 13: PCM Timing Diagram (Long Frame Sync, Master Mode) 1 2 3 PCM_BCLK 4 PCM_SYNC 8 PCM_OUT Bit 0 Bit 1 Bit 0 Bit 1 HIGH IMPEDANCE 5 6 PCM_IN 7 Table 8: PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 12 MHz 2 PCM bit clock LOW 41 – – ns 3 PCM bit clock HIGH 41 – – ns 4 PCM_SYNC delay 0 – 25 ns 5 PCM_OUT delay 0 – 25 ns 6 PCM_IN setup 8 – – ns 7 PCM_IN hold 8 – – ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns Broadcom® November 5, 2015 • 43455-DS109-R Page 52 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Long Frame Sync, Slave Mode Figure 14: PCM Timing Diagram (Long Frame Sync, Slave Mode) 1 2 3 PC M _BC LK 4 5 PCM_SYNC 9 B it 0 PC M _O U T H IG H IM P E D A N C E B it 1 6 8 7 P C M _ IN B it 0 B it 1 Table 9: PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – 12 2 PCM bit clock LOW 41 – – ns 3 PCM bit clock HIGH 41 – – ns 4 PCM_SYNC setup 8 – – ns 5 PCM_SYNC hold 8 – – ns 6 PCM_OUT delay 0 – 25 ns 7 PCM_IN setup 8 – – ns 8 PCM_IN hold 8 – – ns 9 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns Broadcom® November 5, 2015 • 43455-DS109-R – MHz Page 53 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Short Frame Sync, Burst Mode Figure 15: PCM Burst Mode Timing (Receive Only, Short Frame Sync) 1 2 3 PCM_BCLK 4 5 PCM_SYNC 7 6 PCM_IN Table 10: PCM Burst Mode (Receive Only, Short Frame Sync) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 24 MHz 2 PCM bit clock LOW 20.8 – – ns 3 PCM bit clock HIGH 20.8 – – ns 4 PCM_SYNC setup 8 – – ns 5 PCM_SYNC hold 8 – – ns 6 PCM_IN setup 8 – – ns 7 PCM_IN hold 8 – – ns Broadcom® November 5, 2015 • 43455-DS109-R Page 54 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCM Interface Long Frame Sync, Burst Mode Figure 16: PCM Burst Mode Timing (Receive Only, Long Frame Sync) 1 2 3 PCM_BCLK 4 5 PCM_SYNC 7 6 PCM_IN Bit 0 Bit 1 Table 11: PCM Burst Mode (Receive Only, Long Frame Sync) Reference Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 24 MHz 2 PCM bit clock LOW 20.8 – – ns 3 PCM bit clock HIGH 20.8 – – ns 4 PCM_SYNC setup 8 – – ns 5 PCM_SYNC hold 8 – – ns 6 PCM_IN setup 8 – – ns 7 PCM_IN hold 8 – – ns Broadcom® November 5, 2015 • 43455-DS109-R Page 55 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet UART Interface UART Interface The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command. UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the AHB interface through either DMA or the CPU. The UART supports the Bluetooth 4.1 UART HCI specification: H4, a custom Extended H4, and H5. The default baud rate is 115.2 Kbaud. The UART supports the 3-wire H5 UART transport, as described in the Bluetooth specification (Three-wire UART Transport Layer). Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals. The BCM43455 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP). It can also perform wake-on activity. For example, activity on the RX or CTS inputs can wake the chip from a sleep state. Normally, the UART baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The BCM43455 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%. Table 12: Example of Common Baud Rates Desired Rate Actual Rate Error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00 Broadcom® November 5, 2015 • 43455-DS109-R Page 56 BROADCOM CONFIDENTIAL I2S Interface BCM43455 Preliminary Data Sheet Figure 17: UART Timing BT_UART_CTS_N 1 2 BT_UART_TXD Midpoint of STOP bit Midpoint of STOP bit BT_UART_RXD 3 BT_UART_RTS_N Table 13: UART Timing Specifications Ref Characteristics 1 2 3 Min. Typ. Max. Unit Delay time, BT_UART_CTS_N low to BT_UART_TXD valid – – 1.5 Bit periods Setup time, BT_UART_CTS_N high before midpoint of stop – bit – 0.5 Bit periods Delay time, midpoint of stop bit to BT_UART_RTS_N high – 0.5 Bit periods – I2S Interface The BCM43455 supports an I2S digital audio port for Bluetooth audio. The I2S signals are: • I2S clock: I2S SCK • I2S Word Select: I2S WS • I2S Data Out: I2S SDO • I2S Data In: I2S SDI I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the BCM43455 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. The clock rate in master mode is either of the following: 48 kHz x 32 bits per frame = 1.536 MHz 48 kHz x 50 bits per frame = 2.400 MHz The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. Broadcom® November 5, 2015 • 43455-DS109-R Page 57 BROADCOM CONFIDENTIAL I2S Interface BCM43455 Preliminary Data Sheet I2S Timing Note: Timing values specified in Table 14 are relative to high and low threshold levels. Table 14: Timing for I2S Transmitters and Receivers Transmitter Clock Period T Receiver Lower LImit Upper Limit Lower Limit Upper Limit Min. Max. Min. Max. Min. Max. Min. Max. Notes Ttr – – – Tr – – – a Master Mode: Clock generated by transmitter or receiver HIGH tHC 0.35Ttr – – – 0.35Ttr – – – b LOWtLC 0.35Ttr – – – 0.35Ttr – – – b Slave Mode: Clock accepted by transmitter or receiver HIGH tHC – 0.35Ttr – – – 0.35Ttr – – c LOW tLC – 0.35Ttr – – – 0.35Ttr – – c Rise time tRC – – 0.15Ttr – – – – – d Delay tdtr – – – 0.8T – – – – e Hold time thtr 0 – – – – – – – d Setup time tsr – – – – – 0.2Tr – – f Hold time thr – – – – – 0 – – f Transmitter Receiver a. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. d. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. f. The data setup and hold time must not be less than the specified receiver setup and hold time. Broadcom® November 5, 2015 • 43455-DS109-R Page 58 BROADCOM CONFIDENTIAL I2S Interface BCM43455 Preliminary Data Sheet Note: The time periods specified in Figure 18 and Figure 19 are defined by the transmitter speed. The receiver specifications must match transmitter performance. Figure 18: I2S Transmitter Timing T tRC* tLC > 0.35T tHC > 0.35T VH = 2.0V SCK VL = 0.8V thtr > 0 totr < 0.8T SD and WS T = Clock period Ttr = Minimum allowed clock period for transmitter T = Ttr * tRC is only relevant for transmitters in slave mode. Figure 19: I2S Receiver Timing T tLC > 0.35T tHC > 0.35 VH = 2.0V SCK VL = 0.8V tsr > 0.2T thr > 0 SD and WS T = Clock period Tr = Minimum allowed clock period for transmitter T > Tr Broadcom® November 5, 2015 • 43455-DS109-R Page 59 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Subsystem Section 8: FM Receiver Subsystem FM Radio The BCM43455 includes a completely integrated FM radio receiver with RDS/RBDS covering all FM bands from 65 MHz to 108 MHz. The receiver is controlled through commands on the HCI. FM received audio is available in analog form or in digital form through I2S or PCM. The FM radio operates from the external clock reference. Digital FM Audio Interfaces The FM audio can be transmitted via the shared PCM and I2S pins, and the sampling rate is programmable. The BCM43455 supports a three-wire PCM or I2S audio interface in either master or slave configuration. The master or slave configuration is selected using vendor specific commands over the HCI interface. In addition, multiple sampling rates are supported, derived from either the FM or Bluetooth clocks. In master mode, the clock rate is either of the following: • 48 kHz x 32 bits per frame = 1.536 MHz • 48 kHz x 50 bits per frame = 2.400 MHz In slave mode, any clock rate is supported up to a maximum of 3.072 MHz. FM Over Bluetooth The BCM43455 can output received FM audio onto Bluetooth using one of following three links: eSCO, WBS, and A2DP. In all of the above modes, once the link has been set up, the host processor can enter sleep mode while the BCM43455 continues to stream FM audio to the remote Bluetooth device, allowing the system current consumption to be minimized. eSCO In this use case, the stereo FM audio is downsampled to 8 kHz and a mono or stereo stream is then sent through the Bluetooth eSCO link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. Broadcom® November 5, 2015 • 43455-DS109-R Page 60 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Wideband Speech Link Wideband Speech Link In this case, the stereo FM audio is downsampled to 16 kHz and a mono or stereo stream is then sent through the Bluetooth wideband speech link to a remote Bluetooth device, typically a headset. Two Bluetooth voice connections must be used to transport stereo. A2DP In this case, the stereo FM audio is encoded by the on-chip SBC encoder and transported as an A2DP link to a remote Bluetooth device. Sampling rates of 48 kHz, 44.1 kHz, and 32 kHz joint stereo are supported. An A2DP “lite” stack is implemented in the BCM43455 to support this use case, which eliminates the need to route the SBC-encoded audio back to the host to create the A2DP packets. Autotune and Search Algorithms The BCM43455 supports a number of FM search and tune functions that allows the host to implement many convenient user functions, which are accessed through the Broadcom FM stack. • Tune to Play—Allows the FM receiver to be programmed to a specific frequency. • Search for SNR > Threshold—Checks the power level of the available channel and the estimated SNR of the channel to help achieve precise control of the expected sound quality for the selected FM channel. Specifically, the host can adjust its SNR requirements to retrieve a signal with a specific sound quality, or adjust this to return the weakest channels. • Alternate Frequency Jump—Allows the FM receiver to automatically jump to an alternate FM channel that carries the same information, but has a better SNR. For example, when traveling, a user may pass through a region where a number of channels carry the same station. When the user passes from one area to the next, the FM receiver can automatically switch to another channel with a stronger signal to spare the user from having to manually change the channel to continue listening to the same station. Broadcom® November 5, 2015 • 43455-DS109-R Page 61 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Audio Features Audio Features A number of features are implemented in the BCM43455 to provide the best possible audio experience for the user. • Mono/Stereo Blend, Switch, or FME—The BCM43455 provides automatic control of the stereo or mono settings based on the FM signal carrier-to-noise ratio (C/N). This feature is used to maintain the best possible audio SNR based on the FM channel condition. Three modes of operation are supported: – Blend: In this mode, fine control of stereo separation is used to achieve optimal audio quality over a wide range of input C/N. The amount of separation is fully programmable. In Figure 20, the separation is programmed to maintain a minimum 50 dB SNR across the blend range. – Extended blend: In this mode, stereo separation is maximized across a wide range of input CNR. Broadcom static suppression typically gives a static-free user experience to within 3 dB of ultimate sensitivity. – Switch: In this mode, the audio switches from full stereo to full mono at a predetermined level to maintain optimal audio quality. The stereo-to-mono switch point and the mono-to-stereo switch points are fully programmable to provide the desired amount of audio SNR. In Figure 21 on page 63, the switch point is programmed to switch to mono to maintain a 40 dB SNR. – FM enhancement (FME): In this mode, advanced digital signal processing in the FM receiver greatly enhances the stereo separation of the received audio. Traditional FM receivers deliver a full stereo signal at a high carrier-to-noise ratio (CNR) and gradually blend into mono as the CNR drops. The Broadcom stereo extension allows full stereo separation to within 2 dB of the FM receiver sensitivity threshold. The same signal processing delays the onset of pops at the FM sensitivity threshold and reduces the ambient background noise by more than 20 dB in the low CNR region near sensitivity. The result is a low-noise full stereo signal at input RF levels lower than previously achievable. Figure 20: Audio SNR for Blend, Switch, and FME Modes Broadcom® November 5, 2015 • 43455-DS109-R Page 62 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Audio Features Figure 21: Stereo Separation for Blend, Switch, and FME Modes • Soft Mute—Improves the user experience by dynamically muting the output audio proportionate to the FM signal C/N. This prevents the user from being assaulted with a blast of static. The mute characteristic is fully programmable to accommodate fine tuning of the output signal level. An example mute characteristic is shown in Figure 22. Figure 22: Example Soft Mute Characteristic Broadcom® November 5, 2015 • 43455-DS109-R Page 63 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet RDS/RBDS • High Cut—A programmable high-cut filter is provided to reduce the amount of high-frequency noise caused by static in the output audio signal. Like the soft mute circuit, it is fully programmable to allow for any amount of high cut based on the FM signal C/N. • Audio Pause Detect—The FM receiver monitors the magnitude of the audio signal and notifies the host through an interrupt when the magnitude of the signal has fallen below the threshold set for a programmable period. This feature can be used to provide alternate frequency jumps during periods of silence to minimize disturbances to the listener. Filtering techniques are used within the audio pause detection block to provide more robust presence-to-silence detection and silence-to-presence detection. • Automatic Antenna Tuning—The BCM43455 has an on-chip automatic antenna tuning network. When used with a single off-chip inductor, the on-chip circuitry automatically chooses an optimal on-chip matching component to obtain the highest signal strength for the desired frequency. The high-Q nature of this matching network simultaneously provides out-of-band blocking protection as well as a reduction of radiated spurious emissions from the FM antenna. It is designed to accommodate a wide range of external wire antennas. RDS/RBDS The BCM43455 integrates a RDS/RBDS modem and codec, the decoder includes programmable filtering and buffering functions, and the encoder includes the option to encode messages to PS or RT frame format with programmable scrolling in PS mode. The RDS/RBDS data can be read out in receive mode or delivered in transmit mode through either the HCI interface. In addition, the RDS/RBDS functionality supports the following: Receive • Block decoding, error correction and synchronization • Flywheel synchronization feature, allowing the host to set parameters for acquisition, maintenance, and loss of sync. (It is possible to set up the BCM43455 such that synchronization is achieved when a minimum of two good blocks (error free) are decoded in sequence. The number of good blocks required for sync is programmable.) • Storage capability up to 126 blocks of RDS data • Full or partial block B match detect and interrupt to host • Audio pause detection with programmable parameters • Program identification (PI) code detection and interrupt to host • Automatic frequency jump • Block E filtering • Soft mute • Signal dependent mono/stereo blend • Programmable pre-emphasis Broadcom® November 5, 2015 • 43455-DS109-R Page 64 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN Global Functions Section 9: WLAN Global Functions WLAN CPU and Memory Subsystem The BCM43455 WLAN section includes an integrated ARM Cortex-R4 32-bit processor with internal RAM and ROM. The ARM Cortex-R4 is a low-power processor that features low gate count, low interrupt latency, and lowcost debug capabilities. It is intended for deeply embedded applications that require fast interrupt response features. Delivering more than 30% performance gain over ARM7TDMI, the ARM Cortex-R4 implements the ARM v7-R architecture with support for the Thumb-2 instruction set. At 0.19 µW/MHz, the Cortex-R4 is the most power efficient general-purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes. Using multiple technologies to reduce cost, the ARM Cortex-R4 offers improved memory utilization, reduced pin overhead, and reduced silicon area. It supports independent buses for Code and Data access (ICode/DCode and System buses), and extensive debug features including real time trace of program execution. On-chip memory for the CPU includes 800 KB SRAM and 704 KB ROM. One-Time Programmable Memory Various hardware configuration parameters may be stored in an internal 6144-bit (768 bytes) One-Time Programmable (OTP) memory, which is read by the system software after device reset. In addition, customerspecific parameters, including the system vendor ID and the MAC address can be stored, depending on the specific board design. The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Broadcom WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. Prior to OTP programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. GPIO Interface The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the BCM43455 that can be used to connect to various external devices: • WLBGA package – 15 GPIOs Upon power-up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. In addition, the GPIO pins can be assigned to various other functions. Broadcom® November 5, 2015 • 43455-DS109-R Page 65 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet External Coexistence Interface External Coexistence Interface An external handshake interface is available to enable signaling between the device and an external co-located wireless device, such as GPS or LTE to manage wireless medium sharing for optimum performance. Figure 23 shows the WCI-2 LTE coexistence interface. See Table 13: “UART Timing Specifications,” on page 57 for UART baud rate. Figure 23: Broadcom GCI or BT-SIG WCI-2 LTE Coexistence Interface LTE\IC WLAN GCI SECI_OUT/BT_TXD/GPIO5 UART_IN SECI_IN/BT_RXD/GPIO4 UART_OUT BT BCM43455 NOTES: SECI_OUT/BT_TXD and SECI_IN/BT_RXD on the BCM4345X are multiplexed on GPIO5 and GPIO4, respectively. The 2-wire LTE coexistence interface is intended for future compatibility with the BT SIG 2-wire interface that is being standardized for Core 4.1. ORing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by setting the GPIO mask registers appropriately. Figure 24 and Table 15 on page 66 define an alternate 3-wire LTE coexistence interface. Figure 24: 3-Wire LTE Coexistence Interface LTE\IC WLAN ERCX BT GPIO2 ERCX_WL_PRIO GPIO3 ERCX_LTETX GPIO4 ERCX_LTERX BCM43455 Table 15: 3-Wire External Coexistence Interface GPIO Name Coexistence Signal Type Comment GPIO_2 ERCX_WL_PRIO Output Notify LTE of request to sleep GPIO_3 ERCX_LTE_TX Input Notify WLAN RX of requirement to sleep GPIO_4 ERCX_LTE_RX Input Notify WLAN TX to reduce TX power Broadcom® November 5, 2015 • 43455-DS109-R Page 66 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet UART Interface UART Interface A high-speed 4-wire CTS/RTS UART interface can be enabled by software as an alternate function on GPIO pins. Provided primarily for debugging during development, this UART enables the BCM43455 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and provides a FIFO size of 64 × 8 in each direction. JTAG/SWD Interface The BCM43455 supports IEEE 1149.1 JTAG boundary scan and reduced pin-count Serial Wire Debug (SWD) mode to access the chip’s internal blocks and backplane for system bring-up and debugging. This interface allows Broadcom engineers to assist customers with proprietary debug and characterization test tools. It is highly recommended that customers provide access to at least the SWD pins on all PCB designs by using either test points or a header. The SWD interface uses two of the JTAG signals: TMS for bidirectional data (SWDIO) and TCK for the clock (SWCLK). The debug access port (DAP) embedded in the ARM processor supports both SWD and JTAG interfaces and can be switched from one to the other through a specific sequence on the TMS/SWD lines. In addition to the ARM debug interface, an internal JTAG master on the DAP allows access to test access points (TAPs) in the BCM43455 for hardware debugging. Broadcom® November 5, 2015 • 43455-DS109-R Page 67 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN Host Interfaces Section 10: WLAN Host Interfaces SDIO v3.0 All three package options of the BCM43455 WLAN section provide support for SDIO version 3.0, including the new UHS-I modes: • DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). • HS: High speed up to 50 MHz (3.3V signaling). • SDR12: SDR up to 25 MHz (1.8V signaling). • SDR25: SDR up to 50 MHz (1.8V signaling). • SDR50: SDR up to 100 MHz (1.8V signaling). • SDR104: SDR up to 208 MHz (1.8V signaling) • DDR50: DDR up to 50 MHz (1.8V signaling). Note: The BCM43455 is backward compatible with SDIO v2.0 host interfaces. The SDIO interface also has the ability to map the interrupt signal on to a GPIO pin for applications requiring an interrupt different from the one provided by the SDIO interface. The ability to force control of the gated clocks from within the device is also provided. SDIO mode is enabled by strapping options. See Table 20 on page 91 for strapping options. The following three functions are supported: • Function 0 Standard SDIO function (Max BlockSize/ByteCount = 32B) • Function 1 Backplane Function to access the internal system-on-chip (SoC) address space (Max BlockSize/ByteCount = 64B) • Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B). Broadcom® November 5, 2015 • 43455-DS109-R Page 68 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO v3.0 SDIO Pins Table 16: SDIO Pin Description SD 4-Bit Mode SD 1-Bit Mode DATA0 Data line 0 DATA Data line DATA1 Data line 1 or Interrupt IRQ Interrupt DATA2 Data line 2 or Read Wait RW Read Wait DATA3 Data line 3 N/C Not used CLK Clock CLK Clock CMD Command line CMD Command line Figure 25: Signal Connections to SDIO Host (SD 4-Bit Mode) CLK SD Host CMD BCM43455 DAT[3:0] Figure 26: Signal Connections to SDIO Host (SD 1-Bit Mode) CLK CMD SD Host DATA BCM43455 IRQ RW Note: Per Section 6 of the SDIO specification, pull-ups in the 10 kΩ to 100 kΩ range are required on the four DATA lines and the CMD line. This requirement must be met during all operating states either through the use of external pull-up resistors or through proper programming of the SDIO host’s internal pull-ups. Broadcom® November 5, 2015 • 43455-DS109-R Page 69 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCI Express Interface PCI Express Interface The PCI Express (PCIe) core on the BCM43455 is a high-performance serial I/O interconnect that is protocol compliant and electrically compatible with the PCI Express Base Specification v2.0. This core contains all the necessary blocks, including logical and electrical functional subblocks to perform PCIe functionality and maintain high-speed links, using existing PCI system configuration software implementations without modification. Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 27. A configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and reception of System Management Messages by communicating with PCIe layers. Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and BCM43455 device. The transmit side processes outbound packets while the receive side processes inbound packets. Packets are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving device. A header is added at the beginning to indicate the packet type and any other optional fields. Figure 27: PCI Express Layer Model HW/SW Interface HW/SW Interface Transaction Layer Transaction Layer Data Link Layer Data Link Layer Physical Layer Physical Layer Logical Subblock Logical Subblock Electrical Subblock Electrical Subblock TX RX TX RX Broadcom® November 5, 2015 • 43455-DS109-R Page 70 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCI Express Interface Transaction Layer Interface The PCIe core employs a packet-based protocol to transfer data between the host and BCM43455 device, delivering new levels of performance and features. The upper layer of the PCIe is the Transaction Layer. The Transaction layer is primarily responsible for assembly and disassembly of Transaction Layer Packets (TLPs). TLP structure contains header, data payload, and End-to-End CRC (ECRC) fields, which are used to communicate transactions, such as read and write requests and other events. A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with credit-based flow control of TLP, which eliminates wasted link bandwidth due to retries. Data Link Layer The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is to provide reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services provided by the data link layer include data exchange, initialization, error detection and correction, and retry services. Data Link Layer Packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer link management information between data link layers of the two directly connected components on the link, including TLP acknowledgment, power management, and flow control. Physical Layer The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks. Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between the host and BCM43455 device. The transmit section prepares outgoing information passed from the data link layer for transmission, and the receiver section identifies and prepares received information before passing it to the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a specific format. Logical Subblock The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission and identify received data before passing it to the data link layer. Scrambler/Descrambler This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and recovery for testing and debugging purposes. Broadcom® November 5, 2015 • 43455-DS109-R Page 71 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCI Express Interface 8B/10B Encoder/Decoder The PCIe core on the BCM43455 uses an 8b/10b encoder/decoder scheme to provide DC balancing, synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4. Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a 6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are concatenated to form a 10-bit symbol, which is then transmitted serially. Special Symbols are used for link management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished. Elastic FIFO An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique reduces the elastic FIFO size and the average receiver latency by half. Electrical Subblock The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and de-emphasis for best-in-class signal integrity. A de-emphasis technique is employed to reduce the effects of Intersymbol Interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to receive data with acceptable Bit-Error Rate (BER). To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized. Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for maximum interoperability while minimizing the complexity of controlling the de-emphasis values. The highspeed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the receiver. The range of AC capacitance allowed is 75 nF to 200 nF. Configuration Space The PCIe function in the BCM43455 implements the configuration space as defined in the PCI Express Base Specification v2.0. Broadcom® November 5, 2015 • 43455-DS109-R Page 72 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Wireless LAN MAC and PHY S e c t i o n 11 : Wi r e l e s s L A N M A C a n d P H Y IEEE 802.11ac MAC The BCM43455 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without compromising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing synchronization. The architecture diagram of the MAC is shown in Figure 28. The following sections provide an overview of the important modules in the MAC. Figure 28: WLAN MAC Architecture Embedded CPU Interface Host Registers, DMA Engines TX-FIFO (32 KB) PMQ RX-FIFO (10 KB) PSM UCODE PSM Memory IFS Backoff, BTCX WEP TKIP, AES, WAPI TSF SHM BUS IHR NAV EXT- IHR BUS RXE TXE TX A-MPDU RX A-MPDU Shared Memory (6 KB) MAC-PHY Interface Broadcom® November 5, 2015 • 43455-DS109-R Page 73 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet IEEE 802.11ac MAC The BCM43455 WLAN media access controller (MAC) supports features specified in the IEEE 802.11 base standard, and amended by IEEE 802.11n. The key MAC features include: • Enhanced MAC for supporting IEEE 802.11ac features • Transmission and reception of aggregated MPDUs (A-MPDU) for high throughput (HT) • Support for power management schemes, including WMM power-save, power-save multi-poll (PSMP) and multiphase PSMP operation • Support for immediate ACK and Block-ACK policies • Interframe space timing support, including RIFS • Support for RTS/CTS and CTS-to-self frame sequences for protecting frame exchanges • Back-off counters in hardware for supporting multiple priorities as specified in the WMM specification • Timing synchronization function (TSF), network allocation vector (NAV) maintenance, and target beacon transmission time (TBTT) generation in hardware • Hardware offload for AES-CCMP, legacy WPA TKIP, legacy WEP ciphers, WAPI, and support for key management • Support for coexistence with Bluetooth and other external radios • Programmable independent basic service set (IBSS) or infrastructure basic service set functionality • Statistics counters for MIB support PSM The programmable state machine (PSM) is a microcoded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are predominant in implementations of communication protocols. The instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. It also allows for changes to the algorithms to track evolving IEEE 802.11 specifications. The PSM fetches instructions from the microcode memory. It uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the MAC data pipeline (via the SHM bus). The PSM also uses a scratchpad memory (similar to a register bank) to store frequently accessed and temporary variables. The PSM exercises fine-grained control over the hardware engines, by programming internal hardware registers (IHR). These IHRs are co-located with the hardware functions they control, and are accessed by the PSM via the IHR bus. The PSM fetches instructions from the microcode memory using an address determined by the program counter, instruction literal, or a program stack. For ALU operations the operands are obtained from shared memory, scratchpad, IHRs, or instruction literals, and the results are written into the shared memory, scratchpad, or IHRs. There are two basic branch instructions: conditional branches and ALU based branches. To better support the many decision points in the IEEE 802.11 algorithms, branches can depend on either a readily available signals from the hardware modules (branch condition signals are available to the PSM without polling the IHRs), or on the results of ALU operations. Broadcom® November 5, 2015 • 43455-DS109-R Page 74 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet IEEE 802.11ac MAC WEP The wired equivalent privacy (WEP) engine encapsulates all the hardware accelerators to perform the encryption and decryption, and MIC computation and verification. The accelerators implement the following cipher algorithms: legacy WEP, WPA TKIP, WPA2 AES-CCMP. The PSM determines, based on the frame type and association information, the appropriate cipher algorithm to be used. It supplies the keys to the hardware engines from an on-chip key table. The WEP interfaces with the TXE to encrypt and compute the MIC on transmit frames, and the RXE to decrypt and verify the MIC on receive frames. TXE The transmit engine (TXE) constitutes the transmit data path of the MAC. It coordinates the DMA engines to store the transmit frames in the TXFIFO. It interfaces with WEP module to encrypt frames, and transfers the frames across the MAC-PHY interface at the appropriate time determined by the channel access mechanisms. The data received from the DMA engines are stored in transmit FIFOs. The MAC supports multiple logical queues to support traffic streams that have different QoS priority requirements. The PSM uses the channel access information from the IFS module to schedule a queue from which the next frame is transmitted. Once the frame is scheduled, the TXE hardware transmits the frame based on a precise timing trigger received from the IFS module. The TXE module also contains the hardware that allows the rapid assembly of MPDUs into an A-MPDU for transmission. The hardware module aggregates the encrypted MPDUs by adding appropriate headers and pad delimiters as needed. RXE The receive engine (RXE) constitutes the receive data path of the MAC. It interfaces with the DMA engine to drain the received frames from the RXFIFO. It transfers bytes across the MAC-PHY interface and interfaces with the WEP module to decrypt frames. The decrypted data is stored in the RXFIFO. The RXE module contains programmable filters that are programmed by the PSM to accept or filter frames based on several criteria such as receiver address, BSSID, and certain frame types. The RXE module also contains the hardware required to detect A-MPDUs, parse the headers of the containers, and disaggregate them into component MPDUS. IFS The IFS module contains the timers required to determine interframe space timing including RIFS timing. It also contains multiple backoff engines required to support prioritized access to the medium as specified by WMM. The interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the PHY. These timers provide precise timing to the TXE to begin frame transmission. The TXE uses this information to send response frames or perform transmit frame-bursting (RIFS or SIFS separated, as within a TXOP). Broadcom® November 5, 2015 • 43455-DS109-R Page 75 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet IEEE 802.11ac PHY The backoff engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the backoff counters. When the backoff counters reach 0, the TXE gets notified, so that it may commence frame transmission. In the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the PSM. The IFS module also incorporates hardware that allows the MAC to enter a low-power state when operating under the IEEE power save mode. In this mode, the MAC is in a suspended state with its clock turned off. A sleep timer, whose count value is initialized by the PSM, runs on a slow clock and determines the duration over which the MAC remains in this suspended state. Once the timer expires the MAC is restored to its functional state. The PSM updates the TSF timer based on the sleep duration ensuring that the TSF is synchronized to the network. The IFS module also contains the PTA hardware that assists the PSM in Bluetooth coexistence functions. TSF The timing synchronization function (TSF) module maintains the TSF timer of the MAC. It also maintains the target beacon transmission time (TBTT). The TSF timer hardware, under the control of the PSM, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. The TSF module also generates trigger signals for events that are specified as offsets from the TSF timer, such as uplink and downlink transmission times used in PSMP. NAV The network allocation vector (NAV) timer module is responsible for maintaining the NAV information conveyed through the duration field of MAC frames. This ensures that the MAC complies with the protection mechanisms specified in the standard. The hardware, under the control of the PSM, maintains the NAV timer and updates the timer appropriately based on received frames. This timing information is provided to the IFS module, which uses it as a virtual carriersense indication. MAC-PHY Interface The MAC-PHY interface consists of a data path interface to exchange RX/TX data from/to the PHY. In addition, there is an programming interface, which can be controlled either by the host or the PSM to configure and control the PHY. IEEE 802.11ac PHY The BCM43455 WLAN Digital PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n singlestream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance handheld applications. Broadcom® November 5, 2015 • 43455-DS109-R Page 76 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet IEEE 802.11ac PHY The PHY has been designed to work in the presence of interference, radio nonlinearity, and various other impairments. It incorporates optimized implementations of the filters, FFT and Viterbi decoder algorithms. Efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, channel estimation and tracking. The PHY receiver also contains a robust IEEE 802.11b demodulator. The PHY carrier sense has been tuned to provide high throughput for IEEE 802.11g/11b hybrid networks with Bluetooth coexistence. It has also been designed for shared single antenna systems between WL and BT to support simultaneous RX-RX. The key PHY features include: • Programmable data rates from MCS0–MCS9 in 20, 40, and 80 MHz channels, as specified in IEEE 802.11ac. • Supports Optional Short GI and Green Field modes in TX and RX. • TX and RX LDPC for improved range and power efficiency. • All scrambling, encoding, forward error correction, and modulation in the transmit direction and inverse operations in the receive direction. • Supports IEEE 802.11h/k for worldwide operation. • Advanced algorithms for low power, enhanced sensitivity, range, and reliability. • Algorithms to improve performance in presence of Bluetooth. • Automatic gain control scheme for blocking and non blocking application scenario for cellular applications. • Closed loop transmit power control. • Digital RF chip calibration algorithms to handle CMOS RF chip non-idealities. • On-the-fly channel frequency and transmit power selection. • Supports per-packet RX antenna diversity. • Available per-packet channel quality and signal strength measurements. • Designed to meet FCC and other worldwide regulatory requirements. Figure 29: WLAN PHY Block Diagram Filters and Radio Comp AFE and Radio Radio Control Block Carrier Sense, AGC, and Rx FSM TX FSM Common Logic Block Filters and Radio Comp CCK/DSSS Demodulate Frequency and Timing Synch OFDM Demodulate Buffers Viterbi Decoder Descramble and Deframe FFT/IFFT MAC Interface Modulation and Coding Frame and Scramble PA Comp Modulate/ Spread COEX Broadcom® November 5, 2015 • 43455-DS109-R Page 77 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN Radio Subsystem Section 12: WLAN Radio Subsystem The BCM43455 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Ten RF control signals are available to drive external RF switches and support optional external power amplifiers and low-noise amplifiers for each band. See the reference board schematics for further details. A block diagram of the radio subsystem is shown in Figure 30 on page 79. Note that integrated on-chip baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. Receiver Path The BCM43455 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band or the entire 5 GHz U-NII band. An on-chip low-noise amplifier (LNA) in the 2.4 GHz path is shared between the Bluetooth and WLAN receivers, while the 5 GHz receive path has a dedicated on-chip LNA. Control signals are available that can support the use of optional LNAs for each band, which can increase the receive sensitivity by several dB. Transmit Path Baseband data is modulated and upconverted to the 2.4 GHz ISM or 5-GHz U-NII bands, respectively. Linear on-chip power amplifiers are included, which are capable of delivering high output powers while meeting IEEE 802.11ac and IEEE 802.11a/b/g/n specifications without the need for external PAs. When using the internal PAs, closed-loop output power control is completely integrated. As an option, external PAs can be used for even higher output power, in which case the closed-loop output power control is provided by means of a-band and g-band TSSI inputs from external power detectors. Calibration The BCM43455 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variations across components. These calibration routines are performed periodically in the course of normal radio operation. Examples of some of the automatic calibration algorithms are baseband filter calibration for optimum transmit and receive performance, and LOFT calibration for carrier leakage reduction. In addition, I/Q Calibration, R Calibration, and VCO Calibration are performed on-chip. No per-board calibration is required in manufacturing test, which helps to minimize the test time and cost in large volume production. Broadcom® November 5, 2015 • 43455-DS109-R Page 78 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Calibration Figure 30: Radio Functional Block Diagram WL DAC WL PA WL PGA WL TXLPF WL TX G-Mixer WL DAC WL A-PA WL A-PAD WL A-PGA WL TXLPF WL TX A-Mixer WLAN BB WL ADC WL A-LNA11 WL A-LNA12 Voltage Regulators WL RXLPF WL RX A-Mixer WL ADC SLNA WL G-LNA12 WL RXLPF WL RX G-Mixer WL ATX WL ARX WL GTX WL GRX Gm BT LNA GM WL LOGEN CLB WL PLL Shared XO BT RX BT TX BT LOGEN BT PLL LPO/Ext LPO/RCAL BT ADC BT RXLPF BT ADC BT LNA Load BT PA BT RX Mixer BT RXLPF BT BB BT BT DAC BT DAC BT TX Mixer BT TXLPF Broadcom® November 5, 2015 • 43455-DS109-R Page 79 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Ball Map and Pin Descriptions Section 13: Ball Map and Pin Descriptions Ball Map Figure 31: 140-Ball WLBGA Map—Bottom View (Balls Facing Up) 11 A 10 9 8 7 PCIE_TDN PCIE_RDN PCIE_RDP SDIO_CLK 6 5 4 3 2 1 SDIO_DAT LDO_VDDB LDO_VDD1 SR_VDDBA VOUT_3P3 SR_PVSS A_3 AT5V P5 T5V A B PCIE_RXT PCIE_REF PCIE_CLK SDIO_DAT SDIO_DAT VOUT_BTL VOUT_LNL VOUT_CLD VOUT_PCI PCIE_TDP X_AVDD1P CLKP REQ_L A_1 A_2 DO2P5 DO O ELDO 2 SR_VLX B C PCIE_REF PCIE_PLL_ PCIE_VSS CLKN AVDD1P2 GPIO_0 C D GPIO_13 E NC2 GPIO_14 NC1 VDDC SDIO_DAT SDIO_CMD A_0 VSSC PERST_L PCI_PME_ VDDIO_SD L VDDIO AVSS_BBP AVDD_BBP LL LL NC3 VDDIO_RF GPIO_2 GPIO_1 GPIO_3 GPIO_6 D GPIO_4 GPIO_5 VDDC GPIO_7 E VSSC GPIO_9 GPIO_10 BT_VDDC LPO_IN F GPIO_8 BT_VDDO BT_PCM_S YNC VSSC BT_PCM_I N G NC BT_PCM_O BT_PCM_C BT_I2S_DO UT LK H RF_SWCT JTAG_SEL RL_8 F RF_SW_CT RF_SW_CT RL_0 RL_1 G WRF_XTAL WRF_XTAL RF_SW_CT RF_SW_CT RF_SWCT RF_SWCT _XON _GND1P2 RL_2 RL_3 RL_5 RL_6 H WRF_SYN WRF_XTAL WRF_XTAL WRF_XTAL TH_VDD3P _XOP _VDD1P35 _VDD1P2 3 J WRF_SYN WRF_PMU WRF_SYN WRF_VCO BT_GPIO_ BT_UART_ TH_VDD1P _VDD1P35 TH_GND _GND 2 CTS_N 2 VDDC BT_VDDC BT_I2S_CL BT_I2S_W BT_I2S_DI K S J K WRF_RX5 WRF_AFE_ WRF_GEN WRF_EXT_ G_GND VDD1P35 ERAL_GND TSSIA VSSC BT_GPIO_ BT_UART_ BT_UART_ BT_UART_ 5 RTS_N TXD RXD K L WRF_GEN WRF_RFIN WRF_AFE_ WRF_GPAI BT_LNAVD BT_PLLVS BT_CLK_R BT_HOST_ BT_IFVSS ERAL2_GN _5G GND O_OUT D1P2 S EQ WAKE D M WRF_PAO WRF_PA_ WRF_TXMI WRF_RX2 BT_LNAVS BT_PLLVD FM_PLLVS FM_PLLVD BT_DEV_W BT_PAVSS FM_RFVSS UT_5G GND3P3 X_VDD G_GND S D1P2 S D1P2 AKE M N WRF_PA_V DD3P3 N 11 VSSC RF_SWCT RF_SWCT RL_4 RL_7 WL_REG_ BT_REG_O PMU_AVSS ON N VDDC WRF_PAO WRF_RFIN UT_2G _2G 10 9 8 BT_GPIO_ BT_GPIO_ 3 4 GPIO_15 BT_RF 7 GPIO_16 VSSC BT_VDDC BT_PAVDD BT_IFVDD1 FM_RFVDD FM_RFIN FM_AOUT2 FM_AOUT1 2P5 P2 1P2 6 5 Broadcom® November 5, 2015 • 43455-DS109-R 4 3 2 L 1 Page 80 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin List by Pin Number Pin List by Pin Number Table 17 lists BCM43455 pins by pin number. For a list of BCM43455 pins by pin name, see Table 18 on page 83. Table 17: WLBGA Pin List by Pin Number Table 17: WLBGA Pin List by Pin Number (Cont.) Ball Name Ball Name A1 SR_PVSS D1 GPIO_6 A2 SR_VDDBAT5V D2 GPIO_3 A3 LDO_VDD1P5 D3 GPIO_1 A4 VOUT_3P3 D4 GPIO_2 A5 LDO_VDDBAT5V D5 VDDIO A6 SDIO_DATA_3 D6 VDDIO_SD A7 SDIO_CLK D7 PCI_PME_L A8 PCIE_RDP D8 PERST_L A9 PCIE_RDN D9 NC1 A10 PCIE_TDN D10 GPIO_14 A11 – D11 GPIO_13 B1 SR_VLX E1 GPIO_7 B2 VOUT_PCIELDO E2 VDDC B3 VOUT_CLDO E3 GPIO_5 B4 VOUT_LNLDO E4 GPIO_4 B5 VOUT_BTLDO2P5 E5 JTAG_SEL B6 SDIO_DATA_2 E6 RF_SW_CTRL_8 B7 SDIO_DATA_1 E7 VDDIO_RF B8 PCIE_CLKREQ_L E8 NC3 B9 PCIE_RXTX_AVDD1P2 E9 AVDD_BBPLL B10 PCIE_TDP E10 AVSS_BBPLL B11 PCIE_REFCLKP C1 GPIO_0 C2 PMU_AVSS C3 BT_REG_ON C4 WL_REG_ON C5 VSSC C6 SDIO_CMD C7 SDIO_DATA_0 C8 VDDC C9 PCIE_VSS C10 PCIE_PLL_AVDD1P2 C11 PCIE_REFCLKN E11 NC2 F1 LPO_IN F2 BT_VDDC F3 GPIO_10 F4 GPIO_9 F5 VSSC F6 RF_SW_CTRL_7 F7 RF_SW_CTRL_4 F8 VDDC F9 VSSC F10 RF_SW_CTRL_1 F11 RF_SW_CTRL_0 Broadcom® November 5, 2015 • 43455-DS109-R Page 81 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin List by Pin Number Table 17: WLBGA Pin List by Pin Number (Cont.) Table 17: WLBGA Pin List by Pin Number (Cont.) Ball Name Ball Name G1 BT_PCM_IN K7 GPIO_15 G2 VSSC K8 WRF_EXT_TSSIA G3 BT_PCM_SYNC K9 WRF_GENERAL_GND G4 BT_VDDO K10 WRF_AFE_VDD1P35 G5 GPIO_8 K11 WRF_RX5G_GND G6 RF_SW_CTRL_6 L1 BT_VDDC G7 RF_SW_CTRL_5 L2 VSSC G8 RF_SW_CTRL_3 L3 BT_HOST_WAKE G9 RF_SW_CTRL_2 L4 BT_CLK_REQ G10 WRF_XTAL_GND1P2 L5 BT_PLLVSS G11 WRF_XTAL_XON L6 BT_IFVSS H1 BT_PCM_CLK L7 BT_LNAVDD1P2 H2 BT_I2S_DO L8 WRF_GPAIO_OUT H3 BT_PCM_OUT L9 WRF_AFE_GND H4 NC L10 WRF_GENERAL2_GND H5 BT_GPIO_4 L11 WRF_RFIN_5G H6 BT_GPIO_3 M1 BT_DEV_WAKE H7 – M2 FM_PLLVDD1P2 H8 WRF_SYNTH_VDD3P3 M3 FM_RFVSS H9 WRF_XTAL_VDD1P2 M4 FM_PLLVSS H10 WRF_XTAL_VDD1P35 M5 BT_PLLVDD1P2 H11 WRF_XTAL_XOP M6 BT_PAVSS J1 BT_I2S_CLK M7 BT_LNAVSS J2 BT_I2S_DI M8 WRF_RX2G_GND J3 BT_I2S_WS M9 WRF_TXMIX_VDD J4 BT_VDDC M10 WRF_PA_GND3P3 J5 VDDC M11 WRF_PAOUT_5G J6 BT_UART_CTS_N N1 FM_AOUT1 J7 BT_GPIO_2 N2 FM_AOUT2 J8 WRF_VCO_GND N3 FM_RFVDD1P2 J9 WRF_SYNTH_GND N4 FM_RFIN J10 WRF_SYNTH_VDD1P2 N5 BT_IFVDD1P2 J11 WRF_PMU_VDD1P35 N6 BT_PAVDD2P5 K1 BT_UART_RXD N7 BT_RF K2 BT_UART_TXD N8 WRF_RFIN_2G K3 BT_UART_RTS_N N9 WRF_PAOUT_2G K4 BT_GPIO_5 N10 – K5 VSSC N11 WRF_PA_VDD3P3 K6 GPIO_16 Broadcom® November 5, 2015 • 43455-DS109-R Page 82 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin List by Pin Name Pin List by Pin Name Table 18 lists BCM43455 pins by pin name. For a list of BCM43455 pins by pin number, see Table 17 on page 81. Table 18: WLBGA Pin List by Pin Name Table 18: WLBGA Pin List by Pin Name (Cont.) Name Ball Name Ball AVDD_BBPLL E9 BT_VDDC L1 AVSS_BBPLL E10 BT_VDDO G4 BT_CLK_REQ L4 FM_AOUT1 N1 BT_DEV_WAKE M1 FM_AOUT2 N2 BT_GPIO_2 J7 FM_PLLVDD1P2 M2 BT_GPIO_3 H6 FM_PLLVSS M4 BT_GPIO_4 H5 FM_RFIN N4 BT_GPIO_5 K4 FM_RFVDD1P2 N3 BT_HOST_WAKE L3 FM_RFVSS M3 BT_I2S_CLK J1 GPIO_0 C1 BT_I2S_DI J2 GPIO_1 D3 BT_I2S_DO H2 GPIO_2 D4 BT_I2S_WS J3 GPIO_3 D2 BT_IFVDD1P2 N5 GPIO_4 E4 BT_IFVSS L6 GPIO_5 E3 BT_LNAVDD1P2 L7 GPIO_6 D1 BT_LNAVSS M7 GPIO_7 E1 BT_PAVDD2P5 N6 GPIO_8 G5 BT_PAVSS M6 GPIO_9 F4 BT_PCM_CLK H1 GPIO_10 F3 BT_PCM_IN G1 GPIO_13 D11 BT_PCM_OUT H3 GPIO_14 D10 BT_PCM_SYNC G3 GPIO_15 K7 BT_PLLVDD1P2 M5 GPIO_16 K6 BT_PLLVSS L5 JTAG_SEL E5 BT_REG_ON C3 LDO_VDD1P5 A3 BT_RF N7 LDO_VDDBAT5V A5 BT_UART_CTS_N J6 LPO_IN F1 BT_UART_RTS_N K3 NC H4 BT_UART_RXD K1 NC1 D9 BT_UART_TXD K2 NC2 E11 BT_VDDC F2 NC3 E8 BT_VDDC J4 PCIE_CLKREQ_L B8 Broadcom® November 5, 2015 • 43455-DS109-R Page 83 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin List by Pin Name Table 18: WLBGA Pin List by Pin Name (Cont.) Table 18: WLBGA Pin List by Pin Name (Cont.) Name Ball Name Ball PCIE_PLL_AVDD1P2 C10 VOUT_CLDO B3 PCIE_RDN A9 VOUT_LNLDO B4 PCIE_RDP A8 VOUT_PCIELDO B2 PCIE_REFCLKN C11 VSSC C5 PCIE_REFCLKP B11 VSSC F5 PCIE_RXTX_AVDD1P2 B9 VSSC F9 PCIE_TDN A10 VSSC G2 PCIE_TDP B10 VSSC K5 PCIE_VSS C9 VSSC L2 PCI_PME_L D7 WL_REG_ON C4 PERST_L D8 WRF_AFE_GND L9 PMU_AVSS C2 WRF_AFE_VDD1P35 K10 RF_SW_CTRL_0 F11 WRF_EXT_TSSIA K8 RF_SW_CTRL_1 F10 WRF_GENERAL2_GND L10 RF_SW_CTRL_2 G9 WRF_GENERAL_GND K9 RF_SW_CTRL_3 G8 WRF_GPAIO_OUT L8 RF_SW_CTRL_4 F7 WRF_PAOUT_2G N9 RF_SW_CTRL_5 G7 WRF_PAOUT_5G M11 RF_SW_CTRL_6 G6 WRF_PA_GND3P3 M10 RF_SW_CTRL_7 F6 WRF_PA_VDD3P3 N11 RF_SW_CTRL_8 E6 WRF_PMU_VDD1P35 J11 SDIO_CLK A7 WRF_RFIN_2G N8 SDIO_CMD C6 WRF_RFIN_5G L11 SDIO_DATA_0 C7 WRF_RX2G_GND M8 SDIO_DATA_1 B7 WRF_RX5G_GND K11 SDIO_DATA_2 B6 WRF_SYNTH_GND J9 SDIO_DATA_3 A6 WRF_SYNTH_VDD1P2 J10 SR_PVSS A1 WRF_SYNTH_VDD3P3 H8 SR_VDDBAT5V A2 WRF_TXMIX_VDD M9 SR_VLX B1 WRF_VCO_GND J8 VDDC C8 WRF_XTAL_GND1P2 G10 VDDC E2 WRF_XTAL_VDD1P2 H9 VDDC F8 WRF_XTAL_VDD1P35 H10 VDDC J5 WRF_XTAL_XON G11 VDDIO D5 WRF_XTAL_XOP H11 VDDIO_RF E7 – A11 VDDIO_SD D6 – H7 VOUT_3P3 A4 – N10 VOUT_BTLDO2P5 B5 Broadcom® November 5, 2015 • 43455-DS109-R Page 84 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Pin Descriptions The signal name, type, and description of each pin in the BCM43455 is listed in Table 19. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. Table 19: Signal Descriptions Signal Name WLBGA Ball Type Description I 2.4 GHz Bluetooth and WLAN receiver shared input. WLAN and Bluetooth Receive RF Signal Interface WRF_RFIN_2G N8 WRF_RFIN_5G L11 I 5 GHz WLAN receiver input. WRF_PAOUT_2G N9 O 2.4 GHz WLAN PA output. WRF_PAOUT_5G M11 O 5 GHz WLAN PA output. WRF_EXT_TSSIA K8 I 5 GHz TSSI input from an optional external power amplifier/power detector. WRF_GPAIO_OUT L8 I/O GPIO or 2.4 GHz TSSI input from an optional external power amplifier/power detector. RF_SW_CTRL_0 F11 O RF_SW_CTRL_1 F10 O RF_SW_CTRL_2 G9 O Programmable RF switch control lines. The control lines are programmable via the driver and NVRAM file. RF Switch Control Lines RF_SW_CTRL_3 G8 O RF_SW_CTRL_4 F7 O RF_SW_CTRL_5 G7 O RF_SW_CTRL_6 G6 O RF_SW_CTRL_7 F6 O RF_SW_CTRL_8 E6 O WLAN PCI Express Interface PCIE_CLKREQ_L B8 OD PCIe clock request signal which indicates when the REFCLK to the PCIe interface can be gated. 1 = the clock can be gated. 0 = the clock is required. PERST_L D8 I (PU) PCIe System Reset. This input is the PCIe reset as defined in the PCIe Base Specification Version 1.1. PCIE_RDN A9 I Receiver differential pair (×1 lane). PCIE_RDP A8 I PCIE_REFCLKN C11 I PCIE_REFCLKP B11 I PCIe differential clock inputs (negative and positive), 100 MHz differential. PCIE_TDN A10 O Transmitter differential pair (×1 lane). PCIE_TDP B10 O Broadcom® November 5, 2015 • 43455-DS109-R Page 85 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Table 19: Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description PCI_PME_L D7 OD PCI power management event output. Used to request a change in the device or system power state. The assertion and deassertion of this signal is asynchronous to the PCIe reference clock. This signal has an open-drain output structure, as per the PCI Bus Local Bus Specification, Revision 2.3. WLAN SDIO Bus Interface Note: These signals can also have alternate functionality depending on package and host interface mode. SDIO_CLK A7 I SDIO clock input. SDIO_CMD C6 I/O SDIO command line. SDIO_DATA_0 C7 I/O SDIO data line 0. SDIO_DATA_1 B7 I/O SDIO data line 1. SDIO_DATA_2 B6 I/O SDIO data line 2. SDIO_DATA_3 A6 I/O SDIO data line 3. WLAN GPIO Interface Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to behave as various specific functions. GPIO_0 C1 I/O GPIO_1 D3 I/O GPIO_2 D4 I/O GPIO_3 D2 I/O GPIO_4 E4 I/O GPIO_5 E3 I/O GPIO_6 D1 I/O GPIO_7 E1 I/O GPIO_8 G5 I/O GPIO_9 F4 I/O GPIO_10 F3 I/O GPIO_13 D11 I/O GPIO_14 D10 I/O GPIO_15 K7 I/O GPIO_16 K6 I/O Programmable GPIO pins: GPIO_2 is TCK/SWCLK if JTAG_SEL = 1 GPIO_3 is TMS/SWDIO if JTAG_SEL = 1 GPIO_4 is TDIO if JTAG_SEL = 1 GPIO_5 is TDO if JTAG_SEL = 1 GPIO_6 is TRST_L if JTAG_SEL = 1 Broadcom® November 5, 2015 • 43455-DS109-R Page 86 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Table 19: Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description E5 I/O JTAG select. This pin must be connected to ground if the JTAG/SWD interface is not used. It must be high to select SWD OR JTAG. When JTAG_SEL = 1: • GPIO_2 is TCK/SWCLK • GPIO_3 is TMS/SWDIO • GPIO_4 is TDIO • GPIO_5 is TDO • GPIO_6 is TRST_L WRF_XTAL_XOP H11 I XTAL oscillator input. WRF_XTAL_XON G11 O XTAL oscillator output. JTAG/SWD Interface JTAG_SEL Clocks LPO_IN F1 I External sleep clock input (32.768 kHz). BT_CLK_REQ L4 O Reference clock request (shared by BT and WLAN). Bluetooth/FM Transceiver BT_RF N7 O Bluetooth PA output. FM_RFIN N4 I FM radio antenna port. FM_AOUT1 N1 O FM DAC output 1. FM_AOUT2 N2 O FM DAC output 2. BT_PCM_CLK H1 I/O PCM or SLIMbus clock; can be master (output) or slave (input). BT_PCM_IN G1 I PCM data input or SLIMbus transport sensing. BT_PCM_OUT H3 O PCM data output. BT_PCM_SYNC G3 I/O PCM sync; can be master (output) or slave (input), or SLIMbus data. BT_UART_CTS_N J6 I UART clear-to-send. Active-low clear-tosend signal for the HCI UART interface. BT_UART_RTS_N K3 O UART request-to-send. Active-low request-to-send signal for the HCI UART interface. BT LED control pin. BT_UART_RXD K1 I UART serial input. Serial data input for the HCI UART interface. BT RF disable pin 2. BT_UART_TXD K2 O UART serial output. Serial data output for the HCI UART interface. Bluetooth PCM Bluetooth UART Broadcom® November 5, 2015 • 43455-DS109-R Page 87 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Table 19: Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description BT_I2S_CLK J1 I/O I2S clock, can be master (output) or slave (input). BT_I2S_DI J2 I/O I2S data input. BT_I2S_DO H2 I/O I2S data output. BT_I2S_WS J3 I/O I2S WS; can be master (output) or slave (input). Bluetooth/FM I2S Bluetooth GPIO BT_GPIO_2 J7 I/O Bluetooth general-purpose I/O. BT_GPIO_3 H6 I/O Bluetooth general-purpose I/O. BT_GPIO_4 H5 I/O Bluetooth general-purpose I/O. BT_GPIO_5 K4 I/O Bluetooth general-purpose I/O. WL_REG_ON C4 I Used by PMU to power-up or power down the internal BCM43455 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. BT_REG_ON C3 I Used by PMU to power-up or power down the internal BCM43455 regulators used by the Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/FM section in reset. This pin has an internal 200 kΩ pull-down resistor that is enabled by default. It can be disabled through programming. BT_DEV_WAKE M1 I/O Bluetooth DEV_WAKE. BT_HOST_WAKE L3 I/O Bluetooth HOST_WAKE. Miscellaneous Integrated Voltage Regulators SR_VDDBAT5V A2 I VBAT. SR_VLX B1 O CBUCK switching regulator output. Refer to Table 44 on page 130 for details of the inductor and capacitor required on this output. LDO_VDD1P5 A3 I LNLDO input. LDO_VDDBAT5V A5 I LDO VBAT. WRF_XTAL_VDD1P35 H10 I XTAL LDO input (1.35V). WRF_XTAL_VDD1P2 H9 O XTAL LDO output (1.2V). VOUT_LNLDO B4 O Output of LNLDO. VOUT_CLDO B3 O Output of core LDO. VOUT_BTLDO2P5 B5 O Output of BT LDO. Broadcom® November 5, 2015 • 43455-DS109-R Page 88 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Table 19: Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description VOUT_3P3 A4 O LDO 3.3V output. BT_PAVDD2P5 N6 PWR Bluetooth PA power supply. BT_LNAVDD1P2 L7 PWR Bluetooth LNA power supply. BT_IFVDD1P2 N5 PWR Bluetooth IF block power supply. BT_PLLVDD1P2 M5 PWR Bluetooth RF PLL power supply. FM_RFVDD1P2 N3 PWR FM RF power supply. FM_PLLVDD1P2 M2 PWR FM PLL power supply. WRF_SYNTH_VDD3P3 H8 PWR Synthesizer VDD 3.3V supply. WRF_PA_VDD3P3 N11 PWR 2 GHz and 5 GHz PA 3.3V VBAT supply. WRF_PMU_VDD1P35 J11 PWR PMU 1.35V supply. WRF_TXMIX_VDD M9 PWR 3.3V supply for the TX Mix. WRF_SYNTH_VDD1P2 J10 PWR 1.2V supply for the synthesizer. WRF_AFE_VDD1P35 K10 PWR 1.35V supply for the AFE. Bluetooth Supplies FM Transceiver Supplies WLAN Supplies Miscellaneous Supplies VDDC C8, E2, F8, J5 PWR 1.2V core supply for the WLAN. VDDIO D5 PWR 1.8V–3.3V VDDIO supply for the WLAN. Must be directly connected to PMU_VDDO and BT_VDDO on the PCB. BT_VDDC F2, J4, L1 PWR 1.2V core supply for the BT. BT_VDDO G4 PWR 1.8V–3.3V VDDIO supply for the BT. Must be directly connected to PMU_VDDO and VDDIO on the PCB. VDDIO_SD D6 PWR 1.8V–3.3V supply for the SDIO pads. VDDIO_RF E7 PWR IO supply for the RF switch control pads (3.3V). AVDD_BBPLL E9 PWR 1.2V supply for the baseband PLL. PCIE_PLL_AVDD1P2 C10 PWR 1.2V supply for the PCIe PLL. VOUT_PCIELDO B2 PWR 1.2V supply for the PCIe. PCIE_RXTX_AVDD1P2 B9 PWR 1.2V supply for the PCIe TX/RX. WRF_VCO_GND J8 GND VCO/LOGEN ground. WRF_AFE_GND L9 GND AFE ground. WRF_XTAL_GND1P2 G10 GND XTAL ground. WRF_RX2G_GND M8 GND RX 2 GHz ground. WRF_RX5G_GND K11 GND RX 5 GHz ground. WRF_PA_GND3P3 M10 GND PA ground. WRF_GENERAL_GND K9 GND General ground. Ground Broadcom® November 5, 2015 • 43455-DS109-R Page 89 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Pin Descriptions Table 19: Signal Descriptions (Cont.) Signal Name WLBGA Ball Type Description WRF_GENERAL2_GND L10 GND General ground. WRF_SYNTH_GND J9 GND Ground. VSSC C5, F5, F9, G2, K5, L2 GND Core ground for WLAN and BT. SR_PVSS A1 GND Power ground. PMU_AVSS C2 GND Quiet ground. BT_PAVSS M6 GND Bluetooth PA ground. BT_LNAVSS M7 GND Bluetooth LNA ground. BT_IFVSS L6 GND Bluetooth IF block ground. BT_PLLVSS L5 GND Bluetooth PLL ground. FM_PLLVSS M4 GND FM PLL ground. FM_RFVSS M3 GND FM RF ground. AVSS_BBPLL E10 GND Baseband PLL ground. PCIE_VSS C9 GND PCIe ground. NC1 D9 – No connect. NC2 E11 No Connect NC3 E8 NC H4 – No connect. A11, H7, N10 – – Depopulated Pins – Broadcom® November 5, 2015 • 43455-DS109-R Page 90 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN GPIO Signals and Strapping Options WLAN GPIO Signals and Strapping Options This section describes WLAN GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a 10 kΩ resistor or less. Note: Refer to the reference board schematics for more information. Table 20: Strapping Options Pin Name Strap WLBGA Ball GPIO_7 sdio_padvddio E1 Default Internal Pull During Strap Description 1 Default pull = 1. SDIO interface voltage. 1 = 1.8V, 0 = 3.3V. Default is 1.8V. GPIO_16 host_iface_sdio K6 0 Broadcom® November 5, 2015 • 43455-DS109-R Default is PCIe. Pull high during POR to select SDIO. Page 91 BROADCOM CONFIDENTIAL WLAN GPIO Signals and Strapping Options BCM43455 Preliminary Data Sheet Multiplexed Bluetooth GPIO Signals The Bluetooth GPIO pins (BT_GPIO_0 to BT_GPIO_7) are multiplexed pins and can be programmed to be used as GPIOs or for other Bluetooth interface signals such as I2S. The specific function for a given BT_GPIO_X pin is chosen by programming the Pad Function Control register for that specific pin. Table 21 shows the possible options for each BT_GPIO_X pin. Note that each BT_GPIO_X pin's Pad Function Control register setting is independent (BT_GPIO_5 can be set to pad function 7 at the same time that BT_GPIO_3 is set to pad function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the BCM43455's PCM and I2S interface pins. Table 21: GPIO Multiplexing Matrix Pad Function Control Register Setting Pin Name 0 1 2 3 4 5 6 7 15 BT_UART_CTS_N UART_CTS_N – – – – – – A_GPIO[1] – BT_UART_RTS_N UART_RTS_N – – – – – – A_GPIO[0] – BT_UART_RXD UART_RXD – – – – – – GPIO[5] – BT_UART_TXD UART_TXD – – – – – – GPIO[4] – BT_PCM_IN A_GPIO[3] PCM_IN PCM_IN HCLK – – – I2S_SSDI/MSDI SF_MISO BT_PCM_OUT A_GPIO[2] PCM_OUT PCM_OUT LINK_IND – I2S_MSDO – I2S_SSDO SF_MOSI BT_PCM_SYNC A_GPIO[1] PCM_SYNC PCM_SYNC HCLK – I2S_MWS – I2S_SWS SF_SPI_CSN BT_PCM_CLK A_GPIO[0] PCM_CLK PCM_CLK – – I2S_MSCK – I2S_SSCK SF_SPI_CLK BT_I2S_DO A_GPIO[5] PCM_OUT – – I2S_SSDO I2S_MSDO – STATUS – BT_I2S_DI A_GPIO[6] PCM_IN – HCLK I2S_SSDI/MSDI – – TX_CON_FX – BT_I2S_WS GPIO[7] PCM_SYNC – LINK_IND – I2S_MWS – I2S_SWS – BT_I2S_CLK GPIO[6] PCM_CLK – – INT_LPO I2S_MSCK – I2S_SSCK – BT_GPIO_5 GPIO[5] HCLK – I2S_MSCK I2S_SSCK – – CLK_REQ – BT_GPIO_4 GPIO[4] LINK_IND – I2S_MSDO I2S_SSDO – – – – BT_GPIO_3 GPIO[3] – – I2S_MWS I2S_SWS – – – – BT_GPIO_2 GPIO[2] – – – I2S_SSDI/MSDI – – – – BT_CLK_REQ WL/BT_CLK_REQ – – – – – A_GPIO[7] – Broadcom® November 5, 2015 • 43455-DS109-R – Page 92 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN GPIO Signals and Strapping Options The multiplexed GPIO signals are described in Table 22. Table 22: Multiplexed GPIO Signals Pin Name Type Description UART_CTS_N I Host UART clear to send. UART_RTS_N O Device UART request to send. UART_RXD I Device UART receive data. UART_TXD O Host UART transmit data. PCM_IN I PCM data input. PCM_OUT O PCM data output. PCM_SYNC I/O PCM sync signal, can be master (output) or slave (input). PCM_CLK I/O PCM clock, can be master (output) or slave (input). GPIO[7:0] I/O General-purpose I/O. A_GPIO[7:0] I/O A group general-purpose I/O. I2S_MSDO O I2S master data output. I2S_MWS O I2S master word select. I2S_MSCK O I2S master clock. I2S_SSCK I I2S slave clock. I2S_SSDO O I2S slave data output. I2S_SWS I I2S slave word select. I2S_SSDI/MSDI I I2S slave/master data input. STATUS O Signals Bluetooth priority status. TX_CON_FX I WLAN-BT coexist. Transmission confirmation; permission for BT to transmit. RF_ACTIVE O WLAN-BT coexist. Asserted (logic high) during local BT RX and TX slots. LINK_IND O BT receiver/transmitter link indicator. CLK_REQ O WLAN/BT clock request output. SF_SPI_CLK O SFlash SCLK: serial clock (output from master). SF_MISO I SFlash MISO; SOMI: master input, slave output (output from slave). SF_MOSI O SFlash MOSI; SIMO: master output, slave input (output from master). SF_SPI_CSN O SFlash SS: slave select (active low, output from master). Broadcom® November 5, 2015 • 43455-DS109-R Page 93 BROADCOM CONFIDENTIAL I/O States BCM43455 Preliminary Data Sheet I/O States The following notations are used in Table 23: • I: Input signal • O: Output signal • I/O: Input/Output signal • PU = Pulled up • PD = Pulled down • NoPull = Neither pulled up nor pulled down Table 23: I/O States Power-downb Low Power State/Sleep (BT_REG_ON and (All Power Present) WL_REG_ON Held Low) Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High) (WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present Power Rail Name I/O Keepera Active Mode WL_REG_ON I N Input; PD (pull-down can Input; PD (pull-down can Input; PD (of 200K) be disabled) be disabled) Input; PD (of 200K) Input; PD (of 200K) – BT_REG_ON I N Input; PD (pull down can Input; PD (pull down can Input; PD (of 200K) be disabled) be disabled) Input; PD (of 200K) Input; PD (of 200K) – BT_CLK_REQ I/O Y Open drain or push-pull Open drain or push-pull High-Z, NoPull (programmable). Active (programmable). Active high. high Open drain. Active high Open drain. Active high. BT_VDDO BT_HOST_WAKE I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable) NoPull (programmable) Input, PU Input, PD BT_VDDO BT_DEV_WAKE I/O Y Input/Output; PU, PD, Input; PU, PD, NoPull NoPull (programmable) (programmable) High-Z, NoPull Input, PD Input, PD BT_VDDO BT_GPIO_2, BT_GPIO_3 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable) NoPull (programmable) Input, PD Input, PD BT_VDDO BT_GPIO_4, BT_GPIO_5 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable) NoPull (programmable) Input, PU Input, PU BT_VDDO BT_UART_CTS_N I Y Input; NoPull Input; NoPull High-Z, NoPull Input; PU Input; PU BT_VDDO BT_UART_RTS_N O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Input; PU BT_VDDO BT_UART_RXD I Y Input; PU Input; NoPull High-Z, NoPull Input; PU Input; PU BT_VDDO BT_UART_TXD O Y Output; NoPull Output; NoPull High-Z, NoPull Input; PU Input; PU BT_VDDO SDIO_DATA[0:3] I/O N Input/Output; PU (SDIO Input; PU (SDIO Mode) High-Z, NoPull Mode) Input; PU (SDIO Mode) Input; PU (SDIO Mode) WL_VDDIO Broadcom® November 5, 2015 • 43455-DS109-R Page 94 BROADCOM CONFIDENTIAL I/O States BCM43455 Preliminary Data Sheet Table 23: I/O States (Cont.) Power-downb Low Power State/Sleep (BT_REG_ON and (All Power Present) WL_REG_ON Held Low) Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High) (WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present Power Rail Name I/O Keepera Active Mode SDIO_CMD I/O N Input/Output; PU (SDIO Input; PU (SDIO Mode) High-Z, NoPull Mode) Input; PU (SDIO Mode) Input; PU (SDIO Mode) WL_VDDIO SDIO_CLK I N Input; NoPull Input; noPull High-Z, NoPull Input; noPull Input; noPull WL_VDDIO Input; NoPull c High-Z, NoPull Input, PD Input, PD BT_VDDO Input; NoPull c High-Z, NoPull Input, PD Input, PD BT_VDDO BT_PCM_CLK I/O Y Input; NoPull c BT_PCM_IN I/O Y Input; NoPull c BT_PCM_OUT I/O Y Input; NoPullc Input; NoPullc High-Z, NoPull Input, PD Input, PD BT_VDDO BT_PCM_SYNC I/O Y Input; NoPull c Input; NoPullc High-Z, NoPull Input, PD Input, PD BT_VDDO BT_I2S_WS I/O Y Input; NoPulld Input; NoPulld High-Z, NoPull Input, PD Input, PD BT_VDDO BT_I2S_CLK I/O Y Input; NoPulld Input; NoPulld High-Z, NoPull Input, PD Input, PD BT_VDDO BT_I2S_DI I/O Y Input; NoPull d High-Z, NoPull Input, PD Input, PD BT_VDDO BT_I2S_DO I/O Y Input; NoPulld Input; NoPulld High-Z, NoPull Input, PD Input, PD BT_VDDO GPIO_0 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD Input; PD WL_VDDIO GPIO_1 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_2 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_3 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD Input; PD WL_VDDIO GPIO_4 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_5 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD Input; PD WL_VDDIO GPIO_6 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_7 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO d Input; NoPull Broadcom® November 5, 2015 • 43455-DS109-R Page 95 BROADCOM CONFIDENTIAL I/O States BCM43455 Preliminary Data Sheet Table 23: I/O States (Cont.) Power-downb Low Power State/Sleep (BT_REG_ON and (All Power Present) WL_REG_ON Held Low) Out-of-Reset; Before SW Download (BT_REG_ON High; WL_REG_ON High) (WL_REG_ON High and BT_REG_ON = 0) and VDDIOs Are Present Power Rail Name I/O Keepera Active Mode GPIO_8 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD])e [Default: PD])e Input; PDe Input; PDe WL_VDDIO GPIO_9 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: PD]) [Default: PD]) Input; PD Input; PD WL_VDDIO GPIO_10 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_13 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_14 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_15 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO GPIO_16 I/O Y Input/Output; PU, PD, Input/Output; PU, PD, High-Z, NoPull NoPull (programmable NoPull (programmable [Default: NoPull]) [Default: NoPull]) Input; NoPull Input; NoPull WL_VDDIO RF_SW_CTRL [0:8] I/O Y Output; NoPull Output; NoPull Output; NoPull VDDIO_RF Output; NoPull High-Z a. Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in power-down state. If there is no keeper, and it is an input and there is NoPull, then the pad should be driven to prevent leakage due to floating pad (SDIO_CLK, for example). b. In the power-down state (xx_REG_ON=0): High-Z; NoPull => the pad is disabled because power is not supplied. c. Depending on whether the PCM interface is enabled and the configuration of PCM is in master or slave mode, it can be either output or input. d. Depending on whether the I2S interface is enabled and the configuration of I2S is in master or slave mode, it can be either output or input. e. NoPull when in SDIO mode. Broadcom® November 5, 2015 • 43455-DS109-R Page 96 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet DC Characteristics S e c t i o n 1 4 : D C C h a r a c t e ri s t i c s Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 24 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. Table 24: Absolute Maximum Ratings Rating Symbol Value Unit DC supply for the VBAT and PA driver supply VBAT –0.5 to +6.0 V DC supply voltage for digital I/O VDDIO –0.5 to 3.9 V DC supply voltage for RF switch I/Os VDDIO_RF –0.5 to 3.9 V DC input supply voltage for CLDO and LNLDO – –0.5 to 1.575 V DC supply voltage for RF analog VDDRF –0.5 to 1.32 V DC supply voltage for core VDDC –0.5 to 1.32 V – –0.5 to 3.63 V Vundershoot –0.5 V Maximum overshoot voltage for I/Oa Vovershoot VDDIO + 0.5 V Maximum junction temperature Tj 125 °C WRF_TCXO_VDD Maximum undershoot voltage for I/O a a. Duration not to exceed 25% of the duty cycle. Broadcom® November 5, 2015 • 43455-DS109-R Page 97 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Environmental Ratings Environmental Ratings The environmental ratings are shown in Table 25. Table 25: Environmental Ratings Characteristic Value Units Conditions/Comments Ambient Temperature (TA) –30 to +85 °C Functional operationa Storage Temperature –40 to +125 °C – Relative Humidity Less than 60 % Storage Less than 85 % Operation a. Functionality is guaranteed across this ambient temperature range. Optimal RF performance specified in the data sheet, however, is guaranteed only for –20°C to 75°C. Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. Table 26: ESD Specifications Minimum ESD Rating Unit Pin Type Symbol Condition ESD Handling Reference: NQY00083, Section 3.4, Group D9, Table B ESD_HAND_HBM Human body model contact discharge per JEDEC EID/JESD22-A114 1 kV CDM ESD_HAND_CDM Charged device model contact discharge per JEDEC EIA/JESD22C101 250 V Broadcom® November 5, 2015 • 43455-DS109-R Page 98 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Recommended Operating Conditions and DC Characteristics Recommended Operating Conditions and DC Characteristics Caution! Functional operation is not guaranteed outside of the limits shown in Table 27. Operation outside these limits for extended periods can adversely affect long-term reliability of the device. Note: For DC absolute maximum rating (AMR), see Table 24 on page 97. Table 27: Recommended Operating Conditions and DC Characteristics Value Parameter Symbol Minimum Typical Maximum Unit DC supply voltage for VBAT VBAT – VDD VDDRF WRF_TCXO_VDD VDDIO VDDIO_RF TSSI Vth_POR 1.2 1.2 1.8 – 3.3 – – 5.25 b 1.26 1.26 1.98 3.63 3.46 0.95 0.7 V DC supply voltage for core DC supply voltage for RF blocks in chip DC supply voltage for TCXO input buffer DC supply voltage for digital I/O DC supply voltage for RF switch I/Os External TSSI input Internal POR threshold 3.0a 1.14 1.14 1.62 1.62 3.13 0.15 0.4 V V V V V V V VIH VIL VOH VOL 0.65 × VDDIO – VDDIO – 0.45 – – – – – – 0.35 × VDDIO – 0.45 V V V V VIH VIL VOH VOL 2.00 – VDDIO – 0.4 – – – – – – 0.80 – 0.40 V V V V VOH VOL COUT VDDIO – 0.4 – – – – – – 0.40 5 V V pF Other Digital I/O Pins For VDDIO = 1.8V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low voltage @ 2 mA For VDDIO = 3.3V: Input high voltage Input low voltage Output high voltage @ 2 mA Output low Voltage @ 2 mA RF Switch Control Output Pinsc For VDDIO_RF = 3.3V: Output high voltage @ 2 mA Output low voltage @ 2 mA Output capacitance a. The BCM43455 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.2V < VBAT < 4.8V. b. The maximum continuous voltage is 5.25V. c. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. Broadcom® November 5, 2015 • 43455-DS109-R Page 99 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications S e c t i on 1 5 : B l u e t o o th R F S p e c i f i c a t i o n s Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 25: “Environmental Ratings,” on page 98 and Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 99. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Figure 32: Port Locations for Bluetooth Testing 2.4G Configured with iTR 2.4G Configured with eTR BT PA BT PA 2G PA Chip Port RF Port Optional Filter Optional Filter Diplexer Chip Port LNA 2G RF Port Chip Port Chip Port LNA 2G Antenna Port Antenna Port Chip Port Diplexer 2G PA Chip Port 5G PA RF Port LNA 5G Chip Port Chip Port 5G PA LNA 5G Note: All Bluetooth specifications are measured at the chip port, unless otherwise defined. Note: The specifications in Table 28 on page 101 are measured at the chip port input, unless otherwise defined. Broadcom® November 5, 2015 • 43455-DS109-R Page 100 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 28: Bluetooth Receiver RF Specifications Parameter Conditions Minimum – 2402 Typical Maximum Unit General Frequency range – 2480 MHz GFSK, 0.1% BER, 1 Mbps – –93.5 – dBm /4-DQPSK, 0.01% BER, 2 Mbps – –95.5 – dBm 8-DPSK, 0.01% BER, 3 Mbps – –89.5 – dBm Input IP3 – –16 – – dBm Maximum input at RF port – – – –20 dBm – – – –90 dBm C/I co-channel GFSK, 0.1% BER – – 11 dB C/I 1 MHz adjacent channel GFSK, 0.1% BER – – 0 dB C/I 2 MHz adjacent channel GFSK, 0.1% BER – – –30 dB C/I 3 MHz adjacent channel GFSK, 0.1% BER – – –40 dB C/I image channel GFSK, 0.1% BER – – –9 dB C/I 1-MHz adjacent to image channel GFSK, 0.1% BER – – –20 dB C/I co-channel /4-DQPSK, 0.1% BER – – 13 dB C/I 1 MHz adjacent channel /4-DQPSK, 0.1% BER – – 0 dB C/I 2 MHz adjacent channel /4-DQPSK, 0.1% BER – – –30 dB C/I 3 MHz adjacent channel /4-DQPSK, 0.1% BER – – –40 dB C/I image channel /4-DQPSK, 0.1% BER – – –7 dB C/I 1 MHz adjacent to image channel /4-DQPSK, 0.1% BER – – –20 dB C/I co-channel 8-DPSK, 0.1% BER – – 21 dB C/I 1 MHz adjacent channel 8-DPSK, 0.1% BER – – 5 dB C/I 2 MHz adjacent channel RX sensitivitya RX LO Leakage 2.4 GHz band Interference Performanceb 8-DPSK, 0.1% BER – – –25 dB C/I 3 MHz adjacent channel 8-DPSK, 0.1% BER – – –33 dB C/I Image channel 8-DPSK, 0.1% BER – – 0 dB C/I 1 MHz adjacent to image channel 8-DPSK, 0.1% BER – – –13 dB Broadcom® November 5, 2015 • 43455-DS109-R Page 101 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 28: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Blocking Performance (CW) 30–2000 MHz 0.1% BER – –10 – dBm 2000–2399 MHz 0.1% BER – –27 – dBm 2498–3000 MHz 0.1% BER – –27 – dBm 3000 MHz–12.75 GHz 0.1% BER – –10 – dBm Out-of-Band Blocking Performance, Modulated Interferer GFSK (1 Mbps) c 698–716 MHz WCDMA – –14 – dBm 776–849 MHz WCDMA – –14 – dBm 824–849 MHz GSM850 – –14 – dBm 824–849 MHz WCDMA – –14 – dBm 880–915 MHz E-GSM – –13 – dBm 880–915 MHz WCDMA – –13 – dBm 1710–1785 MHz GSM1800 – –18 – dBm 1710–1785 MHz WCDMA – –17 – dBm 1850–1910 MHz GSM1900 – –20 – dBm 1850–1910 MHz WCDMA – –19 – dBm 1880–1920 MHz TD-SCDMA – –20 – dBm 1920–1980 MHz WCDMA – –20 – dBm 2010–2025 MHz TD–SCDMA – –20 – dBm 2500–2570 MHz WCDMA – –23 – dBm 2500–2570 MHz Band 7 – –25 – dBm 2300–2400 MHze Band 40 – –35.2 – dBm 2570–2620 MHzf Band 38 – –21 – dBm 2545–2575 MHzg XGP Band – –22 – dBm d /4-DPSK (2 Mbps) c 698–716 MHz WCDMA – –10 – dBm 776–794 MHz WCDMA – –10 – dBm 824–849 MHz GSM850 – –11 – dBm 824–849 MHz WCDMA – –11 – dBm 880–915 MHz E-GSM – –10 – dBm 880–915 MHz WCDMA – –10 – dBm 1710–1785 MHz GSM1800 – –16 – dBm 1710–1785 MHz WCDMA – –16 – dBm 1850–1910 MHz GSM1900 – –17 – dBm 1850–1910 MHz WCDMA – –16 – dBm 1880–1920 MHz TD-SCDMA – –18 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 102 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 28: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 1920–1980 MHz WCDMA – –17 – dBm 2010–2025 MHz TD-SCDMA – –19 – dBm 2500–2570 MHz WCDMA – –23 – dBm 2500–2570 MHzd Band 7 – –24.4 – dBm 2300–2400 MHze Band 40 – –36.5 – dBm 2570–2620 MHzf Band 38 – –21 – dBm 2545–2575 MHzg XGP Band – –22 – dBm 8-DPSK (3 Mbps) c 698-716 MHz WCDMA – –13 – dBm 776-794 MHz WCDMA – –13 – dBm 824-849 MHz GSM850 – –13 – dBm 824-849 MHz WCDMA – –14 – dBm 880-915 MHz E-GSM – –13 – dBm 880-915 MHz WCDMA – –13 – dBm 1710-1785 MHz GSM1800 – –18 – dBm 1710-1785 MHz WCDMA – –17 – dBm 1850-1910 MHz GSM1900 – –19 – dBm 1850-1910 MHz WCDMA – –19 – dBm 1880-1920 MHz TD-SCDMA – –19 – dBm 1920-1980 MHz WCDMA – –19 – dBm 2010-2025 MHz TD-SCDMA – –20 – dBm 2500-2570 MHz WCDMA – –23 – dBm 2500–2570 MHzd Band 7 – –24.7 – dBm 2300–2400 MHze Band 40 – –36.7 – dBm 2570–2620 MHzf Band 38 – –21 – dBm 2545–2575 MHzg XGP Band – –22 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 103 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 28: Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 30 MHz–1 GHz – –95 –62 dBm 1–12.75 GHz – –70 –47 dBm 851–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz – –147 – dBm/Hz 1930–1990 MHz – –147 – dBm/Hz 2110–2170 MHz – –147 – dBm/Hz Spurious Emissions a. Dirty TX is off. b. The maximum value represents the actual Bluetooth specification required for Bluetooth qualification as defined in the version 4.1 specification. c. 3 dB receiver desense. d. 2560 MHz performance is used. e. 2360 MHz performance is used. f. 2580 MHz performance is used. g. 2555 MHz performance is used. Table 29: Bluetooth Transmitter RF Specifications Parameter Conditions Minimum Typical Maximum Unit Note: The specifications in this table are measured at the Bluetooth chip port output, unless otherwise defined. General Frequency range 2402 – 2480 MHz Basic rate (GFSK) TX power at Bluetooth – 12 – dBm QPSK TX Power at Bluetooth – 8 – dBm 8PSK TX Power at Bluetooth – 8 – dBm 2 4 8 dB – 0.93 1 MHz M – N = the frequency range for – which the spurious emission is – measured relative to the – transmit center frequency. –38 –26 dBc Power control step – Note: Output power is with TCA and TSSI enabled. GFSK In-Band Spurious Emissions –20 dBc BW – EDR In-Band Spurious Emissions 1.0 MHz < |M – N| < 1.5 MHz 1.5 MHz < |M – N| < 2.5 MHz |M – N| 2.5 MHza Broadcom® November 5, 2015 • 43455-DS109-R –31 –20 dBm –43 –40 dBm Page 104 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 29: Bluetooth Transmitter RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Spurious Emissions 30 MHz to 1 GHz – – – –36 b, c dBm 1 GHz to 12.75 GHz – – – –30 b, d, e dBm 1.8 GHz to 1.9 GHz – – – –47 dBm 5.15 GHz to 5.3 GHz – – – –47 dBm – – –103 – dBm FM RX – –147 – dBm/Hz 776–794 MHz CDMA2000 – –146 – dBm/Hz 869–960 MHz cdmaOne, GSM850 – –146 – dBm/Hz 925–960 MHz E-GSM – –146 – dBm/Hz 1570–1580 MHz GPS – –146 – dBm/Hz 1805–1880 MHz GSM1800 – –144 – dBm/Hz 1930–1990 MHz GSM1900, cdmaOne, WCDMA – –143 – dBm/Hz 2110–2170 MHz WCDMA – –137 – dBm/Hz 2500–2570 MHz Band 7 – –130 – dBm/Hz 2300–2400 MHz Band 40 – –130 – dBm/Hz 2570–2620 MHz Band 38 – –132 – dBm/Hz 2545–2575 MHz XGP Band – –135 – dBm/Hz GPS Band Spurious Emissions Spurious emissions Out-of-Band Noise Floor f 65–108 MHz a. b. c. d. e. f. The typical number is measured at ± 3 MHz offset. The maximum value represents the value required for Bluetooth qualification as defined in the v4.1 specification. The spurious emissions during Idle mode are the same as specified in Table 29 on page 104. Specified at the Bluetooth Antenna port. Meets this specification using a front-end band-pass filter. Transmitted power in cellular and FM bands at the antenna port. See Figure 32 on page 100 for location of the port. Broadcom® November 5, 2015 • 43455-DS109-R Page 105 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Bluetooth RF Specifications Table 30: Local Oscillator Performance Parameter Minimum Typical Maximum Unit LO Performance Lock time – 72 – s Initial carrier frequency tolerance – ±25 ±75 kHz DH1 packet – ±8 ±25 kHz DH3 packet – ±8 ±40 kHz DH5 packet – ±8 ±40 kHz Drift rate – 5 20 kHz/50 µs 00001111 sequence in payloada 140 155 175 kHz 10101010 sequence in payloadb 115 140 – kHz Channel spacing – 1 – MHz Frequency Drift Frequency Deviation a. This pattern represents an average deviation in payload. b. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. Table 31: BLE RF Specifications Parameter Conditions Minimum Typical Maximum Unit Frequency range – 2402 – 2480 MHz GFSK, 0.1% BER, 1 Mbps – –96.5 – dBm – – 8.5 – dBm Mod Char: delta F1 average – 225 255 275 kHz Mod Char: delta F2 max.c – 230 – – % Mod Char: ratio – 0.8 1 – % RX sensea TX powerb a. Dirty TX is Off. b. The BLE TX power cannot exceed 10 dBm EIRP specification limit. The front-end losses and antenna gain/loss must be factored in so as not to exceed the limit. c. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz. Broadcom® November 5, 2015 • 43455-DS109-R Page 106 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Specifications Section 16: FM Receiver Specifications Unless otherwise stated, limit values apply for the conditions specified in Table 25: “Environmental Ratings,” on page 98 and Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 99. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Table 32: FM Receiver Specifications Conditionsa Minimum Typical Maximum Units Operating frequencyb Frequencies inclusive 65 – 108 MHz Sensitivityc FM only SNR > 26 dB – –1 – dBμV EMF – 0.9 – μV EMF – –7 – dBμV – dB Parameter RF Parameters Receiver adjacent channel selectivityc, d Measured for 30 dB SNR at the audio output with best tune. Signal of interest: 23 dBμV EMF (14.1 μV EMF), At ± 200 kHz. – 51 At ± 400 kHz – 62 – dB Intermediate signal plus noise-to-noise ratio (S+N)/Nc Vin = 20 dBμV EMF (10 μV EMF) 45 53 – dB Intermodulation performancec, d Blocker level increased until desired at – 30 dB SNR Wanted Signal: 33 dBμV EMF (45 μV EMF) Modulated Interferer: At fWanted + 400 kHz and +4 MHz CW Interferer: At fWanted + 800 kHz and + 8 MHz 55 – dBc AM suppression, monoc Vin = 23 dBμV EMF (14.1 μV EMF) AM at 400 Hz with m = 0.3 No A-weighted or any other filtering applied. 40 – – dB RDS deviation = 1.2 kHz – 16 – dBμV EMF – 6.3 – μV EMF RDS RDS Sensitivity e, f RDS deviation = 2 kHz – 10 – dBμV – 12 – dBμV EMF – 4 – μV EMF – 6 – dBμV Broadcom® November 5, 2015 • 43455-DS109-R Page 107 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Specifications Table 32: FM Receiver Specifications (Cont.) Parameter Conditionsa RDS selectivityf Wanted Signal: 33 dBμV EMF (45 μV EMF), 2 kHz RDS deviation with best tune Interferer: ∆f = 40 kHz, fmod = 1 kHz Minimum Typical Maximum Units ± 200 kHz – 49 – dB ± 300 kHz – 52 – dB ± 400 kHz – 52 – dB – 1.5 – – kΩ Antenna tuning capacitor – 2.5 – 30 pF – – 113 dBμV EMF – – 446 mV EMF – – 107 dBμV RF conducted emissions Local oscillator breakthrough measured – on the reference port – –55 dBm – – –90 dBm GSM850, E-GSM (std), BW = 0.2 MHz, – 824–849 MHz 880–915 MHz 5 – dBm – –4 – dBm GSM DCS 1800, PCS 1900 (std/edge), – BW = 0.2 MHz, 1710–1785 MHz 1850–1910 MHz 12 – dBm – 12 – dBm RF input impedance c Maximum input level SNR > 26 dB 869–894 MHz, 925–960 MHz, 1805–1880 MHz, 1930–1990 MHz. GPS RF blocking levels at the FM antenna input 40 dB SNR (assumes a 50Ω at the radio input and excludes spurs) GSM850, E-GSM (edge), BW = 0.2 MHz, 824–849 MHz 880–915 MHz WCDMA: II(I), III (IV, X), BW = 5 MHz, 1850–1980 MHz (1920–1980 MHz), 1710–1785 MHz (1710–1755 MHz, 1710–1770 MHz) Broadcom® November 5, 2015 • 43455-DS109-R Page 108 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Specifications Table 32: FM Receiver Specifications (Cont.) Parameter Conditionsa Minimum Typical Maximum Units – WCDMA: V(VI), VIII, XII, XIII, XIV, BW = 5 MHz, 824–849 MHz (830–840 MHz), 880–915 MHz – 1 – dBm CDMA2000, cdmaOne, BW = 1.25 MHz, 824–849 MHz, 887–925 MHz, 776–794 MHz – –3 – dBm CDMA2000, cdmaOne, BW = 1.25 MHz, 1850–1910 MHz, 1750–1780 MHz, 1920–1980 MHz – 12 – dBm Bluetooth, BW = 1 MHz, 2402–2480 MHz – 11 – dBm IEEE 802.11g/b, BW = 20 MHz, 2400–2483.5 MHz – 11 – dBm IEEE 802.11a, BW = 20 MHz, 4915–5825 MHz – 6 – dBm 2500–2570 MHz Band 7 – 11 – dBm 2300–2400 MHz Band 40 – 11 – dBm 2570–2620 MHz Band 38 – 11 – dBm 2545–2575 MHz XGP Band – 11 – dBm Frequency step – 10 – – kHz Settling time Single-frequency switch in any direction – to a frequency within the bands 88– 108 MHz or 76–90 MHz. Time measured to within 5 kHz of the final frequency. 150 – μs Search time – Total time for an automatic search to sweep from 88–108 MHz or 76–90 MHz (and reverse direction) assuming no channels are found. – 8 sec Audio output levelg – –14.5 – –12.5 dBFS Maximum audio output levelh – – – 0 dBFS 72 – 88 mVrms Tuning General Audio Audio DAC output levelg – Maximum DAC audio output levelh – – 333 – mVrms Audio DAC output level differencei – –1 – 1 dB Broadcom® November 5, 2015 • 43455-DS109-R Page 109 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Specifications Table 32: FM Receiver Specifications (Cont.) Parameter Conditionsa Minimum Typical Maximum Units Left and right AC mute FM input signal fully muted with DAC enabled 60 – – dB Left and right hard mute FM input signal fully muted with DAC disabled 80 – – dB – Soft mute attenuation and Muting is performed dynamically start level proportional to the FM wanted input signal C/N. The muting characteristic is fully programmable. Refer to “Audio Features” on page 62 for further details. – – – Maximum signal plus noise-to-noise ratio (S + N)/N, mono i – – 68 – dB Maximum signal plus noise-to-noise ratio (S + N) ÷ N, stereog – – 64 – dB – – 1.5 % ∆f = 75 kHz, fmod = 1 kHz – – –60 % ∆f = 75 kHz, fmod = 3 kHz – – 0.8 % ∆f = 100 kHz, fmod = 1 kHz – – 1.0 % Total harmonic distortion, Vin = 66 dBμV EMF (2 mV EMF) stereo ∆f = 67.5 kHz, fmod = 1 kHz, ∆f Pilot = 7.5 kHz, L = R – – 1.5 % Audio spurious productsi Range from 300 Hz to 15 kHz, with respect to 1 kHz tone – – –60 dBc Audio bandwidth, upper (–3 dB point) 15 – – kHz – – 20 Hz Total harmonic distortion, Vin = 66 dBμV EMF (2 mV EMF), mono ∆f = 75 kHz, fmod = 400 Hz Vin = 66 dBμV EMF (2 mV EMF) ∆f = 8 kHz, for 50 μs Audio bandwidth, lower (–3 dB point) Audio in-band ripple 100 Hz to 13 kHz, Vin = 66 dBμV EMF (2 mV EMF) ∆f = 8 kHz, for 50 μs –0.5 – 0.5 dB De-emphasis time constant tolerance With respect to 50 and 75 μs – – ±5 % RSSI range With 1 dB resolution and ± 5 dB accuracy at room temp 3 – 83 dBμV EMF 1.41 – 1.41E + 04 μV EMF –3 – 77 dBμV – 48 – dB Stereo Decoder Stereo channel separation Forced Stereo mode Vin = 66 dBμV EMF (2 mV EMF), ∆f = 67.5 kHz, fmod = 1 kHz, ∆f Pilot = 6.75 kHz R = 0, L = 1 Broadcom® November 5, 2015 • 43455-DS109-R Page 110 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet FM Receiver Specifications Table 32: FM Receiver Specifications (Cont.) Parameter Conditionsa Mono stereo blend and switching Blending and switching is dynamically – proportional to the FM wanted input signal C/N. The blending and switching characteristics are fully programmable. Refer to “Audio Features” on page 62 for further details. Pilot suppression Vin = 66 dBμV EMF (2 mV EMF), ∆f = 75 kHz, fmod = 1 kHz 46 – – – – – dB Audio level at which a pause is detected Relative to 1 kHz tone, ∆f = 22.5 kHz – – – – Four values in 3 dB steps –21 – –12 dB Audio pause duration Four values 20 – 40 ms Minimum Typical Maximum Units Pause detection a. Following conditions are applied to all relevant tests unless otherwise indicated: Pre-emphasis and de-emphasis of 50 us, R = L for mono, DAC Load > 20 kΩ, BAF = 300 Hz to 15 kHz, and A-weighted filtering applied. b. Contact Broadcom regarding applications that operate between 65 and 76 MHz. c. Wanted Signal: ∆f = 22.5 kHz, and fmod = 1 kHz. d. Interferer: ∆f = 22.5 kHz, and fmod = 1 kHz. e. RDS sensitivity numbers are for 87.5–108 MHz only. f. Vin = ∆f = 32 kHz, fmod = 1 kHz, ∆f Pilot = 7.5 kHz, and 95% of blocks decoded with no errors after correction g. Vin = 66 dBμV EMF (2 mV EMF), ∆f = 22.5 kHz, fmod = 1 kHz, and ∆f Pilot = 6.75 kHz. h. Vin = 66 dBμV EMF (2 mV EMF), ∆f = 100 kHz, fmod = 1 kHz, and ∆f Pilot = 6.75 kHz. i. Vin = 66 dBμV EMF (2 mV EMF), ∆f = 22.5 kHz, and fmod = 1 kHz. Broadcom® November 5, 2015 • 43455-DS109-R Page 111 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN RF Specifications Section 17: WLAN RF Specifications Introduction The BCM43455 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This section describes the RF characteristics of the 2.4 GHz and 5 GHz radio. Note: Values in this section of the data sheet are design goals and are subject to change based on device characterization results. Unless otherwise stated, limit values apply for the conditions specified in Table 25: “Environmental Ratings,” on page 98 and Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 99. Typical values apply for the following conditions: • VBAT = 3.6V • Ambient temperature +25°C Figure 33: Port Locations for WLAN Testing 2.4G Configured with iTR 2.4G Configured with eTR BT PA BT PA 2G PA Chip Port RF Port Optional Filter Optional Filter Diplexer Chip Port LNA 2G RF Port Chip Port Chip Port LNA 2G Antenna Port Antenna Port Chip Port Diplexer 2G PA Chip Port 5G PA RF Port LNA 5G Chip Port Chip Port 5G PA LNA 5G Note: Unless otherwise defined, all WLAN specifications are provided at the chip port. Broadcom® November 5, 2015 • 43455-DS109-R Page 112 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet 2.4 GHz Band General RF Specifications 2.4 GHz Band General RF Specifications Table 33: 2.4 GHz Band General RF Specifications Item Condition Minimum Typical Maximum Unit TX/RX switch time Including TX ramp down – – 5 µs RX/TX switch time Including TX ramp up – – 2 µs Power-up and power-down ramp time DSSS/CCK modulations – – <2 µs WLAN 2.4 GHz Receiver Performance Specifications Note: The specifications shown in the following table are provided at the chip port, unless otherwise defined. Table 34: WLAN 2.4 GHz Receiver Performance Specifications Parameter Condition/Notes Frequency range RX sensitivity IEEE 802.11b (8% PER for 1024 octet PSDU) – 2400 1 Mbps DSSS – 2 Mbps DSSS – 5.5 Mbps DSSS – 11 Mbps DSSS – 6 Mbps OFDM – 9 Mbps OFDM – 12 Mbps OFDM – 18 Mbps OFDM – 24 Mbps OFDM – 36 Mbps OFDM – 48 Mbps OFDM – 54 Mbps OFDM – 20 MHz channel spacing for all MCS rates MCS0 – MCS1 – MCS2 – MCS3 – MCS4 – MCS5 – MCS6 – MCS7 – RX sensitivity IEEE 802.11g (10% PER for 1024 octet PSDU) RX sensitivity IEEE 802.11n (10% PER for 4096 octet PSDU) a Defined for default parameters: 800 ns GI and non-STBC. Minimum Typical Broadcom® November 5, 2015 • 43455-DS109-R Maximum Unit – –98.7 –96.0 –94.4 –90.7 –95.3 –94.3 –93.5 –90.9 –87.7 –84.4 –79.6 –78.2 2500 – – – – – – – – – – – – MHz dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm –94.8 –92.3 –89.8 –86.4 –83.3 –78.6 –76.7 –74.7 – – – – – – – – dBm dBm dBm dBm dBm dBm dBm dBm Page 113 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 34: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical RX sensitivity 20 MHz channel spacing for all MCS rates IEEE 802.11ac MCS0 – (10% PER for 4096 octet MCS1 – PSDU) b Defined for default MCS2 – parameters: 800 ns GI and MCS3 – non-STBC MCS4 – MCS5 – MCS6 – MCS7 – MCS8 – 20 MHz channel spacing for all MCS rates RX sensitivity IEEE 802.11ac with LDPC (10% MCS7 – PER for 4096 octet PSDU) MCS8 – at RF port. Defined for MCS9 – default parameters: 800 ns GI, LDPC coding, and nonSTBC. Broadcom® November 5, 2015 • 43455-DS109-R Maximum Unit –95.0 –92.3 –90.1 –87.0 –83.6 –78.7 –76.8 –75.9 –71.5 – – – – – – – – – dBm dBm dBm dBm dBm dBm dBm dBm dBm –77.8 –74.0 –72.0 – – – dBm dBm dBm Page 114 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 34: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Blocking level for 3 dB RX sensitivity degradation (without external filtering)c 776–794 MHz (CDMA2000): Blocker frequency = 794 MHz – –16 – dBm – –11 – dBm – –11 – dBm – –11 – dBm – –12 – dBm – –13 – dBm – –5 – dBm – –19 – dBm – –19 – dBm – – –29 –35 – – dBm dBm – – –39 –35 – – dBm dBm – –35 – dBm – – –42 –17 – – dBm dBm – –80 –33 – – – dBm dBm – – –10 15 – – dBm dBm MHzd (cdmaOne): 824–849 Blocker frequency = 849 MHz 824–849 MHz (GSM850): Blocker frequency = 849 MHz 880–915 MHz (E-GSM): Blocker frequency = 915 MHz 1710–1785 MHz (GSM1800): Blocker frequency = 1785 MHz 1850–1910 MHz (GSM1900): Blocker frequency = 1910 MHz 1850–1910 MHz (cdmaOne): Blocker frequency = 1910 MHz 1850–1910 MHz (WCDMA): Blocker frequency = 1910 MHz 1920–1980 MHz (WCDMA): Blocker frequency = 1980 MHz 2300–2400 MHz (LTE band 40) Blocker frequency = 2300 MHz Blocker frequency = 2365 MHz 2500–2570 MHz (LTE band 7): Blocker frequency = 2505 MHz Blocker frequency = 2565 MHz 2570–2620 MHz (LTE band 38): Blocker frequency = 2575 MHz 2496-2690 MHz (LTE band 41): Blocker frequency = 2501 MHz Blocker frequency = 2685 MHz 2545–2575 MHz (XGP Band): Blocker frequency = 2550 MHz In-band static CW jammer RX PER < 1%, 54 Mbps OFDM, immunity 1000 octet PSDU for: (fc – 8 MHz < fcw < + 8 MHz) (RxSens + 23 dB < Rxlevel < max. input level) Input In-Band IP3 Maximum LNA gain Minimum LNA gain Broadcom® November 5, 2015 • 43455-DS109-R Page 115 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 2.4 GHz Receiver Performance Specifications Table 34: WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Maximum Receive Level @ 2.4 GHz @ 1, 2 Mbps (8% PER, 1024 octets) @ 5.5, 11 Mbps (8% PER, 1024 octets) @ 6–54 Mbps (10% PER, 1024 octets) @ MCS0–MCS7 rates (10% PER, 4095 octets) @ MCS8–MCS9 rates (10% PER, 4095 octets) –3.5 –9.5 – – – – dBm dBm –9.5 – – dBm –9.5 – – dBm –11.5 – – dBm – – – – dB dB – – dB – – dB – – – – – – – – – – – – – – – – – – 70 3 – – – – – – – – – – – – – – – – – – – – – 5 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Range above –30 dBm –8 Zo = 50Ω, across the dynamic range 10 – 11.5 8 13 dB dB At maximum gain 4 – dB Adjacent channel rejection- Desired and interfering signal 30 MHz apart DSSS 1 Mbps DSSS –74 dBm 35 (Difference between 2 Mbps DSSS –74 dBm 35 interfering and desired signal at 8% PER for 1024 Desired and interfering signal 25 MHz apart octet PSDU with desired 5.5 Mbps –70 dBm 35 signal level as specified in DSSS Condition/Notes) 11 Mbps –70 dBm 35 DSSS –79 dBm 16 Adjacent channel rejection- 6 Mbps OFDM OFDM 9 Mbps OFDM –78 dBm 15 (Difference between 12 Mbps OFDM –76 dBm 13 interfering and desired 18 Mbps OFDM –74 dBm 11 signal (25 MHz apart) at 24 Mbps OFDM –71 dBm 8 10% PER for 1024 octet PSDU with desired signal 36 Mbps OFDM –67 dBm 4 level as specified in 48 Mbps OFDM –63 dBm 0 Condition/Notes) 54 Mbps OFDM –62 dBm –1 –79 dBm 16 Adjacent channel rejection MCS0 MCS0–MCS9 (Difference MCS1 –76 dBm 13 between interfering and MCS2 –74 dBm 11 desired signal (25 MHz –71 dBm 8 apart) at 10% PER for 4096 MCS3 octet PSDU with desired MCS4 –67 dBm 4 signal level as specified in MCS5 –63 dBm 0 Condition/Notes) MCS6 –62 dBm –1 MCS7 –61 dBm –2 MCS8 –59 dBm –4 MCS9 –57 dBm –6 Maximum receiver gain – – – Gain control step – – – e f –5 RSSI accuracy Range –95 dBm to –30 dBm Return loss Receiver cascaded noise figure – Broadcom® November 5, 2015 • 43455-DS109-R Page 116 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 2.4 GHz Transmitter Performance Specifications a. Sensitivity degradations for alternate settings in MCS modes. SGI: 2 dB drop. b. Sensitivity degradations for alternate settings in MCS modes. SGI: 2 dB drop. c. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. d. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 × 824 MHz) falling within band.) e. The minimum and maximum values shown have a 95% confidence level. f. –95 dBm with calibration at time of manufacture, –92 dBm without calibration. WLAN 2.4 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output. Table 35: WLAN 2.4 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range – 2400 – 2500 MHz – –164 – dBm/Hz – –163 – dBm/Hz – –153.6 – dBm/Hz – –151.2 – dBm/Hz Transmitted power in 776-794 MHz (CDMA2000) cellular and FM bands (at 869–960 MHz (cdmaOne, +21 dBm, 100% duty cycle, GSM850) 1 Mbps CCK) a 1450–1495 (DAB) 1570–1580 MHz (GPS) 1592–1610 MHz (GLONASS) – –150.4 – dBm/Hz 1710–1800 (DSC-1800-Uplink) – –145 – dBm/Hz 1805–1880 MHz (GSM 1800) – –139 – dBm/Hz 1850–1910 MHz (GSM 1900) – –139 – dBm/Hz 1910–1930 MHz (TDSCDMA,LTE) – –140 – dBm/Hz 1930–1990 MHz (GSM1900, cdmaOne, WCDMA) – –128 – dBm/Hz 2010–2075 MHz (TDSCDMA) – –131 – dBm/Hz 2110–2170 MHz (WCDMA) – –125 – dBm/Hz 2305–2370 (LTE band 40) – –95 – dBm/Hz 2370–2400 (LTE band 40) – –80 – dBm/Hz 2496-2530 (LTE band 41) – –90 – dBm/Hz 2530-2560 (LTE band 41) – –110 – dBm/Hz 2570-2690 (LTE band 41) – –116 – dBm/Hz 5000-5900 (WLAN 5G) – –155 – dBm/Hz Broadcom® November 5, 2015 • 43455-DS109-R Page 117 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 35: WLAN 2.4 GHz Transmitter Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit EVM Does Not Exceed TX power at the chip port for highest power level setting at 25°C and VBAT = 3.6V with spectral mask and EVM compliance Phase noise 802.11b (DSSS/CCK) –9 dB – 21.5 – dBm OFDM, BPSK –8 dB – 20 – dBm OFDM, 64QAM –25 dB – 19 – dBm MCS7 –27 dB – 19 – dBm MCS8 –30 dB – 17 – dBm 0.45 – Degrees 37.4 MHz crystal, integrated from – 10 kHz to 10 MHz TX power control dynamic – range 10 – – dB Closed-loop TX power variation at highest power level setting Across full temperature and voltage range. Applies to 10 dBm to 20 dBm output power range. – – ±1.5 dB Carrier suppression – 15 – – dBc Gain control step – – 0.25 – dB – 6 – dB Return loss at Chip port TX Zo = 50Ω a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. WLAN 5 GHz Receiver Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the chip port input. Table 36: WLAN 5 GHz Receiver Performance Specifications Parameter Condition/Notes Minimum Typical Maximum Unit Frequency range – 4900 – 5845 MHz – –94.5 – dBm 6 Mbps OFDM RX sensitivity a IEEE 802.11a (10% PER 9 Mbps OFDM for 1000 octet PSDU) 12 Mbps OFDM – –93.5 – dBm – –92.7 – dBm 18 Mbps OFDM – –90.1 – dBm 24 Mbps OFDM – –86.9 – dBm 36 Mbps OFDM – –83.6 – dBm 48 Mbps OFDM – –78.6 – dBm 54 Mbps OFDM – –77.4 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 118 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes RX sensitivity a IEEE 802.11n (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. 20 MHz channel spacing for all MCS rates a RX sensitivity IEEE 802.11n (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. a RX sensitivity IEEE 802.11ac (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. RX sensitivity a IEEE 802.11ac (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. Minimum Typical Maximum Unit MCS0 – –94.0 – dBm MCS1 – –91.5 – dBm MCS2 – –89.0 – dBm MCS3 – –85.6 – dBm MCS4 – –82.5 – dBm MCS5 – –77.8 – dBm MCS6 – –75.9 – dBm MCS7 – –73.9 – dBm 40 MHz channel spacing for all MCS rates MCS0 – –92.0 – dBm MCS1 – –89.0 – dBm MCS2 – –86.5 – dBm MCS3 – –83.2 – dBm MCS4 – –79.9 – dBm MCS5 – –75.3 – dBm MCS6 – –73.8 – dBm MCS7 – –72.2 – dBm 20 MHz channel spacing for all MCS rates MCS0 – –94.2 – dBm MCS1 – –91.5 – dBm MCS2 – –89.3 – dBm MCS3 – –86.2 – dBm MCS4 – –82.8 – dBm MCS5 – –77.9 – dBm MCS6 – –76.0 – dBm MCS7 – –75.1 – dBm MCS8 – –70.7 – dBm 40 MHz channel spacing for all MCS rates MCS0 – –92.3 – dBm MCS1 – –89.3 – dBm MCS2 – –86.9 – dBm MCS3 – –83.6 – dBm MCS4 – –80.2 – dBm MCS5 – –75.6 – dBm MCS6 – –74.0 – dBm MCS7 – –72.6 – dBm MCS8 – –68.3 – dBm MCS9 – –66.7 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 119 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes RX sensitivity a IEEE 802.11ac (10% PER for 4096 octet PSDU) Defined for default parameters: 800 ns GI and non-STBC. 80 MHz channel spacing for all MCS rates RX sensitivity a IEEE 802.11ac 20/40/80 MHz channel spacing with LDPC (10% PER for 4096 octet PSDU) at RF port. Defined for default parameters: 800 ns GI, LDPC coding and nonSTBC. Minimum Typical Maximum Unit MCS0 – –89.0 – dBm MCS1 – –86.0 – dBm MCS2 – –83.3 – dBm MCS3 – –80.1 – dBm MCS4 – –76.8 – dBm MCS5 – –72.2 – dBm MCS6 – –70.9 – dBm MCS7 – –69.2 – dBm MCS8 – –65.2 – dBm MCS9 – –63.6 – dBm MCS7 20 MHz – –76.8 – dBm MCS8 20 MHz – –72.9 – dBm MCS9 20 MHz – –70.7 – dBm MCS7 40 MHz – –74.8 – dBm MCS8 40 MHz – –70.9 – dBm MCS9 40 MHz – –68.9 – dBm MCS7 80 MHz – –71.5 – dBm MCS8 80 MHz – –67.6 – dBm MCS9 80 MHz – –65.5 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 120 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit –21 – dBm – –20 – dBm – –10 – dBm – –12 – dBm –13 – dBm –13 – dBm –18 – dBm –20 – dBm –20 – dBm –19 – dBm –16 – dBm –16 – dBm –16 – dBm –18 – dBm Blocking level for 3 dB RX 776–794 MHz (CDMA2000): sensitivity degradation Blocker frequency = – (without external 794 MHz filtering)b 824–849 MHzc (cdmaOne): Blocker frequency = 849 MHz 824–849 MHz (GSM850): Blocker frequency = 849 MHz 880–915 MHz (E-GSM): Blocker frequency = 915 MHz 1710–1785 MHz (GSM1800): Blocker frequency = 1785 MHz – 1850–1910 MHz (GSM1900): Blocker frequency = 1910 MHz – 1850–1910 MHz (cdmaOne): Blocker frequency = 1910 MHz – 1850–1910 MHz (WCDMA): Blocker frequency = 1910 MHz – 1920–1980 MHz (WCDMA): Blocker frequency = 1980 MHz – 2300–2400 MHz (LTE band 40) Blocker frequency = 2395 MHz – 2500–2570 MHz (LTE band 7): Blocker frequency = 2565 MHz – 2570–2620 MHz (LTE band 38): Blocker frequency = 2615 MHz – 2496-2690 MHz (LTE band 41): Blocker frequency = 2685 MHz – 2545–2575 MHz (XGP Band): Blocker frequency = 2570 MHz – Broadcom® November 5, 2015 • 43455-DS109-R Page 121 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Input In-Band IP3 Maximum LNA gain – –11 – dBm Minimum LNA gain – 5 – dBm Maximum receive level @ @ 6, 9, 12 Mbps –9.5 5.24 GHz @ 18, 24, 36, 48, 54 Mbps –14.5 – – dBm – – dBm 6 Mbps OFDM –79 dBm 16 – – dB 9 Mbps OFDM –78 dBm 15 – – dB 12 Mbps OFDM –76 dBm 13 – – dB 18 Mbps OFDM –74 dBm 11 – – dB 24 Mbps OFDM –71 dBm 8 – – dB 36 Mbps OFDM –67 dBm 4 – – dB 48 Mbps OFDM –63 dBm 0 – – dB 54 Mbps OFDM –62 dBm –1 – – dB 65 Mbps OFDM –61 dBm –2 – – dB 6 Mbps OFDM –78.5 dBm 32 – – dB 9 Mbps OFDM –77.5 dBm 31 – – dB 12 Mbps OFDM –75.5 dBm 29 – – dB 18 Mbps OFDM –73.5 dBm 27 – – dB 24 Mbps OFDM –70.5 dBm 24 – – dB 36 Mbps OFDM –66.5 dBm 20 – – dB 48 Mbps OFDM –62.5 dBm 16 – – dB 54 Mbps OFDM –61.5 dBm 15 – – dB 65 Mbps OFDM –60.5 dBm 14 – – dB Adjacent channel rejection (Difference between interfering and desired signal (20 MHz apart) at 10% PER for 1000 octet PSDU with desired signal level as specified in Condition/Notes) Alternate adjacent channel rejection (Difference between interfering and desired signal (40 MHz apart) at 10% PER for 1000d octet PSDU with desired signal level as specified in Condition/Notes) Maximum receiver gain – – 65 – dB Gain control step – – 3 – dB Broadcom® November 5, 2015 • 43455-DS109-R Page 122 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Receiver Performance Specifications Table 36: WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RSSI accuracye Range –98 dBm to –30 dBm –5 – 5 dB Range above –30 dBm –8 – 8 dB Zo = 50Ω, across the dynamic range 10 – 13 dB – 4 – dB Return loss Receiver cascaded noise At maximum gain figure a. For PCIE derate 5G RX sensitivity by 1.5 dB b. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. c. The blocking levels are valid for channels 1 to 11. (For higher channels, the performance may be lower due to third harmonic signals (3 × 824 MHz) falling within band.) d. For 65 Mbps, the size is 4096. e. The minimum and maximum values shown have a 95% confidence level. Broadcom® November 5, 2015 • 43455-DS109-R Page 123 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN 5 GHz Transmitter Performance Specifications WLAN 5 GHz Transmitter Performance Specifications Note: Unless otherwise noted, the values shown in the following table are provided at the WLAN chip port output. Table 37: WLAN 5 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum Typical Maximu m Unit Frequency range – 4900 – 5845 MHz – –164 – dBm/Hz – –166 – dBm/Hz – –166 – dBm/Hz – –166 – dBm/Hz 1592–1610 MHz (GLONASS) – –165.5 – dBm/Hz 1710–1800(DSC-1800-Uplink) – –135 – dBm/Hz 1805–1880 MHz (GSM 1800) – –165 – dBm/Hz 1850–1910 MHz (GSM 1900) – –165 – dBm/Hz 1910–1930 MHz (TDSCDMA, LTE) – –165 – dBm/Hz 1930–1990 MHz (GSM1900, cdmaOne, WCDMA) – –165 – dBm/Hz 2010–2075 MHz (TDSCDMA) – –164.5 – dBm/Hz 2110–2170 MHz (WCDMA) – –164 – dBm/Hz 2305–2370 (LTE band 40) – –160 – dBm/Hz 2370–2400 (LTE band 40) – –163 – dBm/Hz 2400–2500 (WLAN 2G) – –160 – dBm/Hz 2496–2530 (LTE band 41) – –161.5 – dBm/Hz 2530–2560 (LTE band 41) – –161.5 – dBm/Hz 2570–2690 (LTE band 41) – –161 – dBm/Hz Transmitted power in 776–794 MHz (CDMA2000) cellular and FM bands (at 869–960 MHz (cdmaOne, GSM850) +18.5 dBm, 100% duty 1450–1495 (DAB) cycle, 6 Mbps OFDM) a 1570–1580 MHz (GPS) EVM Does Not Exceed TX power at the chip port for highest power level setting at 25°C and VBAT = 3.6V with spectral mask and EVM compliance OFDM, BPSK –8 dB – 21.5 – dBm OFDM, 64QAM –25 dB – 19 – dBm MCS7 –27 dB – 19 – dBm MCS9 –32 dB – 17 – dBm Broadcom® November 5, 2015 • 43455-DS109-R Page 124 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet General Spurious Emissions Specifications Table 37: WLAN 5 GHz Transmitter Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximu m Unit Phase noise 37.4 MHz Crystal, Integrated from 10 kHz to 10 MHz – 0.5 – Degrees TX power control dynamic – range 10 – – dB Across full-temperature and voltage Closed loop TX power variation at highest power range. Applies across 10 to 20 dBm output power range. level setting – – ±2.0 dB Carrier suppression 15 – – dBc – Gain control step – – 0.25 – dB Return loss Zo = 50Ω – 6 – dB a. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. General Spurious Emissions Specifications This section provides the TX and RX spurious emissions specifications for both the WLAN 2.4 GHz and 5 GHz bands. The recommended spectrum analyzer settings for the spurious emissions specifications are provided in Table 38. Table 38: Recommended Spectrum Analyzer Settings Parameter Setting Resolution Bandwidth (RBW): 1 MHz Video Bandwidth (VBW): 1 MHz Sweep: Auto Span: 100 MHz Detector: Maximum Peak Trace: Maximum Hold Modulation: OFDM (Orthogonal Frequency-division Multiplexing) Transmitter Spurious Emissions Specifications The TX spurious emissions specifications in this subsection are based on the following definitions: • AFE = VCO/16 for 2G channels • AFE = VCO/18 for 5G 20 MHz channels • AFE = VCO/9 for 5G 40 MHz channels • AFE = VCO/6 for 5G 80 MHz channels • LO = Channel frequency Broadcom® November 5, 2015 • 43455-DS109-R Page 125 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet General Spurious Emissions Specifications 2.4 GHz Band Spurious Emissions 20 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/16 specifications for channel 2442 are listed in Table 39. Table 39: 2.4 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specificationsa Frequency (Fch; MHz) Channel 2442 Spurious Frequency Power (dBm) Typical (dBm) Maximum (dBm) HD2 21 –22.78 – HD3 21 –19.54 – HD4 21 –41.79 – HD5 21 –61.78 – VCO – LO 21 –55.13 – VCO + LO 21 –63.40 – VCO 21 –48.56 – LO + AFE 21 –59.2 – LO-AFE 21 –59.3 – LO + AFE × 2 21 –68.2 – LO – AFE × 2 21 –67.4 – LO + XTAL × 2 21 –56.2 – LO – XTAL × 2 21 –56.3 – LO + XTAL × 4 21 –57.5 – LO – XTAL × 4 21 –56.7 – LO + XTAL × 8 21 –59.1 – LO – XTAL × 8 21 –67.2 – a. VCO = 1.5 × Fch, where Fch is the center frequency of the channel. Broadcom® November 5, 2015 • 43455-DS109-R Page 126 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet General Spurious Emissions Specifications 5 GHz Band Spurious Emissions 20 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/18 specifications for channels 5180, 5500, and 5825 are listed in Table 40. Table 40: 5 GHz Band, 20 MHz Channel Spacing TX Spurious Emissions Specifications CH5180a CH5500a CH5825a Spurious Frequency Power (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) HD2 19 –29.33 – –32.56 – –33.14 – HD3 19 –39.71 – –38.93 – –39.87 – VCO 19 –49.03 – –48.35 – –46.70 – VCO × 2 19 –55.64 – –60.40 – –64.77 – LO + VCO 19 –63.94 – –62.80 – –62.16 – LO – VCO 19 –81.58 – –72.56 – –70.58 – LO – AFE 19 –62.1 – –63.3 – –60.4 – LO + AFE 19 –57.8 – –59.6 – –60.6 – LO – XTAL × 4 19 –60.1 – –60.1 – –58.7 – LO + XTAL × 4 19 –57.2 – –57.4 – –58.2 – LO – XTAL × 6 19 –63.4 – –59.3 – –61.1 – LO + XTAL × 6 19 –60.2 – –58.9 – –60.8 – LO – XTAL × 8 19 –66.1 – –67.3 – –63.8 – LO + XTAL × 8 19 –64.2 – –63.8 – –65.8 – AFE × 12 19 – – – – – – a. VCO = (2/3) × Fch, where Fch is the center frequency of the channel. Broadcom® November 5, 2015 • 43455-DS109-R Page 127 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet General Spurious Emissions Specifications 40 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/9 specifications for channels 5190, 5510, and 5795 are listed in Table 41. Table 41: 5 GHz Band, 40 MHz Channel Spacing TX Spurious Emissions Specifications CH5190ma CH5510ma CH5795ma Spurious Frequency Power (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) HD2 19 –33.43 – –35.53 – –36.49 – HD3 19 –41.81 – –42.13 – –42.33 – VCO 19 –48.36 – –47.65 – –46.93 – VCO × 2 19 –55.87 – –59.26 – –64.45 – LO + VCO 19 –65.58 – –64.96 – – – LO – VCO 19 – – – – – – LO – AFE 19 –65.3 – –67.2 – –65.2 – LO + AFE 19 –63.2 – –64.3 – –67.3 – LO – XTAL × 4 19 –59.3 – –59.7 – –59.6 – LO + XTAL × 4 19 –58.3 – –57.4 – –57.9 – LO – XTAL × 6 19 –64.1 – –63.4 – –63.2 – LO + XTAL × 6 19 –61.5 – –59.4 – –61.2 – LO – XTAL × 8 19 –66.3 – –67.1 – –64.3 – LO + XTAL × 8 19 –63.8 – –64.7 – –61.2 – AFE × 12 19 –65.2 – –66.3 – –65.4 – a. VCO = (2/3) × Fch, where Fch is the center frequency of the channel. Broadcom® November 5, 2015 • 43455-DS109-R Page 128 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet General Spurious Emissions Specifications 80 MHz Channel Spacing Note: Possible AFE combinations are as follows. The AFE=VCO/6 specifications for channels 5210, 5530, and 5775 are listed in Table 42. Table 42: 5 GHz Band, 80 MHz Channel Spacing TX Spurious Emissions Specifications CH5210qa CH5530qa CH5775qa Spurious Frequency Power (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) Typ. (dBm) Max. (dBm) HD2 19 –36.28 – –39.59 – –41.02 – HD3 19 –45.00 – –44.82 – –46.10 – VCO 19 –48.00 – –47.34 – –46.01 – VCO × 2 19 –57.04 – –62.82 – –66.84 – LO + VCO 19 –66.66 – –66.11 – –66.40 – LO – VCO 19 – – – – – – LO – AFE 19 –68.5 – –67.8 – –66.9 – LO + AFE 19 –63.8 – –66.3 – –68.6 – LO – XTAL × 4 19 – – – – – – LO + XTAL × 4 19 – – – – – – LO – XTAL × 6 19 – – – – – – LO + XTAL × 6 19 – – – – – – LO – XTAL × 8 19 – – – – – – LO + XTAL × 8 19 – – – – – – AFE × 12 19 – – – – – – a. VCO = (2/3) × Fch, where Fch is the center frequency of the channel. Receiver Spurious Emissions Specifications Table 43: 2G and 5G General Receiver Spurious Emissions Band Frequency Range Typical Maximum Unit 2G 2.4 GHz < f < 2.5 GHz –92 – dBm 3.6 GHz < f < 3.8 GHz –75.16 – dBm 5150 MHz < f < 5850 MHz –70.4 – dBm 3.45 GHz < f < 3.9 GHz –59.2 – dBm 5G Broadcom® November 5, 2015 • 43455-DS109-R Page 129 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Internal Regulator Electrical Specifications Section 18: Internal Regulator Electrical Specifications Core Buck Switching Regulator Note: Values in this data sheet are design goals and are subject to change based on device characterization results. Note: Functional operation is not guaranteed outside of the specification limits provided in this section. Table 44: Core Buck Switching Regulator (CBUCK) Specifications Specification Notes Min. Typ. Max. Unit Input supply voltage (DC) DC voltage range inclusive of disturbances. 3.0 3.6 PWM mode switching frequency PWM output current Output current limit Output voltage range PWM output voltage DC accuracy PWM ripple voltage, static CCM, Load > 100 mA VBAT = 3.6V – 4 5.25a V – MHz – – 1.2 –4 – 1400 1.35 – 600 – 1.5 4 mA mA V % – 7 20 mVpp 78 70 – 86 80 400 – – 500 % % μs – 2.2 – μH 2.0 4.7 10b μF 0.67b 4.7 – μF 40 – μs – – Programmable, 30 mV steps. Default = 1.35V Includes load and line regulation. Forced PWM mode. Measure with 20 MHz bandwidth limit. Static Load. Max. Ripple based on VBAT = 3.6V, Vout = 1.35V, Fsw = 4 MHz, 2.2 μH inductor L > 1.05 μH, Cap + Board total-ESR < 20 mΩ, Cout > 1.9 μF, ESL<200 pH PWM mode peak efficiency Peak Efficiency at 200 mA load PFM mode efficiency 10 mA load current Start-up time from power VIO already ON and steady. Time from REG_ON down rising edge to CLDO reaching 1.2V. External inductor 0806 size, 2.2 µH, DCR=0.11Ω, ACR=1.18Ω @ 4 MHz External output capacitor Ceramic, X5R, 0402, ESR <30 mΩ at 4 MHz, 4.7 µF ±20%, 6.3V External input capacitor For SR_VDDBATP5V pin, ceramic, X5R, 0603, ESR < 30 mΩ at 4 MHz, ±4.7uF ±20%, 6.3V Input supply voltage ramp-up 0 to 4.3V time – a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Total capacitance includes those connected at the far end of the active load. Broadcom® November 5, 2015 • 43455-DS109-R Page 130 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet 3.3V LDO (LDO3P3) 3.3V LDO (LDO3P3) Table 45: LDO3P3 Specifications Specification Notes Input supply voltage, Vin Min. Typ. Max. Units Min. = Vo + 0.2V = 3.5V dropout voltage 3.0 requirement must be met under maximum load for performance specifications. 3.6 5.25a V Output current – 0.001 – 450 mA Nominal output voltage, Vo Default = 3.3V – 3.3 – V Dropout voltage At max. load. – – 200 mV Output voltage DC accuracy Includes line/load regulation. –5 – +5 % Quiescent current No load – – 100 μA Line regulation Vin from (Vo + 0.2V) to 5.25V, max. load – – 3.5 mV/V Load regulation load from 1 mA to 450 mA – – 0.3 mV/mA PSRR Vin ≥ Vo + 0.2V, Vo = 3.3V, Co = 4.7 μF, Max. load, 100 Hz to 100 kHz 20 – – dB LDO turn-on time Chip already powered up. – 160 250 μs External output capacitor, Co Ceramic, X5R, 0402, (ESR: 5 mΩ–240 mΩ), ± 10%, 10V 1.0b 4.7 10 μF External input capacitor For SR_VDDBATA5V pin (shared with – Bandgap) Ceramic, X5R, 0402, (ESR: 30m-200 mΩ), ± 10%, 10V. Not needed if sharing VBAT capacitor 4.7 μF with SR_VDDBATP5V. 4.7 – μF a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® November 5, 2015 • 43455-DS109-R Page 131 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet 2.5V LDO (BTLDO2P5) 2.5V LDO (BTLDO2P5) Table 46: BTLDO2P5 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage Min. = 2.5V + 0.2V = 2.7V. Dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.6 5.25a V Nominal output voltage Default = 2.5V. – 2.5 – V Output voltage programmability Range 2.2 2.5 2.8 V Accuracy at any step (including line/ load regulation), load > 0.1 mA. –5 – 5 % Dropout voltage At maximum load. – – 200 mV Output current – 0.1 – 70 mA Quiescent current No load. – 8 16 μA Maximum load at 70 mA. – 660 700 μA Leakage current Power-down mode. – 1.5 5 μA Line regulation Vin from (Vo + 0.2V) to 5.25V, maximum load. – – 3.5 mV/V Load regulation Load from 1 mA to 70 mA, Vin = 3.6V. – – 0.3 mV/mA PSRR Vin ≥ Vo + 0.2V, Vo = 2.5V, Co = 2.2 μF, 20 maximum load, 100 Hz to 100 kHz. – – dB LDO turn-on time Chip already powered up. – – 150 μs In-rush current Vin = Vo + 0.15V to 5.25V, Co = 2.2 μF, – No load. – 250 mA External output capacitor, Co Ceramic, X5R, 0402, (ESR: 5m–240 mΩ), ±10%, 10V 2.2 2.64 μF External input capacitor For SR_VDDBATA5V pin (shared with – Bandgap) ceramic, X5R, 0402, (ESR: 30–200 mΩ), ±10%, 10V. Not needed if sharing VBAT 4.7 μF capacitor with SR_VDDBATP5V. 4.7 – μF 0.7b a. The maximum continuous voltage is 5.25V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DCbias, temperature, and aging. Broadcom® November 5, 2015 • 43455-DS109-R Page 132 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet CLDO CLDO Table 47: CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output current – 0.2 – 200 mA Output voltage, Vo Programmable in 10 mV steps. Default = 1.2.V 0.95 1.2 1.26 V Dropout voltage At max. load – – 150 mV Output voltage DC accuracy Includes line/load regulation –4 – +4 % No load – 13 – μA 200 mA load – 1.24 – mA Quiescent current Line Regulation Vin from (Vo + 0.15V) to 1.5V, maximum load – – 5 mV/V Load Regulation Load from 1 mA to 300 mA – 0.02 0.05 mV/mA Leakage Current Power down – 5 20 μA Bypass mode – 1 3 μA PSRR @1 kHz, Vin ≥ 1.35V, Co = 4.7 μF 20 – – dB Start-up Time of PMU VIO up and steady. Time from the REG_ON rising edge to the CLDO reaching 1.2V. – – 700 μs LDO Turn-on Time LDO turn-on time when rest of the chip is up – 140 180 μs External Output Capacitor, Co Total ESR: 5 mΩ–240 mΩ 1.1a 2.2 – μF External Input Capacitor Only use an external input capacitor at the – VDD_LDO pin if it is not supplied from CBUCK output. 1 2.2 μF a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® November 5, 2015 • 43455-DS109-R Page 133 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet LNLDO LNLDO Table 48: LNLDO Specifications Specification Notes Input supply voltage, Vin Min. Typ. Max. Units Min. VIN = VO + 0.15V = 1.35V (where VO = 1.3 1.2V)dropout voltage requirement must be met under maximum load. 1.35 1.5 V Output Current – 0.1 – 150 mA Output Voltage, Vo Programmable in 25 mV steps. Default = 1.2V 1.1 1.2 1.275 V Dropout Voltage At maximum load – – 150 mV Output Voltage DC Accuracy Includes line/load regulation –4 – +4 % Quiescent current No load – 44 – μA Max. load – 970 990 μA Line Regulation Vin from (Vo + 0.1V) to 1.5V, 150 mA load – – 5 mV/V Load Regulation Load from 1 mA to 150 mA – 0.02 0.05 mV/mA Leakage Current Power-down – – 10 μA Output Noise @30 kHz, 60–150 mA load Co = 2.2 μF @100 kHz, 60–150 mA load Co = 2.2 μF – – 60 35 nV/rt Hz nV/rt Hz PSRR @ 1kHz, Input > 1.35V, Co= 2.2 μF, Vo = 1.2V 20 – – dB LDO Turn-on Time LDO turn-on time when rest of chip is up – 140 180 μs External Output Capacitor, Co Total ESR (trace/capacitor): 5 mΩ–240 mΩ 2.2 4.7 μF External Input Capacitor Only use an external input capacitor at the – VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ 1 2.2 μF 0.5 a a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® November 5, 2015 • 43455-DS109-R Page 134 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCIe LDO PCIe LDO Table 49: PCIe LDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. VIN = VO + 0.15V = 1.35V (where VO = 1.2V)dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 V Output Current Peak load=80 mA. Average load=35 mA 0.1 – 55 mA Output Voltage, Vo Programmable in 25 mV steps. Default = 1.2V 1.1 1.2 1.275 V Dropout Voltage At maximum load – – 150 mV Output Voltage DC Accuracy Includes line/load regulation –4 – +4 % Quiescent current No load – 10 12 μA 55 mA load – 550 570 μA Line Regulation VIN from (VO + 0.1V) to 1.5V, 150 mA load – – 5 mV/V Load Regulation Load from 1 mA to 150 mA – 0.02 0.05 mV/mA Leakage Current Power-down – 5 20 μA Bypass mode – 0.02 1.5 μA Output Noise @30 kHz, 60–150 mA load Co = 2.2 μF @100 kHz, 60–150 mA load Co = 2.2 μF – – 60 35 nV/rt Hz nV/rt Hz PSRR @ 1kHz, Input > 1.35V, Co= 2.2 μF, Vo = 1.2V 20 – – dB LDO Turn-on Time LDO turn-on time when balance of chip is up – 140 180 μs 0.47 – μF 1 2.2 μF External Output Capacitor, Co Total ESR (trace/capacitor): 5 mΩ–240 mΩ External Input Capacitor 0.27a Only use an external input capacitor at the – VDD_LDO pin if it is not supplied from CBUCK output. Total ESR (trace/capacitor): 30 mΩ–200 mΩ a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. Broadcom® November 5, 2015 • 43455-DS109-R Page 135 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet System Power Consumption Section 19: System Power Consumption Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization. Note: Unless otherwise stated, these values apply for the conditions specified in Table 27: “Recommended Operating Conditions and DC Characteristics,” on page 99. WLAN Current Consumption The tables in this subsection show the typical, total current consumed by the BCM43455. All values shown are with the Bluetooth core in reset mode with Bluetooth off. 2.4 GHz Mode Table 50: 2.4 GHz Mode WLAN Power Consumption VBAT = 3.6V, VDDIO = 1.8V, TA25°C VBAT, mA VIO, uAa Radio off b 0.006 5 Sleep c 0.020 200 IEEE Power Save: DTIM = 1, single RX d 1.25 200 IEEE Power Save: DTIM = 3, single RX 0.45 200 Continuous RX mode: MCS7, HT20, 1SS e, f 55 60 CRS: HT20 g 50 60 Mode Sleep Modes Active RX Modes Broadcom® November 5, 2015 • 43455-DS109-R Page 136 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet WLAN Current Consumption Table 50: 2.4 GHz Mode WLAN Power Consumption (Cont.) VBAT = 3.6V, VDDIO = 1.8V, TA25°C VBAT, mA VIO, uAa 400 60 Continuous TX mode: MCS7, HT20, 1SS, 1 TX @ 19 dBm h 350 60 Mode Active TX Modes – Internal PA Continuous TX mode: 1 Mbps @ 21.5 dBm h a. b. c. d. e. f. g. h. VIO is specified with all pins idle (not switching) and not driving any loads. WL_REG_ON and BT_REG_ON are both low. All supplies are present. Idle, not associated, or inter-beacon. Beacon Interval = 102.4 ms. Beacon duration = 1 ms @ 1 Mbps. Average current over 3× DTIM intervals. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. Measured using packet engine test mode. Carrier sense (CCA) when no carrier present. Duty cycle is 100%. 5 GHz Mode Table 51: 5 GHz Mode WLAN Power Consumption VBAT = 3.6V, VDDIO = 1.8V, TA25°C VBAT , mA VIO, uAa 0.006 5 0.025 200 1.1 200 0.4 200 Continuous RX mode: MCS7, HT20, 1SS e, f 74 60 Continuous RX mode: MCS7, HT40, 1SS e, f 82 60 Continuous RX mode: MCS9, HT40, 1SS e, f 86 60 Continuous RX mode: MCS9, HT80, 1SS e, f 117 60 CRS: HT20 g 70 60 g 79 60 100 60 Continuous TX mode: MCS7, HT20, 1SS, 1 TX @ 19 dBm h 330 Continuous TX mode: MCS7, HT40, 1SS, 1 TX @ 19 dBm h 340 60 Continuous TX mode: MCS9, HT40, 1SS, 1 TX @ 16 dBm h 270 Continuous TX mode: MCS9, HT80, 1SS, 1 TX @ 16 dBm h 270 60 Mode Sleep Modes Radio off b Sleep c IEEE Power Save: DTIM = 1, single RX IEEE Power Save: DTIM = 3, single RX d Active RX Modes CRS: HT40 CRS: HT80 g Active TX Modes – Internal PA Broadcom® November 5, 2015 • 43455-DS109-R 60 60 Page 137 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet a. b. c. d. e. f. g. h. Bluetooth Current Consumption VIO is specified with all pins idle (not switching) and not driving any loads. WL_REG_ON and BT_REG_ON are both low. All supplies present. Idle, not associated, or inter-beacon. Beacon Interval = 102.4 ms. Beacon duration = 1ms @ 1Mbps. Average current over 3x DTIM intervals. Duty cycle is 100%. Carrier sense (CS) detect/packet receive. Measured using packet engine test mode. Carrier sense (CCA) when no carrier present. Duty cycle is 100%. Bluetooth Current Consumption The Bluetooth and BLE current consumption measurements are shown in Table 52. Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 52. Note: The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. Table 52: Bluetooth and BLE Current Consumption Operating Mode VBAT VDDIO Units Sleep Standard 1.28s Inquiry Scan 500 ms Sniff Master DM1/DH1 Master DM3/DH3 Master DM5/DH5 Master 3DH5/3DH1 Master SCO HV3 Master 6 153 216 23.9 29.1 29.8 24.8 11.5 179 295 294 291 0.155 0.164 0.166 0.210 0.166 296 µA µA µA mA mA mA mA mA µA 295 146 µA µA BLE Scana BLE Adv—Unconnectable 1.00 sec 69 BLE Connected 1 sec 1960 a. No devices present. A 1.28 second interval with a scan window of 11.25 ms. Broadcom® November 5, 2015 • 43455-DS109-R Page 138 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Interface Timing and AC Characteristics S e c t i o n 2 0 : I n t e r f a c e Ti m i n g a n d A C C h a r a c t e ri s t i c s SDIO Timing SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 34 and Table 53. Figure 34: SDIO Bus Timing (Default Mode) fPP tWL tWH SDIO_CLK tTHL tTLH tISU tIH Input Output tODLY tODLY (max) (min) Table 53: SDIO Bus Timinga Parameters (Default Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (All values are referred to minimum VIH and maximum VILb) Frequency – Data Transfer mode fPP 0 – 25 MHz Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock low time tTHL – – 10 ns Broadcom® November 5, 2015 • 43455-DS109-R Page 139 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing Table 53: SDIO Bus Timinga Parameters (Default Mode) (Cont.) Parameter Symbol Minimum Typical Maximum Unit Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 5 – – ns Input hold time tIH 5 – – ns Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns Outputs: CMD, DAT (referenced to CLK) a. Timing is based on CL 40 pF load on CMD and Data. b. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO. Broadcom® November 5, 2015 • 43455-DS109-R Page 140 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 35 and Table 54. Figure 35: SDIO Bus Timing (High-Speed Mode) fPP tWL tWH 50% VDD SDIO_CLK tTHL tISU tTLH tIH Input Output tODLY tOH Table 54: SDIO Bus Timinga Parameters (High-Speed Mode) Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (all values are referred to minimum VIH and maximum VILb) Frequency – Data Transfer Mode fPP 0 – 50 MHz Frequency – Identification Mode fOD 0 – 400 kHz Clock low time tWL 7 – – ns Clock high time tWH 7 – – ns Clock rise time tTLH – – 3 ns Clock low time tTHL – – 3 ns Inputs: CMD, DAT (referenced to CLK) – – – – – Input setup Time tISU 6 – – ns Input hold Time tIH 2 – – ns Outputs: CMD, DAT (referenced to CLK) – – – – – Output delay time – Data Transfer Mode tODLY – – 14 ns Output hold time tOH 2.5 – – ns Total system capacitance (each line) CL – – 40 pF a. Timing is based on CL 40 pF load on CMD and Data. b. Min (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO. Broadcom® November 5, 2015 • 43455-DS109-R Page 141 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing SDIO Bus Timing Specifications in SDR Modes Clock Timing Figure 36: SDIO Clock Timing (SDR Modes) tCLK SDIO_CLK tCR tCF tCR Table 55: SDIO Bus Clock Timing Parameters (SDR Modes) Parameter Symbol Minimum Maximum Unit Comments – tCLK 40 – ns SDR12 mode 20 – ns SDR25 mode 10 – ns SDR50 mode 4.8 – ns SDR104 mode – tCR, tCF – 0.2 × tCLK ns tCR, tCF < 2.00 ns (max) @ 100 MHz, CCARD = 10 pF tCR, tCF < 0.96 ns (max) @ 208 MHz, CCARD = 10 pF Clock duty cycle – 30 70 % – Broadcom® November 5, 2015 • 43455-DS109-R Page 142 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing Card Input Timing Figure 37: SDIO Bus Input Timing (SDR Modes) SDIO_CLK tIS tIH CMD input DAT[3:0] input Table 56: SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments tIS 1.4 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V tIS 3.00 – ns CCARD = 10 pF, VCT = 0.975V tIH 0.8 – ns CCARD = 5 pF, VCT = 0.975V SDR104 Mode SDR50 Mode Broadcom® November 5, 2015 • 43455-DS109-R Page 143 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing Card Output Timing Figure 38: SDIO Bus Output Timing (SDR Modes up to 100 MHz) tCLK SDIO_CLK tODLY tOH CMD input DAT[3:0] input Table 57: SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments tODLY – 7.5 ns tCLK ≥ 10 ns CL= 30 pF using driver type B for SDR50 tODLY – 14.0 ns tCLK ≥ 20 ns CL= 40 pF using for SDR12, SDR25 tOH 1.5 – ns Hold time at the tODLY (min) CL= 15 pF Figure 39: SDIO Bus Output Timing (SDR Modes 100 MHz to 208 MHz) tCLK SDIO_CLK tOP tODW CMD input DAT[3:0] input Broadcom® November 5, 2015 • 43455-DS109-R Page 144 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing Table 58: SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit Comments tOP 0 2 UI Card output phase ∆tOP –350 +1550 ps Delay variation due to temp change after tuning tODW 0.60 – UI tODW = 2.88 ns @ 208 MHz • ∆tOP = +1550 ps for junction temperature of ∆tOP = 90°C during operation. • ∆tOP = –350 ps for junction temperature of ∆tOP = –20°C during operation. • ∆tOP = +2600 ps for junction temperature of ∆tOP = –20°C to +125°C during operation. Figure 40: ∆tOP Consideration for Variable Data Window (SDR 104 Mode) Data valid window Sampling point after tuning ǻtOP = 1550 ps ǻtOP = –350 ps Data valid window Sampling point after card junction heating by +90°C from tuning temperature Data valid window Sampling point after card junction cooling by –20°C from tuning temperature Broadcom® November 5, 2015 • 43455-DS109-R Page 145 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing SDIO Bus Timing Specifications in DDR50 Mode Figure 41: SDIO Clock Timing (DDR50 Mode) tCLK SDIO_CLK tCR tCF tCR Table 59: SDIO Bus Clock Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments – tCLK 20 – ns DDR50 mode – tCR,tCF – 0.2 × tCLK ns tCR, tCF < 4.00 ns (max) @50 MHz, CCARD = 10 pF Clock duty cycle – 45 55 % – Broadcom® November 5, 2015 • 43455-DS109-R Page 146 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet SDIO Timing Data Timing Figure 42: SDIO Data Timing (DDR50 Mode) FPP SDIO_CLK tISU2x DAT[3:0] input Invalid tIH2x tISU2x Data Invalid Data tODLY2x (max) tODLY2x Invalid tODLY2x (min) DAT[3:0] output tIH2x Data Invalid tODLY2x (max) (min) Data Available timing window for card output transition Data Data Available timing window for host to sample data from card In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line) Table 60: SDIO Bus Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments Input setup time tISU 6 – ns CCARD < 10 pF (1 Card) Input hold time tIH 0.8 – ns CCARD < 10 pF (1 Card) Output delay time tODLY – 13.7 ns CCARD < 30 pF (1 Card) Output hold time tOH 1.5 – ns CCARD < 15 pF (1 Card) Input setup time tISU2x 3 – ns CCARD < 10 pF (1 Card) Input hold time tIH2x 0.8 – ns CCARD < 10 pF (1 Card) Output delay time tODLY2x – 7.5 ns CCARD < 25 pF (1 Card) Output hold time tODLY2x 1.5 – ns CCARD < 15 pF (1 Card) Input CMD Output CMD Input DAT Output DAT Broadcom® November 5, 2015 • 43455-DS109-R Page 147 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCI Express Interface Parameters PCI Express Interface Parameters Table 61: PCI Express Interface Parameters Parameter Symbol Comments Minimum Typical Maximum Unit Baud rate BPS – – 5 – Gbau d Reference clock amplitude Vref LVPECL, AC coupled 1 – – V General Receiver Differential termination ZRX-DIFF-DC Differential termination 80 100 120 Ω DC impedance ZRX-DC DC common-mode impedance 50 60 Ω Powered down termination (POS) ZRX-HIGH-IMP-DCPOS Power-down or RESET 100k high impedance – – Ω Powered down termination (NEG) ZRX-HIGH-IMP-DCNEG Power-down or RESET 1k high impedance – – Ω Input voltage VRX-DIFFp-p AC coupled, differential 175 p-p – – mV Jitter tolerance TRX-EYE Minimum receiver eye 0.4 width – – UI Differential return loss RLRX-DIFF Differential return loss – – dB Common-mode return RLRX-CM loss Common-mode return 6 loss – – dB – Unexpected electrical TRX-IDEL-DET-DIFF- An unexpected ENTERTIME electrical idle must be idle enter detect recognized no longer threshold integration than this time to signal time an unexpected idle condition. – 10 ms Signal detect threshold VRX-IDLE-DETDIFFp-p 40 10 Electrical idle detect threshold 65 – 175 mV – 1200 mV Transmitter Output voltage VTX-DIFFp-p Differential p-p, programmable in 16 steps 0.8 Output voltage rise time VTX-RISE 20% to 80% 0.125 – (2.5 GT/s) 0.15 (5 GT/s) – UI Output voltage fall time VTX-FALL 80% to 20% – 0.125 (2.5 GT/s) 0.15 (5 GT/s) – UI Broadcom® November 5, 2015 • 43455-DS109-R Page 148 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet PCI Express Interface Parameters Table 61: PCI Express Interface Parameters (Cont.) Parameter Symbol Comments RX detection voltage swing VTX-RCV-DETECT The amount of voltage – change allowed during receiver detection. – 600 mV TX AC peak common- VTX-CM-AC-PP mode voltage (5 GT/s) TX AC common mode – voltage (5 GT/s) – 100 mV TX AC peak common- VTX-CM-AC-P mode voltage (2.5 GT/s) TX AC common mode – voltage (2.5 GT/s) – 20 mV 0 Absolute delta of DC VTX-CM-DC-ACTIVE- Absolute delta of DC IDLE-DELTA common-model voltage common-model during L0 and electrical voltage during L0 and idle. electrical idle – 100 mV Absolute delta of DC common-model voltage between D+ and D- – 25 mV VTX-CM-DC-LINEDELTA Minimum Typical Maximum Unit DC offset between D+ 0 and D- Electrical idle VTX-IDLE-DIFF-AC-p Peak-to-peak voltage differential peak output voltage 0 – 20 mV TX short circuit current ITX-SHORT Current limit when TX output is shorted to ground. – – 90 mA DC differential TX termination ZTX-DIFF-DC Low impedance defined 80 during signaling (parameter is captured for 5.0 GHz by RLTXDIFF) – 120 Ω Differential return loss RLTX-DIFF Differential return loss – dB Common-mode return loss RLTX-CM Common-mode return 6 loss – – dB TX eye width TTX-EYE Minimum TX eye width – – UI Broadcom® November 5, 2015 • 43455-DS109-R 10 (min.) – for 0.05: 1.25 GHz 8 (min.) for 1.25: 2.5 GHz 0.75 Page 149 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet JTAG Timing JTAG Timing Table 62: JTAG Timing Characteristics Signal Name Period Output Maximum Output Minimum Setup Hold TCK 125 ns – – – – TDI – – – 20 ns 0 ns TMS – – – 20 ns 0 ns TDO – 100 ns 0 ns – – JTAG_TRST 250 ns – – – – SWD Timing The probe outputs data to SWDIO on the falling edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK. The target outputs data to SWDIO on the rising edge of SWDCLK and captures data from SWDIO on the rising edge of SWDCLK. SWD timing is defined through the combination of Figure 43 and Table 63. Figure 43: SWD Read and Write Timing Read Cycle RVI probe output to SWDIO Thigh Tlow Stop Park TOS Tri-State Data Data Parity Start RVI probe output to SWDCLK Target output to SWDIO Tri-State Acknowledge Tri-State Write Cycle RVI probe output to SWDIO Stop Park Tri-State Tih Tis Start RVI probe output to SWDCLK Target output to SWDIO Tri-State Acknowledge Data Data Parity Tri-State Table 63: SWD Read and Write Timing Parameters Parameter Description Min. Max. Units Tcyc SWDCLK cycle time 125 – ns Thigh SWDCLK high period 50 – ns Tlow SWDCLK low period 50 – ns Tos SWDIO output skew to the falling edge of SWDCLK –5 5 ns Tis Input setup time between SWDIO and the rising edge of SWDCLK 20 – ns Tih Input hold time between SWDIO and the rising edge of SWDCLK 0 100 ns Broadcom® November 5, 2015 • 43455-DS109-R Page 150 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Power-Up Sequence and Timing Section 21: Power-Up Sequence and Ti m i n g Sequencing of Reset and Regulator Control Signals The BCM43455 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 44, Figure 45 on page 152, and Figure 46 on page 153 and Figure 47 on page 153). The timing values indicated are minimum required values; longer delays are also acceptable. Description of Control Signals • WL_REG_ON: Used by the PMU to power-up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal BCM43455 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. • BT_REG_ON: Used by the PMU (OR-gated with WL_REG_ON) to power-up the internal BCM43455 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. Note: For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. Note: The BCM43455 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold. Wait at least 150 ms after VDDC and VDDIO are available before initiating PCIe accesses. Note: VBAT should not rise 10%–90% faster than 40 microseconds. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Broadcom® November 5, 2015 • 43455-DS109-R Page 151 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Sequencing of Reset and Regulator Control Signals Control Signal Timing Diagrams Figure 44: WLAN = ON, Bluetooth = ON 32.678 kHz Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 45: WLAN = OFF, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT* VDDIO WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Broadcom® November 5, 2015 • 43455-DS109-R Page 152 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Sequencing of Reset and Regulator Control Signals Figure 46: WLAN = ON, Bluetooth = OFF 32.678 kHz Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Figure 47: WLAN = OFF, Bluetooth = ON 32.678 kHz Sleep Clock VBAT* 90% of VH VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds. 2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Broadcom® November 5, 2015 • 43455-DS109-R Page 153 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Package Information Section 22: Package Information Package Thermal Characteristics Table 64: Package Thermal Characteristicsa Characteristic WLBGA JA (°C/W) (value in still air) 38.73 JB (°C/W) 1.97 JC (°C/W) 3.16 JT (°C/W) 9.3 JB (°C/W) 16.21 Maximum Junction Temperature Tj (°C) 123.6 Maximum Power Dissipation (W) 1.38 a. No heat sink, TA = 70°C. This is an estimate, based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm × 101.6 mm × 1.6 mm) and P = 1.119W continuous dissipation. Junction Temperature Estimation and PSIJT Versus THETAJC Package thermal characterization parameter PSI–JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta–JC (JC). The reason for this is that JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is: TJ = TT + P x JT Where: • TJ = Junction temperature at steady-state condition (°C) • TT = Package case top center temperature at steady-state condition (°C) • P = Device power dissipation (Watts) • JT = Package thermal characteristics; no airflow (°C/W) Environmental Characteristics For environmental characteristics data, see Table 25: “Environmental Ratings,” on page 98. Broadcom® November 5, 2015 • 43455-DS109-R Page 154 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Mechanical Information Section 23: Mechanical Information Figure 48: 140-Ball WLBGA Package Mechanical Information Broadcom® November 5, 2015 • 43455-DS109-R Page 155 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Mechanical Information Figure 49: 140-Balls WLBGA Keep-out Areas for PCB Layout—Top View with Balls Facing Down Keep out # Horizental (mm) vertical (mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0.11 0.11 0.09 0.09 0.12 0.12 0.08 0.08 0.08 0.08 0.20 0.20 0.15 0.15 0.14 0.14 0.17 0.14 0.05 0.05 0.15 0.15 0.27 0.27 0.16 0.16 0.15 0.15 0.18 0.18 0.13 0.10 0.13 0.13 0.13 0.13 0.18 0.18 0.08 0.08 0.14 0.18 0.10 0.10 0.07 0.07 0.07 0.07 Note: No top-layer metal is allowed in keep-out areas. Note: A DXF file for the WLBGA keep-out area is available for importation into a layout program. Contact your Broadcom FAE for more information. Broadcom® November 5, 2015 • 43455-DS109-R Page 156 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Ordering Information S e c t i o n 2 4 : O rd e r i n g I n f o r m a t i o n Table 65: Part Ordering Information Operating Ambient Temperature Part Number Package Description BCM43455XKUBG 140-ball WLBGA (4.47 mm × 5.27 mm, 0.4 mm pitch) Dual-band 2.4 GHz and 5 GHz WLAN+ BT 4.1 + FMRX –30°C to +85°C BCM43455HKUBG 140-ball WLBGA (4.47 mm × 5.27 mm, 0.4 mm pitch) Dual-band 2.4 GHz and 5 GHz WLAN + BT 4.1 + FMRX, BSP –30°C to +85°C Broadcom® November 5, 2015 • 43455-DS109-R Page 157 BROADCOM CONFIDENTIAL BCM43455 Preliminary Data Sheet Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. ® Broadcom Corporation 5300 California Avenue Irvine, CA 92617 © 2015 by BROADCOM CORPORATION. All rights reserved. 43455-DS109-R November 5, 2015 Phone: 949-926-5000 Fax: 949-926-5203 E-mail: [email protected] Web: www.broadcom.com