CSD88539ND SLPS456 – FEBRUARY 2014 CSD88539ND, Dual 60 V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • 1 Product Summary Ultra-Low Qg and Qgd Avalanche Rated Pb Free RoHS Compliant Halogen Free TA = 25°C 2 Applications • • TYPICAL VALUE Drain-to-Source Voltage 60 V Qg Gate Charge Total (10 V) 7.2 nC Qgd Gate Charge Gate to Drain RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage Half Bridge for Motor Control Synchronous Buck Converter 1.1 This dual SO-8, 60 V, 23 mΩ NexFET™ power MOSFET is designed to serve as a half bridge in lowcurrent motor control applications. 27 mΩ VGS = 10 V 23 mΩ 3.0 Top View 8 2 G1 7 3 S2 6 4 G2 V Device Qty Media Package Ship CSD88539ND 2500 13-Inch Reel CSD88539NDT 250 7-Inch Reel SO-8 Plastic Package Tape and Reel Absolute Maximum Ratings TA = 25°C 1 nC VGS = 6 V Ordering Information 3 Description S1 UNIT VDS 5 D1 VALUE UNIT VDS Drain-to-Source Voltage 60 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 15 ID Continuous Drain Current (Silicon limited), TC = 25°C 11.7 (1) Continuous Drain Current D1 D2 D2 A 6.3 IDM Pulsed Drain Current (2) 46 A PD Power Dissipation(1) 2.1 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 22 A, L = 0.1 mH, RG = 25 Ω 24 mJ (1) Typical RθJA = 60°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB (2) Pulse duration ≤ 300 μs, duty cycle ≤ 2% RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 5A TC = 125°C, I D = 5A 54 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 60 48 42 36 30 24 18 12 6 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 5A VDS = 30V 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 Qg - Gate Charge (nC) 6 7 8 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD88539ND SLPS456 – FEBRUARY 2014 www.ti.com 4 Specifications 4.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 48 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 60 2.6 V 3.0 3.6 V VGS = 6 V, ID = 5 A 27 34 mΩ VGS = 10 V, ID = 5 A 23 28 mΩ VDS = 30 V, ID = 5 A 19 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (10 V) Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = 30 V, f = 1 MHz VDS = 30 V, ID = 5 A VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 10 V, IDS = 5 A, RG = 0 Ω 570 741 pF 70 91 pF 2.0 2.6 pF 6.6 13.2 Ω 7.2 9.4 nC 1.1 nC 2.7 nC 1.8 nC 9.6 nC 5 ns 9 ns 14 ns 4 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 5 A, VGS = 0 V 0.8 VDS= 30 V, IF = 5A, di/dt = 300A/μs 1 V 37 nC 21 ns 4.2 Thermal Characteristics (TA = 25°C unless otherwise stated) MAX UNIT RθJL Junction-to-Lead Thermal Resistance (1) PARAMETER 20 °C/W RθJA Junction-to-Ambient Thermal Resistance (1) (2) 75 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND CSD88539ND www.ti.com SLPS456 – FEBRUARY 2014 4.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) 50 40 45 36 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) Figure 1. Transient Thermal Impedance 40 35 30 25 20 15 VGS =10V VGS =8V VGS =6V 10 5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS - Drain-to-Source Voltage (V) 1.8 2 VDS = 5V 32 28 24 20 16 12 TC = 125°C TC = 25°C TC = −55°C 8 4 0 0 G001 Figure 2. Saturation Characteristics 1 2 3 4 VGS - Gate-to-Source Voltage (V) 5 Product Folder Links: CSD88539ND G001 Figure 3. Transfer Characteristics Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated 6 3 CSD88539ND SLPS456 – FEBRUARY 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 5A VDS = 30V 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 10 2 1 0 0 1 2 3 4 5 Qg - Gate Charge (nC) 6 7 1 8 0 6 12 G001 Figure 4. Gate Charge RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 60 G001 60 ID = 250uA 3.4 3.2 3 2.8 2.6 2.4 2.2 2 −75 −25 25 75 125 TC - Case Temperature (ºC) 42 36 30 24 18 12 6 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage 100 ISD − Source-to-Drain Current (A) VGS = 6V VGS = 10V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 48 G001 Figure 6. Threshold Voltage vs Temperature 2 TC = 25°C, I D = 5A TC = 125°C, I D = 5A 54 0 175 2.2 Normalized On-State Resistance 54 Figure 5. Capacitance 3.6 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID = 5A −25 25 75 125 TC - Case Temperature (ºC) 175 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs Temperature 4 18 24 30 36 42 48 VDS - Drain-to-Source Voltage (V) 1 G001 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND CSD88539ND www.ti.com SLPS456 – FEBRUARY 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 10us 100us 1ms 10ms DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 Single Pulse Max RthetaJL = 20ºC/W 0.1 0.1 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25ºC TC = 125ºC 10 1 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 18 15 12 9 6 3 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND 5 CSD88539ND SLPS456 – FEBRUARY 2014 www.ti.com 5 Mechanical Data 5.1 SO-8 Package Dimensions 1. All linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.006 (0,15) each side. 4. Body width does not include interlead flash. Interlead flas shall not exceed 0.017 (0,43) each side. 5. Reference JEDEC MS-012 variation AA. 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND CSD88539ND www.ti.com SLPS456 – FEBRUARY 2014 5.2 Recommended PCB Pattern and Stencil Opening 1. 2. 3. 4. All linear dimensions are in millimeters. This drawing is subject to change without notice. Publication IPC-7351 is recommended for alternate designs. Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste release. Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525 for other stencil recommendations. 5. Customers should contact their board fabrication site for solder mask tolerances between and around signal pads. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND 7 CSD88539ND SLPS456 – FEBRUARY 2014 www.ti.com 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD88539ND PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD88539ND ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 88539N CSD88539NDT ACTIVE SOIC D 8 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 88539N (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CSD88539ND SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 CSD88539NDT SOIC D 8 250 178.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD88539ND SOIC D 8 2500 336.6 336.6 41.3 CSD88539NDT SOIC D 8 250 210.0 210.0 52.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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