TI1 LM21215AMHX-1 Lm21215a-1 15a high efficiency synchronous buck regulator with frequency synchronization Datasheet

LM21215A
LM21215A-1 15A High Efficiency Synchronous Buck Regulator with Frequency
Synchronization
Literature Number: SNOSB87A
LM21215A-1
15A High Efficiency Synchronous Buck Regulator with
Frequency Synchronization
General Description
The LM21215A-1 is a monolithic synchronous buck regulator
that is capable of delivering up to 15A of continuous output
current while producing an output voltage down to 0.6V with
outstanding efficiency. The device is optimized to work over
an input voltage range of 2.95V to 5.5V, making it suited for
a wide variety of low voltage systems. The voltage mode control loop provides high noise immunity, narrow duty cycle
capability and can be compensated to be stable with any type
of output capacitance, providing maximum flexibility and ease
of use.
The LM21215A-1 features internal over voltage protection
(OVP) and over-current protection (OCP) for increased system reliability. A precision enable pin and integrated UVLO
allow turn-on of the device to be tightly controlled and sequenced. Startup inrush currents are limited by both an internally fixed and externally adjustable soft-start circuit. Fault
detection and supply sequencing are possible with the integrated power good circuit.
The LM21215A-1 is designed to work well in multi-rail power
supply architectures. The output voltage of the device can be
configured to track an external voltage rail using the SS/TRK
pin. The switching frequency can be synchronized to the
falling edge of a clock between frequencies of 300kHz to
1.5MHz.
If the output is pre-biased at startup, it will not sink current,
allowing the output to smoothly rise past the pre-biased voltage. The regulator is offered in a 20-pin eTSSOP package
with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks.
Features
■ Integrated 7.0 mΩ high side and 4.3 mΩ low side FET
switches
■ 300 kHz to 1.5 MHz frequency SYNC pin
■ Adjustable output voltage from 0.6V to VIN (100% duty
■
■
■
■
■
■
■
■
cycle capable), ±1% reference
Input voltage range 2.95V to 5.5V
Startup into pre-biased loads
Output voltage tracking capability
Wide bandwidth voltage loop error amplifier
Adjustable soft-start with external capacitor
Precision enable pin with hysteresis
Integrated OVP, OCP, OTP, UVLO and Power-Good
Thermally Enhanced eTSSOP-20 exposed pad package
Applications
■ Broadband, networking and wireless communications
■ High-performance FPGAs, ASICs and microprocessors
■ Simple to design, high efficiency point of load regulation
from a 5V or 3.3V bus
Simplified Application Circuit
30152101
PowerWise® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301521
www.national.com
LM21215A-1 15A High Efficiency Synchronous Buck Regulator
March 27, 2011
LM21215A-1
Connection Diagram
30152102
Top View
eTSSOP-20 Package
Ordering Information
Order Number
Package Type
NSC Package Drawing
Package Marking
Supplied As
LM21215AMH-1
eTSSOP-20
MYB20A
LM21215AMH-1
73 Units per Rail
LM21215AMHX-1
eTSSOP-20
MYB20A
LM21215AMH-1
2500 Units Per Reel
LM21215AMHE-1
eTSSOP-20
MYB20A
LM21215AMH-1
250 Units Per Reel
Pin Descriptions
Pins
Name
Description
1
SYNC
Frequency Synchronization input pin. Applying a clock signal to this pin will force
the device to switch at the clock frequency. If left unconnected, the frequency will
default to 500 kHz.
2
SS/TRK
Soft-start control pin. An internal 2 µA current source charges an external capacitor
connected between this pin and AGND to set the output voltage ramp rate during
startup. This pin can also be used to configure the tracking feature.
3
EN
4
AVIN
Analog input voltage supply that generates the internal bias. It is recommended to
connect PVIN to AVIN through a low pass RC filter to minimize the influence of
input rail ripple and noise on the analog control circuitry.
5,6,7
PVIN
Input voltage to the power switches inside the device. These pins should be
connected together at the device. A low ESR input capacitance should be located
as close as possible to these pins.
8,9,10
PGND
Power ground pins for the internal power switches.
11-16
SW
17
PGOOD
18
COMP
19
FB
20
AGND
EP
Exposed Pad
www.national.com
Active high enable input for the device. If not used, the EN pin can be left open,
which will go high due to an internal current source.
Switch node pins. These pins should be tied together locally and connected to the
filter inductor.
Open-drain power good indicator.
Compensation pin is connected to the output of the voltage loop error amplifier.
Feedback pin is connected to the inverting input of the voltage loop error amplifier.
Quiet analog ground for the internal reference and bias circuitry.
Exposed metal pad on the underside of the package with an electrical and thermal
connection to PGND. It is recommended to connect this pad to the PC board
ground plane in order to improve thermal dissipation.
2
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN(Note 2), AVIN to GND
SW(Note 3), EN, FB, COMP,
PGOOD, SS/TRK to GND
Storage Temperature
Soldering Specification for
TSSOP Pb-Free Infrared or
Convection (30 sec)
2kV
Operating Ratings
(Note 1)
PVIN, AVIN to GND
Junction Temperature
−0.3V to +6V
−0.3V to PVIN + 0.3V
+2.95V to +5.5V
−40°C to +125°C
24°C/W
θJA(Note 5)
−65°C to 150°C
260°C
Electrical Characteristics
Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in
standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of −40°C to +125°C.
Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
Symbol
Parameter
Conditions
Min
Feedback pin voltage
VIN = 2.95V to 5.5V
-1%
Typ
Max
0.6
1%
Units
SYSTEM
VFB
ΔVOUT/ΔIOUT
Load Regulation
ΔVOUT/ΔVIN Line Regulation
RDSON HS
High Side Switch On Resistance
ISW = 12A
RDSON LS
Low Side Switch On Resistance
ISW = 12A
ICLR
HS Rising Switch Current Limit
ICLF
LS Falling Switch Current Limit
VZX
Zero Cross Voltage
Shutdown Quiescent Current
VEN = 0V
VUVLO
AVIN Under Voltage Lockout
AVIN Rising
VTRACKOS
SS/TRACK PIN accuracy (VSS - VFB)
ISS
0 < VTRACK < 0.55V
Soft-Start Pin Source Current
tINTSS
Internal Soft-Start Ramp to Vref
tRESETSS
Device Reset to Soft-Start Ramp
%VOUT/
V
mΩ
4.3
6.0
mΩ
20
22.8
A
3
12
mV
1.5
3.0
mA
50
70
µA
2.45
2.70
2.95
V
140
200
280
mV
14
Operating Quiescent Current
AVIN Under Voltage Lockout Hysteresis
0.1
9.0
-8
IQ
VUVLOHYS
%VOUT/
A
7.0
17.3
ISD
CSS = 0
V
0.02
A
-10
6
20
mV
1.3
1.9
2.5
µA
350
500
675
µs
50
110
200
µs
1500
kHz
525
kHz
OSCILLATOR
SYNC Frequency Range
300
fDEFAULT
fSYNCR
Default (no SYNC signal) Frequency
475
tSY_SW
Time from SYNC falling to VSW Rising
200
ns
tSY_MIN
Minimum SYNC pin pulse width, high or low
100
ns
500
tHSBLANK
HS OCP Blanking Time
Rising edge of SW to ICLR
comparison
55
ns
tLSBLANK
LS OCP Blanking Time
Falling edge of SW to ICLF
comparison
400
ns
tZXBLANK
Zero Cross Blanking Time
Falling edge of SW to VZX
comparison
120
ns
Minimum HS on-time
140
ns
PWM Ramp p-p Voltage
0.8
V
95
dBV/V
11
MHz
tMINON
ΔVramp
ERROR AMPLIFIER
VOL
Error Amplifier Open Loop Voltage Gain
GBW
Error Amplifier Gain-Bandwidth Product
ICOMP = -65µA to 1mA
3
www.national.com
LM21215A-1
ESD Rating
Human Body Model (Note 4)
Absolute Maximum Ratings (Note 1)
LM21215A-1
Symbol
Parameter
Conditions
Feedback Pin Bias Current
VFB = 0.6V
Min
Typ
Max
Units
SYSTEM
1
nA
ICOMPSRC
IFB
COMP Output Source Current
1
mA
ICOMPSINK
COMP Output Sink Current
65
µA
POWERGOOD
VOVP
VOVPHYS
VUVP
VUVPHYS
Over Voltage Protection Rising Threshold
VFB Rising
Over Voltage Protection Hysteresis
VFB Falling
Under Voltage Protection Rising Threshold
VFB Rising
Under Voltage Protection Hysteresis
VFB Falling
tPGDGL
PGOOD Deglitch Low (OVP/UVP Condition
Duration to PGOOD Falling)
tPGDGH
PGOOD Deglitch High (minimum low pulse)
RPGOOD
PGOOD Pull-down Resistance
IPGOODLEAK
PGOOD Leakage Current
105
112.5
120
2
82
90
%VFB
97
VPGOOD = 5V
%VFB
2.5
%VFB
15
µs
12
10
%VFB
20
µs
40
1
Ω
nA
LOGIC
VIHSYNC
SYNC Pin Logic High
VILSYNC
SYNC Pin Logic Low
VIHENR
EN Pin Rising Threshold
VENHYS
EN Pin Hysteresis
IEN
EN Pin Pullup Current
2.0
V
0.8
VEN Rising
VEN = 0V
V
1.20
1.35
1.45
V
50
110
180
mV
2
µA
165
°C
10
°C
THERMAL SHUTDOWN
TTHERMSD
Thermal Shutdown
TTHERMSDHYS Thermal Shutdown Hysteresis
Note 1: Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: The PVIN pin can tolerate transient voltages up to 6.5 V for a period of up to 6ns. These transients can occur during the normal operation of the device.
Note 3: The SW pin can tolerate transient voltages up to 9.0 V for a period of up to 6ns, and -1.0V for a duration of 4ns. These transients can occur during the
normal operation of the device.
Note 4: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor to each pin.
Note 5: Thermal measurements were performed on a 2x2 inch, 4 layer, 2 oz. copper outer layer, 1 oz.copper inner layer board with twelve 8 mil. vias underneath
the EP of the device and an additional sixteen 8 mil. vias under the unexposed package.
www.national.com
4
Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH
(1.8mΩ RDCR), CSS = 33nF, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all
others.
Efficiency
100
100
FSW = 500 kHz
FSW = 750 kHz
FSW = 1 MHz
98
96
94
92
90
88
86
94
92
90
88
86
84
84
82
82
80
80
0
VOUT = 1.2V
VOUT = 3.3V
98
EFFICIENCY (%)
96
EFFICIENCY (%)
Efficiency
3
6
9
12
OUTPUT CURRENT (A)
15
0
3
6
9
12
OUTPUT CURRENT (A)
15
30152153
30152156
Efficiency
(VOUT = 2.5 V, fSW= 500 kHz , Inductor P/N SER2010-601MLD)
Load Regulation
0.04
100
Δ OUTPUT VOLTAGE (%)
0.03
EFFICIENCY (%)
98
96
94
VIN = 3.3V
VIN = 4.0V
VIN = 5.0V
VIN = 5.5V
92
90
0
3
6
9
12
OUTPUT CURRENT (A)
0.02
0.01
0.00
-0.01
-0.02
VIN = 3.3V
VIN = 5.0V
-0.03
-0.04
15
0
3
6
9
12
OUTPUT CURRENT (A)
15
30152154
30152177
Line Regulation
Non-Switching IQTOTAL vs. VIN
0.10
1.5
0.06
1.4
0.04
IPVIN + IAVIN (mA)
Δ OUTPUT VOLTAGE (%)
0.08
0.02
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
3.0
1.2
1.1
IOUT = 0A
IOUT = 12A
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
1.3
1.0
3.0
5.5
30152155
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
30152157
5
www.national.com
LM21215A-1
Typical Performance Characteristics
0.602
0.172
1.14
0.164
1.11
0.156
1.08
0.148
1.05
0.140
1.02
0.132
0.99
0.124
0.96
0.116
0.93
0.108
0.601
0.600
0.599
0.598
0.90
0.100
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
30152175
30152176
Enable Threshold and Hysteresis vs. Temperature
V IHENR
V ENHYS
2.80
V UVLO
V UVLOHYS
300
152
2.78
1.36
144
2.76
270
1.35
136
2.74
255
1.34
128
2.72
240
1.33
120
2.70
225
1.32
112
2.68
210
1.31
104
2.66
195
1.30
96
2.64
180
1.29
88
2.62
165
1.28
80
2.60
150
VUVLO (V)
VENHYS (V)
VIHENR (V)
1.37
UVLO Threshold and Hysteresis vs. Temperature
160
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
285
VUVLOHYS (mV)
IAVIN (mA)
0.180
VFB (V)
IAVIN
IPVIN
1.17
VFB vs. Temperature
IPVIN (mA)
1.20
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
30152171
30152170
Enable Low Current vs. Temperature
OVP/UVP Threshold vs. Temperature
60
58
0.68
56
0.66
54
0.64
VOVP ,VUVP (V)
SHUTDOWN CURRENT ISD (μA)
LM21215A-1
Non-Switching IAVIN and IPVIN vs. Temperature
52
50
48
46
44
0.62
0.60
0.58
0.57
0.54
42
0.52
40
0.50
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
30152173
www.national.com
VUVP
VOVP
30152174
6
160
10
156
9
152
LOW SIDE
HIGH SIDE
8
148
RDSON (mΩ)
MINIMUM ON-TIME (nS)
FET Resistance vs. Temperature
LM21215A-1
Minimum On-Time vs. Temperature
144
140
136
132
7
6
5
4
128
124
3
120
2
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
30152172
30152168
Peak Current Limit vs. Temperature
SYNC Signal Lost
CURRENT LIMIT ICLR (A)
19.6
19.5
19.4
19.3
19.2
19.1
19.0
18.9
18.8
18.7
-40 -20 0 20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
30152165
4 µs/DIV
30152158
SYNC Signal Acquired
Load Transient Response
30152161
100 µs/DIV
30152160
10 µs/DIV
7
www.national.com
LM21215A-1
Output Voltage Ripple
Startup with Prebiased Output
30152164
2 µs/DIV
30152163
2 ms/DIV
Startup with SS/TRK Open Circuit
Startup with applied Track Signal
30152166
30152167
200 µs/DIV
200 ms/DIV
Output Over-Current Condition
30152180
10 µs/DIV
www.national.com
8
LM21215A-1
Block Diagram
30152103
9
www.national.com
LM21215A-1
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the voltage exceeds 1.35V (typical). The EN pin has 110 mV of
hysteresis and will disable the output when the enable voltage
falls below 1.24V (typical). If the EN pin is not used, it can be
left open, and will be pulled high by an internal 2 µA current
source. Since the enable pin has a precise turn-on threshold
it can be used along with an external resistor divider network
from VIN to configure the device to turn-on at a precise input
voltage.
Operation Description
GENERAL
The LM21215A-1 switching regulator features all of the functions necessary to implement an efficient low voltage buck
regulator using a minimum number of external components.
This easy to use regulator features two integrated switches
and is capable of supplying up to 15A of continuous output
current. The regulator utilizes voltage mode control with trailing edge modulation to optimize stability and transient response over the entire output voltage range. The device can
operate at high switching frequency allowing use of a small
inductor while still achieving high efficiency. The precision internal voltage reference allows the output to be set as low as
0.6V. Fault protection features include: current limiting, thermal shutdown, over voltage protection, and shutdown capability. The device is available in the eTSSOP-20 package
featuring an exposed pad to aid thermal dissipation. The
LM21215A-1 can be used in numerous applications to efficiently step-down from a 5V or 3.3V bus.
UVLO
The LM21215A-1 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input
voltage reaches 2.7V (typical). The UVLO threshold has 200
mV of hysteresis that keeps the device from responding to
power-on glitches during start up. If desired the turn-on point
of the supply can be changed by using the precision enable
pin and a resistor divider network connected to VIN as shown
in Figure 6 in the design guide.
FREQUENCY SYNCHRONIZATION
The sync (SYNC) pin allows the LM21215A-1 to be switched
at an external clock frequency. When a clock signal is present
on the SYNC pin within the allowable frequency range, 300
kHz to 1.5 MHz, the device will synchronize the turn-on of the
high side FET (switch rising) to the negative edge of the clock
signal, as seen in Figure 1 . If no clock signal is present, the
LM21215A-1 will default to a switching frequency of 500 kHz.
The clock signal can be present on the SYNC pin before the
device is powered on with no loading on the clock signal. Alternatively, if no clock is present while the device is powered
up, it will begin switching at the default frequency of 500 kHz.
Once the clock signal is present, the device will begin synchronizing to the clock frequency. The length of time necessary for the synchronization depends on the clock frequency.
CURRENT LIMIT
The LM21215A-1 has current limit protection to avoid dangerous current levels on the power FETs and inductor. A
current limit condition is met when the current through the high
side FET exceeds the rising current limit level (ICLR). The control circuitry will respond to this event by turning off the high
side FET and turning on the low side FET. This forces a negative voltage on the inductor, thereby causing the inductor
current to decrease. The high side FET will not conduct again
until the lower current limit level (ICLF) is sensed on the low
side FET. At this point, the device will resume normal switching.
A current limit condition will cause the internal soft-start voltage to ramp downward. After the internal soft-start ramps
below the Feedback (FB) pin voltage, (nominally 0.6 V), FB
will begin to ramp downward, as well. This voltage foldback
will limit the power consumption in the device, thereby protecting the device from continuously supplying power to the
load under a condition that does not fall within the device
SOA. After the current limit condition is cleared, the internal
soft-start voltage will ramp up again. Figure 2 shows current
limit behavior with VSS, VFB, VOUT and VSW.
30152133
FIGURE 1. Frequency synchronization
www.national.com
10
30152119
FIGURE 2. Current Limit Conditions
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the
integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the
LM21215A-1 tri-states the power FETs and resets soft start.
After the junction cools to approximately 155°C, the device
starts up using the normal start up routine. This feature is
provided to prevent catastrophic failures from accidental device overheating. Note that thermal limit will not stop the die
from operating above the specified operating maximum temperature,125°C. The die should be kept under 125°C to guarantee correct operation.
POWERGOOD FLAG
The PGOOD pin provides the user with a way to monitor the
status of the LM21215A-1. In order to use the PGOOD pin,
the application must provide a pull-up resistor to a desired DC
voltage (i.e. Vin). PGOOD will respond to a fault condition by
pulling the PGOOD pin low with the open-drain output.
PGOOD will pull low on the following conditions – 1) VFB
moves above or below the VOVP or VUVP, respectively 2) The
enable pin is brought below the enable threshold 3) The device enters a pre-biased output condition (VFB>VSS).
Figure 3 shows the conditions that will cause PGOOD to fall.
11
www.national.com
LM21215A-1
both power FETs and discharging the soft-start capacitor after
tRESETSS (nominally 110 µs). The device will then attempt to
restart. If the short-circuit condition still exists, it will reset
again, and repeat until the short-circuit is cleared. The reset
prevents excess current flowing through the FETs in a highly
inefficient manner, potentially causing thermal damage to the
device or the bus supply.
SHORT-CIRCUIT PROTECTION
In the unfortunate event that the output is shorted with a low
impedance to ground, the LM21215A-1 will limit the current
into the short by resetting the device. A short-circuit condition
is sensed by a current-limit condition coinciding with a voltage
on the FB pin that is lower than 100 mV. When this condition
occurs, the device will begin its reset sequence, turning off
LM21215A-1
30152118
FIGURE 3. PGOOD Conditions
It can be seen that in diode emulation mode, whenever the
inductor current reaches zero the SW node will become high
impedance. Ringing will occur on this pin as a result of the LC
tank circuit formed by the inductor and the parasitic capacitance at the node. If this ringing is of concern an additional
RC snubber circuit can be added from the switch node to
ground.
At very light loads, usually below 500mA, several pulses may
be skipped in between switching cycles, effectively reducing
the switching frequency and further improving light-load efficiency.
LIGHT LOAD OPERATION
The LM21215A-1 offers increased efficiency when operating
at light loads. Whenever the load current is reduced to a point
where the peak to peak inductor ripple current is greater than
two times the load current, the device will enter the diode emulation mode preventing significant negative inductor current.
The output current at which this occurs is the critical conduction boundary and can be calculated by the following equation:
Several diagrams are shown in Figure 4 illustrating continuous conduction mode (CCM), discontinuous conduction
mode (DCM), and the boundary condition.
www.national.com
12
LM21215A-1
30152179
FIGURE 4. Modes of Operation for LM21215A-1
13
www.national.com
LM21215A-1
In the above equation, RA is the resistor from VIN to enable,
RB is the resistor from enable to ground, IEN is the internal
enable pull-up current (2µA) and 1.35V is the fixed precision
enable threshold voltage. Typical values for RB range from
10kΩ to 100kΩ.
Design Guide
OUTPUT VOLTAGE
The first step in designing the LM21215A-1 application is setting the output voltage. This is done by using a voltage divider
between VOUT and AGND, with the middle node connected to
VFB. When operating under steady-state conditions, the
LM21215A-1 will force VOUT such that VFB is driven to 0.6 V.
SOFT START
When EN has exceeded 1.35V, and both PVIN and AVIN
have exceeded the UVLO threshold, the LM21215A-1 will begin charging the output linearly to the voltage level dictated
by the feedback resistor network. The LM21215A-1 employs
a user adjustable soft start circuit to lengthen the charging
time of the output set by a capacitor from the soft start pin to
ground. After enable exceeds 1.35V, an internal 2 µA current
source begins to charge the soft start capacitor. This allows
the user to limit inrush currents due to a high output capacitance and not cause an over current condition. Adding a softstart capacitor can also reduce the stress on the input rail.
Larger capacitor values will result in longer startup times. Use
the equation below to approximate the size of the soft-start
capacitor:
30152104
FIGURE 5. Setting VOUT
A good starting point for the lower feedback resistor, RFB2, is
10kΩ. RFB1 can then be calculated the following equation:
where ISSis nominally 2 µA and tSS is the desired startup time.
If VIN is higher than the UVLO level and enable is toggled high
the soft start sequence will begin. There is a small delay between enable transitioning high and the beginning of the soft
start sequence. This delay allows the LM21215A-1 to initialize
its internal circuitry. Once the output has charged to 90% of
the nominal output voltage the power good flag will transition
high. This behavior is illustrated in Figure 7.
PRECISION ENABLE
The enable (EN) pin of the LM21215A-1 allows the output to
be toggled on and off. This pin is a precision analog input.
When the voltage exceeds 1.35V, the controller will try to regulate the output voltage as long as the input voltage has
exceeded the UVLO voltage of 2.70V. There is an internal
current source connected to EN so if enable is not used, the
device will turn on automatically. If EN is not toggled directly
the device can be preprogrammed to turn on at a certain input
voltage higher than the UVLO voltage. This can be done with
an external resistor divider from AVIN to EN and EN to AGND
as shown below in Figure 6.
30152131
30152128
FIGURE 7. Soft Start Timing
FIGURE 6. Enable Startup Through Vin
As shown above, the size of the capacitor is influenced by the
nominal feedback voltage level 0.6V, the soft-start charging
current ISS (2 µA), and the desired soft start time. If no softstart capacitor is used then the LM21215A-1 defaults to a
minimum startup time of 500 µs. The LM21215A-1 will not
startup faster than 500 µs. When enable is cycled or the device enters UVLO, the charge developed on the soft-start
capacitor is discharged to reset the startup process. This also
happens when the device enters short circuit mode from an
over-current event.
The resistor values of RA and RB can be relatively sized to
allow EN to reach the enable threshold voltage depending on
the input supply voltage. With the enable current source accounted for, the equation solving for RA is shown below:
www.national.com
14
where, COUT (F) is the minimum required output capacitance,
L (H) is the value of the inductor, VDROOP (V) is the output
voltage drop ignoring loop bandwidth considerations, ΔIOUTSTEP (A) is the load step change, RESR (Ω) is the output
capacitor ESR, VIN (V) is the input voltage, and VOUT (V) is
the set regulator output voltage. Both the tolerance and voltage coefficient of the capacitor should be examined when
designing for a specific output ripple or transient droop target.
INPUT CAPACITOR SELECTION
Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the switch current
during the on-time. Additionally, they help minimize input voltage droop in an output current transient condition. In general,
it is recommended to use a ceramic capacitor for the input as
it provides both a low impedance and small footprint. Use of
a high grade dielectric for the ceramic capacitor, such as X5R
or X7R, will provide improved performance over temperature
and also minimize the DC voltage derating that occurs with
Y5V capacitors. The input capacitors should be placed as
close as possible to the PVIN and PGND pins.
Non-ceramic input capacitors should be selected for RMS
current rating and minimum ripple voltage. A good approximation for the required ripple current rating is given by the
relationship:
30152107
FIGURE 8. Switch and Inductor Current Waveforms
Once the ripple current has been determined, the appropriate
inductor size can be calculated using the following equation:
OUTPUT CAPACITOR SELECTION
The output capacitor, COUT, filters the inductor ripple current
and provides a source of charge for transient load conditions.
A wide range of output capacitors may be used with the
LM21215A-1 that provide various advantages. The best performance is typically obtained using ceramic, SP or OSCON
type chemistries. Typical trade-offs are that the ceramic capacitor provides extremely low ESR to reduce the output
ripple voltage and noise spikes, while the SP and OSCON
capacitors provide a large bulk capacitance in a small volume
for transient loading conditions.
When selecting the value for the output capacitor, the two
performance characteristics to consider are the output voltage ripple and transient response. The output voltage ripple
can be approximated by using the following formula:
As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle.
For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best
performance, low ESR ceramic capacitors should be placed
in parallel with higher capacitance capacitors to provide the
best input filtering for the device.
When operating at low input voltages (3.3V or lower), additional capacitance may be necessary to protect from triggering an under-voltage condition on an output current transient.
This will depend on the impedance between the input voltage
supply and the LM21215A-1, as well as the magnitude and
slew rate of the output transient.
The AVIN pin requires a 1 µF ceramic capacitor to AGND and
a 1Ω resistor to PVIN. This RC network will filter inherent
noise on PVIN from the sensitive analog circuitry connected
to AVIN.
where ΔVOUT (V) is the amount of peak to peak voltage ripple
at the power supply output, RESR (Ω) is the series resistance
of the output capacitor, fSW (Hz) is the switching frequency,
and COUT (F) is the output capacitance used in the design.
The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep
the output ripple less than 1% of the rated output voltage.
Keep in mind ceramic capacitors are sometimes preferred
because they have very low ESR; however, depending on
CONTROL LOOP COMPENSATION
The LM21215A-1 incorporates a high bandwidth amplifier between the FB and COMP pins to allow the user to design a
compensation network that matches the application. This
section will walk through the various steps in obtaining the
open loop transfer function.
15
www.national.com
LM21215A-1
package and voltage rating of the capacitor the value of the
capacitance can drop significantly with applied voltage. The
output capacitor selection will also affect the output voltage
droop during a load transient. The peak droop on the output
voltage during a load transient is dependent on many factors;
however, an approximation of the transient droop ignoring
loop bandwidth can be obtained using the following equation:
INDUCTOR SELECTION
The inductor (L) used in the application will influence the ripple
current and the efficiency of the system. The first selection
criteria is to define a ripple current, ΔIL. In a buck converter,
it is typically selected to run between 20% to 30% of the maximum output current. Figure 8 shows the ripple current in a
standard buck converter operating in continuous conduction
mode. Larger ripple current will result in a smaller inductance
value, which will lead to lower inductor series resistance, and
improved efficiency. However, larger ripple current will also
cause the device to operate in discontinuous conduction
mode at a higher average output current.
A Bode plot showing the power train response can be seen
below.
0
60
-40
40
-120
0
-160
-20
-200
-240
-40
-60
-80
100
PHASE (°)
-80
20
GAIN (dB)
LM21215A-1
There are three main blocks of a voltage mode buck switcher
that the power supply designer must consider when designing
the control system; the power train, modulator, and the compensated error amplifier. A closed loop diagram is shown in
Figure 9.
-280
-320
GAIN
PHASE
1k
10k 100k
1M
FREQUENCY (HZ)
-360
10M
30152140
FIGURE 10. Power Train Bode Plot
The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant frequency as
seen in Figure 10. The phase is boosted back up to -90° because of the output capacitor ESR zero. The 180° phase shift
must be compensated out and phase boosted through the
error amplifier to stabilize the closed loop response. The compensation network shown around the error amplifier in Figure
9 creates two poles, two zeros and a pole at the origin. Placing
these poles and zeros at the correct frequencies will stabilize
the closed loop response. The Compensated Error Amplifier
transfer function is:
30152112
FIGURE 9. Loop Diagram
The power train consists of the output inductor (L) with DCR
(DC resistance RDCR), output capacitor (C0) with ESR (effective series resistance RESR), and load resistance (Ro). The
error amplifier (EA) constantly forces FB to 0.6V. The passive
compensation components around the error amplifier help
maintain system stability. The modulator creates the duty cycle by comparing the error amplifier signal with an internally
generated ramp set at the switching frequency.
There are three transfer functions that must be taken into
consideration when obtaining the total open loop transfer
function; COMP to SW (Modulator) , SW to VOUT (Power
Train), and VOUT to COMP (Error Amplifier). The COMP to SW
transfer function is simply the gain of the PWM modulator.
The pole located at the origin gives high open loop gain at DC,
translating into improved load regulation accuracy. This pole
occurs at a very low frequency due to the limited gain of the
error amplifier; however, it can be approximated at DC for the
purposes of compensation. The other two poles and two zeros can be located accordingly to stabilize the voltage mode
loop depending on the power stage complex poles and Q.
Figure 11 is an illustration of what the Error Amplifier Compensation transfer function will look like.
where ΔVRAMP is the oscillator peak-to-peak ramp voltage
(nominally 0.8 V). The SW to COMP transfer function includes
the output inductor, output capacitor, and output load resistance. The inductor and capacitor create two complex poles
at a frequency described by:
In addition to two complex poles, a left half plane zero is created by the output capacitor ESR located at a frequency
described by:
www.national.com
16
45
60
0
40
-45
20
-90
0
-135
-20
-180
1k
10k 100k 1M
FREQUENCY (Hz)
PHASE (°)
GAIN (dB)
80
100
the open-loop gain is a magnitude of 1. It is recommended
that the fcrossover not exceed one-fifth of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For Multi-Layer Ceramic Capacitors
(MLCC), the total capacitance will degrade as the DC bias
voltage is increased. Measuring the actual capacitance value
for the output capacitors at the output voltage is recommended to accurately calculate the compensation network. The
example given here is the total output capacitance using the
three MLCC output capacitors biased at 1.2V, as seen in the
typical application schematic, Figure 16. Note that it is more
conservative, from a stability standpoint, to err on the side of
a smaller output capacitance value in the compensation calculations rather than a larger, as this will result in a lower
bandwidth but increased phase margin.
First, a the value of RFB1 should be chosen. A typical value is
10kΩ. From this, the value of RC1 can be calculated to set the
mid-band gain so that the desired crossover frequency is
achieved:
90
GAIN
PHASE
10M
30152141
FIGURE 11. Type 3 Compensation Network Bode Plot
As seen in Figure 11, the two zeros (fLC/2, fLC) in the comensation network give a phase boost. This will cancel out the
effects of the phase loss from the output filter. The compensation network also adds two poles to the system. One pole
should be located at the zero caused by the output capacitor
ESR (fESR) and the other pole should be at half the switching
frequency (fSW/2) to roll off the high frequency response. The
dependancy of the pole and zero locations on the compensation components is described below.
Next, the value of CC1 can be calculated by placing a zero at
half of the LC double pole frequency (fLC):
Now the value of CC2 can be calculated to place a pole at half
of the switching frequency (fSW):
An example of the step-by-step procedure to generate compensation component values using the typical application
setup (see Figure 16) is given. The parameters needed for
the compensation values are given in the table below.
Parameter
Value
VIN
5.0V
VOUT
1.2V
IOUT
15A
fCROSSOVER
100 kHz
L
0.56 µH
RDCR
1.8 mΩ
CO
150 µF
RESR
1.0 mΩ
ΔVRAMP
0.8V
fSW
500 kHz
RC2 can then be calculated to set the second zero at the LC
double pole frequency:
Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR:
An illustration of the total loop response can be seen in Figure
12.
where ΔVRAMP is the oscillator peak-to-peak ramp voltage
(nominally 0.8V), and fCROSSOVER is the frequency at which
17
www.national.com
LM21215A-1
100
GAIN
PHASE
140
120
100
80
100
60
50
40
20
0
30
THERMAL RESISTANCE (θJA)
150
GAIN (dB)
additional sixteen 8 mil. vias under the rest of the device were
used to connect the 4 layers.
160
PHASE MARGIN (°)
LM21215A-1
200
0
-20
-50
-40
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
28
26
24
22
20
18
16
14
12
10
30152139
2
3
4
5
6
7
8
BOARD AREA (in2)
FIGURE 12. Loop Response
9
10
30152142
It is important to verify the stability by either observing the load
transient response or by using a network analyzer. A phase
margin between 45° and 70° is usually desired for voltage
mode systems. Excessive phase margin can cause slow system response to load transients and low phase margin may
cause an oscillatory load transient response. If the load step
response peak deviation is larger than desired, increasing
fCROSSOVER and recalculating the compensation components
may help but usually at the expense of phase margin.
FIGURE 13. Thermal Resistance vs PCB Area (4 Layer
Board)
Figure 14 shows a plot of the maximum ambient temperature
vs. output current for the typical application circuit shown in
Figure 16, assuming a θJA value of 24 °C/W.
MAX. AMBIENT TEMPERATURE (°C)
125
THERMAL CONSIDERATIONS
The thermal characteristics of the LM21215A-1 are specified
using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is
dependant on many variables, it still can be used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one
may use the following relationship:
and
115
105
95
85
75
0
3
6
9
IOUT (A)
12
15
30152144
Where:
TJ is the junction temperature in °C, PIN is the input power in
Watts (PIN = VIN x IIN), θJA is the junction to ambient thermal
resistance for the LM21215A-1, TA is the ambient temperature in °C, and IOUT is the output load current in A.
It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the junction
temperature exceeds 165°C the device will cycle in and out
of thermal shutdown. If thermal shutdown occurs it is a sign
of inadequate heatsinking or excessive power dissipation in
the device.
Figure 13, shown below, provides a better approximation of
the θJA for a given PCB copper area. The PCB used in this
test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper
weight. To provide an optimal thermal connection, a 3 x 4 array of 8 mil. vias under the thermal pad were used, and an
www.national.com
FIGURE 14. Maximum Ambient Temperature vs. Output
Current (0 LFM)
PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI,
ground bounce, and resistive voltage loss in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability.
Good layout can be implemented by following a few simple
design rules.
1. Minimize area of switched current loops. In a buck regulator
there are two loops where currents are switched at high slew
rates. The first loop starts from the input capacitor, to the regulator PVIN pin, to the regulator SW pin, to the inductor then
out to the output capacitor and load. The second loop starts
18
4. Carefully route the connection from the VOUT signal to the
compensation network. This node is high impedance and can
be susceptible to noise coupling. The trace should be routed
away from the SW pin and inductor to avoid contaminating
the feedback signal with switch noise. Additionally,feedback
resistors RFB1 and RFB2 should be located near the device to
minimize the trace length to FB between these resistors.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or output of
the converter and can improve efficiency. Voltage accuracy
at the load is important so make sure feedback voltage sense
is made at the load. Doing so will correct for voltage drops at
the load and provide the best output accuracy.
6. Provide adequate device heatsinking. For most 15A designs a four layer board is recommended. Use as many vias
as possible to connect the EP to the power plane heatsink.
The vias located underneath the EP will wick solder into them
if they are not filled. Complete solder coverage of the EP to
the board is required to achieve the θJA values described in
the previous section. Either an adequate amount of solder
must be applied to the EP pad to fill the vias, or the vias must
be filled during manufacturing. See the Thermal Considerations section to ensure enough copper heatsinking area is
used to keep the junction temperature below 125°C.
30152148
FIGURE 15. Schematic of LM21215A-1 Highlighting Layout Sensitive Nodes
19
www.national.com
LM21215A-1
from the output capacitor ground, to the regulator GND pins,
to the inductor and then out to the load (see Figure 15). To
minimize both loop areas, the input capacitor should be
placed as close as possible to the VIN pin. Grounding for both
the input and output capacitor should be close. Ideally, a
ground plane should be placed on the top layer that connects
the PGND pins, the exposed pad (EP) of the device, and the
ground connections of the input and output capacitors in a
small area near pins 10 and 11 of the device. The inductor
should be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. The six SW
pins should be routed on a single top plane to the pad of the
inductor. The inductor should be placed as close as possible
to the switch pins of the device with a wide trace to minimize
conductive losses. The inductor can be placed on the bottom
side of the PCB relative to the LM21215A-1, but care must be
taken to not allow any coupling of the magnetic field of the
inductor into the sensitive feedback or compensation traces.
3. Have a solid ground plane between PGND, the EP and the
input and output cap. ground connections. The ground connections for the AGND, compensation, feedback, and softstart components should be physically isolated (located near
pins 1 and 20) from the power ground plane but a separate
ground connection is not necessary. If not properly handled,
poor grounding can result in degraded load regulation or erratic switching behavior.
LM21215A-1
30152143
FIGURE 16. Typical Application Schematic 1
Bill of Materials (VIN = 3.3V - 5.5V, VOUT = 1.2V, IOUT = 15A, fSW = 500kHz)
ID
DESCRIPTION
VENDOR
PART NUMBER
QUANTITY
CF
CAP, CERM, 1 uF, 10V, +/-10%,
X7R, 0603
MuRata
GRM188R71A105KA61D
1
CIN1, CIN2, CIN3,
CO1, CO2, CO3
CAP, CERM, 100 uF, 6.3V,
+/-20%, X5R, 1206
MuRata
GRM31CR60J107ME39L
6
CC1
CAP, CERM, 1800 pF, 50V,
+/-5%, C0G/NP0, 0603
TDK
C1608C0G1H182J
1
CC2
CAP, CERM, 68 pF, 50V, +/-5%,
C0G/NP0, 0603
TDK
C1608C0G1H680J
1
CC3
CAP, CERM, 820 pF, 50V, +/-5%,
C0G/NP0, 0603
TDK
C1608C0G1H821J
1
CSS
CAP, CERM, 0.033 uF, 16V,
+/-10%, X7R, 0603
MuRata
GRM188R71C333KA01D
1
LO
Inductor, Shielded Drum Core,
Powdered Iron, 560nH, 27.5A,
0.0018 ohm, SMD
Vishay-Dale
IHLP4040DZERR56M01
1
RF
RES, 1.0 ohm, 5%, 0.1W, 0603
Vishay-Dale
CRCW06031R00JNEA
1
RC1
RES, 9.31 kohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW06039K31FKEA
1
RC2
RES, 165 ohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW0603165RFKEA
1
RFB1, RFB2, RPGOOD RES, 10 kohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW060310K0FKEA
3
www.national.com
20
LM21215A-1
30152181
FIGURE 17. Typical Application Schematic 2
Bill of Materials (VIN = 4.0V - 5.5V, VOUT = 0.9V, IOUT = 8A, fSW = 1MHz)
ID
DESCRIPTION
VENDOR
PART NUMBER
QUANTITY
CF
CAP, CERM, 1 uF, 10V, +/-10%,
X7R, 0603
MuRata
GRM188R71A105KA61D
1
CIN1, CO1, CO2
CAP, CERM, 100 uF, 6.3V,
+/-20%, X5R, 1206
MuRata
GRM31CR60J107ME39L
3
CC1
CAP, CERM, 1800 pF, 50V,
+/-5%, C0G/NP0, 0603
MuRata
GRM1885C1H182JA01D
1
CC2
CAP, CERM, 68 pF, 50V, +/-5%,
C0G/NP0, 0603
TDK
C1608C0G1H680J
1
CC3
CAP, CERM, 470 pF, 50V, +/-5%,
C0G/NP0, 0603
TDK
C1608C0G1H471J
1
CSS
CAP, CERM, 0.033 uF, 16V,
+/-10%, X7R, 0603
MuRata
GRM188R71C333KA01D
1
LO
Inductor, Shielded Drum Core,
Superflux, 240nH, 20A, 0.001
ohm, SMD
Wurth Elektronik
744314024
1
RF
RES, 1.0 ohm, 5%, 0.1W, 0603
Vishay-Dale
CRCW06031R00JNEA
1
RC1
RES, 4.87 kohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW06034K87FKEA
1
RC2
RES, 210 ohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW0603210RFKEA
1
REN1, RFB1, RPGOOD RES, 10k ohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW060310K0FKEA
3
REN2
RES, 19.6 kohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW060319K6FKEA
1
RFB2
RES, 20.0 kohm, 1%, 0.1W, 0603
Vishay-Dale
CRCW060320K0FKEA
1
21
www.national.com
LM21215A-1
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead eTSSOP Package
NS Package Number MYB20
www.national.com
22
LM21215A-1
Notes
23
www.national.com
LM21215A-1 15A High Efficiency Synchronous Buck Regulator
Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
www.national.com
Products
Design Support
Amplifiers
www.national.com/amplifiers
WEBENCH® Tools
www.national.com/webench
Audio
www.national.com/audio
App Notes
www.national.com/appnotes
Clock and Timing
www.national.com/timing
Reference Designs
www.national.com/refdesigns
Data Converters
www.national.com/adc
Samples
www.national.com/samples
Interface
www.national.com/interface
Eval Boards
www.national.com/evalboards
LVDS
www.national.com/lvds
Packaging
www.national.com/packaging
Power Management
www.national.com/power
Green Compliance
www.national.com/quality/green
Switching Regulators
www.national.com/switchers
Distributors
www.national.com/contacts
LDOs
www.national.com/ldo
Quality and Reliability
www.national.com/quality
LED Lighting
www.national.com/led
Feedback/Support
www.national.com/feedback
Voltage References
www.national.com/vref
Design Made Easy
www.national.com/easy
www.national.com/powerwise
Applications & Markets
www.national.com/solutions
Mil/Aero
www.national.com/milaero
PowerWise® Solutions
Serial Digital Interface (SDI) www.national.com/sdi
Temperature Sensors
www.national.com/tempsensors SolarMagic™
www.national.com/solarmagic
PLL/VCO
www.national.com/wireless
www.national.com/training
PowerWise® Design
University
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2011 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email: [email protected]
Tel: 1-800-272-9959
www.national.com
National Semiconductor Europe
Technical Support Center
Email: [email protected]
National Semiconductor Asia
Pacific Technical Support Center
Email: [email protected]
National Semiconductor Japan
Technical Support Center
Email: [email protected]
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated