HVLED002 High performance current mode LED controller Datasheet - production data Description SO-8 Features Trimmed oscillator for precise frequency control Oscillator frequency guaranteed at 250 kHz Current mode operation to 500 kHz Latching PWM for cycle-by-cycle current limiting The HVLED002 control IC provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes to implement LED drivers. Internally implemented circuits include a trimmed oscillator for the precise duty cycle control, undervoltage lockout, a precision reference trimmed for accuracy at the error amplifier input, a PWM comparator which also provides current limit control and a totem pole output stage designed to the source or sink high peak current. The output stage, suitable for driving N-channel MOSFETs, is low in the offstate. Internally trimmed reference with undervoltage lockout Order codes High current totem pole output Undervoltage lockout with hysteresis Low start-up and operating current Table 1. Device summary HVLED002 HVLED002TR Package SO8 Packaging Tube Tape and reel Figure 1. Block diagram December 2015 This is information on a product in full production. DocID028720 Rev 1 1/19 www.st.com Contents HVLED002 Contents 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin connection and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 5.1 Supply voltage and undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.6 Totem pole output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.7 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 7 2/19 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DocID028720 Rev 1 HVLED002 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 20. Figure 16. Figure 17. Figure 18. Figure 19. Figure 21. Figure 22. Figure 23. Figure 24. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Open loop test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing resistor vs. oscillator frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output deadtime vs. oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Oscillator discharge current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Maximum output duty cycle vs. timing resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Error amplifier open loop gain and phase vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current sense input threshold vs. error amplifier output voltage . . . . . . . . . . . . . . . . . . . . . 9 Reference voltage change vs. source current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reference short-circuit current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output saturation voltage vs. load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Oscillator and output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Error amplifier configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Error amplifier compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Soft-start circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Leading edge blanking circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Shutdown circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO-8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DocID028720 Rev 1 3/19 19 Absolute maximum ratings 1 HVLED002 Absolute maximum ratings Table 2. Absolute maximum ratings(1) Symbol Parameter Value Unit Vi Supply voltage 30 V IO Output current ±1 A EO Output energy (capacitive load) 5 µJ - 0.3 to 5.5 V 10 mA Analog inputs (pins 2, 3) Error amplifier output sink current 1. All voltages are with respect to the pin 5, all currents are positive into the specified terminal. 4/19 DocID028720 Rev 1 HVLED002 2 Pin connection and functions Pin connection and functions Figure 2. Pin connection (top view) Table 3. Pin functions No. Function 3 Description 1 COMP This pin is the error amplifier output and is made available for loop compensation. 2 VFB 3 ISENSE A voltage proportional to the inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 RT/CT The oscillator frequency and maximum output duty cycle are programmed by the connecting resistor RT to VREF and the capacitor CT to ground. An operation to 500 kHz is possible. This is the inverting input of the error amplifier. It is normally connected to the switching power supply output through a resistor divider. 5 GROUND This pin is the ground reference of the device. 6 OUTPUT 7 Vi 8 VREF This output directly drives the gate of a power MOSFET. Peak currents up to 1 A are sourced and sunk by this pin. This pin is the positive supply of the control IC. This is the reference output. It provides the charging current for the capacitor CT through the resistor RT. Thermal data Table 4. Thermal data Symbol Rth j-amb Description Thermal resistance junction ambient SO8 Unit 150 °C/W Tstg Storage temperature range -65 to 150 °C TJ Junction operating temperature -40 to 150 °C TL Lead temperature (soldering 10 s) 300 °C DocID028720 Rev 1 5/19 19 Electrical characteristics 4 HVLED002 Electrical characteristics Unless otherwise stated, these specifications apply for 0 ≤ Tamb ≤ 85 °C; Vi = 15 V; RT = 10 K; CT = 3.3 nF(a). Table 5. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit 25 V 5.00 5.05 V SUPPLY VOLTAGE Vi Max. operative volt. REFERENCE SECTION VREF Output voltage TJ = 25 °C, Io = 1 mA VREF Line regulation 12 V ≤ Vi ≤ 25 V 2 20 mV VREF Load regulation 1 ≤ Io ≤ 20 mA 3 25 mV VREF/T Temperature stability Total output variation eN ISC 4.95 (1) 0.2 Line, load, temperature Output noise voltage 10 Hz ≤ f ≤ 10 KHz, Tj = 25 Long term stability Tamb = 125 °C, 1000 hrs(1) 4.82 °C(1) Output short-circuit mV/°C 5.18 50 V µV 5 25 mV -30 -100 -180 mA 49 48 225 52 250 55 56 275 KHz OSCILLATOR SECTION fOSC Frequency TJ = 25 °C TA = 0 to 85 °C TJ = 25 °C (RT = 6.2 k, CT = 1 nF) fOSC/V Frequency change with volt. VCC = 12 V to 25 V - 0.2 1 % fOSC/T Frequency change with temp. Tamb = 0 °C to 85 °C - 0.5 - % Peak-to-peak - 1.6 - V 7.8 8.3 8.8 mA TA = 0°C to 85°C 7.6 - 8.8 mA Input voltage V(COMP) = 2.5 V 2.42 2.50 2.58 V Input bias current VFB = 5 V -0.1 -2 µA AVOL 2 V ≤ Vo ≤ 4 V VOSC Oscillator voltage swing Idischg Discharge current (VOSC = 2 V) TJ = 25 °C ERROR AMPLIFIER SECTION VREF,EA Ib BW PSRR Io °C(1) 65 90 dB 0.7 1 MHz Unity gain bandwidth TJ = 25 Power supply reject. ratio 12 V ≤ Vi ≤ 25 V 60 70 dB Output sink current V(VFB) = 2.7 V, V(COMP) = 1.1 V 2 12 mA a. Max. package power dissipation limits must be respected; low duty cycle pulse techniques are used during the test maintaining TJ as close to Tamb as possible. 6/19 DocID028720 Rev 1 HVLED002 Electrical characteristics Table 5. Electrical characteristics (continued) Symbol Io Parameter Test conditions Output source current V(VFB) = 2.3 V, V(COMP) = 5 V VCOMP high V(VFB) = 2.3 V; RL = 15 K between COMP and ground VCOMP low V(VFB) = 2.7 V; RL = 15 K between COMP and VREF Min. Typ. -0.5 -1 mA 5 6.2 V 0.8 Max. 1.1 Unit V CURRENT SENSE SECTION GV MAXCS SVR Ib Gain (2) (3) Maximum input signal V(COMP) = 5.6 V Supply voltage rejection , 12 ≤ Vi ≤ 25 3 258 V(1) 267 V/V 276 70 Input bias current mV dB -2 -10 µA 150 300 ns ISINK = 20 mA 0.1 0.4 V ISINK = 200 mA 1.6 2.2 V Delay to output OUTPUT SECTION VOL VOH VOLS tr tf Output low level Output high level ISOURCE = 20 mA 13 13.5 V ISOURCE = 200 mA 12 13.5 V UVLO saturation VCC = 6 V; ISINK = 1 mA 0.1 1.1 V Rise time TJ = 25 °C; CL = 1 nF(1) 50 150 ns nF(1) 50 150 ns Fall time TJ = 25 °C; CL = 1 UNDERVOLTAGE LOCKOUT SECTION VON Start threshold Increasing voltage 7.8 8.4 9.0 V VOFF Min. operating voltage after turn-on Decreasing voltage 7.0 7.6 8.2 V 94 96 100 % 0 % 0.3 0.5 mA 12 17 mA PWM SECTION Maximum duty cycle Minimum duty cycle TOTAL STANDBY CURRENT Ist Start-up current Ii Operating supply current V(VFB) = V(COMP) = 0 V 1. These parameters, although guaranteed, are not 100% tested in production. 2. Parameter measured at the trip point of the latch with V(VFB) = 0. 3. Gain defined as : A = V(COMP)/V(ISENSE) ; 0 ≤ V(ISENSE) ≤ 267 mV. DocID028720 Rev 1 7/19 19 Electrical characteristics HVLED002 Figure 3. Open loop test circuit VREF RT 2N2222 COMP VFB ERROR AMP. ADJUST ISENSE ADJUST A VREF ISENSE RT/CT 1 Vi 0.1 μF 8 7 2 HVLED002 3 6 4 5 Vi 0.1 μF OUTPUT 1W OUTPUT GROUND CT GROUND AM039820 High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to the pin 5 in a single point ground. The transistor and 5 K potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to the pin 3. Figure 4. Timing resistor vs. oscillator frequency 8/19 Figure 5. Output deadtime vs. oscillator frequency DocID028720 Rev 1 HVLED002 Electrical characteristics Figure 6. Oscillator discharge current vs. temperature Figure 7. Maximum output duty cycle vs. timing resistor Figure 8. Error amplifier open loop gain and phase vs. frequency Figure 9. Current sense input threshold vs. error amplifier output voltage DocID028720 Rev 1 9/19 19 Electrical characteristics HVLED002 Figure 10. Reference voltage change vs. source current Figure 11. Reference short-circuit current vs. temperature Figure 12. Output saturation voltage vs. load current Figure 13. Supply current vs. supply voltage Figure 14. Oscillator and output waveforms Figure 15. Error amplifier configuration 10/19 DocID028720 Rev 1 HVLED002 Electrical characteristics Figure 16. Undervoltage lockout Figure 17. Current sense circuit Figure 18. Soft-start circuit Figure 19. External clock synchronization Figure 20. Error amplifier compensation 'SPN70 7 N" 3J 3 3E $G &" 3 3G &SSPSBNQMJGJFSDPNQFOTBUJPODJSDVJUGPSTUBCJMJ[JOHBOZDVSSFOUNPEFUPQPMPHZFYDFQU GPSCPPTUBOEGMZCBDLDPOWFSUFSTPQFSBUJOHXJUIDPOUJOVPVTJOEVDUPSDVSSFOU 'SPN70 7 N" 31 3 3J $1 3E $G &" 3G 3 &SSPSBNQMJGJFSDPNQFOTBUJPODJSDVJUGPSTUBCJMJ[JOHDVSSFOUNPEFCPPTUBOEGMZCBDL UPQPMPHJFTPQFSBUJOHXJUIDPOUJOVPVTJOEVDUPSDVSSFOU ". DocID028720 Rev 1 11/19 19 Application information HVLED002 5 Application information 5.1 Supply voltage and undervoltage lockout The HVLED002 device is able to operate with a very wide range of supply voltage between 8.4 V and 30 V. The UVLO circuit insures that VCC is adequate to make the HVLED002 fully operational before enabling the output stage. Figure 16 shows that the UVLO turn-on and turn-off thresholds are fixed internally at 8.4 V and 7.6 V respectively. The hysteresis prevents VCC oscillations during power sequencing and the start-up current is less than 1 mA. During UVLO, the output driver is in a low state and it can easily sink 1 mA, enough to insure the MOSFET is held off. 5.2 Reference voltage The HVLED002 contains a precision reference voltage (5 V) that generates all the internal reference voltages such as the error amplifier's reference (connected to its non-inverting input), current sense clamp limit (MAXCS) and oscillator's internal bias currents and thresholds. The reference voltage is also available on the VREF pin that, thanks to its high output current capability (over 20 mA), is able to supply not only nearby passive circuitries but also auxiliary microcontrollers. The pin must be bypassed with at least a 0.1 µF ceramic capacitor placed as close as possible to the respective VREF and GND pins. 5.3 Oscillator The HVLED002 oscillator is programmed as shown in Figure 14. The timing capacitor CT is charged from a reference voltage (e.g.: VREF) through the timing resistor RT, and discharged by an internal current source. The MOSFET is turned on (GD pin high) when the oscillator starts the charge of the CT. As soon as the voltage of the CT reaches an upper threshold the internal discharge current is activated until the CT voltage reaches a lower threshold. This occurrence initiates a new oscillator cycle. The difference between the upper and the lower thresholds (Vosc) determines the duration of charging and discharging time. During the discharging time (also called deadtime) the MOSFET is off and any spurious GD triggering is avoided. The deadtime also limits the maximum obtainable duty cycle. The oscillator can be differently connected to external circuitry to obtain different operating schemes. Connecting the RT to VREF a very accurate fixed frequency operation is achieved: the RT,CT combinations are plot into Figure 5 on page 8, Figure 6 and Figure 8 for a quick reference, or calculated as follows: Equation 1 FOSC (kHz) = 1.72 / [RT (k) x CT (µF)] 12/19 DocID028720 Rev 1 HVLED002 Application information Connecting the RT to a variable voltage, dependency of the operating frequency on said voltage is introduced. A pull-down switch can be used to reset the CT during the MOSFET's on time, for example to operate in fixed off time. A synchronous operation is also possible using circuitries like the one proposed as an example in Figure 19. The HVLED002 oscillator can be used to a maximum of 500 kHz. 5.4 Current sense The peak current mode operation of the HVLED002 is made by the embedded current sense comparator: the said element turns off the MOSFET as soon as the current sense input voltage is greater than the internal threshold derived by the COMP pin voltage (Figure 17). The current sense pin (ISENSE) is normally connected to a shunt resistor, put in series with the main switch, but different connections are also possible. Under the normal operation the threshold voltage (VCS) is controlled by the E/A according to the following relation: Equation 2 VCS = 1/3 * (VCOMP - 1.4 V) VCS is upper limited to MAXCS to reduce the shunt resistor power dissipation without the need of current transformers or offsets circuitries. This parameter is beneficial in those applications where both the peak current accuracy and the operating power dissipation are critical aspects (e.g.: LED secondary side LED current regulators). When the sensing current resistor is in series with the power switch, the current waveform will often have a large spike at its leading edge due to parasitic capacitances and gate driver charging currents. A very simple leading edge blanking (LEB) circuit consists on an RC filter, but more effective active circuitries are also possible. Figure 21. Leading edge blanking circuitries 065165 *4 *4 )7-&% )7-&% $ *4&/4& 3 *4&/4& 34 $ 34 (/% 3 (/% ". DocID028720 Rev 1 13/19 19 Application information 5.5 HVLED002 Error amplifier An error amplifier (E/A) structure is present in the HVLED002 (Figure 15 on page 10). The non-inverting input is internally connected to a very precise reference voltage (2.5 V ± 2%). The E/A output and inverting pin are connected respectively to the pin 1 and 2, available for external compensation. The E/A output will source at least 0.5 mA and sink 2 mA. Figure 8 on page 9 shows the open loop frequency response of the E/A. The output of the error amplifier can be forced to ground in different ways to shut down the application as shown in Figure 22. Figure 22. Shutdown circuitries 4 OSC 8 R BIAS R + 1 mA 2R + 2 - EA R 1 5 2N 3905 2N 3903 The SCR must be selected for a holding current of less than 0.5 mA at TA(min). The simple two-transistor circuit can be used in place of the SCR as shown. All resistors are 10 K . AM039818 5.6 Totem pole output The HVLED002 has a single totem pole output which can be operated to the ± 1 Amp peak current for driving MOSFET gates, and a + 200 mA average current for bipolar power transistors. Cross conduction between the driver's output transistors is minimal, the average added power with VIN = 30 V is around 80 mW at 200 kHz. Limiting the peak current through the IC is accomplished by placing a resistor between the totem pole output and the gate of the MOSFET. Without this resistor, the peak current is limited only by the dV/dT rate of the totem pole switching and the FET gate capacitance. An additional discharging diode can be put in parallel with the said limiting resistor to quickly turn off the MOSFET, reducing the switching losses and the control to output delay. 14/19 DocID028720 Rev 1 HVLED002 5.7 Application information Typical application The HVLED002 device can be used as a secondary side step-down current regulator in the multiple staged LED driver - see Figure 23. It is easy to configure the device to drive an inverse (or modified) buck topology based on the fixed off-time (FOT) algorithm. The MOSFET remains on until the current sense threshold is reached; during the on time, the oscillator remains reset to ground. The current sense threshold is set by the saturation of the E/A to MAXCS to guarantee the higher precision as possible. The MOSFET is then turned off and the oscillator is released: the resulting off time is fixed by the charging of the CT by RT, connected to VREF. An optional auxiliary microcontroller, supplied by VREF itself can be used to dim the LED current according to the information sent to the application by a remote controller. Figure 23. Typical application VIN 5.6 V(1) VFB VREF VDD 2 1 8 μC User interface Vaux COMP 7 6 HVLED002 GPIO RT/CT 3 4 Vi OUTPUT D Q1 L Isense 5 GND GROUND RS Osc. reset Dimming 1. Optional for better performances. DocID028720 Rev 1 15/19 19 Package information 6 HVLED002 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 SO-8 package information Figure 24. SO-8 package outline $09 16/19 DocID028720 Rev 1 HVLED002 Package information Table 6. SO-8 package mechanical data Dimensions (mm) Dimensions (inch) Symbol Min. Typ. A Max. Min. Typ. 1.750 0.0689 A1 0.100 A2 1.250 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 (1) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(2) 3.800 3.900 4.000 0.1496 0.1535 0.1575 D e 0.250 Max. 0.0039 0.0098 0.0492 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 L 0.400 1.270 0.0157 0.0500 L1 k ccc 1.040 0° 0.0409 8° 0.10 0° 8° 0.0039 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold Flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides). 2. Dimension “E1” does not include interlead Flash or protrusions. Interlead Flash or protrusions shall not exceed 0.25 mm per side. DocID028720 Rev 1 17/19 19 Revision history 7 HVLED002 Revision history Table 7. Document revision history 18/19 Date Revision 15-Dec-2015 1 Changes Initial release. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID028720 Rev 1 19/19 19