ON FL7930B Single-stage flyback and boundary-mode pfc controller for lighting Datasheet

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FL7930B
Single-Stage Flyback and Boundary-Mode PFC
Controller for Lighting
Features
Description















The FL7930B is an active power factor correction
(PFC) controller for boost PFC applications that
operate in critical conduction mode (CRM). It uses a
voltage-mode PWM that compares an internal ramp
signal with the error amplifier output to generate a
MOSFET turn-off signal. Because the voltage-mode
CRM PFC controller does not need rectified AC line
voltage information, it saves the power loss of an input
voltage sensing network necessary for a current-mode
CRM PFC controller.
Additional OVP Detection Pin
VIN-Absent Detection
Maximum Switching Frequency Limitation
Internal Soft-Start and Startup without Overshoot
Internal Total Harmonic Distortion (THD) Optimizer
Precise Adjustable Output Over-Voltage Protection
Open-Feedback Protection and Disable Function
Zero Current Detector (ZCD)
150 μs Internal Startup Timer
MOSFET Over-Current Protection (OCP)
Under-Voltage Lockout with 3.5 V Hysteresis
Low Startup and Operating Current
Totem-Pole Output with High State Clamp
+500/-800 mA Peak Gate Drive Current
8-Pin, Small-Outline Package (SOP)
FL7930B provides over-voltage protection (OVP), openfeedback protection, over-current protection (OCP),
input-voltage-absent detection, and under-voltage
lockout protection (UVLO). The additional OVP pin can
be used to shut down the boost power stage when
output voltage exceeds OVP level due to the resistors
that are connected at INV pin are damaged. The
FL7930B can be disabled if the INV pin voltage is lower
than 0.45 V and the operating current decreases to a
very low level. Using a new variable on-time control
method, total harmonic distortion (THD) is lower than in
conventional CRM boost PFC ICs.
Applications




Ballast
General LED Lighting
Industrial, Commercial, and Residential Fixtures
Outdoor Lighting: Street, Roadway, Parking,
Construction, Ornamental LED Lighting Fixtures
Ordering Information
Part Number
Operating
Temperature Range
Top Mark
Package
Packing
Method
FL7930BMX_G
-40 to +125°C
FL7930BG
8-Lead Small Outline Package (SOP)
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
October 2013
DC OUTPUT
Vcc
Line Filter
FL7930B
8
AC INPUT
VCC
5
ZCD
3
COMP
Out
7
CS
4
INV
GND OVP
1
2
6
Figure 1.
Typical Boost PFC Application
FL7930B
1 INV
CF1
CF2
CHF
2 OVP
VCC 8
GATE 7
3 COMP
GND 6
4 CS
ZCD 5
Figure 2. Typical Application of Single-Stage Flyback Converter
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Application Diagram
www.fairchildsemi.com
2
VCC
H:open
VREF
VCC
-
Internal
Bias
reset
ZCD
8
VCC
7
OUT
4
CS
6
GND
VZ
+
Clamp
Circuit
VBIAS
2.5VREF
VTH(S/S)
8.5
12
-
5
VCC
+
Restart
Tmer
VTH(ZCD)
Gate
Driver
fMAX
Limit
THD
Optimized
Sawtooth
Generator
Control Range
Compensation
S
Q
R
Q
VO(MAX)
+
Overshoot-less
Control
40kW
+
8pF
INV
-
1
VREF
VREF
Stair
Step
VCS_LIM
+
Clamp
Circuit
reset
VIN Absent
COMP
3
disable
disable
VREF
-
0.35
Thermal
Shutdown
0.45
2.5
2.675
+
OVP
2
INV_open
OVP
VOVP,LH
disable
+
-
2.5
Figure 3.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
2.88
Functional Block Diagram
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Internal Block Diagram
www.fairchildsemi.com
3
VCC
OUT
GND
ZCD
FL7930BG
8-SOP
INV
Figure 4.
OVP COMP
CS
Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
INV
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter
should be resistively divided to 2.5 V.
2
OVP
This pin is used to detect PFC output over voltage when INV pin information is not correct.
3
COMP
4
CS
5
ZCD
This pin is the input of the zero-current detection (ZCD) block. If the voltage of this pin goes
higher than 1.5 V, then goes lower than 1.4 V, the MOSFET is turned on.
6
GND
This pin is used for the ground potential of all the pins. For proper operation, the signal ground
and the power ground should be separated.
7
OUT
This pin is the gate drive output. The peak sourcing and sinking current levels are +500 mA and
-800 mA, respectively. For proper operation, the stray inductance in the gate driving path must be
minimized.
8
VCC
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
This pin is the output of the transconductance error amplifier. Components for the output voltage
compensation should be connected between this pin and GND.
This pin is the input of the over-current protection comparator. The MOSFET current is sensed
using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is
included to filter switching noise.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Pin Configuration
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Min.
Supply Voltage
Max.
Unit
VZ
V
IOH, IOL
Peak Drive Output Current
-800
+500
mA
ICLAMP
Driver Output Clamping Diodes VO>VCC or VO<-0.3 V
-10
+10
mA
Detector Clamping Diodes
-10
+10
mA
-0.3
8.0
-10.0
6.0
IDET
(1)
VIN
Error Amplifier Input, Output, OVP Input, ZCD, RDY, and OVP Pins
CS Input Voltage
(2)
V
TJ
Operating Junction Temperature
+150
°C
TA
Operating Temperature Range
-40
+125
°C
TSTG
Storage Temperature Range
-65
+150
°C
ESD
Electrostatic Discharge
Capability
Human Body Model, JESD22-A114
2.5
Charged Device Model, JESD22-C101
2.0
kV
Notes:
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50 mA.
2. In case of DC input, the acceptable input range is -0.3 V~6 V: within 100 ns -10 V~6 V is acceptable, but
electrical specifications are not guaranteed during such a short time.
Thermal Impedance
Symbol
JA
Parameter
Min.
(3)
Thermal Resistance, Junction-to-Ambient
150
Note:
3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Max.
Unit
°C/W
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Absolute Maximum Ratings
www.fairchildsemi.com
5
VCC = 14 V and TA = -40°C~+125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VCC Section
VSTART
Start Threshold Voltage
VCC Increasing
11
12
13
V
VSTOP
Stop Threshold Voltage
VCC Decreasing
7.5
8.5
9.5
V
3.0
3.5
4.0
V
20
22
24
V
20
V
HYUVLO
UVLO Hysteresis
VZ
Zener Voltage
ICC=20 mA
VOP
Recommended Operating Range
13
Supply Current Section
ISTART
Startup Supply Current
VCC=VSTART-0.2 V
120
190
µA
IOP
Operating Supply Current
Output Not Switching
1.5
3.0
mA
IDOP
Dynamic Operating Supply Current 50 kHz, CI=1 nF
2.5
4.0
mA
90
160
230
µA
2.465
2.500
2.535
V
0.1
10.0
mV
IOPDIS
Operating Current at Disable
VINV=0 V
Error Amplifier Section
VREF1
Voltage Feedback Input Threshold1 TA=25°C
VREF1
Line Regulation
VREF2
Temperature Stability of VREF1
VCC=14 V~20 V
(4)
20
mV
IEA,BS
Input Bias Current
VINV=1 V~4 V
IEAS,SR
Output Source Current
VINV=VREF -0.1 V
-12
µA
IEAS,SK
Output Sink Current
VINV=VREF +0.1 V
12
µA
VEAH
Output Upper Clamp Voltage
VINV=1 V, VCS=0 V
VEAZ
Zero Duty Cycle Output Voltage
gm
Transconductance
(4)
-0.5
0.5
µA
6.0
6.5
7.0
V
0.9
1.0
1.1
V
90
115
140
µmho
Maximum On-Time Section
tON,MAX1
Maximum On-Time Programming 1 TA=25°C, VZCD=1 V
35.5
41.5
47.5
µs
tON,MAX2
T =25°C,
Maximum On-Time Programming 2 A
IZCD=0.469 mA
11.2
13.0
14.8
µs
0.7
0.8
0.9
V
-1.0
-0.1
1.0
µA
350
500
ns
Current-Sense Section
VCS
Current Sense Input Threshold
Voltage Limit
ICS,BS
Input Bias Current
tCS,D
Current Sense Delay to Output
VCS=0~1 V
(4)
dV/dt=1 V/100 ns,
from 0 V to 5 V
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Electrical Characteristics
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
6
VCC = 14 V and TA = -40°C~+125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
1.35
1.50
1.65
V
Zero-Current Detect Section
VZCD
HYZCD
Input Voltage Threshold
(4)
0.05
0.10
0.15
V
VCLAMPH
Input High Clamp Voltage
IDET=3 mA
5.5
6.2
7.5
V
VCLAMPL
Input Low Clamp Voltage
IDET=-3 mA
0
0.65
1.00
V
-1.0
-0.1
1.0
µA
TA=25°C
-4
mA
TA=25°C
10
mA
200
ns
IZCD,BS
Detect Hysteresis
(4)
Input Bias Current
VZCD=1 V~5 V
(4)
IZCD,SR
Source Current Capability
IZCD,SK
Sink Current Capability
tZCD,D
Maximum Delay From ZCD to Output
(4)
Turn-On
(4)
dV/dt=-1 V/100 ns, from
5 V to 0 V
100
9.2
Output Section
VOH
Output Voltage High
IO=-100 mA, TA=25°C
11.0
12.8
V
VOL
Output Voltage Low
IO=200 mA, TA=25°C
1.0
2.5
V
(4)
CIN=1 nF
50
100
ns
(4)
CIN=1 nF
50
100
ns
13.0
14.5
V
1
V
tRISE
tFALL
Rising Time
Falling Time
VO,MAX
Maximum Output Voltage
VCC=20 V, IO=100 µA
VO,UVLO
Output Voltage with UVLO Activated
VCC=5 V, IO=100 µA
11.5
Restart / Maximum Switching Frequency Limit Section
tRST
fMAX
Restart Timer Delay
Maximum Switching Frequency
(4)
50
150
300
µs
250
300
350
kHz
3
5
7
ms
Soft-Start Timer Section
tSS
(4)
Internal Soft-Soft
Protections
TA=25°C
2.620
2.675
2.730
V
HYOVP,INV OVP Hysteresis at INV Pin
VOVP,INV
TA=25°C
0.120
0.175
0.230
V
VOVP,OVP OVP Threshold Voltage at OVP Pin
TA=25°C
2.740
2.845
2.960
V
HYOVP,OVP OVP Hysteresis at OVP Pin
TA=25°C
VEN
HYEN
TSD
THYS
OVP Threshold Voltage at INV Pin
Enable Threshold Voltage
Enable Hysteresis
Thermal Shutdown Temperature
Hysteresis Temperature of TSD
(4)
0.345
V
0.40
0.45
0.50
V
0.05
0.10
0.15
V
125
140
155
°C
(4)
60
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Electrical Characteristics
°C
Note:
4. These parameters, although guaranteed by design, are not production tested.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
7
Function
FL6961
FL7930B
None
Integrated


No External Circuit for additional OVP
OVP Pin
None
Integrated


Abnormal CCM Operation Prohibited
Frequency Limit
VIN-Absent Detection
Soft-Start and
Startup without
Overshoot
None
None
Integrated
Integrated
FL7930B Advantages
Reduction of Power Loss and BOM Cost Caused by
Additional OVP Circuit
Abnormal Inductor Current Accumulation Can Be
Prohibited

Increase System Reliability by Testing for Input Supply
Voltage

Guarantee Stable Operation at Short Electric Power
Failure


Reduce Voltage and Current Stress at Startup

Can Avoid Burst Operation at Light Load and High Input
Voltage
Eliminate Audible Noise Due to Unwanted OVP
Triggering
Control Range
Compensation
None
Integrated

Reduce Probability of Audible Noise Due to Burst
Operation
THD Optimizer
External
Internal
No External Resistor is Needed
TSD
None
140°C with
60°C Hysteresis



Control Range
Compensation
None
Integrated
Stable and Reliable TSD Operation
Converter Temperature Range Limited Range
Comparison of FL7930B and FL7930C
Function
FL7930B
FL7930C
RDY Pin
None
Integrated
OVP Pin
Integrated
None
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
FL7930B Remark

User Choice for the Use of Number #2 Pin
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Comparison of FL6961 and FL7930B
www.fairchildsemi.com
8
Figure 5.
Voltage Feedback Input Threshold 1
(VREF1) vs. TA
Figure 7.
Stop Threshold Voltage (VSTOP) vs. TA
Figure 9.
Operating Supply Current (IOP) vs. TA
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Figure 6.
Figure 8.
Figure 10.
Start Threshold Voltage (VSTART) vs. TA
Startup Supply Current (ISTART) vs. TA
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Typical Performance Characteristics
Output Upper Clamp Voltage (VEAH) vs. TA
www.fairchildsemi.com
9
Figure 11. Zero Duty Cycle Output Voltage (VEAZ)
vs. TA
Figure 12.
Maximum On-Time Program 1 (tON,MAX1)
vs. TA
Figure 13.Maximum On-Time Program 2 (tON,MAX2)
vs. TA
Figure 14.
Current-Sense Input Threshold Voltage
Limit (VCS) vs. TA
Figure 15. Input High Clamp Voltage (VCLAMPH)
vs. TA
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Figure 16.
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Typical Performance Characteristics
Input Low Clamp Voltage (VCLAMPL) vs. TA
www.fairchildsemi.com
10
Figure 17.
Output Voltage High (VOH) vs. TA
Figure 19.
Restart Timer Delay (tRST) vs. TA
Figure 20.
OVP Threshold at OVP Pin (VOVP,OVP)
vs. TA
Output Saturation Voltage (VRDY,SAT)
vs. TA
Figure 22.
OVP Threshold Voltage (VOVP) vs. TA
Figure 21.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Figure 18.
Output Voltage Low (VOL) vs. TA
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Typical Performance Characteristics
www.fairchildsemi.com
11
VOUTPFC
1. Startup: Normally, supply voltage (VCC) of a PFC
block is fed from the additional power supply, which can
be called standby power. Without this standby power,
auxiliary winding for zero current detection can be used
as a supply source. Once the supply voltage of the PFC
block exceeds 12 V, internal operation is enabled until
the voltage drops to 8.5 V. If VCC exceeds VZ, 20 mA
current is sinking from VCC.
+
high
disable
OVP
2.885
2.5
2.675
0.35
0.45
disable
-
VOUTPFC
0.45V/0.35V
+
INV Open
2.5V
INV
-
Aux. Winding
3
External VCC circuit
when no standby power exists.
Figure 24.
Circuit Around INV Pin
413V
390VDC
VREF
2.5VREF
VBIAS
internal
bias
1
FL7930B Rev. 00
COMP
VOUTPFC
VCC’
2
2.675V/2.5V
+
OVP
+
VIN
PFC Inductor
PFC
2.885V
2nd OVP
390V
VCC
H:open
8
reset
VZ
70V
+
VTH(S/S) 20mA
8.5
55V
VINV
2.65V
2.50V
12
2.50V
2.24V
Figure 23.
Startup Circuit
1.64V
0.45V
0.35V
VCC
15V
2. INV Block: Scaled-down voltage from the output is
the input for the INV pin. Many functions are embedded
based on the INV pin: transconductance amplifier,
output OVP comparator, and disable comparator.
2.0V
IOUTCOMP
Current Sourcing
For the output voltage control, a transconductance
amplifier is used instead of the conventional voltage
amplifier. The transconductance amplifier (voltagecontrolled current source) aids the implementation of
the OVP and disable functions. The output current of
the amplifier changes according to the voltage
difference of the inverting and non-inverting input of
the amplifier. To cancel down the line input voltage
effect on power factor correction, the effective control
response of the PFC block should be slower than the
line frequency and this conflicts with the transient
response of the controller. Two-pole one-zero type
compensation can meet both requirements.
I sinking
OVP
VCC<2V, internal logic is not alive.
- Internal signals are unknown.
t
Figure 25.
Timing Chart for INV Block
3. OVP Pin: Over-Voltage Protection (OVP) is
embedded by the information at the INV pin. That
information comes from the output through the voltage
dividing resistors. To scale down from a high voltage to
a low one, high resistance is normally used with low
resistance. If the resistor of high resistance gets
damaged and resistance is changed to high, though INV
pin information is normal, output voltage exceeds its
rated output. If this occurs, the output electrolytic
capacitor may be damaged. To prevent such a
catastrophe additional OVP pin is assigned to doublecheck output voltage. Additional OVP may be called
“second” OVP, while INV pin OVP is called “first” OVP.
Since the two OVP conditions are quite different, the
protection recovering mode is different.
The OVP comparator shuts down the output drive block
when the voltage of the INV pin is higher than 2.675 V
and there is 0.175 V hysteresis. The disable comparator
disables operation when the voltage of the inverting input
is lower than 0.35 V and there is 100 mV hysteresis. An
external small-signal MOSFET can be used to disable the
IC, as shown in Figure 24. The IC operating current
decreases to reduce power consumption if the IC is
disabled. Figure 25 is the timing chart of the internal
circuit near the INV pin when rated PFC output voltage is
390 VDC and VCC supply voltage is 15 V.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Current Sourcing
Disable
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Applications Information
www.fairchildsemi.com
12
where, VAUX is the auxiliary winding voltage; TIND and
TAUX are boost inductor turns and auxiliary winding turns,
respectively; VAC is input voltage for PFC converter; and
VOUT_PFC is output voltage from the PFC converter.
PFC Inductor
VINPFC
VOUTPFC
Aux. Winding
VCC
VCC
RZCD
VSTOP
VSTART
Negative Clamp
Circuit
ZCD
VINV
INV OVP
Level
hysteresis
+
CZCD
OVP Level
Though OutputVoltage Reduced,
no Switching.
THD
Optimized
Sawtooth
Generator
OVP Level
Figure 27.
IMOSFET
Switching stop
until VCC drops
below VSTOP and
recovers to
VSTART
Switching stop
only during
OVP
Comparison of First and Second
OVP Recovery Modes
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Q
Gate
Driver
Circuit Near ZCD
VACIN
VAUX
VZCD
6.2V
0.65V
t
Figure 28. Auxiliary Voltage Depends
on MOSFET Switching
The auxiliary winding voltage is used to check the boost
inductor current zero instance. When boost inductor
current becomes zero, there is a resonance between
boost inductor and all capacitors at the MOSFET drain
pin, including COSS of the MOSFET; an external
capacitor at the D-S pin to reduce the voltage rising and
falling slope of the MOSFET; a parasitic capacitor at
inductor; and so on to improve performance. Resonated
voltage is reflected to the auxiliary winding and can be
used for detecting zero current of boost inductor and
valley position of MOSFET voltage stress. For valley
detection, a minor delay by the resistor and capacitor is
needed. A capacitor increases the noise immunity at the
ZCD pin. If ZCD voltage is higher than 1.5 V, an internal
ZCD comparator output becomes HIGH and LOW when
the ZCD goes below 1.4 V. At the falling edge of
comparator output, internal logic turns on the MOSFET.
5. Zero-Current Detection: Zero-current detection
(ZCD) generates the turn-on signal of the MOSFET
when the boost inductor current reaches zero using an
auxiliary winding coupled with the inductor. When the
power switch turns on, negative voltage is induced at the
auxiliary winding due to the opposite winding direction
(see Equation 1). Positive voltage is induced (see
Equation 2) when the power switch turns off:
(2)
R
fMAX
Limit
VAUX & VZCD
unwanted burst operation easily happens at light load
and audible noise may be generated from the boost
inductor or inductor at input filter. Different from the
other converters, burst operation in PFC block is not
needed because the PFC block itself is normally
disabled during standby mode. To reduce unwanted
burst operation at light load, an internal control range
compensation function is implemented and shows no
burst operation until 5% load at high line.
T
VAUX  AUX  VPFCOUT  VAC 
TIND
IDIODE
IMOSFET
input voltage
(1)
Q
ISW
4. Control Range Compensation: On time is controlled
by the output voltage compensator with FL7930B. Due
to this when input voltage is high and load is light,
control range becomes narrow compared to when input
voltage is low. That control range decrease is inversely
proportional to the double square of the input voltage
1
( control range ∝
Thus at high line,
2 ).
T
VAUX   AUX  VAC
TIND
S
Because auxiliary winding voltage can swing from
negative to positive voltage, the internal block in ZCD
pin has both positive and negative voltage clamping
circuits. When the auxiliary voltage is negative, an
internal circuit clamps the negative voltage at the ZCD
pin around 0.65 V by sourcing current to the serial
resistor between the ZCD pin and the auxiliary winding.
When the auxiliary voltage is higher than 6.5 V, current
is sinked through a resistor from the auxiliary winding to
the ZCD pin.
If error
still exist,
OVP
triggers
again
t
Figure 26.
Restart
Timer
VTH(ZCD)
Positive Clamp
Circuit
Optional
VOVP
-
5
Error on INV
Resistors
Happens
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Once the first OVP triggers, switching stops immediately
and recovers switching when the output voltage is
decreased with a hysteresis. When the second OVP
triggers, switching can be recovered only when the VCC
supply voltage falls below VSTOP and builds up higher
than VSTART again and VOVP should be lower than
hysteresis. If the second OVP is not used, the OVP pin
must be connected to the INV pin or to the ground.
www.fairchildsemi.com
13
Ignores ZCD
Noise
ZCD after COMPARATOR
VOUTPFC - VIN
VOUTPFC - VIN
VIN
MOSFET Gate
Error Happens!
IINDUCTOR
Max fSW Limit
IMOSFET
t
IDIODE
Inhibit Region
Figure 31. Maximum Switching Frequency
Limit Operation
VZCD
1.5V
6. Control: The scaled output is compared with the
internal reference voltage and sinking or sourcing
current is generated from the COMP pin by the
transconductance amplifier. The error amplifier output is
compared with the internal sawtooth waveform to give
proper turn-on time based on the controller.
1.4V
MOSFET gate
150ns Delay
ON
ON
VOUTPFC
t
Figure 29.
Auxiliary Voltage Threshold
6.2V
THD optimized
Sawtooth
Generator
When no ZCD signal is available, the PFC controller
cannot turn on the MOSFET, so the controller checks
every switching off time and forces MOSFET turn on
when the off time is longer than 150 μs. This restart
timer triggers MOSFET turn-on at startup and may be
used at the input voltage zero cross period.
1V
+
Sawtooth
MOSFET Off
INV
-
1
VREF
Stair
Step
+
Clamp
Circuit
COMP
3
VOUT
VIN
C2
R1
C1
Figure 32.
VCC
Unlike a conventional voltage-mode PWM controller,
FL7930B turns on the MOSFET at the falling edge of
ZCD signal. The “ON” instant is determined by the
external signal and the turn-on time lasts until the error
amplifier output (VCOMP) and sawtooth waveform meet.
When load is heavy, output voltage decreases, scaled
output decreases, COMP voltage increases to
compensate low output, turn-on time lengthens to give
more inductor turn-on time, and increased inductor
current raises the output voltage. This is how a PFC
negative feedback controller regulates output.
tRESTART
150s
MOSFET Gate
ZCD after COMPARATOR
t
Figure 30.
Restart Timer at Startup
Because the MOSFET turn-on depends on the ZCD
input, switching frequency may increase to higher than
several megahertz due to the mis-triggering or noise on
the nearby ZCD pin. If the switching frequency is higher
than needed for critical conduction mode (CRM),
operation mode shifts to continuous conduction mode
(CCM). In CCM, unlike CRM where the boost inductor
current is reset to zero at the next switch on; inductor
current builds up at every switching cycle and can be
raised to very high current that exceeds the current
rating of the power switch or diode. This can seriously
damage the power switch. To avoid this, maximum
switching frequency limitation is embedded. If ZCD
signal is applied again within 3.3 μs after the previous
rising edge of gate signal, this signal is ignored
internally and FL7930B waits for another ZCD signal.
This slightly degrades the power factor performance at
light load and high input voltage.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Control Circuit
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
VDS
The maximum of VCOMP is limited to 6.5 V, which
dictates the maximum turn-on time. Switching stops
when VCOMP is lower than 1.0 V.
ZCD after COMPARATOR
VCOMP & Sawtooth
0.155 V / s
MOSFET Gate
t
Figure 33.
Turn-On Time Determination
www.fairchildsemi.com
14
VCC
VSTART=12V
VREFSS
VREFEND=2.5V
5ms
VINV=0.4V
gM
Gain
C1
Integrator
ISOURCECOMP
(VREFSS-VINV)
VCOMP
ISOURCECOMP
gM=ISOURCECOMP
Proportional
Gain
R1
Freq.
RCOMP=VCOMP
C2
High-Frequency
Noise Filter
Figure 34.
t
Figure 36.
Compensators Gain Curve
8. Startup without Overshoot: Feedback control speed
of PFC is quite slow. Due to the slow response, there is
a gap between output voltage and feedback control.
That is why over-voltage protection (OVP) is critical at
the PFC controller and voltage dip caused by fast load
changes from light to heavy is diminished by a bulk
capacitor. OVP can be triggered during startup phase.
Operation on and off by OVP at startup may cause
audible noise and can increase voltage stress at startup,
which is normally higher than in normal operation. This
operation is improved when soft start time is very long.
However, too much startup time enlarges the output
voltage building time at light load. FL7930B has
overshoot protection at startup. During startup, the
feedback loop is controlled by an internal proportional
gain controller and when the output voltage reaches the
rated value, it switches to an external compensator after
a transition time of 30 ms. This internal proportional gain
controller eliminates overshoot at startup and an
external conventional compensator takes over
successfully afterward.
For the transconductance error amplifier side, gain
changes based on differential input. When the error is
large, gain is large to suppress the output dip or peak
quickly. When the error is small, low gain is used to
improve power factor performance.
ICOMP
250 mho
2.6V
2.5V
2.4V
Sourcing
Powering
Sinking
115 mho
Braking
Figure 35.
Soft-Start Sequence
VOUT
Gain Characteristic
Startup
Overshoot
7. Soft-Start: When VCC reaches VSTART, the internal
reference voltage is increased like a stair step for 5 ms.
As a result, VCOMP is also raised gradually and MOSFET
turn-on time increases smoothly. This reduces voltage
and current stress on the power switch during startup.
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
The roles of PFC controller are regulating output voltage
and input current shaping to increase power factor. Duty
control based on the output voltage should be fast
enough to compensate output voltage dip or overshoot.
For the power factor, however, the control loop must not
react to the fluctuating AC input voltage. These two
requirements conflict; therefore, when designing a
feedback loop, the feedback loop should be least ten
times slower than AC line frequency. That slow
response is made by C1 at the compensator. R1 makes
gain boost around operation region and C2 attenuates
gain at higher frequency. Boost gain by R1 helps raise
the response time and improves phase margin.
Conventional Controller
Overshoot-less Startup Control
Control Transition
VCOMP
Depend on Load
Internal Controller
t
Figure 37.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Startup without Overshoot
www.fairchildsemi.com
15
To improve this, lengthened turn-on time near the zero
cross region is a well-known technique, though the
method may vary and may be proprietary. FL7930B
optimizes this by sourcing current through the ZCD pin.
Auxiliary winding voltage becomes negative when the
MOSFET turns on and is proportional to input voltage.
The negative clamping circuit of ZCD outputs the
current to maintain the ZCD voltage at a fixed value.
The sourcing current from the ZCD is directly
proportional to the input voltage. Some portion of this
current is applied to the internal sawtooth generator
together with a fixed-current source. Theoretically the
fixed-current source and the capacitor at sawtooth
generator determine the maximum turn-on time when no
current is sourcing at ZCD clamp circuit and available
turn-on time gets shorter proportional to the ZCD
sourcing current.
VAUX
RZCD
VCC
IIN
THD Optimizer
N
1
IINDUCTOR
IMOSFET
ZCD
5
IDIODE
VZCD
INEGATIVE
Zero Current
Detect
VREF
1.5V
IMOT
1.4V
150ns
MOSFET Gate
reset
ON
CMOT
ON
Sawtooth Generator
t
Figure 38.
Figure 40.
Input and Output Current
Near Input Voltage Peak
VZCD
tON
IIN
Circuit of THD Optimizer
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
9. THD Optimization: Total harmonic distortion (THD)
is the factor that dictates how closely input current
shape matches sinusoidal form. The turn-on time of the
PFC controller is almost constant over one AC line
period due to the extremely low feedback control
response. The turn-off time is determined by the current
decrease slope of the boost inductor made by the input
voltage and output voltage. Once inductor current
becomes zero, resonance between COSS and the boost
inductor makes oscillating waveforms at the drain pin
and auxiliary winding. By checking the auxiliary winding
voltage through the ZCD pin, the controller can check
the zero current of boost inductor. At the same time, a
minor delay is inserted to determine the valley position
of drain voltage. The input and output voltage difference
is at its maximum at the zero cross point of AC input
voltage. The current decrease slope is steep near the
zero cross region and more negative inductor current
flows during a drain voltage valley detection time. Such
a negative inductor current cancels down the positive
current flows and input current becomes zero, called
“zero-cross distortion” in PFC.
tON is typically constant over 1 AC line frequency
but tON is changed by ZCD voltage.
IINDUCTOR
VZCD
tON not shortter
tON get shortter
INEGATIVE
t
VZCD at FET on
1.5V
1.4V
Figure 41.
150ns
MOSFET Gate
ON
ON
ON
By THD optimizer, turn-on time over one AC line period
is proportionally changed, depending on input voltage.
Near zero cross, lengthened turn-on time improves
THD performance.
ON
t
Figure 39.
Effect of THD Optimizer
Input and Output Current Near
Input Voltage Peak Zero Cross
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
16
VOUT
VIN
Though VIN is eliminated,
operation of controller is
normal due to the large
bypass capacitor.
VAUX
MOSFET Gate
DMAX
fMIN
fMIN
DMIN
NewVCOMP
Input Voltage Absent Detected
IDS
VOUT
VIN
Smooth SoftStart
t
Though VIN is eliminated,
operation of controller is
normal due to the large
bypass capacitor.
Figure 43.
With VIN-Absent Circuit
11. Current Sense: The MOSFET current is sensed
using an external sensing resistor for over-current
protection. If the CS pin voltage is higher than 0.8 V, the
over-current protection comparator generates a
protection signal. An internal RC filter of 40 kΩ and 8 pF
is included to filter switching noise.
VAUX
MOSFET Gate
fMIN
12. Gate Driver Output: FL7930B contains a single
totem-pole output stage designed for a direct drive of
the power MOSFET. The drive output is capable of up
to +500 / -800 mA peak current with a typical rise and
fall time of 50 ns with 1 nF load. The output voltage is
clamped to 13 V to protect the MOSFET gate even if the
VCC voltage is higher than 13 V.
DMAX
VCOMP
IDS
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
10. VIN-Absent Detection: To reduce power loss
caused by input voltage sensing resistors and to
optimize THD, the FL7930B omits AC input voltage
detection. Therefore, no information about AC input is
available from the internal controller. In many cases, the
VCC of PFC controller is supplied by an independent
power source like standby power. In this scheme, some
mismatch may exist. For example, when the electric
power is suddenly interrupted during two or three AC
line periods; VCC is still live during that time, but output
voltage drops because there is no input power source.
Consequently, the control loop tries to compensate for
the output voltage drop and VCOMP reaches its
maximum. This lasts until AC input voltage is live again.
When AC input voltage is live again, high VCOMP allows
high switching current and more stress is put on the
MOSFET and diode. To protect against this, FL7930B
checks if the input AC voltage exists. If input does not
exist, soft-start is reset and waits until AC input is live
again. Soft-start manages the turn-on time for smooth
operation when it detects AC input is applied again and
applies less voltage and current stress on startup.
High Drain
Current!
t
Figure 42.
Without VIN-Absent Circuit
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
17
PFC block normally handles high switching current and
the voltage low-energy signal path can be affected by
the high-energy path. Cautious PCB layout is mandatory
for stable operation.
1
2
3
4
5
The gate drive path should be as short as possible.
The closed-loop that starts from the gate driver,
MOSFET gate, and MOSFET source to ground of
PFC controller should be as close as possible. This
is also crossing point between power ground and
signal ground. Power ground path from the bridge
diode to the output bulk capacitor should be short
and wide. The sharing position between power
ground and signal ground should be only at one
position to avoid ground loop noise. Signal path of
the PFC controller should be short and wide for
external components to contact.
The PFC output voltage sensing resistor is normally
high to reduce current consumption. This path can
be affected by external noise. To reduce noise
potential at the INV pin, a shorter path for output
sensing is recommended. If a shorter path is not
possible, place some dividing resistors between
PFC output and the INV pin — closer to the INV pin
is better. Relative high voltage close to the INV pin
can be helpful.
The ZCD path is recommended close to auxiliary
winding from boost inductor and to the ZCD pin. If
that is difficult, place a small capacitor (below
50 pF) to reduce noise.
The switching current sense path should not share
with another path to avoid interference. Some
additional components may be needed to reduce
the noise level applied to the CS pin.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
A stabilizing capacitor for VCC is recommended as
close as possible to the VCC and ground pins. If it is
difficult, place the SMD capacitor as close to the
corresponding pins as possible.
Figure 44.
Recommended PCB Layout
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
PCB Layout Guide
www.fairchildsemi.com
18
Application
Device
Input Voltage
Range
Rated Output
Power
Output Voltage
(Maximum Current)
LED Lighting
FL7930B
90-265 VAC
195 W
390 V (0.5 A)
Features



Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input.
Power factor at rated load is higher than 0.98 at universal input.
Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.
Key Design Notes

When auxiliary VCC supply is not available, VCC power can be supplied through Zero Current Detect (ZCD)
winding. The power consumption of R103 is quite high, so its power rating needs checking.

Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should
be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need
to strike a balance between power consumption and noise immunity.

Quick charge diode (D106) can be eliminated if output diode inrush current capability is sufficient. Through D106,
system operation is normal due to the controller’s highly reliable protection features.
Schematic
Optional
D106
600V 3A
D105
600V 8A
194H, 39:5
LP101,EER3124N
4
1
C111
220F, 450V
INV
R118
3.9M
CS
R114
3.9M
ZCD
Comp
R108 D103,1N4148
4.7
7
OVP
R119
75k
R115
75k
R111
0.08, 5W
C116,1nF
C110,1nF
C112,470pF
C109,
47nF
R110,10k
6
D104,1N4148
GND
R107, C108,
10k 220nF
C105, 100nF
3
2
Out
R117
3.9M
R113
3.9M
Q101
FCPF
20N60
VCC
R116
3.9M
R112
3.9M
D101,1N4746
R104,
30k
5
C115,
2.2nF
R109
47
D102,
UF4004
8
C107,
33F
LF101,
23mH
C114,
2.2nF
C104,
12nF
TH101,
5D15
C102,
680nF
VAUX
R103,
10k,1W
R102,
330k
C1030,68F
,630Vdc
BD101,
600V,15A
DC OUTPUT
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Typical Application Circuit
C101,
220nF
R101,1M-J
ZNR101,
10D471
FS101,
250V,5A
Circuit for VCC. If external VCC is used, this circuit is not needed.
Figure 45.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
Demonstration Circuit
www.fairchildsemi.com
19
EER3019N
Naux 9,10
1,2
9,10
1,2
NP
Naux
6,7
6,7
Np
3,4
3,4
Figure 46.
Transformer Schematic Diagram
Winding Specifications
Position
Bottom
Top
No
Pin (S → F)
Wire
Turns
Winding Method
Np
3, 4 → 1, 2
0.1φ×50
39
Solenoid Winding
5
Solenoid Winding
Insulation: Polyester Tape t = 0.05mm, 3 Layers
NAUX
9,10 → 6,7
0.3φ
Insulation: Polyester Tape t = 0.05 mm, 4 Layers
Electrical Characteristics
Inductance
Pin
Specification
Remark
3, 4 → 1, 2
194 H ± 5%
100 kHz, 1 V
Core & Bobbin
2
Core: EER3019, Samhwa (PL-7) (Ae=137.0mm )
Bobbin: EER3019
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Transformer
www.fairchildsemi.com
20
Part #
Value
Note
Part #
Resistor
Value
Note
Switch
1 MW
1W
R102
330 kW
1/2W
R103
10 kW
1W
D101
1N4746
1 W, 18 V, Zener Diode
30 kW
1/4W
D102
UF4004
1 A, 400 V Glass Passivated
High-Efficiency Rectifier
R107
10 kW
1/4W
D103
1N4148
1 A, 100 V Small-Signal Diode
R108
4.7 kW
1/4W
D104
1N4148
1 A, 100 V Small-Signal Diode
R104
R109
R110
47 kW
10 kW
R111
0.80 kW
R112, 113,
114,116,117,118
3.9 kW
R115,119
75 kW
Q101
FCPF20N60
®
R101
Diode
1/4W
1/4W
D105
8 A, 600 V, General-Purpose
Rectifier
D106
3 A, 600 V, General-Purpose
Rectifier
5W
1/4W
IC101
FL7930B
CRM PFC Controller
1/4W
Capacitor
Fuse
C101
220 nF / 275 VAC
Box Capacitor
C102
680 nF / 275 VAC
Box Capacitor
C103
0.68 µF / 630 V
Box Capacitor
C104
12 nF / 50 V
Ceramic Capacitor
C105
100 nF / 50 V
SMD (1206)
C107
33 µF / 50 V
Electrolytic Capacitor
C108
220 nF / 50 V
Ceramic Capacitor
C109
47 nF / 50 V
Ceramic Capacitor
C110,116
1 nF / 50 V
Ceramic Capacitor
C112
47 nF / 50 V
Ceramic Capacitor
C111
220 µF / 450 V
C114
2.2 nF / 450 V
Box Capacitor
C115
2.2 nF / 450 V
Box Capacitor
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
20 A, 600 V, SuperFET
FS101
5 A / 250 V
NTC
TH101
5D-15
Bridge Diode
BD101
15 A, 600 V
Line Filter
LF101
23 mH
Transformer
T1
Electrolytic Capacitor ZNR101
EER3019
Ae=137.0 mm
ZNR
10D471
2
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Bill of Materials
www.fairchildsemi.com
21
5.00
4.80
A
0.65
3.81
5
8
B
1.75
6.20
5.80
PIN ONE
INDICATOR
4.00
3.80
1
5.60
4
1.27
(0.33)
1.27
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
0.51
0.33
OPTION A - BEVEL EDGE
0.50 x 45°
0.25
R0.10
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
0.40
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08Arev14
F) FAIRCHILD SEMICONDUCTOR.
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 47.
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
Physical Dimensions
8-Lead, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M0/M08A.pdf.
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
22
FL7930B — Single-Stage Flyback and Boundary-Mode PFC Controller for Lighting
© 2010 Fairchild Semiconductor Corporation
FL7930B • Rev. 1.0.4
www.fairchildsemi.com
23
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