IDT IDT6198S85D Cmos static ram 64k (16k x 4-bit) with output control Datasheet


IDT6198S
IDT6198L
CMOS STATIC RAM
64K (16K x 4-BIT)
with Output Control
Integrated Device Technology, Inc.
FEATURES:
• High-speed (equal access and cycle times)
— Military: 20/25/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/35ns (max.)
• Output Enable (OE) pin available for added system flexibility
• Low-power consumption
• JEDEC compatible pinout
• Battery back-up operation—2V data retention (L version
only)
• 24-pin CERDIP, high-density 28-pin leadless chip carrier,
and 24-pin SOJ
• Produced with advanced CMOS technology
• Bidirectional data inputs and outputs
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT6198 is a 65,536-bit high-speed static RAM organized as 16K x 4. It is fabricated using IDT’s high-performance, high-reliability technology—CMOS. This state-of-theart technology, combined with innovative circuit design tech-
niques, provides a cost-effective approach for memory intensive applications. Timing parameters have been specified to
meet the speed demands of the IDT79R3000 RISC processors.
Access times as fast as 15ns are available. The IDT6198
offers a reduced power standby mode, ISB1, which is activated
when CS goes HIGH. This capability significantly decreases
system, while enhancing system reliability. The low-power
version (L) also offers a battery backup data retention capability where the circuit typically consumes only 30µW when
operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate
from a single 5V supply.
The IDT6198 is packaged in either a 24-pin 300 mil CERDIP,
28-pin leadless chip carrier or 24-pin J-bend small outline IC.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
65,536-BIT
MEMORY ARRAY
DECODER
A13
I/O0
I/O1
I/O2
COLUMN I/O
INPUT
DATA
CONTROL
I/O3
CS
WE
OE
2987 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1994 Integrated Device Technology, Inc.
MAY 1994
6.3
DSC-1010/4
1
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE(1)
PIN CONFIGURATIONS
A0
A1
A2
A3
A4
A5
A6
A7
A8
CS
OE
GND
1
24
2
23
3
22
4
D24-1
&
SO24-4
5
6
V CC
A 13
A 12
A 11
A 10
A9
NC
I/O 3
I/O 2
I/O 1
I/O 0
21
20
19
7
18
8
17
9
16
10
15
11
14
12
13
Mode
CS
WE
OE
I/O
Power
Standby
H
X
X
High-Z
Standby
Read
L
H
L
DATAOUT
Write
L
L
X
DATAIN
Active
Read
L
H
H
High-Z
Active
NOTE:
1. H = VIH, L = VIL, X = Don't Care
WE
Symbol
A0
NC
NC
V CC
NC
3
1
28 27
26
5
25
6
24
7
23
L28-2
8
22
9
21
10
20
11
19
18
12
13 14 15 16 17
OE
GND
NC
WE
I/O0
CS
2
4
NC
A 13
A 12
A 11
A 10
A9
I/O3
I/O2
I/O1
2987 drw 03
CS
WE
OE
Mil.
Unit
Terminal Voltage –0.5 to +7.0
with Respect
to GND
–0.5 to +7.0
V
TA
Operating
Temperature
0 to +70
–55 to +125
°C
TBIAS
Temperature
Under Bias
–55 to +125
–65 to +135
°C
TSTG
Storage
Temperature
–55 to +125
–65 to +150
°C
PT
Power Dissipation
1.0
1.0
W
IOUT
DC Output
Current
50
50
mA
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
PIN DESCRIPTIONS
A0–A13
Com’l.
NOTE:
2987 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
LCC
TOP VIEW
Name
Rating
VTERM
DIP/SOJ
TOP VIEW
A1
A2
A3
A4
A5
A6
A7
A8
2987 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
2987 drw 02
INDEX
Active
Parameter(1)
CIN
Input Capacitance
CI/O
I/O Capacitance
Conditions
Max.
Unit
VIN = 0V
7
pF
VOUT = 0V
7
pF
NOTE:
2987 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
Description
Address Inputs
Chip Select
Write Enable
Output Enable
I/O0–I/O3
Data Input/Output
VCC
Power
GND
Ground
2987 tbl 01
6.3
2
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Parameter
Min.
Typ.
VCC
Supply Voltage
4.5
5.0
5.5
V
Military
GND
Supply Voltage
0
0
0
V
Commercial
VIH
Input High Voltage
2.2
—
6.0
V
—
0.8
V
VIL
Input Low Voltage
–0.5
(1)
Max. Unit
Grade
Temperature
GND
VCC
–55°C to +125°C
0V
5V ± 10%
0°C to +70°C
0V
5V ± 10%
2987 tbl 06
NOTE:
2987 tbl 05
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT6198S
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
VCC = Max.,
VIN = GND to VCC
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
Output Leakage Current
VCC = Max., CS = VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
Output Low Voltage
IOL = 10mA, VCC = Min.
0.5
—
0.5
V
IOL = 8mA, VCC = Min.
—
0.4
—
0.4
IOH = –4mA, VCC = Min.
2.4
—
2.4
—
|ILI|
Input Leakage Current
|ILO|
VOL
VOH
Test Condition
IDT6198L
Output High Voltage
V
2987 tbl 07
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
6198S15
6198L15
Symbol
ICC1
ICC2
ISB
ISB1
Parameter
6198S20
6198L20
6198S25
6198L25
Power Com’l. Mil. Com’l. Mil. Com’l.
6198S35
6198L35
6198S45
6198L45
6198S55/70/85
6198L55/70/85
Mil.
Com’l.
Mil.
Unit
Operating Power
Supply Current
CS = VIL, Outputs Open
VCC = Max., f = 0(2)
S
100
—
100
105
100
105
100
105
—
105
—
105
mA
L
75
—
70
80
70
80
70
80
—
80
—
80
Dynamic Operating
Current
CS = VIL, Outputs Open
VCC = Max., f = fMAX(2)
S
135
—
130
160
125
155
125
140
—
140
—
140
L
125
—
115
130
105
120
105
115
—
110
—
110
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
Outputs Open, f = fMAX(2)
S
60
—
55
70
50
60
45
50
—
50
—
50
L
45
—
40
50
35
40
30
35
—
35
—
35
Full Standby Power
Supply Current (CMOS
Level) CS ≥ VHC,
VCC=Max., VIN ≥ V HC or
VIN ≤ VLC, f = 0(2)
S
20
—
15
25
15
20
15
20
—
20
—
20
L
1.5
—
0.5
1.5
0.5
1.5
0.5
1.5
—
1.5
—
1.5
Mil.
Com’l. Mil. Com’l.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.3
mA
mA
mA
2987 tbl 06
3
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Typ. (1)
VCC @
Symbol
Parameter
Test Condition
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR(3)
Chip Deselect to Data
Retention Time
tR(3)
Operation Recovery Time
(3)
|ILI|
—
MIL.
COM’L.
Min.
2.0v
3.0V
2.0V
3.0V
Unit
2.0
—
—
—
—
V
—
—
10
10
15
15
600
150
900
225
µA
0
—
—
—
—
ns
tRC(2)
—
—
—
—
ns
—
—
—
2
2
µA
CS ≥ VHC
VIN ≥ VHC or ≤ VLC
Input Leakage Current
Max.
VCC @
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
2987 tbl 09
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥2V
tCDR
CS
tR
VIH
VIH
VDR
2987 drw 04
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
AC Test Load
See Figures 1 and 2
2987 tbl 10
5V
5V
480Ω
480Ω
DATA OUT
DATA OUT
255Ω
255Ω
30pF*
2987 drw 05
5pF*
2987 drw 06
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tOLZ, tCLZ, tOHZ, tWHZ, tCHZ and tOW)
*Includes scope and jig capacitances
6.3
4
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6198S15(1)
6198L15(1)
Symbol
Parameter
6198S20
6198L20
6198S25
6198L25
Min. Max. Min. Max. Min.
6198S35
6198L35
6198S45/55(2) 6198S70/85(2)
6198L45/55(2) 6198L70/85(2)
Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
15
—
20
—
25
—
35
—
45/55
—
70/85
—
ns
tAA
Address Access Time
—
15
—
19
—
25
—
35
—
45/55
—
70/85
ns
Chip Select Access Time
—
15
—
20
—
25
—
35
—
45/55
—
70/85
ns
Chip Select to Output in Low-Z
5
—
5
—
5
—
5
—
5
—
5
—
ns
tACS
(3)
tCLZ
tOE
tOLZ
Output Enable to Output Valid
—
8
—
9
—
11
—
18
—
25/35
—
45/55
ns
(3)
Output Enable to Output in Low-Z
5
—
5
—
5
—
5
—
5
—
5
—
ns
(3)
Chip Select to Output in High-Z
2
7
2
8
2
10
2
14
—
15/20
—
25/30
ns
(3)
Output Disable to Output in High-Z
2
7
2
8
2
9
2
15
—
15/20
—
25/30
ns
tCHZ
tOHZ
tOH
Output Hold from Address Change
5
—
5
—
2
—
5
—
5
—
5
—
ns
tPU
(3)
Chip Select to Power Up Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tPD
(3)
Chip Deselect to Power Down Time
—
15
—
20
—
25
—
35
—
45/55
—
70/85
ns
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization but is not production tested.
2987 tbl 11
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
CS
tOLZ
tOHZ (5)
(5)
tACS
tCHZ (5)
tCLZ (5)
DATA VALID
DATAOUT
2987 drw 07
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
6.3
5
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
DATAOUT
tOH
PREVIOUS DATA VALID
DATA VALID
2987 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
tACS
tCHZ
tCLZ (5)
DATAOUT
(5)
DATA VALID
tPU
tPD
ICC
VCC SUPPLY
CURRENT ISB
2987 drw 09
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state voltage.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
6198S15(1)
6198L15(1)
Symbol
Parameter
6198S20
6198L20
6198S25
6198L25
Min. Max. Min. Max. Min.
6198S35
6198L35
6198S45/55(2) 6198S70/85(2)
6198L45/55(2) 6198L70/85(2)
Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
Write Cycle Time
14
—
17
—
20
—
30
—
40/50
—
60/75
—
ns
tCW
Chip Select to End-of-Write
14
—
17
—
20
—
25
—
35/50
—
60/75
—
ns
tAW
Address Valid to End-of-Write
14
—
17
—
20
—
25
—
35/50
—
60/75
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tWP
Write Pulse Width
14
—
17
—
20
—
25
—
35/50
—
60/75
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tWHZ(3)
Write Enable to Output in High-Z
—
5
—
6
—
7
—
10
—
15/25
—
30/40
ns
tDW
Data Valid to End-of-Write
10
—
10
—
13
—
15
—
20/25
—
30/35
—
ns
tDH
Data Hold Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
tOW(3)
Output Active from End-of-Write
5
—
5
—
5
—
5
—
5
—
5
—
ns
NOTES:
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only.
3. This parameter is guaranteed by device characterization, but is not production tested.
6.3
2987 tbl 12
6
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7)
tWC
ADDRESS
OE
tAW
CS
tWP
tAS
tWR
WE
tWZ (6)
DATAOUT
tOW (6)
(4)
(4)
tDW
DATAIN
tDH
DATA VALID
2987 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1, 2, 3)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
tDW
DATAIN
tDH
DATA VALID
2987 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap ( tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
6.3
7
IDT6198S/L
CMOS STATIC RAM 64K (16K x 4-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT6198
X
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
L
Y
300 mil CERDIP (D24-1)
Leadless Chip Carrier (L28-2)
Small Outline IC J-Bend (SO24-4)
15
20
25
35
45
55
70
85
Commercial Only
S
L
Standard Power
Low Power
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
2987 drw 12
6.3
8
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