ETC2 ML9478C Static, 1/2 duty, 1/3 duty, 1/4 duty 80 outputs lcd driver Datasheet

FEDL9478C-01
Issue Date:
Apr. 25, 2012
ML9478C
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 80 Outputs LCD Driver
GENERAL DESCRIPTION
The ML9478C is an LCD driver LSI, consists of a 80-bit shift register, a 320-bit data latch, 80 sets of LCD
drivers, and a common signal generation circuit.
It can directly drive an LCD up to 80 segments for static display, 160 segments for 1/2-duty display, 240
segments for 1/3-duty display, and 320 segments for 1/4-duty display.
The three-wire serial interface and I2C interface are selectable.
FEATURES











Logic power supply voltage
: 2.7 to 5.5 V
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
: 80 segments
1/2-duty display
: 160 segments
1/3-duty display
: 240 segments
1/4-duty display
: 320 segments
Interface with microcomputer :
Serial interface : DATA, CLOCK, LOAD
CLOCK transfer speed up to 1 MHz
: SDA, SCL, SDAACK
I2C interface
SCL transfer speed up to 400 kHz
Built-in CR oscillator circuit using the internal resistor or External resistor
Cascade connectable (up to sixteen chips)
Built-in common signal generation circuit
Built-in common output intermediate-value voltage generation circuit
Built-in POC (Power On Clear) circuit
Gold bump chip (ML9478CDVWA)
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FEDL9478C-01
ML9478C
BLOCK DIAGRAM
SEG1
SEG80
VLCD
BIAS
80-Dot Segment Driver
Bias
Resi.
80-Ch Data Selector
Duty0
Duty1
M/S
80
80
80
80
80-Bit
Latch4
80-Bit
Latch3
80-Bit
Latch2
80-Bit
Latch1
LATCH
SELECTOR
80
I2C
LOAD
DATA(SDA)
CLOCK(SCL)
Command
Decoder
80-bit Shift Register
SDAACK
SA1
SA0
A1
A0
OSC I/E
OSC1
OSCR
OSC2
COM1
OSC
TIMING
GENERATOR
COMMON
Driver
COM2
COM3
COM4
CKO
SYNCB
POCEB
RESETB
POC
Circuit
TEST1
TEST2
VDD
GND
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ML9478C
ABSOLUTE MAXIMUM RATINGS
Item
Logic power supply voltage
LCD drive power supply voltage
Input voltage
Output short-circuit current
Chip temperature
Storage temperature
Symbol
VDD
VLCD
VI
Is
Tc
TSTG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
—
Rating
-0.3 to 6.0
-0.3 to 6.0
– 0.3 to VDD + 0.3
-2.0 to +2.0
125
-55 to +150
Unit
V
V
V
mA
°C
°C
Note: Do not use the ML9478C by short-circuiting one output pin to another output pin as well as to other pin
(input pin, input/output pin, or power supply pin).
RECOMMENDED OPERATION CONDITIONS
Item
Logic power supply voltage
LCD drive power supply voltage
OSC IN clock frequency
Data clock frequency
SCL clock frequency
Operating temperature
Symbol
Condition
Range
Unit
VDD*
VLCD*
fCP1
fCP2
fSCL
Ta
—
—
—
—
—
—
2.7 to 5.5
4.5 to 5.5
up to 10
up to 1.0
up to 400
-40 to +105
V
V
kHz
MHz
kHz
°C
Note(*): Use at VDD  VLCD.
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
Recommended setting range for external component (oscillator circuit)
Item
Oscillation resistor
Frame frequency
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= –40 to +105°C)
Min
TYP
Max
Unit
Symbol
Condition
Rf
—
423
470
517
kΩ
fFRM
(F1,F0)=(0,1)
47
75
114
Hz
The relation between oscillation resistor and frame frequency is as the equation below.
fFRM = fOSC /(16 x 24)
fosc = 1 / (Device coefficient x External resistor Rf)
Device coefficient = 73.8 x 10-12 ± 25%
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ML9478C
ELECTRICAL CHARACTERISTICS
DC Characteristics
Item
"H" input voltage
"L" input voltage
Input leakage current 1
Symbol
VIH
VIL
IL1
Input leakage current 2
IL2
Pull-up current
Ipu
"H" output voltage
"L" output voltage 1
"L" output voltage 2
Driver
ON resistor
VOH
VOL1
VOL2
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Condition
Min.
Typ.
Max.
Unit
Applicable pin
—
0.8VDD
—
VDD
V
(*1)
—
GND
—
0.2VDD
V
(*1)
VI = VDD or 0 V
-1.0
—
1.0
μA (*1)
VI = VDD or 0V
-1.0
—
1.0
μA RESETB
POCEB="H"
VDD = 5.0V,VI = 0 V
30
—
140
μA RESETB
POCEB = "L"
IO = -600uA
0.9VDD
—
—
V CKO, SYNCB
IO = 600uA
—
—
0.1VDD
V
CKO, SYNCB
IO = 600uA
—
—
0.1VDD
V
SDAACK
Segment
VOHS
VLCD = 5V
—
5
15
kΩ
SEG1 to SEG80
Common
VOHC
VLCD = 5V
—
5
12
kΩ
COM 1 to COM4
(*1) : DATA(SDA), CLOCK(SCL), LOAD, M/S, SYNCB, Duty1, Duty0, BIAS, SA1,SA0, A1, A0, OSC1,
OSC I/E, I2C, POCEB
Item
Static supply
current
Dynamic supply
current 1
Dynamic supply
current 2
Dynamic supply
current 3
Dynamic supply
current 4
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta= -40 to +105°C)
Applicable
Min.
Typ.
Max.
Unit
pin
Symbol
Condition
IDDS
VDD=VLCD=5.5 V
Input pin fixed to "H" or "L"
Oscillation stopped, output no-load
POCEB="L"
VDD=VLCD= 5.5 V (*2)(*3)
(*6)
Clock OSC1 external input
(*7)
fCP1=1.8kHz
—
8
15
μA
VDD
—
9
15
μA
VLCD
—
10
18
μA
VDD
—
9
15
μA
VLCD
(*6)
—
61
90
μA
VDD
(*7)
—
9
15
μA
VLCD
—
130
250
μA
VDD
—
9
15
μA
VLCD
—
202
330
μA
VDD
—
9
15
μA
VLCD
ILCDS
IDD1
ILCD1
IDD2
ILCD2
IDD3
ILCD3
IDD4
ILCD4
VDD=VLCD= 5.5 V (*2)(*3)
Internal oscillation
VDD=VLCD= 5.5 V (*2)(*4)(*6)
Internal oscillation
At three-wire serial IF data input
VDD=VLCD= 5.5 V (*2)(*5)(*6)
Internal oscillation
2
At I C IF data input
(*2) : M/S = "H", 1/4-duty, 1/3-bias, (F1,F0) = (1,1) 95 Hz, POCEB = "L", output pin no-load.
(*3) : Three-wire serial or I2C interface. Input pin fixed to "H" or "L".
(*4) : Serial interface, data input frequency = 1 MHz.
(*5) : I2C interface, data input frequency = 400 kHz.
(*6) : Alternately inputs "0" and "1" for LCD display data (checkered display).
(*7) : Inputs all "1s" for LCD display data (all illuminated).
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Switching Characteristics

OSC timing
Item
OSC IN clock frequency
(external input)
Clock pulse width
(External input)
Clock rise and fall time
(external input)
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min.
Typ. Max.
Unit
Applicable pin
Symbol
fCP1
tWCP1
Clock input from OSC1.
OSC2 and OSCR open.
OSC I/E = "L"
tOSC
External Rf clock
frequency
(Internal oscillation)
fOSC1
Internal clock frequency
(Internal oscillation)
fOSC2
Between OSC1 and OSC2
Rf = 470kΩ
(F1,F0)=(0,1)
OSCR open.
OSC I/E = "H"
OSC1 open.
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
OSC I/E = "H"
—
1.8
10
kHz
OSC1
40
—
—
μs
OSC1
—
—
(*1)
μs
OSC1
18
28.8
44
kHz
OSC1, OSC2
18
28.8
44
kHz
OSC1, OSCR,
OSC2
The relation between OSC IN clock frequency and frame frequency is as the equation below.
fFRM = fOSC /24
(*1) tOSC is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2μs.

Serial interface timing
Item
Data clock frequency
Data clock pulse width
Data setup time
Data hold time
CLOCK-LOAD timing
LOAD-CLOCK timing
LOAD pulse width
Symbol
fCP2
tWCP2
tSU
tHD
tCL
tLC
tWLD
Signal rise and fall time
tsr,tsf
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. Unit
Applicable pin
—
—
1
MHz CLOCK
100
—
—
ns CLOCK
50
—
—
ns DATA
50
—
—
ns CLOCK
100
—
—
ns CLOCK
100
—
—
ns LOAD
100
—
—
ns LOAD
CLOCK,DATA,
—
—
(*2)
ns
LOAD
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
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ML9478C

I2C interface timing
Item
SCL clock frequency
Hold time (repeat)
"STATRT" condition
SCL "L" pulse width
SCL "H" pulse width
Setup time for repeat
"START" condition
Data hold time
Data setup time
Setup time for "STOP"
condition
Bus free time between
"STOP" condition and
"START" condition
Data valid acknowledge
time
Signal rise and fall time
Data bus load
capacitance
Noise pulse width
tolerance
Symbol
fSCL
(VDD = 2.7 to 5.5 V, VLCD = 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. Unit
Applicable pin
—
—
400 kHz SCL
tHD,STA
0.6
—
—
μs
SCL,SDA
tLOW
tHIGH
1.3
0.6
—
—
—
—
μs
μs
SCL
SCL
tSU,STA
0.6
—
—
μs
SCL,SDA
tHD,DAT
tSU,DAT
0
200
—
—
—
—
ns
ns
SCL,SDA
SCL,SDA
tSU,STO
0.6
—
—
μs
SCL,SDA
tBUF
1.3
—
—
μs
SCL
tVD,ACK
—
—
1.2
μs
SCL,SDAAACK
tir,tif
—
—
(*3)
μs
SCL,SDA
Cb
—
—
400
pF
SDA,SDAACK
twf
—
—
50
ns
SCL,SDA
(*3) tir and tif shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=0.1μs.
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ML9478C
Timing chart (OSC1)
1/fCP1
tWCP1
VIH
OSC1
(External clock)
tWCP1
VIH
V IH
V IL
V IL
tOSC
Timing chart (Serial interface)
VIH
DATA
V IH
VIL
VIL
tSU
tsf
tWCP2
tsr
VIH
VIH
V IL
V IL
V IL
tHD
tWCP2
CLOCK
VIH
V IH
V IL
V IH
VIH
V IL
V IL
VIL
1/f CP2
tCL
tWLD
tsr
t LC
tsf
V IH VIH
LOAD
V IL
V IL
tsr
tsf
Timing chart (I2C interface)
tVD;ACK
VIH
VIH
SDA
VIH
VIL
VIL
tBUF
VIH
VIH
SCL
tHD;STA
VIL
tf
tLOW
VIH
VIL
VIL
VIH
VIL
tHiGH
tHD;DAT
tr
VIH
VIH
VIL
VIL
tSU;DAT
VIH
SDA
tSU;STA
VIL
tSU;STO
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REFERENCE DATA
Frame frequency Characteristics
VDD=5.5V/2.7V Rf=470Ω
Frame frequency fFRM = fOSC /(16 x 24)
fosc = 1 / (Device coefficient x External resistor Rf)
Device coefficient = 73.8 x 10-12 ± 25%
Frame frequency Characteristics Rf=470k,VDD=5.5V
120
Frame Frequency fFRM[Hz]
110
(F1,F0)=(1,1)
100
(F1,F0)=(1,0)
90
(F1,F0)=(0,1)
80
(F1,F0)=(0,0)
70
60
50
-60
-40
-20
0
20
40
60
80
100
120
Temp Ta[℃]
Frame frequency Characteristics Rf=470k,VDD=2.7V
130
120
Frame Frequency fFRM[Hz]
(F1,F0)=(1,1)
110
(F1,F0)=(1,0)
100
90
(F1,F0)=(0,1)
80
(F1,F0)=(0,0)
70
60
50
-60
-40
-20
0
20
40
60
80
100
120
Temp Ta[℃]
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POWER ON/OFF TIMING
To turn on the power supply, raise the logic power supply first, then LCD drive power supply in order to prevent
the IC from malfunctioning.
To fall the power supply, fall the LCD drive power supply first, then the logic power supply.
For a VDD pin ranging from 0 V to VDDmin, set VDD ≥ VLCD and t1 ≥ 0 [ns].
To enable the Internal POC circuit, the VDD power supply rise time t2 range needs to be 100 [µs] t2 500 [ms].
For the VDD power supply to turn OFF then turn ON again, it is necessary to secure the POC discharge time t3
100 [ms].
Voltage
VLCD
VDD
VDD
0.9VDD
t3
t1
t2
t1
Time
INITIALIZATION SIGNAL TIMING
When RESETB signal is externally input
The RESETB pin input is valid both for POCEB = "L" and "H". Usable in combination with the POC.
Keep the RESETB pin at "L" level until the VDD reaches VDDmin. (t4 ≥ 200[ns])
VDD
VDDmin
RESETB
VIL
t4
When Internal POC circuit is used
When using the Internal POC circuit in the initialization, set the POCEB pin to "L".
At this time, the power ON/OFF timing conditions are t1 to t3 above mentioned.
When RESETB pin POC circuit is used
If the power ON/OFF timing conditions t1 to t3 cannot be kept, the RESETB pin needs to have a capacitance
to configure the POC circuit. For this case, connect a capacitance value according to the power supply rise
time.
For the power supply rise time t2 and external capacitance value, use the following formula as a guide:
CRST [F]
> t2 [sec]/(30×103)
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PIN DESCRIPTIONS
Pad
number
Symbol
I/O
67-68
M/S
I
6-7
4-5
Duty0
Duty1
*1
I
73-74
BIAS
I
14-15
12-13
10-11
8-9
SA1
SA0
A1
A0
71-72
OSC I/E
Description
This is the input to switch between the master and slave modes. It has a
schmitt circuit. When this pin is "H", the mode is master. When this pin is "L",
the mode is slave.
Display duty switch pins. These have schmitt circuits.
Duty0="L", Duty1="L" : Static
(COM1=COM2=COM3=COM4)
Duty0="H", Duty1="L" : 1/2Duty
(COM1=COM3, COM2=COM4)
Duty0="L", Duty1="H" : 1/3Duty
(COM2=COM4)
Duty0="H", Duty1="H" : 1/4Duty
This pin sets the LCD bias. It has a schmitt circuit.
BIAS="L": 1/3bias
BIAS="H": 1/2bias
I
Slave address input pins. These have schmitt circuits.
I
Sub address input pins. These have schmitt circuits.
I
This input selects whether to use the external clock input mode or to use the
Internal oscillation mode or external oscillation mode. It has a schmitt circuit.
When this pin is "H", the mode is the Internal or external Rf oscillation mode.
When this pin is "L", the mode is the external clock input mode.
Use the slave chip as it is connected to GND.
46-48
53-55
49-52
OSC1,
OSCR,
OSC2
*2
I
I
O
56-56
CKO
O
These pins are for the oscillator circuit to generate common signals.
The OSC1 and OSCR pins are input pins and have a schmitt circuit.
OSC2 is an output pin. It becomes an output when the OSC I/E pin = "H" and
a high impedance when the OSC I/E pin = "L".
【In the master mode (M/S pin ="H") 】
Three types are selectable: Internal oscillation mode, external oscillation
mode, and external clock input mode.
•Internal oscillation mode: Set the OSC I/E pin to "H", short the OSCR and
OSC2 pins, and open the OSC1 pin.
•External Rf oscillation mode: Set the OSC I/E pin to "H", connect an
oscillation resistor Rf between the OSC1 and OSC2 pins, and open the
OSCR pin.
•External clock input mode: Set the OSC I/E pin to "L", open the OSCR and
OSC2 pins, and input the external clock to the OSC1 pin.
【 In the slave mode (M/S pin ="L") 】
Open the OSCR and OSC2 pins and connect the OSC1 pin to the
ML9478C's CKO pin that has been set to the master mode.
Clock output pin.
In the master mode (M/S pin = "H"), the 1/16 division signal of the oscillation
frequency is output.
In the slave mode (M/S pin = "L"), the output is fixed to "L".
For a cascade connection, connect this pin to the OSC1 pin of the chip that
has been set to the slave mode.
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FEDL9478C-01
ML9478C
60-63
SYNCB
I/O
65-66
I2C
I
20-21
DATA
(SDA)
I
22-23
CLOCK
(SCL)
I
24-25
LOAD
I
17-19
SDAACK
O
69-70
POCEB
I
44-45
RESETB
*3
I
Input/output pin for common synchronization. It has a schmitt circuit.
It becomes the synchronization signal output pin in the master mode (M/S
pin = "H").
It becomes the synchronization signal input pin in the slave mode (M/S pin = "L").
For cascade connection, connect all of the involved ML9478Cs' SYNC pins
by the common line.
Interface switching pin. It has a schmitt circuit.
2
When this pin is "H", the interface is I C.
When this pin is "L", the interface is three-wire serial.
Display data input pin. It has a schmitt circuit.
I2C="L": Serial interface; DATA
Input the display data in the order of SEG80, SEG79, ... , SEG2, and SEG1.
The display data turns on at "H" and turns off at "L".
2
I2C="H": I C interface; SDA
Input the display data in units of 8 bits. The display data turns on at "H" and
turns off at "L".
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Shift clock input pin for display data. It has a schmitt circuit.
I2C="L": Serial interface; CLOCK
The display data input to the DATA pin is serially input to the shift register at
the CLOCK signal rise.
2
I2C="H": I C interface; SCL
The display data input to the SDA pin is serially input to the shift register at
the SCL signal rise.
This pin has a built-in noise filter through which noises in widths up to 50 ns
are removed. This noise filter is valid only when I2C = "H".
Input pin for the load signal of display data. It has a schmitt circuit.
I2C="L": Serial interface; LOAD
The display data in the shift register is transmitted as is to the segment driver
for the "H" duration. When this pin is brought into "L", the shift register is
disconnected from the segment driver. The display data in the shift register
immediately before it become "L" is held in the data latch and transmitted to
the segment driver.
2
I2C="H": I C interface
Use this pin as it is connected to GND.
I2C="L": Serial interface
Use this pin as it is opened.
2
I2C="H": I C interface
2
The I C bus acknowledge output signal. Normally, use it as it is connected
with the SDA pin.
Connect an external pull-up resistor whenever
necessary, as it is an open drain pin. The pull-up connection destination
supply voltage shall be the VDD supply voltage or less.
Internal POC circuit enable pin. It has a schmitt circuit.
When this pin is "H", the POC circuit becomes OFF and the constant current
(8µA) is cut. The RESETB pin pull-up resistor is cut as well.
When this pin is "L", the POC circuit becomes ON.
The RESETB pin is connected to a pull-up resistor.
Reset signal input pin for initializing inside the IC. It has a schmitt circuit.
The "L" level enables the reset.
This pin has an Internal pull-up resistor. Open when POCEB = "H".
Pull-up when POCEB = "L". The power-on reset operation is available by
connecting an external capacitor.
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32-37
VDD
-
Pin for testing the IC. It has an Internal pull-down resistor.
Use it as it is connected to GND.
Outputs for LCD display. Connected to the segment pins on the LCD panel.
In the display off mode, all the outputs are fixed to GND.
Outputs for LCD display. Connected to the common pins on the LCD panel.
The output pins are located at three positions: both ends of the chip and
between SEG40 and SEG41. Each is connected inside the chip. Use the
COM pins in accordance with the panel to be used.
In the display off mode, all the outputs are fixed to GND.
When the slave is set (M/S=”L”), COM1 to COM4 outputs are GND level
fixed.
Power supply pin for logic circuit.
38-43
VLCD
-
Power supply pin for LCD driver.
26-31
16
64
3
79
1-2
80-84
89-94
179-182
187-190
GND
-
VDDO
-
GNDO
-
Ground pin.
VDD output pin.
Use this pin when fixing the mode setting input pin to "H" on the COG.
Ground output pin.
Use this pin when fixing the mode setting input pin to "L" on the COG.
DUMMY
-
77-78
75-76
95-134
139-178
TEST1
TEST2
SEG1
SEG80
85-88
135-138
183-186
COM1
COM4
I
O
O
Floating pin.
At this time, avoid this pin from shorting with pins other than DUMMY in the
wiring on the COG.
*1: For details of the COM /SEG waveform when a duty is selected, refer to "Common waveform" on page 18
and "Common Segment waveform" on page 19 to 23.
*2: Oscillator circuit configuration
• When M/S = "H", OSC I/E = "H"
[Internal Rf oscillation mode]
OPEN
[External Rf oscillation mode]
OSC1
OSC1
Rf
OSC2
OSC2
OSCR
OPEN
OSCR
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FEDL9478C-01
ML9478C
• External clock input mode when M/S = "H" and OSC I/E = "L"
External
clock
OSC1
OPEN
OSC2
OPEN
OSCR
• M/S = "L", slave mode, external clock input mode
Master CKO
OSC1
OPEN
OSC2
OPEN
OSCR
*3: Reset circuit configuration
• External input to RESTB when POCEB = "H"
VDD
External
input
RESETB
• POC circuit configuration when POCEB = "L"
VDD
Crst
RESETB
13/31
FEDL9478C-01
ML9478C
DESCRIPTION
Operation description (Serial interface)
• Display data input
As described in the Data configuration section, the display data consists of the data field that corresponds to
each segment on/off and the command field that indicates the display data input.
When inputting the display data, the "F3" command is set in the command field. When the "F1" or "F2"
command is set in the command field, the display data in the data field becomes invalid.
The data input to the DATA pin is loaded to the shift register at the CLOCK pulse rise, transferred to the
display data latch during the LOAD pulse at the "H" level, then output via the segment driver.
CLOCK
DATA
D1
D2
D3
D4
D80 C0
C1
C2
C3
C4
C5
C6
C7
Command field
Data field
LOAD
Display output
Old data
New data
• Display on, Display off
The display becomes off at power-on reset. To display, write the display on command.
The display off is the command that makes all segments off. Writing the display off command turns off the
lights regardless of the display data.
The display on is the command to release the display off. Writing the display on command returns the display
to the original state.
CLOCK
DATA
D1 D2
C6 C7
C4 C5 C6 C7
C4 C5 C6 C7
LOAD
Display ON/OFF
RESET
Display data input
Display on
Display off
command write
command write
14/31
FEDL9478C-01
ML9478C
List of Commands
Command
name
F0
C7
C6
C5
C4
C3
C2
C1
C0
Operation
0
0
0
0
x
x
x
x
Disabled
F1
0
1
F1
(*2)
F0
(*2)
x
x
x
x
F2
1
0
1
D
(*2)
x
x
x
x
F3(*1)
1
1
SA1
SA0
A1
A0
Co1
Co0
Frame frequency setting
(F1,F0)=(0, 0): 65Hz
(F1,F0)=(0, 1): 75Hz
(F1,F0)=(1, 0): 85Hz
(F1,F0)=(1, 1): 95Hz
(valid for Internal CR oscillation)
Display on/off
"0" : Off (COM=SEG=GND)
"1" : On
Data write address setting
(Co1,Co0)=(0, 0): Corresponding to
common 1
(Co1,Co0)=(0, 1): Corresponding to
common 2
(Co1,Co0)=(1, 0): Corresponding to
common 3
(Co1,Co0)=(1, 1): Corresponding to
common 4
SA1, SA0, A1, A0: Chip address
x: Don't care
(*1): For the I2C interface, SA1 and SA0 are set at a slave address.
These bits become "Don't care".
(*2): The register is set to the following value by the RESETB = "L" input or by the power-on POC.
F1="0", F0="0", D="0"
Data configuration
• Data configuration (Serial interface)
First bit
Corresponding to SEG80
Corresponding to SEG1
C7
C6
C5
C4
C3
C2
Command
C1
C0
D80
D79
D78
D3
D2
D1
LCD display data
Note 1 : The commands F1 and F2 settings become valid when the least four bits of C4 to C7 are input.
(The bits from D1 to D80 and from C0 to C3 are not necessary.)
Note 2 : If the dummy bit is needed for the reason of number of transfer bits, put it on the first bit side.
Note 3 : The command execution follows the contents of the C7 to C0 registers immediately before the LOAD
becomes "H".
15/31
FEDL9478C-01
ML9478C
• Data configuration (I2C interface)
S
0
Slave address
1 1 0 0
SA1 SA0
R/W
0 A CO RS
Control byte
DATA/Command
A
LSB
MSB
P
Salve address: 0 1 1 0 0 1
CO: Consecutive control byte setting bit
0: Last control byte, 1: Consecutive control byte
RS: Command/data setting bit
0: Command data, 1: Display data
For the I2C interface, each IC is assigned with a 7-bit slave address. The first one byte in the transfer consists of
this 7-bit slave address and the R/W bit that indicates the data transfer direction. Always input "0" to the eighth
R/W bit because the ML9478C is a write-only LSI.
The eight bits next to the slave address is a control byte. The first one bit is CO: consecutive command setting bit
and the next one bit is RS: command/data setting bit (the remaining six bits are the Don't care bits).
When CO = "0": Means the last control byte.
When CO = "1": Means the control bytes are successively input.
When RS = "0": Means the data to be input next is the command data.
When RS = "1": Means the data to be input next is the display data.
The display data can be successively input.
Example of Data Setting

When inputting two commands
When inputting two commands
S

0
1
0
0
1
0
0
SA1 SA0
0
A
1
0
COMMAND
A
COMMAND
A
A
COMMAND
A
A
Display data
A
A
Display data
A
A
A
P
When inputting the command and display data
S
0
1
0
1
1
0
0
SA1 SA0
0
A
A
Display data
A
1
0
Display data
P
16/31
FEDL9478C-01
ML9478C
Data write method
• Serial interface
The data is written to the address set by the data write setting command (F3).
For the Serial interface, the data is written in units of 80 bits.
Written from D80 to SEG1, D79 to SEG2, ... , D2 to SEG79, and D1 to SEG80.
MSB
COM1
COM2
COM3
COM4
1
2
3
4
D80
D80
D80
D80
D79
D79
D79
D79
D78
D78
D78
D78
D77
D77
D77
D77
MSB
41
COM1
COM2
COM3
COM4
D40
D40
D40
D40
42
D39
D39
D39
D39
43
D38
D38
D38
D38
44
D37
D37
D37
D37
Segment output
32
33
34
35
36
37
38
39
D49
D49
D49
D49
D48
D48
D48
D48
D47
D47
D47
D47
D46
D46
D46
D46
D45
D45
D45
D45
D44
D44
D44
D44
D43
D43
D43
D43
D42
D42
D42
D42
Segment output
72
173
74
75
76
77
78
79
D9
D9
D9
D9
D8
D8
D8
D8
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
LSB
40
D41
D41
D41
D41
LSB
80
D1
D1
D1
D1
• I2C interface
The data is written to the address set by the slave address.
For the I2C interface, the data is written to the specified address starting with the LSB side in units of 8 bits.
(The data is written in the order from SEG73-80, SEG65-SEG72, ... , SEG9-16, and SEG1-SEG8.)
LSB
COM1
COM2
COM3
COM4
2
3
4
32
33
34
35
36
37
38
39
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D8
D8
D8
D8
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
LSB
41
COM1
COM2
COM3
COM4
Segment output
1
D1
D1
D1
D1
42
D2
D2
D2
D2
43
D3
D3
D3
D3
44
D4
D4
D4
D4
Segment output
72
73
74
75
76
77
78
79
D8
D8
D8
D8
D1
D1
D1
D1
D2
D2
D2
D2
D3
D3
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
D6
D6
D7
D7
D7
D7
MSB
40
D8
D8
D8
D8
MSB
80
D8
D8
D8
D8
17/31
FEDL9478C-01
ML9478C
 Common waveforms
(1) At static
VLCD
COM1~4
GND
(2) At 1/2-duty
At 1/2-bias
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
At 1/3-bias
COM1
COM3
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
(3) At 1/3-duty
COM1
COM2
COM4
COM3
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
(4) At 1/4-duty
COM1
COM2
COM3
COM4
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
18/31
FEDL9478C-01
ML9478C
● Common segment output waveform
・At Static
Display example
COM1
S
E
G
1
S
E
G
2
S
E
G
3
On
Off
COM1
COM2
COM3
COM4
VLCD
2VLCD/3
VLCD/3
GND
SEG1
VLCD
2VLCD/3
VLCD/3
GND
SEG2
VLCD
2VLCD/3
VLCD/3
GND
SEG3
VLCD
2VLCD/3
VLCD/3
GND
19/31
FEDL9478C-01
ML9478C
● Common and segment output waveforms
・At 1/2Duty, 1/2bias
Display example
S
E
G
1
S
E
G
2
S
E
G
3
COM1
On
COM2
Off
VLCD
COM1
COM3
VLCD/2
GND
VLCD
COM2
COM4
VLCD/2
GND
VLCD
SEG1
VLCD/2
GND
VLCD
SEG2
VLCD/2
GND
VLCD
SEG3
VLCD/2
GND
20/31
FEDL9478C-01
ML9478C
● Common and segment output waveforms
・At 1/2Duty, 1/3bias
Display example
COM1
COM3
S
E
G
1
S
E
G
2
S
E
G
3
COM1
On
COM2
Off
VLCD
2VLCD/3
VLCD/3
GND
COM2
COM4
VLCD
2VLCD/3
VLCD/3
GND
SEG1
VLCD
2VLCD/3
VLCD/3
GND
SEG2
VLCD
2VLCD/3
VLCD/3
GND
SEG3
VLCD
2VLCD/3
VLCD/3
GND
21/31
FEDL9478C-01
ML9478C
● Common and segment output waveforms
・At 1/3Duty, 1/3bias
Display example
S
E
G
1
S
E
G
2
S
E
G
3
COM1
On
COM2
Off
COM3
VLCD
COM1
2VLCD/3
VLCD/3
GND
VLCD
COM2
COM4
2VLCD/3
VLCD/3
GND
VLCD
COM3
2VLCD/3
VLCD/3
GND
VLCD
SEG1
2VLCD/3
VLCD/3
GND
VLCD
SEG2
2VLCD/3
VLCD/3
GND
VLCD
SEG3
2VLCD/3
VLCD/3
GND
22/31
FEDL9478C-01
ML9478C
● Common and segment output waveforms
・At 1/4Duty, 1/3bias
Display example
S
E
G
1
S
E
G
2
S
E
G
3
COM1
COM2
On
COM3
Off
COM4
COM1
VLCD
2VLCD/3
VLCD/3
GND
COM2
VLCD
2VLCD/3
VLCD/3
GND
COM3
VLCD
2VLCD/3
VLCD/3
GND
COM4
SEG1
VLCD
2VLCD/3
VLCD/3
GND
VLCD
2VLCD/3
VLCD/3
GND
SEG2
VLCD
2VLCD/3
VLCD/3
GND
SEG3
VLCD
2VLCD/3
VLCD/3
GND
23/31
FEDL9478C-01
ML9478C
EXAMPLE OF APPLICATION CIRCUIT
Cascade configuration 1
Serial interface
Internal CR oscillator circuit used
1/4Duty
RESETB pin + external capacitance connection to configure POC circuit
The common outputs of the slave chip output GND-level. So Com1 to Com4 set to open.
[External component]
Cp = 0.1 [µF] (bypass capacitor between power supplies)
Crst = 4.7 [µF] (capacitance for external POC circuit)
Crst
SEG80
(Slave)
OSC1
OSC2
OSCR
CKO
OPEN
OPEN
OPEN
RESETB
Crst
SYNCB
RESETB
ML9478C
SDAACK
OPEN
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
TEST1
TEST2
GND
CLOCK
OSC1
OSC2
OSCR
CKO
Cp
DATA
Cp
(Master)
OPEN
VLCD
VDD
SEG1
SEG80
ML9478C
COM1
COM2
COM3
COM4
LOAD
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
TEST1
TEST2
GND
SYNCB
Cp
CLOCK
Cp
OPEN
5V
5V
SDAACK
VLCD
VDD
DATA
5V
5V
LOAD
COM1
COM2
COM3
COM4
SEG1
Liquid crystal panel 1/4-duty x 80 x n segments
OPEN
CPU
24/31
FEDL9478C-01
ML9478C
Cascade configuration 2
II2C interface
External Rf-based CR oscillator circuit used
1/4Duty
External RESETB signal input
The common outputs of the slave chip output GND-level. So Com1 to Com4 set to open.
[External component]
Cp = 0.1 [µF] (bypass capacitor between power supplies),
Rf = 470 [k] (external R, resistor for CR oscillator circuit),
Rup = Resistor for SDA data bus pull-up
SEG80
(Slave)
OSC1
OSC2
OSCR
CKO
OPEN
OPEN
OPEN
RESETB
SYNCB
SDAACK
OPEN
ML9478C
SCL
RESETB
Rf
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
TEST1
TEST2
GND
SEG1
SEG80
OSC1
OSC2
OSCR
CKO
Cp
SDA
Rup
VLCD
VDD
Cp
(Master)
COM1
COM2
COM3
COM4
LOAD
5V
M/S
BIAS
OSCI/E
POCEB
Duty0
Duty1
I2C
SA1
SA0
A1
A0
TEST1
TEST2
GND
SYNCB
Cp
SDAACK
Cp
OPEN
5V
5V
ML9478C
SDA
VLCD
VDD
SCL
5V
5V
LOAD
COM1
COM2
COM3
COM4
SEG1
Liquid crystal panel 1/4-duty x 80 x n segments
CPU
25/31
FEDL9478C-01
ML9478C
PAD CONFIGURATION
Pad layout (pattern face)
Chip size
Chip thickness
Minimum bump pitch
Bump height
B
: 4.80 mm x 0.90 mm
: 400 m ± 20 m
: 50 m
: 15 m ±3 m
93
180
Y
181
(0,0)
190
92
X
82
1
81
A
Bump and alignment mark dimensions (pattern face)
: 32 m x 80 m
PAD No.181
PAD No.82190
: 30 m x 84 m
Alignment marks A and B : See below
[Mark A]
[Mark B]
Coordinate position
Coordinate position
30μm
47μm
30μm
55μm
30μm
30μm
30μm
30μm
Aluminum (top metal) Passivation
Alignment mark
Mark A
Mark B
X-coordinate (m)
2289
-2289
47μm
55μm
Aluminum (top metal) Passivation
Y-coordinate (m)
-308
309
26/31
FEDL9478C-01
ML9478C
Pad center coordinates
Pad
number
1
Pad name
DUMMY
X-coordinate Y-coordinate
(m)
(m)
-2206
-308
Pad
number
41
VLCD
X-coordinate
(m)
27
Y-coordinate
(m)
-308
VLCD
81
-308
Pad name
2
DUMMY
-2149
-308
42
3
GNDO
-2092
-308
43
VLCD
135
-308
4
Duty1
-2035
-308
44
RESETB
192
-308
5
Duty1
-1978
-308
45
RESETB
244
-308
6
Duty0
-1921
-308
46
OSC1
298
-308
7
Duty0
-1869
-308
47
OSC1
350
-308
8
A0
-1815
-308
48
OSC1
404
-308
9
A0
-1763
-308
49
OSC2
458
-308
10
A1
-1709
-308
50
OSC2
510
-308
11
A1
-1657
-308
51
OSC2
564
-308
12
SA0
-1603
-308
52
OSC2
618
-308
13
SA0
-1549
-308
53
OSCR
672
-308
14
SA1
-1492
-308
54
OSCR
724
-308
15
SA1
-1436
-308
55
OSCR
776
-308
16
VDDO
-1379
-308
56
CKO
830
-308
17
SDAACK
-1322
-308
57
CKO
882
-308
18
SDAACK
-1265
-308
58
CKO
934
-308
19
SDAACK
-1208
-308
59
CKO
986
-308
20
DATA(SDA)
-1151
-308
60
SYNCB
1040
-308
21
DATA(SDA)
-1094
-308
61
SYNCB
1092
-308
22
CLOCK(SCL)
-1037
-308
62
SYNCB
1144
-308
23
CLOCK(SCL)
-980
-308
63
SYNCB
1196
-308
24
LOAD
-923
-308
64
VDDO
1250
-308
25
LOAD
-866
-308
65
I2C
1304
-308
26
GND
-809
-308
66
I2C
1356
-308
27
GND
-752
-308
67
M/S
1413
-308
28
GND
-695
-308
68
M/S
1465
-308
29
GND
-638
-308
69
POCEB
1522
-308
30
GND
-581
-308
70
POCEB
1574
-308
31
GND
-524
-308
71
OSCI/E
1628
-308
32
VDD
-467
-308
72
OSCI/E
1680
-308
33
VDD
-412
-308
73
BIAS
1737
-308
34
VDD
-357
-308
74
BIAS
1789
-308
35
VDD
-302
-308
75
TEST2
1846
-308
36
VDD
-247
-308
76
TEST2
1900
-308
37
VDD
-192
-308
77
TEST1
1957
-308
38
VLCD
-135
-308
78
TEST1
2014
-308
39
VLCD
-81
-308
79
GNDO
2071
-308
40
VLCD
-27
-308
80
DUMMY
2128
-308
27/31
FEDL9478C-01
ML9478C
125
SEG31
X-coordinate
(m)
585
82
83
DUMMY
DUMMY
2289
2289
-232
-182
126
127
SEG32
SEG33
535
485
309
309
84
85
DUMMY
COM1
2289
2289
-132
-82
128
129
SEG34
SEG35
435
385
309
309
86
87
COM2
COM3
2289
2289
-32
18
130
131
SEG36
SEG37
335
285
309
309
88
89
COM4
DUMMY
2289
2289
68
118
132
133
SEG38
SEG39
235
185
309
309
90
91
DUMMY
DUMMY
2289
2289
168
218
134
135
SEG40
COM1
135
85
309
309
92
93
DUMMY
DUMMY
2289
2185
268
309
136
137
COM2
COM3
35
-15
309
309
94
95
DUMMY
SEG1
2135
2085
309
309
138
139
COM4
SEG41
-65
-115
309
309
96
97
SEG2
SEG3
2035
1985
309
309
140
141
SEG42
SEG43
-165
-215
309
309
98
99
SEG4
SEG5
1935
1885
309
309
142
143
SEG44
SEG45
-265
-315
309
309
100
101
SEG6
SEG7
1835
1785
309
309
144
145
SEG46
SEG47
-365
-415
309
309
102
103
SEG8
SEG9
1735
1685
309
309
146
147
SEG48
SEG49
-465
-515
309
309
104
105
SEG10
SEG11
1635
1585
309
309
148
149
SEG50
SEG51
-565
-615
309
309
106
107
SEG12
SEG13
1535
1485
309
309
150
151
SEG52
SEG53
-665
-715
309
309
108
109
SEG14
SEG15
1435
1385
309
309
152
153
SEG54
SEG55
-765
-815
309
309
110
111
SEG16
SEG17
1335
1285
309
309
154
155
SEG56
SEG57
-865
-915
309
309
112
113
SEG18
SEG19
1235
1185
309
309
156
157
SEG58
SEG59
-965
-1015
309
309
114
115
SEG20
SEG21
1135
1085
309
309
158
159
SEG60
SEG61
-1065
-1115
309
309
116
117
SEG22
SEG23
1035
985
309
309
160
161
SEG62
SEG63
-1165
-1215
309
309
118
119
SEG24
SEG25
935
885
309
309
162
163
SEG64
SEG65
-1265
-1315
309
309
120
121
SEG26
SEG27
835
785
309
309
164
165
SEG66
SEG67
-1365
-1415
309
309
122
123
SEG28
SEG29
735
685
309
309
166
167
SEG68
SEG69
-1465
-1515
309
309
124
SEG30
635
309
168
SEG70
-1565
309
Pad
number
81
Pad name
DUMMY
X-coordinate Y-coordinate
(m)
(m)
2185
-308
Pad number Pad name
Y-coordinate
(m)
309
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FEDL9478C-01
ML9478C
Pad
number
169
170
Pad name
SEG71
SEG72
X-coordinate Y-coordinate
(m)
(m)
-1615
309
-1665
309
171
172
SEG73
SEG74
-1715
-1765
309
309
173
174
SEG75
SEG76
-1815
-1865
309
309
175
176
SEG77
SEG78
-1915
-1965
309
309
177
178
SEG79
SEG80
-2015
-2065
309
309
179
180
DUMMY
DUMMY
-2115
-2165
309
309
181
182
DUMMY
DUMMY
-2289
-2289
203
153
183
184
COM4
COM3
-2289
-2289
103
53
185
186
COM2
COM1
-2289
-2289
3
-47
187
188
DUMMY
DUMMY
-2289
-2289
-97
-147
189
190
DUMMY
DUMMY
-2289
-2289
-197
-247
Pad
number
Pad name
X-coordinate Y-coordinate
(m)
(m)
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FEDL9478C-01
ML9478C
REVISION HISTORY
Page
Document No.
Issue Date
Previous
Edition
New
Edition
FEDL9478C-01
Apr .25,2012
–
–
Description
Final edition 1 issued
30/31
FEDL9478C-01
ML9478C
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