ON NCP51200MNTXG Termination regulator Datasheet

NCP51200, NCV51200
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51200 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51200 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51200 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51200 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51200 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
http://onsemi.com
DFN10, 3x3, 0.5P
CASE 485C
MARKING DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
For Automotive Applications
Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
PVCC Voltage Range: 1.1 to 3.5 V
Integrated Power MOSFETs
Fast Load−Transient Response
PGOOD − Logic output pin to Monitor VTT Regulation
EN − Logic input pin for Shutdown mode
VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
Remote Sensing (VTTS)
Built−in Soft Start, Under Voltage Lockout and Over Current Limit
Thermal Shutdown
Small, Low−Profile 10−pin, 3x3 DFN Package
NCV51200MWTXG − Wettable Flank Option for Enhanced Optical
Inspection
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
These Devices are Pb−Free and are RoHS Compliant
DDR Memory Termination
Desktop PC’s, Notebooks, and Workstations
Servers and Networking equipment
Telecom/Datacom, GSM Base Station
Graphics Processor Core Supplies
Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
Chipset/RAM Supplies as Low as 0.5 V
Active Bus Termination
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 5
51200 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
1
PVCC
2
VTT
3
PGND
VTTS
+
10
VCC
9
PGOOD
8
GND
4
7
EN
5
6
VRO
GND
Exposed Pad
ORDERING INFORMATION
Applications
•
•
•
•
•
•
•
•
51200
ALYWG
G
Package
Shipping†
NCP51200MNTXG
DFN10
(Pb−Free)
3000 / Tape &
Reel
NCV51200MNTXG*
DFN10
(Pb−Free)
3000 / Tape &
Reel
NCV51200MWTXG*
DFN10
(Pb−Free)
3000 / Tape &
Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCP51200/D
NCP51200, NCV51200
PIN FUNCTION DESCRIPTION
Pin Number
Pin Name
1
VRI
Pin Function
2
PVCC
3
VTT
4
PGND
Power Ground. Internally connected to the output sink MOSFET.
5
VTTS
VTT Sense Input. The VTTS pin provides accurate remote feedback sensing of VTT. Connect VTTS to the
remote DDR termination bypass capacitors.
6
VRO
Independent Buffered VTT Reference Output. Sources and sinks over 5 mA. Connect to GND thru
0.1 mF ceramic capacitor.
7
EN
Shutdown Control Input. CMOS compatible input. Logic high = enable, logic low = shutdown. Connect
to VDDQ for normal operation.
8
GND
9
PGOOD
10
VCC
VTT External Reference Input ( set to VDDQ / 2 thru resistor network ).
Power input. Internally connected to the output source MOSFET.
Power Output of the Linear Regulator.
Common Ground.
Power Good (Open Drain output).
Analog power supply input. Connect to GND thru a 1 − 4.7 mF ceramic capacitor.
THERMAL
PAD
Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple
vias for maximum power dissipation performance.
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
−0.3 to 6.0
V
EN, PGOOD (Note 1)
−0.3 to 6.0
V
PGND to GND (Note 1)
−0.3 to +0.3
V
TSTG
−55 to 150
°C
TJ
150
°C
ESDHBM
2000
V
VCC, PVCC, VTT, VTTS, VRI, VRO (Note 1)
Storage Temperature
Operating Junction Temperature Range
ESD Capability, Human Body Model (Note 2)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following method:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78.
DISSIPATION RATINGS
Package
TA = 255C Power Rating
Derating Factor above
TA = 255C
TA = +855C Power Rating
10−Pin DFN
1.92 W
19 mW/°C
0.79 W
RECOMMENED OPERATING CONDITIONS
Rating
Symbol
Value
Unit
Supply Voltage
VCC
2.375 to 5.5
V
Voltage Range
VRO
−0.1 to 1.8
V
VRI
0.5 to 1.8
PVCC, VTT, VTTS, EN, PGOOD
−0.1 to 3.5
PGND
−0.1 to +0.1
TA
−40 to +125
Operating Free−Air Temperature
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
http://onsemi.com
2
NCP51200, NCV51200
ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.
Parameter
Conditions
Symbol
Min
Typ
Max
Units
0.7
1
mA
mA
Supply Current
VCC Supply Current
TA = +25°C, EN = 3.3 V, No Load
VCC Shutdown Current
TA = +25°C, EN = 0 V, VRI = 0 V, No Load
IVCC
IVCC SHD
TA = +25°C, EN = 0 V, VRI > 0.4 V, No Load
VCC UVLO Threshold
Wake−up, TA = +25°C
VUVLO
2.2
Hysteresis
65
80
200
400
2.3
2.375
50
V
mV
IPVCC
1
50
mA
TA = +25°C, EN = 0 V, No Load
IPVCC SHD
0.1
50
mA
VRO = 1.25 V (DDR1), ITT = 0 A
VOS
mV
PVCC Supply Current
TA = +25°C, EN = 3.3 V, No Load
PVCC Shutdown Current
VTT Output
VTT Output Offset Voltage
−15
+15
VRO = 0.9 V (DDR2), ITT = 0 A
−15
+15
PVCC = 1.5 V, VRO = 0.75 V (DDR3),
ITT = 0 A
−15
+15
VTT Voltage Tolerance to VRO
−2 A ≤ ITT ≤ +2 A
−25
+25
mV
Source Current Limit
VTTS = 90% * VRO
3
4.5
A
Sink Current Limit
VTTS = 110% * VRO
3.5
5.5
A
Soft−start Current Limit
Timeout
Discharge MOSFET
On−resistance
VRI = 0 V, VTT = 0.3 V, EN = 0 V, TA = +25°C
TSS
200
RDIS
18
ms
25
W
1.8
V
+1
mA
435
mV
VRI − Input Reference
VRI Voltage Range
VRI
VRI Input−bias Current
EN = 3.3 V
VRI UVLO Voltage
VRI rising
VRI UVLO
Hysteresis
VRI HYS
0.5
IRI
360
390
60
VRO − Output Reference
VRO Voltage
VRI
V
VRO Voltage Tolerance to VRI
IRO = ±10 mA, 0.6 V ≤ VRI ≤ 1.25 V
−15
VRO Source Current Limit
VRO = 0 V
10
40
mA
VRO Sink Current Limit
VRO = 0 V
10
40
mA
+15
mV
PGOOD − Powergood Comparator
PGOOD Lower Threshold
(with respect to VRO)
−23.5%
−20%
−17.5
%
PGOOD Upper Threshold
(with respect to VRO)
17.5%
20%
23.5%
PGOOD Hysteresis
V/V
5%
PGOOD Start−up Delay
Start−up rising edge, VTTS within 15% of
VRO
PGOOD Leakage Current
VTTS = VRI (PGOOD = True)
PGOOD = VCC + 0.2 V
PGOOD = False Delay
VTTS is beyond ±20% PGOOD trip thresholds
PGOOD Output Low Voltage
IGOOD = 4 mA
2
ms
1
ms
10
0.4
http://onsemi.com
3
mA
V
NCP51200, NCV51200
ELECTRICAL CHARACTERISTICS
−40°C ≤ TA ≤ 125°C; VCC = 3.3 V; PVCC = 1.8 V; VRI = VTTS = 0.9 V; EN = VCC; COUT = 3 x 10 mF (Ceramic); unless otherwise noted.
Parameter
Conditions
Symbol
Min
EN Logic high
VIH
1.7
EN Logic low
VIL
Typ
Max
Units
EN − Enable Logic
Logic Input Threshold
Hysteresis Voltage
EN pin
Logic Leakage Current
EN pin, TA = +25°C
0.3
VENHYS
IILEAK
V
0.5
−1
V
+1
mA
Thermal Shutdown
Thermal Shutdown
Temperature
TSD
150
°C
Thermal Shutdown Hysteresis
TSH
25
°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Figure 1. Typical DDR−3 Application Schematic
http://onsemi.com
4
NCP51200, NCV51200
Figure 2. Block Diagram
http://onsemi.com
5
NCP51200, NCV51200
General
PGOOD − PowerGood
The NCP51200 is a sink/source tracking termination
regulator specifically designed for low input voltage and
low external component count systems where space is a key
application parameter. The NCP51200 integrates a
high−performance, low−dropout (LDO) linear regulator
that is capable of both sourcing and sinking current. The
LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load
transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing
terminal, VTTS, should be connected to the positive terminal
of the output capacitors as a separate trace from the high
current path from VTT.
The NCP51200 provides an open−drain PGOOD output
that goes high when the VTT output is within ±20% of VRO.
PGOOD de−asserts within 10 ms after the output exceeds the
limits of the PowerGood window. During initial VTT
startup, PGOOD asserts high 2 ms after the VTT enters power
good window. Because PGOOD is an open−drain output, a
100 kW, pull−up resistor between PGOOD and a stable active
supply voltage rail is required.
The LDO has a constant over−current limit (OCL). Note
that the OCL level reduces by one−half when the output
voltage is not within the power good window. This reduction
is non−latch protection. For VCC under−voltage lockout
(UVLO) protection, the NCP51200 monitors VCC voltage.
When the VCC voltage is lower than the UVLO threshold
voltage, both the VTT and VRO regulators are powered off.
This shutdown is also non−latch protection.
VRI − Generation of Internal Voltage Reference
The output voltage, VTT, is regulated to VRO. When VRI
is configured for standard DDR termination applications,
VRI can be set by an external equivalent ratio voltage divider
connected to the memory supply bus (VDDQ). The
NCP51200 supports VRI voltage from 0.5 V to 1.8 V,
making it versatile and ideal for many types of low−power
LDO applications.
Thermal Shutdown with Hysteresis
If the NCP51200 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51200 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 150°C, the part will shutdown.
When the junction temperature falls back to 125°C, the
device resumes normal operation. If the junction
temperature exceeds the thermal shutdown threshold then
the VTT and VRO regulators are both shut off, discharged by
the internal discharge MOSFETs. The shutdown is a
non−latch protection.
VRO − Reference Output
When it is configured for DDR termination applications,
VRO generates the DDR VTT reference voltage for the
memory application. It is capable of supporting both a
sourcing and sinking load of 10 mA. VRO becomes active
when VRI voltage rises to 435 mV and VCC is above the
UVLO threshold. When VRO is less than 360 mV, it is
disabled and subsequently discharges to GND through an
internal 10 kW MOSFET. VRO is independent of the EN pin
state.
Tracking Startup and Shutdown
The NCP51200 also supports tracking startup and
shutdown when EN is tied directly to the system bus and not
used to turn on or turn off the device. During tracking
startup, VTT follows VRO once VRI voltage is greater than
435 mV. VRI follows the rise of VDDQ memory supply rail
via a voltage divider. The typical soft−start time for the
VDDQ memory supply rail is approximately 3 ms, however
it may vary depending on the system configuration. The SS
time of the VTT output no longer depends on the OCL
setting, but it is a function of the SS time of the VDDQ
memory supply rail. PGOOD is asserted 2 ms after VTT is
within ±20% of VRO. During tracking shutdown, VTT falls
following VRO until VRO reaches 360 mV. Once VRO falls
below 360 mV, the internal discharge MOSFETs are turned
on and quickly discharge both VRO and VTT to GND.
PGOOD is de−asserted once VTT is beyond the ±20% range
of VRO.
Soft Start
The soft−start function of the VTT pin is achieved via a
current clamp. The current clamp allows the output
capacitors to be charged with low and constant current,
providing a linear ramp−up of the output voltage. When
VTT is outside of the power good window, the current
clamp level is one−half of the full over−current limit (OCL)
level. When VTT rises or falls within the PGOOD window, the
current clamp level switches to the full OCL level.
The soft−start function is completely symmetrical; it
works not only from GND to the VRO voltage but also from
PVCC to the VRO voltage.
EN − Enable Control
When EN is driven high, the NCP51200 VTT regulator
begins normal operation. When EN is driven low, VTT is
discharges to GND through an internal 18−W MOSFET.
VREF remains on when EN is driven low.
http://onsemi.com
6
NCP51200, NCV51200
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE C
D
EDGE OF PACKAGE
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
7. FOR DEVICE OPN CONTAINING W OPTION,
DETAIL B ALTERNATE CONSTRUCTION IS
NOT APPLICABLE.
L1
PIN 1
REFERENCE
0.15 C
2X
ÇÇÇ
ÇÇÇ
ÇÇÇ
E
DETAIL A
Bottom View
(Optional)
MOLD CMPD
0.15 C
2X
(A3)
DETAIL B
0.10 C
A1
A
10X
SIDE VIEW
A1
D2
A3
DETAIL B
Side View
(Optional)
SEATING
PLANE
0.08 C
10X
ÉÉÉ
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
C
SOLDERING FOOTPRINT*
DETAIL A
e
L
1
5
2.6016
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.70
1.90
0.50 BSC
0.19 TYP
0.35
0.45
0.00
0.03
E2
10X
K
1.8508
2.1746
10
10X
b
0.10 C A B
0.05 C
3.3048
6
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP51200/D
Similar pages