TI1 DLP6500FYE Dmd Datasheet

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DLP6500FYE
DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
DLP6500FYE 0.65 1080p MVSP S600 DMD
1 Features
3 Description
•
Featuring over 2 million micromirrors, the high
resolution 0.65 1080p digital micromirror device
(DMD) is a spatial light modulator (SLM) that
modulates the amplitude, direction, and/or phase of
incoming light. The unique capability offered by the
DLP6500FYE makes it well suited to support a wide
variety of industrial, medical, and advanced imaging
applications. Reliable function and operation of the
DLP6500FYE requires that it be used in conjunction
with the DLPC900 digital controller. This dedicated
chipset provides full HD resolution at high speeds
and can be easily integrated into a variety of end
equipment solutions.
1
•
•
•
•
•
High resolution 1080p (1920x1080) Array with > 2
Million Micromirrors
– 0.65-Inch Micromirror Array Diagonal
– 7.56 um Micromirror Pitch
– ± 12° Micromirror Tilt Angle (Relative to Flat
State)
– 2.5 μs Micromirror Crossover Time
– Designed for Corner Illumination
Designed for Use With Broadband Visible Light
(420 nm – 700 nm)
– Window Transmission 97% (Single Pass,
Through Two Window Surfaces)
– Micromirror Reflectivity 88%
– Array Diffraction Efficiency 86%
– Array Fill Factor 92%
Two 16-Bit, Low Voltage Differential Signaling
(LVDS), Double Data Rate (DDR) input-data
buses
Dedicated DLPC900 Controller for high-speed
pattern rates of 9500 Hz (1-Bit Binary) & 250 Hz
(8-Bit Gray)
Up to 400 MHz Input Data Clock Rate
Integrated Micromirror Driver Circuitry
Device Information(1)
PART NUMBER
DLP6500
PACKAGE
FYE (350)
BODY SIZE (NOM)
35.0 × 32.2 × 5.1 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Diagram
Red,Green,Blue PWM
PCLK, DE
LED Strobes
HSYNC, VSYNC
LED
Driver
24-bit RGB Data
Flash
DLPC900
USB
FAN
I2C
2 Applications
•
•
•
Industrial
– 3D scanners for Machine Vision and Quality
Control
– 3D Printing
– Direct Imaging Lithography
– Laser Marking and repair
Medical
– Ophthalmology
– 3D Scanners for Limb and Skin Measurement
– Hyperspectral Imaging
– Hyper-spectral Scanning
Displays
– 3D Imaging Microscopes
– Intelligent and Adaptive Lighting
DMD CTL, DATA
SCP
OSC
DLP6500FYE
Voltage
Supplies
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP6500FYE
DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
Absolute Maximum Ratings .................................... 10
Storage Conditions.................................................. 10
ESD Ratings............................................................ 10
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 13
Electrical Characteristics......................................... 14
Timing Requirements .............................................. 15
Typical Characteristics ............................................ 19
System Mounting Interface Loads .......................... 20
Micromirror Array Physical Characteristics .......... 21
Micromirror Array Optical Characteristics ............ 22
Window Characteristics......................................... 23
Chipset Component Usage Specification ............. 23
Detailed Description ............................................ 24
7.1 Overview ................................................................. 24
7.2 Functional Block Diagram ....................................... 25
7.3 Feature Description................................................. 26
7.4
7.5
7.6
7.7
8
Device Functional Modes........................................
Window Characteristics and Optics .......................
Micromirror Array Temperature Calculation............
Micromirror Landed-on/Landed-Off Duty Cycle ......
29
29
30
31
Application and Implementation ........................ 34
8.1 Application Information............................................ 34
8.2 Typical Application ................................................. 34
9
Power Supply Recommendations...................... 35
9.1 DMD Power Supply Requirements ........................ 35
9.2 DMD Power Supply Power-Up Procedure ............. 35
9.3 DMD Power Supply Power-Down Procedure ........ 35
10 Layout................................................................... 38
10.1 Layout Guidelines ................................................. 38
10.2 Layout Example .................................................... 38
11 Device Documentation Support......................... 43
11.1
11.2
11.3
11.4
11.5
11.6
Device Support ....................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
44
44
44
44
44
12 Mechanical, Packaging, and Orderable
Information ........................................................... 44
4 Revision History
Changes from Original (October 2014) to Revision A
Page
•
Changed the Device Information table package dimensions from: 40.6 x 31.8 x 6 mm to: 35.0 × 32.2 × 5.1 mm ............... 1
•
Changed Note (4) of the Pin Functions table From: "Dielectric Constant for the DMD" Type A To: "Dielectric
Constant for the DMD S600" ................................................................................................................................................. 4
•
Removed pin number Z27 in the Pin Functions (continued) table ......................................................................................... 8
•
Deleted pin number AA25 from VOFFSET in the Pin Functions (continued) table ............................................................... 8
•
Changed ƒclock in Absolute Maximum Ratings From: "DCLK_A and DCLK_B rows To: one row "DCLK (all channels)" ... 10
•
Changed Note (9) of the Absolute Maximum Ratings table. ................................................................................................ 10
•
Added the Storage Conditions table .................................................................................................................................... 10
•
Added the ESD Ratings table .............................................................................................................................................. 10
•
Changed the test conditions in row 1 of the Window Characteristics table From: "Corning 7056" To: "Corning Eagle
XG" ....................................................................................................................................................................................... 23
•
Changed the test conditions in row 2 of the Window Characteristics table From: "at wavelength 589 nm" To: "at
wavelength 546.1 nm" and the NOM value From: 1.487 To 1.5119 .................................................................................... 23
2
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DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
5 Pin Configuration and Functions
Package Connector Terminals
(Bottom View) for FYE (350)
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DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
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Table 1. Pin Functions
PIN
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
D_AN(0)
B14
Input
LVDS
DDR
Differential
Data, Negative
494.88
D_AN(1)
B15
Input
LVDS
DDR
Differential
Data, Negative
486.18
D_AN(2)
C16
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(3)
K24
Input
LVDS
DDR
Differential
Data, Negative
485.67
D_AN(4)
B18
Input
LVDS
DDR
Differential
Data, Negative
494.76
D_AN(5)
L24
Input
LVDS
DDR
Differential
Data, Negative
490.63
D_AN(6)
C19
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(7)
H24
Input
LVDS
DDR
Differential
Data, Negative
485.55
D_AN(8)
H23
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(9)
B25
Input
LVDS
DDR
Differential
Data, Negative
485.59
D_AN(10)
D24
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(11)
E25
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(12)
F25
Input
LVDS
DDR
Differential
Data, Negative
490.04
D_AN(13)
H25
Input
LVDS
DDR
Differential
Data, Negative
485.91
D_AN(14)
L25
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AN(15)
G24
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_AP(0)
C14
Input
LVDS
DDR
Differential
Data, Positive
494.84
D_AP(1)
B16
Input
LVDS
DDR
Differential
Data, Positive
486.22
D_AP(2)
C17
Input
LVDS
DDR
Differential
Data, Positive
494.65
D_AP(3)
K23
Input
LVDS
DDR
Differential
Data, Positive
488.42
D_AP(4)
B19
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_AP(5)
L23
Input
LVDS
DDR
Differential
Data, Positive
490.67
D_AP(6)
C20
Input
LVDS
DDR
Differential
Data, Positive
498.11
D_AP(7)
J24
Input
LVDS
DDR
Differential
Data, Positive
486.22
D_AP(8)
J23
Input
LVDS
DDR
Differential
Data, Positive
495.47
D_AP(9)
C25
Input
LVDS
DDR
Differential
Data, Positive
485.94
D_AP(10)
E24
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_AP(11)
D25
Input
LVDS
DDR
Differential
Data, Positive
494.13
D_AP(12)
G25
Input
LVDS
DDR
Differential
Data, Positive
488.98
D_AP(13)
J25
Input
LVDS
DDR
Differential
Data, Positive
492.56
D_AP(14)
K25
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_AP(15)
F24
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_BN(0)
Z14
Input
LVDS
DDR
Differential
Data, Negative
494.92
D_BN(1)
Z15
Input
LVDS
DDR
Differential
Data, Negative
486.18
D_BN(2)
Y16
Input
LVDS
DDR
Differential
Data, Negative
496.46
D_BN(3)
P24
Input
LVDS
DDR
Differential
Data, Negative
493.74
D_BN(4)
Z18
Input
LVDS
DDR
Differential
Data, Negative
494.76
D_BN(5)
N24
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_BN(6)
Y19
Input
LVDS
DDR
Differential
Data, Negative
492.16
D_BN(7)
T24
Input
LVDS
DDR
Differential
Data, Negative
492.68
NAME
DESCRIPTION
TRACE
(mils) (4)
DATA BUS A
DATA BUS B
(1)
(2)
(3)
(4)
4
The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
DDR = Double Data Rate.
SDR = Single Data Rate.
Refer to the Timing Requirements for specifications and relationships.
Internal term = CMOS level internal termination. Refer to Recommended Operating Conditions for differential termination specification.
Dielectric Constant for the DMD S600 ceramic package is approximately 9.6.
For the package trace lengths shown:
Propagation Speed = 11.8 / sqrt(9.6) = 3.808 in/ns.
Propagation Delay = 0.262 ns/in = 262 ps/in = 10.315 ps/mm.
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DLPS053A – OCTOBER 2014 – REVISED FEBRUARY 2016
Table 1. Pin Functions (continued)
PIN
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
D_BN(8)
T23
Input
LVDS
DDR
Differential
Data, Negative
484.45
D_BN(9)
Z25
Input
LVDS
DDR
Differential
Data, Negative
492.09
D_BN(10)
X24
Input
LVDS
DDR
Differential
Data, Negative
497.72
D_BN(11)
W25
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_BN(12)
V25
Input
LVDS
DDR
Differential
Data, Negative
484.17
D_BN(13)
T25
Input
LVDS
DDR
Differential
Data, Negative
481.42
D_BN(14)
N25
Input
LVDS
DDR
Differential
Data, Negative
495.16
D_BN(15)
U24
Input
LVDS
DDR
Differential
Data, Negative
489.8
D_BP(0)
Y14
Input
LVDS
DDR
Differential
Data, Positive
494.88
D_BP(1)
Z16
Input
LVDS
DDR
Differential
Data, Positive
486.26
D_BP(2)
Y17
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_BP(3)
P23
Input
LVDS
DDR
Differential
Data, Positive
492.48
D_BP(4)
Z19
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_BP(5)
N23
Input
LVDS
DDR
Differential
Data, Positive
497.99
D_BP(6)
Y20
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_BP(7)
R24
Input
LVDS
DDR
Differential
Data, Positive
492.05
D_BP(8)
R23
Input
LVDS
DDR
Differential
Data, Positive
484.45
D_BP(9)
Y25
Input
LVDS
DDR
Differential
Data, Positive
492.24
D_BP(10)
W24
Input
LVDS
DDR
Differential
Data, Positive
495.16
D_BP(11)
X25
Input
LVDS
DDR
Differential
Data, Positive
494.72
D_BP(12)
U25
Input
LVDS
DDR
Differential
Data, Positive
483.78
D_BP(13)
R25
Input
LVDS
DDR
Differential
Data, Positive
489.13
D_BP(14)
P25
Input
LVDS
DDR
Differential
Data, Positive
499.53
D_BP(15)
V24
Input
LVDS
DDR
Differential
Data, Positive
488.66
SCTRL_AN
C23
Input
LVDS
DDR
Differential
Serial Control, Negative
492.95
SCTRL_BN
Y23
Input
LVDS
DDR
Differential
Serial Control, Negative
493.78
SCTRL_AP
C24
Input
LVDS
DDR
Differential
Serial Control, Positive
493.78
SCTRL_BP
Y24
Input
LVDS
DDR
Differential
Serial Control, Positive
493.11
DCLK_AN
B23
Input
LVDS
Differential
Clock, Negative
480.35
DCLK_BN
Z23
Input
LVDS
Differential
Clock, Negative
486.22
DCLK_AP
B22
Input
LVDS
Differential
Clock, Positive
485.83
DCLK_BP
Z22
Input
LVDS
Differential
Clock, Positive
491.93
NAME
DESCRIPTION
TRACE
(mils) (4)
SERIAL CONTROL
CLOCKS
SERIAL COMMUNICATIONS PORT (SCP)
SCP_DO
B8
Output
LVCMOS
SDR
SCP_DI
B7
Input
LVCMOS
SDR
SCP_CLK
B6
Input
SCP_ENZ
C8
Input
Serial Communications Port Output
Pull-Down
Serial Communications Port Data
Input
LVCMOS
Pull-Down
Serial Communications Port Clock
LVCMOS
Pull-Down
Active-low Serial Communications
Port Enable
MICROMIRROR RESET CONTROL
RESET_ADDR(0)
X9
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(1)
X8
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(2)
Z8
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_ADDR(3)
Z7
Input
LVCMOS
Pull-Down
Reset Driver Address Select
RESET_MODE(0)
W11
Input
LVCMOS
Pull-Down
Reset Driver Mode Select
RESET_MODE(1)
Z10
Input
LVCMOS
Pull-Down
Reset Driver Mode Select
RESET_SEL(0)
Y10
Input
LVCMOS
Pull-Down
Reset Driver Level Select
RESET_SEL(1)
Y9
Input
LVCMOS
Pull-Down
Reset Driver Level Select
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Table 1. Pin Functions (continued)
PIN
NAME
RESET_STROBE
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
Y7
Input
LVCMOS
Pull-Down
Reset Address, Mode, & Level
latched on rising-edge
DESCRIPTION
TRACE
(mils) (4)
ENABLES and INTERRUPTS
PWRDNZ
D2
Input
LVCMOS
Pull-Down
Active-low Device Reset
RESET_OEZ
W7
Input
LVCMOS
Pull-Down
Active-low output enable for DMD
reset driver circuits
RESETZ
Z6
Input
LVCMOS
Pull-Down
Active-low sets Reset circuits in
known VOFFSET state
RESET_IRQZ
Z5
Output
LVCMOS
Active-low, output interrupt to ASIC
VOLTAGE REGULATOR MONITORING
PG_BIAS
E11
Input
LVCMOS
Pull-Up
Active-low fault from external VBIAS
regulator
PG_OFFSET
B10
Input
LVCMOS
Pull-Up
Active-low fault from external
VOFFSET regulator
PG_RESET
D11
Input
LVCMOS
Pull-Up
Active-low fault from external
VRESET regulator
EN_BIAS
D9
Output
LVCMOS
Active-high enable for external
VBIAS regulator
EN_OFFSET
C9
Output
LVCMOS
Active-high enable for external
VOFFSET regulator
EN_RESET
E9
Output
LVCMOS
Active-high enable for external
VRESET regulator
LEAVE PIN UNCONNECTED
MBRST(0)
C2
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(1)
C3
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(2)
C5
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(3)
C4
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(4)
E5
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(5)
E4
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(6)
E3
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(7)
G4
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(8)
G3
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(9)
G2
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(10)
J4
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(11)
J3
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(12)
J2
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(13)
L4
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(14)
L3
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
MBRST(15)
L2
Output
Analog
Pull-Down
For proper DMD operation, do not
connect
6
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Table 1. Pin Functions (continued)
PIN
NAME
(1)
NO.
TYPE
(I/O/P)
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
DESCRIPTION
TRACE
(mils) (4)
LEAVE PIN UNCONNECTED
RESERVED_PFE
E7
Input
LVCMOS
Pull-Down
For proper DMD operation, do not
connect
RESERVED_TM
D13
Input
LVCMOS
Pull-Down
For proper DMD operation, do not
connect
RESERVED_XI1
E13
Input
LVCMOS
Pull-Down
For proper DMD operation, do not
connect
RESERVED_TP0
W12
Input
Analog
For proper DMD operation, do not
connect
RESERVED_TP1
Y11
Input
Analog
For proper DMD operation, do not
connect
RESERVED_TP2
X11
Input
Analog
For proper DMD operation, do not
connect
LEAVE PIN UNCONNECTED
RESERVED_BA
Y12
Output
LVCMOS
For proper DMD operation, do not
connect
RESERVED_BB
C12
Output
LVCMOS
For proper DMD operation, do not
connect
RESERVED_TS
D5
Output
LVCMOS
For proper DMD operation, do not
connect
LEAVE PIN UNCONNECTED
NO CONNECT
B11
For proper DMD operation, do not
connect
NO CONNECT
C11
For proper DMD operation, do not
connect
NO CONNECT
C13
For proper DMD operation, do not
connect
NO CONNECT
E12
For proper DMD operation, do not
connect
NO CONNECT
E14
For proper DMD operation, do not
connect
NO CONNECT
E23
For proper DMD operation, do not
connect
NO CONNECT
H4
For proper DMD operation, do not
connect
NO CONNECT
N2
For proper DMD operation, do not
connect
NO CONNECT
N3
For proper DMD operation, do not
connect
NO CONNECT
N4
For proper DMD operation, do not
connect
NO CONNECT
R2
For proper DMD operation, do not
connect
NO CONNECT
R3
For proper DMD operation, do not
connect
NO CONNECT
R4
For proper DMD operation, do not
connect
NO CONNECT
T4
For proper DMD operation, do not
connect
NO CONNECT
U2
For proper DMD operation, do not
connect
NO CONNECT
U3
For proper DMD operation, do not
connect
NO CONNECT
U4
For proper DMD operation, do not
connect
NO CONNECT
W3
For proper DMD operation, do not
connect
NO CONNECT
W4
For proper DMD operation, do not
connect
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Table 1. Pin Functions (continued)
PIN
(1)
NAME
TYPE
(I/O/P)
NO.
SIGNAL
DATA
RATE (2)
INTERNAL
TERM (3)
DESCRIPTION
NO CONNECT
W5
For proper DMD operation, do not
connect
NO CONNECT
W13
For proper DMD operation, do not
connect
NO CONNECT
W14
For proper DMD operation, do not
connect
NO CONNECT
W23
For proper DMD operation, do not
connect
NO CONNECT
X4
For proper DMD operation, do not
connect
NO CONNECT
X5
For proper DMD operation, do not
connect
NO CONNECT
X13
For proper DMD operation, do not
connect
NO CONNECT
Y2
For proper DMD operation, do not
connect
NO CONNECT
Y3
For proper DMD operation, do not
connect
NO CONNECT
Y4
For proper DMD operation, do not
connect
NO CONNECT
Y5
For proper DMD operation, do not
connect
NO CONNECT
Z11
For proper DMD operation, do not
connect
TRACE
(mils) (4)
Pin Functions (continued)
PIN
NAME (1)
NO.
NO.
NO.
TYPE
(I/O/P)
SIGNAL
DESCRIPTION
VBIAS
A6
A7
A8
Power
Analog
Supply voltage for positive Bias level of Micromirror reset signal.
VBIAS
AA6
AA7
AA8
Power
Analog
Supply voltage for positive Bias level of Micromirror reset signal.
VOFFSET
A3
A4
A25
Power
Analog
Supply voltage for HVCMOS logic.
VOFFSET
B26
L26
M26
Power
Analog
Supply voltage for stepped high voltage at Micromirror address electrodes.
VOFFSET
N26
Z26
Power
Analog
Supply voltage for positive Offset level of Micromirror reset signal.
VOFFSET
AA3
AA4
Power
Analog
VRESET
G1
H1
J1
Power
Analog
Supply voltage for negative Reset level of Micromirror reset signal.
VRESET
R1
T1
U1
Power
Analog
Supply voltage for negative Reset level of Micromirror reset signal.
VCC
A9
B3
B5
Power
Analog
VCC
B12
C1
C6
Power
Analog
VCC
C10
D4
D6
Power
Analog
VCC
D8
E1
E2
Power
Analog
Supply voltage for LVCMOS core logic.
VCC
E10
E15
E16
Power
Analog
Supply voltage for normal high level at Micromirror address electrodes.
VCC
E17
F3
H2
Power
Analog
VCC
K1
K3
M4
Power
Analog
Supply voltage for positive Offset level of Micromirror reset signal during
Power Down sequence.
VCC
P1
P3
T2
Power
Analog
VCC
V3
W1
W2
Power
Analog
VCC
W6
W9
W10
Power
Analog
VCC
W15
W16
W17
Power
Analog
VCC
X3
X6
Power
Analog
VCC
Y1
Y8
Y13
Power
Analog
VCC
Z1
Z3
Z12
Power
Analog
VCC
AA2
AA9
AA10
Power
Analog
(1)
8
The following power supplies are required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET. VSS must also be
connected.
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Pin Functions (continued) (continued)
PIN
NAME (1)
TYPE
(I/O/P)
SIGNAL
DESCRIPTION
NO.
NO.
NO.
VCCI
A16
A17
A18
Power
Analog
Supply voltage for LVDS receivers.
VCCI
A20
A21
A23
Power
Analog
Supply voltage for LVDS receivers.
VCCI
AA16
AA17
AA18
Power
Analog
Supply voltage for LVDS receivers.
VCCI
AA20
AA21
AA23
Power
Analog
Supply voltage for LVDS receivers.
VSS
A5
A10
A11
Power
Analog
Device Ground. Common return for all power.
VSS
A19
A22
A24
Power
Analog
Device Ground. Common return for all power.
VSS
B2
B4
B9
Power
Analog
Device Ground. Common return for all power.
VSS
B13
B17
B20
Power
Analog
Device Ground. Common return for all power.
VSS
B21
B24
C7
Power
Analog
Device Ground. Common return for all power.
VSS
C15
C18
C21
Power
Analog
Device Ground. Common return for all power.
VSS
C22
C26
D1
Power
Analog
Device Ground. Common return for all power.
VSS
D3
D7
D10
Power
Analog
Device Ground. Common return for all power.
VSS
D12
D14
D15
Power
Analog
Device Ground. Common return for all power.
VSS
D16
D17
D18
Power
Analog
Device Ground. Common return for all power.
VSS
D19
D20
D21
Power
Analog
Device Ground. Common return for all power.
VSS
D22
D23
D26
Power
Analog
Device Ground. Common return for all power.
VSS
E6
E8
E18
Power
Analog
Device Ground. Common return for all power.
VSS
E19
E20
E21
Power
Analog
Device Ground. Common return for all power.
VSS
E22
E26
F1
Power
Analog
Device Ground. Common return for all power.
VSS
F2
F4
F23
Power
Analog
Device Ground. Common return for all power.
VSS
F26
G23
G26
Power
Analog
Device Ground. Common return for all power.
VSS
H3
H26
J26
Power
Analog
Device Ground. Common return for all power.
VSS
K2
K4
K26
Power
Analog
Device Ground. Common return for all power.
VSS
L1
M1
M2
Power
Analog
Device Ground. Common return for all power.
VSS
M3
M23
M24
Power
Analog
Device Ground. Common return for all power.
VSS
M25
N1
P2
Power
Analog
Device Ground. Common return for all power.
VSS
P4
P26
R26
Power
Analog
Device Ground. Common return for all power.
VSS
T3
T26
U23
Power
Analog
Device Ground. Common return for all power.
VSS
U26
V1
V2
Power
Analog
Device Ground. Common return for all power.
VSS
V4
V23
V26
Power
Analog
Device Ground. Common return for all power.
VSS
W8
W18
W19
Power
Analog
Device Ground. Common return for all power.
VSS
W20
W21
W22
Power
Analog
Device Ground. Common return for all power.
VSS
W26
X1
X2
Power
Analog
Device Ground. Common return for all power.
VSS
X7
X10
X12
Power
Analog
Device Ground. Common return for all power.
VSS
X14
X15
X16
Power
Analog
Device Ground. Common return for all power.
VSS
X17
X18
X19
Power
Analog
Device Ground. Common return for all power.
VSS
X20
X21
X22
Power
Analog
Device Ground. Common return for all power.
VSS
X23
X26
Y6
Power
Analog
Device Ground. Common return for all power.
VSS
Y15
Y18
Y21
Power
Analog
Device Ground. Common return for all power.
VSS
Y22
Y26
Z2
Power
Analog
Device Ground. Common return for all power.
VSS
Z4
Z9
Z13
Power
Analog
Device Ground. Common return for all power.
VSS
Z17
Z20
Z21
Power
Analog
Device Ground. Common return for all power.
VSS
Z24
AA5
AA11
Power
Analog
Device Ground. Common return for all power.
VSS
AA19
AA22
AA24
Power
Analog
Device Ground. Common return for all power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic
(2)
(2)
MIN
MAX
UNIT
–0.5
4
V
–0.5
4
V
–0.5
9
V
VCCI
Supply voltage for LVDS receivers
VOFFSET
Supply voltage for HVCMOS and micromirror electrode
VBIAS
Supply voltage for micromirror electrode
(2)
–0.5
17
V
VRESET
Supply voltage for micromirror electrode
(2)
–11
0.5
V
| VCC – VCCI |
Supply voltage delta (absolute value)
(4)
0.3
V
| VBIAS – VOFFSET |
Supply voltage delta (absolute value)
(5)
8.75
V
–0.5
VCC + 0.15
V
–0.5
VCCI + 0.15
V
700
mV
7
mA
460
MHz
–20
90
ºC
–40
90
ºC
81
ºC
(2) (3)
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins
Input voltage for all other LVDS input pins
| VID |
Input differential voltage (absolute value)
IID
Input differential current
(2)
(2) (6)
(7)
(7)
CLOCKS
ƒclock
Clock frequency for LVDS interface, DCLK (all channels)
ENVIRONMENTAL
Case temperature: operational
TCASE
(8) (9)
Case temperature: non–operational
(9)
Dew Point (Operating and non-Operating)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure above Recommended Operating Conditions for extended periods may affect device reliability.
All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected
VOFFSET supply transients must fall within specified voltages.
To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Recommendations for additional information.
This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential. .
LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors
Exposure of the DMD simultaneously to any combination of the maximum operating conditions for case temperature, differential
temperature, or illumination power density will reduce the device lifetime.
DMD Temperature is the worst-case of any test point shown in Figure 15, or the active array as calculated by the Micromirror Array
Temperature Calculation , or any point along the Window Edge as defined in Figure 15. The locations of thermal test points TP2, TP3,
TP4 and TP5 in Figure 15 are intended to measure the highest window edge temperature. If a particular application causes another
point on the window edge to be at a higher temperature, a test point should be added to that location.
6.2 Storage Conditions
applicable before the DMD is installed in the final product
Tstg
DMD Storage Temperature
Storage Dew Point - long-term
TDP
(1)
(2)
Storage Dew Point - short-term
MIN
MAX
UNIT
–40
85
°C
24
°C
28
°C
(1)
(2)
Long-term is defined as the usable life of the device.
Dew points beyond the specified long-term dew point are for short-term conditions only, where short-term is defined as less than 60
cumulative days over the usable life of the device (operating, non-operating, or storage).
6.3 ESD Ratings
V(ESD)
(1)
10
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
SUPPLY VOLTAGES (1)
MIN
NOM
MAX
UNIT
(2)
VCC
Supply voltage for LVCMOS core logic
3.15
3.3
3.45
V
VCCI
Supply voltage for LVDS receivers
3.15
3.3
3.45
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrodes (2)
8.25
8.5
8.75
V
VBIAS
Supply voltage for micromirror electrodes
15.5
16
16.5
V
VRESET
Supply voltage for micromirror electrodes
–9.5
–10
–10.5
V
|VCCI–VCC|
Supply voltage delta (absolute value)
0.3
V
|VBIAS–VOFFSET|
Supply voltage delta (absolute value) (4)
8.75
V
VCC + 0.15
V
(3)
LVCMOS PINS
VIH
High level Input voltage
(5)
1.7
(5)
VIL
Low level Input voltage
IOH
High level output current at VOH = 2.4 V
– 0.3
IOL
Low level output current at VOL = 0.4 V
TPWRDNZ
PWRDNZ pulse width (6)
2.5
0.7
V
–20
mA
15
mA
10
ns
SCP INTERFACE (7)
ƒclock
SCP clock frequency (8)
tSCP_SKEW
Time between valid SCPDI and rising edge of SCPCLK (9)
tSCP_DELAY
Time between valid SCPDO and rising edge of SCPCLK (9)
tSCP_BYTE_INTERVAL
Time between consecutive bytes
tSCP_NEG_ENZ
Time between falling edge of SCPENZ and the first rising edge of SCPCLK
tSCP_PW_ENZ
SCPENZ inactive pulse width (high level)
tSCP_OUT_EN
Time required for SCP output buffer to recover after SCPENZ (from tri-state)
ƒclock
SCP circuit clock oscillator frequency
(10)
–800
500
kHz
800
ns
700
ns
1
µs
30
ns
1
9.6
µs
1.5
ns
11.1
MHz
(1)
(2)
(3)
(4)
Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Refer to Power Supply
Recommendations for additional information.
(5) Tester Conditions for VIH and VIL:
Frequency = 60MHz. Maximum Rise Time = 2.5 ns at (20% to 80%)
Frequency = 60MHz. Maximum Fall Time = 2.5 ns at (80% to 20%)
(6) PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tri-states the
SCPDO output pin.
(7) For all Serial Communications Port (SCP) operations, DCLK_A and DCLK_B are required.
(8) The SCP clock is a gated clock. Duty cycle shall be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
(9) Refer to Figure 3.
(10) SCP internal oscillator is specified to operate all SCP registers. For all SCP operations, DCLK is required.
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
100
400
MAX
UNIT
400
MHz
600
mV
LVDS INTERFACE
ƒclock
Clock frequency for LVDS interface, DCLK (all channels)
|VID|
Input differential voltage (absolute value) (11)
VCM
Common mode
VLVDS
LVDS voltage (11)
tLVDS_RSTZ
Time required for LVDS receivers to recover from PWRDNZ
ZIN
Internal differential termination resistance
95
ZLINE
Line differential impedance (PWB/trace)
90
ENVIRONMENTAL
(11)
1200
0
mV
2000
mV
10
ns
105
Ω
110
Ω
0
40 to 70 (14)
°C
–20
75
°C
90
°C
30
°C
Long-term dew point (operational, non-operational, long-term)
24
°C
Short-term dew point (15)
28
100
(12)
DMD temperature–operational, long-term
TDMD
(13) (14) (15)
DMD temperature – operational, short-term
TWINDOW
Window temperature – operational (16)
TCERAMIC-WINDOW-DELTA
Delta ceramic-to-window temperature -operational
(18)
(16) (17)
(operational, non-operational, short-term)
ILLUV
Illumination, wavelength < 420 nm
ILLVIS
Illumination, wavelengths between 420 and 700 nm
ILLIR
Illumination, wavelength > 700 nm
°C
0.68
mW/cm2
Thermally
Limited (19)
mW/cm2
10
mW/cm2
(11) Refer to Figure 4, Figure 5, and Figure 6.
(12) Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage
and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that
application-specific effects be considered as early as possible in the design cycle.
(13) DMD Temperature is the worst-case of any test point shown in Figure 15, or the active array as calculated by the Micromirror Array
Temperature Calculation , or any point along the Window Edge as defined in Figure 15. The locations of thermal test points TP2, TP3,
TP4 and TP5 in Figure 15 are intended to measure the highest window edge temperature. If a particular application causes another
point on the window edge to be at a higher temperature, a test point should be added to that location.
(14) Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. Refer to Micromirror Landed-on/Landed-Off Duty Cycle for a definition of micromirror landed duty
cycle.
(15) Long-term is defined as the average over the usable life.
(16) Window temperature as measured at thermal test points TP2, TP3, TP4 and TP5 in Figure 15.The locations of thermal test points TP2,
TP3, TP4 and TP5 in Figure 15 are intended to measure the highest window edge temperature. If a particular application causes
another point on the window edge to be at a higher temperature, a test point should be added to that location.
(17) Ceramic package temperature as measured at test point 1 (TP1) in Figure 15.
(18) Dew points beyond the specified long-term dew point (operating, non-operating, or storage) are for short-term conditions only, where
short-term is defined as< 60 cumulative days over the usable life of the device.
(19) Refer to Thermal Information and Micromirror Array Temperature Calculation .
12
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Max Recommended DMD Temperature –
Operational (°C)
www.ti.com
80
70
60
50
40
30
0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
60/40
Micromirror Landed Duty Cycle
55/45
D001
Figure 1. Max Recommended DMD Temperature – Derating Curve
6.5 Thermal Information
DLP6500FYE
THERMAL METRIC (1)
Active Area-to-Case Ceramic Thermal resistance
(1)
MIN
(1)
FYE (350)
MAX
0.6
UNIT
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions . The total heat load on the DMD is largely driven by the incident light absorbed by the active area;
although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical
systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in
this area can significantly degrade the reliability of the device.
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6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
DESCRIPTION
MIN
TYP MAX
VOH
High-level output voltage
VCC = 3.3 V, IOH = –20 mA
VOL
Low level output voltage
VCC = 3.45 V, IOL = 15 mA
0.4
V
IIH
High–level input current (2)
VCC = 3.45 V , VI = VCC
250
µA
IlL
Low level input current
VCC = 3.45 V, VI = 0
IOZ
High–impedance output current
VCC = 3.45 V
(3)
2.4
UNIT
V
–250
µA
10
µA
CURRENT
ICC
ICCI
IOFFSET
IBIAS
IRESET
Supply current
(4)
Supply current
(5)
Supply current
ITOTAL
VCC = 3.6 V
1076
VCCI = 3.6 V
518
VOFFSET = 8.75 V
4
VBIAS = 16.5 V
14
VRESET = –10.5 V
11
Total Sum
1623
VCC = 3.6 V
3874
VCCI = 3.6 V
1865
mA
mA
mA
POWER
PCC
PCCI
POFFSET
Supply power dissipation
PBIAS
VOFFSET = 8.75 V
35
VBIAS = 16.5 V
PRESET
231
VRESET = –10.5 V
mW
116
Supply power dissipation (6)
Total Sum
6300
CI
Input capacitance
ƒ = 1 MHz
10
pF
CO
Output capacitance
ƒ = 1 MHz
10
pF
CM
Reset group capacitance
MBRST(14:0)
ƒ = 1 MHz 1920 × 72 micromirrors
390
pF
PTOTAL
CAPACITANCE
(1)
(2)
(3)
(4)
(5)
(6)
14
330
All voltages are referenced to common ground VSS. Supply voltages VCC, VCCI, VOFFSET, VBIAS, and VRESET are all required for
proper DMD operation. VSS must also be connected.
Applies to LVCMOS input pins only. Does not apply to LVDS pins and MBRST pins.
LVCMOS input pins utilize an internal 18000 Ω passive resistor for pull-up and pull-down configurations. Refer to Pin Configuration and
Functions to determine pull-up or pull-down configuration used.
To prevent excess current, the supply voltage delta |VCCI – VCC| must be less than specified limit.
To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.
Total power on the active micromirror array is the sum of the electrical power dissipation and the absorbed power from the illumination
source. See the Micromirror Array Temperature Calculation .
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6.7 Timing Requirements
Over Recommended Operating Conditions unless otherwise noted.
DESCRIPTION (1)
SCP INTERFACE
MIN
TYP
MAX
UNIT
(2)
tr
Rise time
20% to 80%
200
ns
tƒ
Fall time
80% to 20%
200
ns
LVDS INTERFACE (2)
tr
Rise time
20% to 80%
100
400
ps
tƒ
Fall time
80% to 20%
100
400
ps
DCLK_A, 50% to 50%
2.5
DCLK_B, 50% to 50%
2.5
DCLK_A, 50% to 50%
1.19
1.25
DCLK_B, 50% to 50%
1.19
1.25
LVDS CLOCKS (3)
tc
Cycle time
tw
Pulse
duration
ns
ns
LVDS INTERFACE (3)
tsu
Setup time
tsu
Setup time
th
Hold time
th
Hold time
D_A(15:0) before rising or falling edge of DCLK_A
0.1
D_B(15:0) before rising or falling edge of DCLK_B
0.1
SCTRL_A before rising or falling edge of DCLK_A
0.1
SCTRL_B before rising or falling edge of DCLK_B
0.1
D_A(15:0) after rising or falling edge of DCLK_A
0.4
D_B(15:0) after rising or falling edge of DCLK_B
0.4
SCTRL_A after rising or falling edge of DCLK_A
0.3
SCTRL_B after rising or falling edge of DCLK_B
0.3
ns
ns
ns
ns
LVDS INTERFACE (4)
tskew
(1)
(2)
(3)
(4)
Skew time
Channel B relative to Channel A
Channel A includes the following LVDS
pairs:
DCLK_AP and DCLK_AN
SCTRL_AP and SCTRL_AN
D_AP(15:0) and D_AN(15:0)
(4)
–1.25
Channel B includes the following LVDS
pairs:
DCLK_BP and DCLK_BN
SCTRL_BP and SCTRL_BN
D_BP(15:0) and D_BN(15:0)
1.25
ns
Refer to Pin Configuration and Functions for pin details.
Refer to Figure 7
Refer to Figure 8
Refer to Figure 9
Timing Requirements
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 2 shows an equivalent test load circuit for the output
under test. The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
Timing reference loads are not intended as a precise representation of any particular system environment or
depiction of the actual load presented by a production test. System designers should use IBIS or other simulation
tools to correlate the timing reference load to a system environment. Refer to the Application and Implementation
section.
Device Pin
Output Under Test
Tester Channel
CLOAD
Figure 2. Test Load Circuit
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tc
SCPCLK
fclock = 1 / tc
50%
50%
tSCP_SKEW
SCPDI
50%
tSCP_DELAY
SCPD0
50%
Not to scale.
Refer to SCP Interface section of the Recommended Operating Conditions table.
Figure 3. SCP Timing Parameters
(VIP + VIN) / 2
DCLK_P , SCTRL_P , D_P(0:?)
LVDS
Receiver
VID
VIP
DCLK_N , SCTRL_N , D_N(0:?)
VCM
VIN
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 4. LVDS Voltage Definitions (References)
16
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VLVDS max = VCM max + | 1/2 * VID max |
VCM
VID
VLVDS min = VCM min ± | 1/2 * VID max |
Not to scale.
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Figure 5. LVDS Voltage Parameters
DCLK_P , SCTRL_P , D_P(0:?)
ESD
Internal
Termination
LVDS
Receiver
DCLK_N , SCTRL_N , D_N(0:?)
ESD
Refer to LVDS Interface section of the Recommended Operating Conditions table.
Refer to Pin Configuration and Functions for list of LVDS pins.
Figure 6. LVDS Equivalent Input Circuit
LVDS Interface
SCP Interface
1.0 * VCC
1.0 * VID
VCM
0.0 * VCC
0.0 * VID
tr
tf
tr
tf
Not to scale.
Refer to the Timing Requirements
Refer to Pin Configuration and Functions for list of LVDS pins and SCP pins..
Figure 7. Rise Time and Fall Time
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tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(0:?)
D_N(0:?)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 8. Timing Requirement Parameter Definitions
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
tskew
DCLK_P
DCLK_N
50%
D_P(0:?)
D_N(0:?)
50%
SCTRL_P
SCTRL_N
50%
Not to scale.
Refer to LVDS INTERFACE section in the Timing Requirements table.
Figure 9. LVDS Interface Channel Skew Definition
18
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6.8 Typical Characteristics
The DLP6500FYE DMD is controlled by the DLPC900 controller. The controller has two modes of operation. The first is Video
mode where the video source is displayed on the DMD. The second is Pattern mode, where the patterns are pre-stored in
flash memory and then streamed to the DMD. The allowed DMD pattern rate depends on which mode and bit-depth is
selected.
Table 2. Bit Depth versus Pattern Rate
BIT DEPTH
VIDEO MODE RATE (Hz)
PATTERN MODE RATE (Hz)
1
2880
9523
2
1440
3289
3
960
2638
4
720
1364
5
480
823
6
480
672
7
360
500
8
247
247
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6.9 System Mounting Interface Loads
PARAMETER
MIN
Maximum system mounting interface
load to be applied to the:
•
Thermal Interface area
•
Electrical Interface areas
(See Figure 10)
NOM
MAX
UNIT
11.30
Kg
0
Kg
Maximum Load 22.64 Applied per
condition 2
•
•
(See Figure 10)
Thermal Interface area
Electrical Interface areas
22.60
Electrical Interface Area
Thermal Interface Area
Figure 10. System Mounting Interface Loads
20
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6.10 Micromirror Array Physical Characteristics
VALUE
M
Number of active columns
N
Number of active rows
P
Micromirror (pixel) pitch
UNIT
1920
micromirrors
1080
micromirrors
7.56
µm
Micromirror active array width
M×P
14.5152
mm
Micromirror active array height
N×P
8.1648
Micromirror active border
Pond of micromirror (POM) (1)
14
mm
micromirrors /side
M±4
M±3
M±2
M±1
The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM.
These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical
bias to tilt toward OFF.
0
1
2
3
(1)
See Figure 11
0
1
2
3
DMD Active Array
NxP
M x N Micromirrors
N±4
N±3
N±2
N±1
MxP
P
Border micromirrors omitted for clarity.
Details omitted for clarity.
Not to scale.
P
P
P
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 11. Micromirror Array Physical Characteristics
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6.11 Micromirror Array Optical Characteristics
See Optical Interface and System Image Quality for important information
PARAMETER
α
Micromirror tilt angle
β
Micromirror tilt angle tolerance (1)
Micromirror tilt direction
CONDITIONS
DMD landed state
MIN
(1)
–1
(5) (6) (7)
44
45
Adjacent micromirrors
(8)
MAX
12
(2) (3) (4) (5)
Number of out-of-specification micromirrors
NOM
°
1
°
46
°
0
Non-adjacent micromirrors
UNIT
10
micromirrors
Micromirror crossover time
(9) (10)
Typical performance
2.5
μs
Micromirror switching time
(10)
Typical performance
5
μs
DMD photopic efficiency within the wavelength range 420 nm
to 700 nm (11)
66%
(1)
(2)
(3)
(4)
Measured relative to the plane formed by the overall micromirror array.
Additional variation exists between the micromirror array and the package datums.
Represents the landed tilt angle variation relative to the nominal landed tilt angle.
Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different
devices.
(5) For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some
system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field
reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in
colorimetry variations, system efficiency variations or system contrast variations.
(6) When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of
the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State
direction. A binary value of 0 results in a micromirror landing in the OFF State direction.
(7) Refer to Figure 12
(8) An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states within the
specified Micromirror Switching Time.
(9) Micromirror crossover time is primarily a function of the natural response time of the micromirrors.
(10) Performance as measured at the start of life.
(11) Efficiency numbers assume 24-degree illumination angle, F/2.4 illumination and collection cones, uniform source spectrum, and uniform
pupil illumination. Efficiency numbers assume 100% electronic mirror duty cycle and do not include optical overfill loss. Note that this
number is specified under conditions described above and deviations from the specified conditions could result in decreased efficiency.
22
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M±4
M±3
M±2
M±1
illumination
0
1
2
3
Not To Scale
0
1
2
3
On-State
Tilt Direction
45°
Off-State
Tilt Direction
N±4
N±3
N±2
N±1
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 12. Micromirror Landed Orientation and Tilt
6.12 Window Characteristics
PARAMETER (1)
CONDITIONS
Window material designation S600
Corning Eagle XG
Window refractive index
at wavelength 546.1 nm
Window aperture
See
Illumination overfill
Refer to Illumination Overfill
Window transmittance, single–pass
through both surfaces and glass (3)
(1)
(2)
(3)
MIN
NOM
MAX
UNIT
1.5119
(2)
Minimum within the wavelength range 420 nm to 680 nm.
Applies to all angles 0° to 30° AOI.
97%
Average over the wavelength range 420 nm to 680 nm.
Applies to all angles 30° to 45° AOI.
97%
See Window Characteristics and Optics for more information.
For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical
ICD in the Mechanical, Packaging, and Orderable Information section,
See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP™ DMD Window.
6.13 Chipset Component Usage Specification
The DLP6500FYE is a component of one or more DLP® chipsets. Reliable function and operation of the
DLP6500FYE requires that it be used in conjunction with the other components of the applicable DLP chipset,
including those components that contain or implement TI DMD control technology. TI DMD control technology is
the TI technology and devices for operating or controlling a DLP DMD.
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7 Detailed Description
7.1 Overview
DLP6500FYE is a 0.65 inch diagonal spatial light modulator which consists of an array of highly reflective
aluminum micromirrors. Pixel array size and square grid pixel arrangement are shown in Figure 11.
The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The electrical
interface is Low Voltage Differential Signaling (LVDS), Double Data Rate (DDR).
DLP6500FYE DMD consists of a two-dimensional array of 1-bit CMOS memory cells. The array is organized in a
grid of M memory cell columns by N memory cell rows. Refer to the Functional Block Diagram .
The positive or negative deflection angle of the micromirrors can be individually controlled by changing the
address voltage of underlying CMOS addressing circuitry and micromirror reset signals (MBRST).
Each cell of the M × N memory array drives its true and complement (‘Q’ and ‘QB’) data to two electrodes
underlying one micromirror, one electrode on each side of the diagonal axis of rotation. Refer to Micromirror
Array Optical Characteristics . The micromirrors are electrically tied to the micromirror reset signals (MBRST) and
the micromirror array is divided into reset groups.
Electrostatic potentials between a micromirror and its memory data electrodes cause the micromirror to tilt
toward the illumination source in a DLP projection system or away from it, thus reflecting its incident light into or
out of an optical collection aperture. The positive (+) tilt angle state corresponds to an 'on' pixel, and the negative
(–) tilt angle state corresponds to an 'off' pixel.
Refer to Micromirror Array Optical Characteristics for the ± tilt angle specifications. Refer to Pin Configuration
and Functions for more information on micromirror reset control.
24
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7.2 Functional Block Diagram
DATA_A
SCTRL_A
DCLK_A
VSS
VCC
VCCI
VOFFSET
VRESET
VBIAS
MBRST
PWRDNZ
SCP
Not to Scale. Details Omitted for Clarity. See Accompanying Notes in this Section.
Channel A
Interface
Column Read & Write
Control
Bit Lines
Control
(0,0)
Voltage
Generators
Voltages
Word Lines
Micromirror Array
Row
Bit Lines
(M-1, N-1)
Control
Control
Column Read & Write
DATA_B
SCTRL_B
DCLK_B
VSS
VCC
VCCI
VOFFSET
VRESET
VBIAS
MBRST
RESET_CTRL
Channel B
Interface
For pin details on Channels A, B, C, and D, refer to Pin Configuration and Functions and LVDS Interface section of
Timing Requirements .
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7.3 Feature Description
DLP6500FYE device consists of highly reflective, digitally switchable, micrometer-sized mirrors (micromirrors)
organized in a two-dimensional orthogonal pixel array. Refer to Figure 11 and Figure 13.
Each aluminum micromirror is switchable between two discrete angular positions, –α and +α. The angular
positions are measured relative to the micromirror array plane, which is parallel to the silicon substrate. Refer to
Micromirror Array Optical Characteristics and Figure 14.
The parked position of the micromirror is not a latched position and is therefore not necessarily perfectly parallel
to the array plane. Individual micromirror flat state angular positions may vary. Tilt direction of the micromirror is
perpendicular to the hinge-axis. The on-state landed position is directed toward the left-top edge of the package,
as shown in Figure 13.
Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a
specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell
contents, after the mirror clocking pulse is applied. The angular position (–α and +α) of the individual
micromirrors changes synchronously with a micromirror clocking pulse, rather than being coincident with the
CMOS memory cell data update.
Writing logic 1 into a memory cell followed by a mirror clocking pulse results in the corresponding micromirror
switching to a +α position. Writing logic 0 into a memory cell followed by a mirror clocking pulse results in the
corresponding micromirror switching to a – α position.
Updating the angular position of the micromirror array consists of two steps:
1. update the contents of the CMOS memory .
2. apply a micromirror reset to all or a portion of the micromirror array (depending upon the configuration of the
system).
Micromirror reset pulses are generated internally by the DLP6500FYE DMD , with application of the pulses being
coordinated by the DLPC900 display controller.
For more information, see the TI application report DLPA008A, DMD101: Introduction to Digital Micromirror
Device (DMD) Technology.
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Feature Description (continued)
Incident
Illumination
Package Pin
A1 Corner
Details Omitted For Clarity.
Not To Scale.
DMD
Micromirror
Array
0
(Border micromirrors eliminated for clarity)
M±1
Active Micromirror Array
0
N±1
Micromirror Hinge-Axis Orientation
Micromirror Pitch
P (um)
45°
P (um)
P (um)
³2Q-6WDWH´
Tilt Direction
³2II-6WDWH´
Tilt Direction
P (um)
Refer to Micromirror Array Physical Characteristics, Figure 11, and Micromirror Landed Orientation and Tilt
Figure 13. Micromirror Array, Pitch, Hinge Axis Orientation
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Feature Description (continued)
g
n t -L i
de n
ci tio
In ina
m
u
Ill
Details Omitted For Clarity.
ht
Not To Scale.
Pa
th
Package Pin
A1 Corner
DMD
Incident
Illumination
Two
³2Q-6WDWH´
Micromirrors
nt t Path
ide
Inc n-Ligh
atio
min
Illu
nt t Path
ide
Inc n-Ligh
tio
ina
m
Illu
Projected-Light
Path
Two
³2II-6WDWH´
Micromirrors
For Reference
gh
Li
eat th
t
S a
ff- P
O
a±b
Flat-State
( ³SDUNHG´ )
Micromirror Position
t
-a ± b
Silicon Substrate
³2Q-6WDWH´
Micromirror
Silicon Substrate
³2II-6WDWH´
Micromirror
Micromirror States: On, Off, Flat
Figure 14. Micromirror States: On, Off, Flat
28
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7.4 Device Functional Modes
DLP6500FYE is part of the chipset comprising of the DLP6500FYE DMD and DLPC900 display controller. To
ensure reliable operation, DLP6500FYE DMD must always be used with a DLPC900 display controller.
DMD functional modes are controlled by the DLPC900 digital display controller. See the DLPC900 data sheet
listed in Related Documents. Contact a TI applications engineer for more information.
7.5 Window Characteristics and Optics
NOTE
TI assumes no responsibility for image quality artifacts or DMD failures caused by optical
system operating conditions exceeding limits described previously.
7.5.1 Optical Interface and System Image Quality
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
Optimizing system optical performance and image quality strongly relate to optical system design parameter
trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.2 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light
path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other
system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt
angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination
numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur.
7.5.3 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° (two degrees) of the entrance pupil of the projection optics. Misalignment of pupils can create
objectionable artifacts in the display’s border and/or active area, which may require additional system apertures
to control, especially if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.4 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical
operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the
window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical
system should be designed to limit light flux incident anywhere on the window aperture from exceeding
approximately 10% of the average flux level in the active area. Depending on the particular system’s optical
architecture, overfill light may have to be further reduced below the suggested 10% level in order to be
acceptable.
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7.6 Micromirror Array Temperature Calculation
Figure 15. DMD Thermal Test Points
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load.
The relationship between micromirror array temperature and the reference ceramic temperature is provided by
the following equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION
QILLUMINATION = (CL2W × SL)
(1)
(2)
where
•
•
•
•
•
30
TARRAY = Computed micromirror array temperature (°C)
TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 15
RARRAY–TO–CERAMIC = DMD package thermal resistance from micromirror array to outside ceramic (°C/W)
specified in Thermal Information
QARRAY = Total DMD power; electrical, specified in Electrical Characteristics , plus absorbed (calculated) (W)
QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics
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Micromirror Array Temperature Calculation (continued)
•
•
CL2W = Conversion constant for screen lumens to absorbed optical power on the DMD (W/lm) specified below
SL = Measured ANSI screen lumens (lm)
(3)
Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. The nominal electrical power dissipation to use when calculating array temperature is 2.9 Watts .
Absorbed optical power from the illumination source is variable and depends on the operating state of the
micromirrors and the intensity of the light source. Equations shown above are valid for a 1-chip DMD system with
total projection efficiency through the projection lens from DMD to the screen of 87%.
The conversion constant CL2W is based on the DMD micromirror array characteristics. It assumes a spectral
efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the DMD active array, and
16.3% on the DMD array border and window aperture. The conversion constant is calculated to be 0.00293
W/lm.
Sample Calculation for typical projection application:
TCERAMIC = 55°C, assumed system measurement; see Recommended Operating Conditions for specific limits
SL = 2000 lm
QELECTRICAL = 2.9 W (see the maximum power specifications in Electrical Characteristics )
CL2W = 0.00293 W/lm
QARRAY = 2.9 W + (0.00293 W/lm × 2000 lm) = 8.76 W
TARRAY = 55°C + (8.76 W × 0.6 × C/W) = 60.26°C
7.7 Micromirror Landed-on/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the On–state versus the amount of time the same
micromirror is landed in the Off–state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On–state 100% of the
time (and in the Off–state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off–state 100% of
the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time.
Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other
state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages)
always add to 100.
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD’s usable life.
Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed
duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed
duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this
interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s
usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
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Micromirror Landed-on/Landed-Off Duty Cycle (continued)
In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at
for a give long-term average Landed Duty Cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the
pixel will experience a 0/100 Landed Duty Cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 3.
Table 3. Grayscale Value and Landed Duty Cycle
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color
cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given
primary must be displayed in order to achieve the desired white point.
During a given period of time, the landed duty cycle of a given pixel can be calculated as follows:
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) +
(Blue_Cycle_% × Blue_Scale_Value)
Where:
Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red,
Green, and Blue are displayed (respectively) to achieve the desired white point.
For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green,
blue color intensities would be as shown in Table 4.
32
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Table 4. Example Landed Duty Cycle for Full-Color
Red Cycle Percentage
50%
Green Cycle Percentage
20%
Blue Cycle Percentage
30%
Red Scale Value
Green Scale Value
Blue Scale Value
Landed Duty Cycle
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLP6500FYE along with the DLPC900 controller provides a solution for many applications including
structured light and video projection. The DMD is a spatial light modulator, which reflects incoming light from an
illumination source to one of two directions, with the primary direction being into a projection or collection optic.
Each application is derived primarily from the optical architecture of the system and the format of the data
coming into the DLPC900. Applications of interest include machine vision and 3D printing.
8.2 Typical Application
A typical embedded system application using the DLPC900 controller and a DLP6500FYE is shown in Figure 16.
In this configuration, the DLPC900 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from
an external source or processor. This system configuration supports still and motion video sources plus
sequential pattern mode. Refer to Related Documents for the DLPC900 digital controller data sheet.
USB_DN,DP
I2C
HDMI
DP
Processor
GUI
RAM
LED EN[2:0]
I2C_SCL1, I2C_SDA1
P1_A[9:0]
Digital Receiver
P1_B[9:0]
P1_C[9:0]
HDMI
LED PWM[2:0]
PWM
DMD_A,B[15:0]
DMD Control
DMD SSP
P1A_CLK, P1_DATEN,
P1_VSYNC, P1_HSYNC
TRIG_OUT[1:0]
Camera
TRIG_IN[1:0]
POWER RAILS
PWRGOOD
POSENSE
MOSC
TDO[1:0],TRST,TCK
RMS[1:0],RTCK
JTAG
LEDs
DLPC900
DISPLAYPORT
Crystal
FAN
LED
Status
LED Driver
USB
HEARTBEAT
FAULT_STATUS
PM_ADDR[22:0],WE
DATA[15:0],OE,CS
Flex
Parallel
Flash
Host
I2C_SCL0
I2C_SDA0
Power
Management
I2C
DLP6500FYE
VCC
12V DC IN
Figure 16. Typical Application Schematic
8.2.1 Design Requirements
Detailed design requirements are located in the DLPC900 digital controller data sheet. Refer to Related
Documents.
8.2.2 Detailed Design Procedure
See the reference design schematic for connecting together the DLPC900 display controller and the
DLP6500FYE DMD. An example board layout is included in the reference design data base. Layout guidelines
should be followed for reliability.
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9 Power Supply Recommendations
9.1 DMD Power Supply Requirements
The following power supplies are all required to operate the DMD: VCC, VCCI, VOFFSET, VBIAS, and VRESET.
VSS must also be connected. DMD power-up and power-down sequencing is strictly controlled by the DLPC900
device.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to the prescribed power-up and
power-down procedures may affect device reliability. VCC, VCCI, VOFFSET, VBIAS,
and VRESET power supplies have to be coordinated during power-up and powerdown operations. VSS must also be connected. Failure to meet any of the below
requirements will result in a significant reduction in the DMD’s reliability and lifetime.
Refer to Figure 17.
9.2 DMD Power Supply Power-Up Procedure
•
•
•
•
•
During power-up, VCC and VCCI must always start and settle before VOFFSET, VBIAS, and VRESET
voltages are applied to the DMD.
During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions. During power-up, VBIAS does not have to start
after VOFFSET.
During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements listed in Absolute Maximum Ratings , in Recommended Operating Conditions , and in DMD
Power Supply Sequencing Requirements .
During power-up, LVCMOS input pins shall not be driven high until after VCC and VCCI have settled at
operating voltages listed in Recommended Operating Conditions .
9.3 DMD Power Supply Power-Down Procedure
•
•
•
•
•
During power-down, VCC and VCCI must be supplied until after VBIAS, VRESET, and VOFFSET are
discharged to within the specified limit of ground. Refer to Table 5.
During power-down, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the
specified limit shown in Recommended Operating Conditions . During power-down, it is not mandatory to stop
driving VBIAS prior to VOFFSET.
During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and
VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements listed in Absolute Maximum Ratings , in Recommended Operating Conditions , and in
Figure 17.
During power-down, LVCMOS input pins must be less than specified in Recommended Operating
Conditions .
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DMD Power Supply Power-Down Procedure (continued)
EN_BIAS, EN_OFFSET, and EN_RESET are disabled by
DLP Controller software or PWRDNZ signal control
Note 5
Waveforms Not To Scale.
Details Omitted For Clarity.
Note 3
VBIAS, VOFFSET, and VRESET are disabled by
DLP Controller software
Refer to Recommended Operating Conditions.
Power Off
Mirror Park Sequence
RESET_OEZ
VCC / VCCI
VSS
VSS
VCC / VCCI
PWRDNZ
VSS
VSS
VCC / VCCI
VCC,
VCCI
VSS
VSS
EN_BIAS,
EN_OFFSET,
EN_RESET
VSS
VCC / VCCI
Note 3
VBIAS
VSS
VBIAS
VBIAS
VBIAS < Specification
Note 1
VSS
Note 4
Note 1
ûV < Specification
VSS
ûV < Specification
VOFFSET
VOFFSET
VOFFSET < Specification
VOFFSET
Note 4
VSS
VSS
VRESET < Specification
VSS
VSS
Note 4
VRESET > Specification
VRESET
VRESET
VRESET
VCC
LVCMOS
Inputs
VSS
VSS
Waveforms Not To Scale.
LVDS
Inputs
VSS
Refer to Recommended Operating Conditions.
Note 2
Note 2
VSS
Figure 17. DMD Power Supply Sequencing Requirements
1. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in
Recommended Operating Conditions . OEMs may find that the most reliable way to ensure this is to power
VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down.
2. LVDS signals are less than the input differential voltage (VID) maximum specified in Recommended
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DMD Power Supply Power-Down Procedure (continued)
Operating Conditions . During power-down, LVDS signals are less than the high level input voltage (VIH)
maximum specified in Recommended Operating Conditions .
3. When system power is interrupted, the DLP controller (DLPC900) initiates a hardware power-down that
activates PWRDNZ and disables VBIAS, VRESET and VOFFSET after the micromirror park sequence.
Software power-down disables VBIAS, VRESET, and VOFFSET after the micromirror park sequence through
software control. For either case, enable signals EN_BIAS, EN_OFFSET, and EN_RESET are used to
disable VBIAS, VOFFSET, and VRESET, respectfully.
4. Refer to Table 5.
5. Figure not to scale. Details have been omitted for clarity. Refer to Recommended Operating Conditions .
Table 5. DMD Power-Down Sequence Requirements
PARAMETER
MIN
VBIAS
VOFFSET
Supply voltage level during power–down sequence
VRESET
–4.0
MAX
V
4.0
V
0.5
V
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4.0
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10 Layout
10.1 Layout Guidelines
The DLP6500FYE along with one DLPC900 controller provides a solution for many applications including
structured light and video projection. This section provides layout guidelines for the DLP6500FYE.
10.1.1 General PCB Recommendations
The PCB shall be designed to IPC2221 and IPC2222, Class 2, Type Z, at level B producibility and built to
IPC6011 and IPC6012, class 2. The PCB board thickness to be 0.062 inches +/- 10%, using standard FR-4
material, and applies after all lamination and plating processes, measured from copper to copper.
Two-ounce copper planes are recommended in the PCB design in order to achieve needed thermal connectivity.
Refer to Related Documents for the DLPC900 Digital Controller Data Sheet for related information on the DMD
Interface Considerations.
High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface)
is dependent on the following factors:
• Total length of the interconnect system
• Spacing between traces
• Characteristic impedance
• Etch losses
• How well matched the lengths are across the interface
Thus, ensuring positive timing margin requires attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
• Setup Margin = (controller output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI
degradation)
• Hold-time Margin = (controller output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI
degradation)
The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as
simultaneously switching output (SSO) noise, crosstalk, and inter-symbol-interference (ISI) noise.
DLPC900 I/O timing parameters can be found in DLPC900 Digital Controller Data Sheet. Similarly, PCB routing
mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as
easy to determine.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design
guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing
requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these
recommendations may work, but should be confirmed with PCB signal integrity analysis or lab measurements.
10.2 Layout Example
10.2.1 Board Stack and Impedance Requirements
Refer to Figure 18 for guidance on the parameters.
PCB design:
38
Configuration:
Asymmetric dual stripline
Etch thickness (T):
1.0-oz copper (1.2 mil)
Flex etch thickness (T):
0.5-oz copper (0.6 mil)
Single-ended signal impedance:
50 Ω (±10%)
Differential signal impedance:
100 Ω (±10%)
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Layout Example (continued)
PCB stack-up:
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground.
Dielectric FR4, (Er):
4.2 (nominal)
Signal trace distance to reference plane 1
(H1):
5.0 mil (nominal)
Signal trace distance to reference plane 2
(H2):
34.2 mil (nominal)
Figure 18. PCB Stack Geometries
Table 6. General PCB Routing (Applies to All Corresponding PCB Signals)
PARAMETER
Line width (W)
APPLICATION
SINGLE-ENDED SIGNALS
DIFFERENTIAL PAIRS
UNIT
Escape routing in ball field
4
(0.1)
4
(0.1)
mil
(mm)
PCB etch data or control
7
(0.18)
4.25
(0.11)
mil
(mm)
PCB etch clocks
7
(0.18)
4.25
(0.11)
mil
(mm)
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Layout Example (continued)
Table 6. General PCB Routing (Applies to All Corresponding PCB Signals) (continued)
PARAMETER
APPLICATION
SINGLE-ENDED SIGNALS
DIFFERENTIAL PAIRS
UNIT
PCB etch data or control
N/A
5.75 (1)
–0.15
mil
(mm)
PCB etch clocks
N/A
5.75 (1)
–0.15
mil
(mm)
PCB etch data or control
N/A
20
(0.51)
mil
(mm)
PCB etch clocks
N/A
20
(0.51)
mil
(mm)
Escape routing in ball field
4
(0.1)
4
(0.1)
mil
(mm)
PCB etch data or control
10
(0.25)
20
(0.51)
mil
(mm)
PCB etch clocks
20
(0.51)
20
(0.51)
mil
(mm)
Total data
N/A
12
0.3
mil
(mm)
Total data
N/A
12
0.3
mil
(mm)
Differential signal pair spacing (S)
Minimum differential pair-to-pair
spacing (S)
Minimum line spacing to other
signals (S)
Maximum differential pair P-to-N
length mismatch
(1)
Spacing may vary to maintain differential impedance requirements
Table 7. DMD Interface Specific Routing
SIGNAL GROUP LENGTH MATCHING
INTERFACE
SIGNAL GROUP
REFERENCE SIGNAL
MAX MISMATCH
UNIT
mil
(mm)
mil
(mm)
DMD (LVDS)
SCTRL_AN / SCTRL_AP
D_AP(15:0)/ D_AN(15:0)
DCKA_P/ DCKA_N
± 150
(± 3.81)
DMD (LVDS)
SCTRL_BN/ SCTRL_BP
D_BP(15:0)/ D_BN(15:0)
DCKB_P/ DCKB_N
± 150
(± 3.81)
Number of layer changes:
• Single-ended signals: Minimize
• Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair
should not change layers.
Table 8. DMD Signal Routing Length (1)
BUS
MIN
MAX
UNIT
DMD (LVDS)
50
375
mm
(1)
Max signal routing length includes escape routing.
Stubs: Stubs should be avoided.
Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100 Ω
internally.
Connector (DMD-LVDS interface bus only):
High-speed connectors that meet the following requirements should be used:
• Differential crosstalk:< 5%
• Differential impedance: 75 to 125 Ω
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Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs should be routed
in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference
for each row should be accounted for on associated PCB etch lengths. Voltage or low frequency signals should
be routed on the outer layers. Signal trace corners shall be no sharper than 45 degrees. Adjacent signal layers
shall have the predominant traces routed orthogonal to each other.
These guidelines will produce a maximum PCB routing mismatch of 4.41 mm (0.174 inch) or approximately 30.4
ps, assuming 175 ps/inch FR4 propagation delay.
These PCB routing guidelines will result in approximately 25-ps system setup margin and 25-ps system hold
margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.
Both the DLPC900 output timing parameters and the DLP6500FYE DMD input timing parameters include timing
budget to account for their respective internal package routing skew.
10.2.1.1 Power Planes
Signal routing is NOT allowed on the power and ground planes. All device pin and via connections to this plane
shall use a thermal relief with a minimum of four spokes. The power plane shall clear the edge of the PCB by
0.2”.
Prior to routing, vias connecting all digital ground layers (GND) should be placed around the edge of the rigid
PWB regions 0.025” from the board edges with a 0.100” spacing. It is also desirable to have all internal digital
ground (GND) planes connected together in as many places as possible. If possible, all internal ground planes
should be connected together with a minimum distance between connections of 0.5”. Extra vias are not required
if there are sufficient ground vias due to normal ground connections of devices. NOTE: All signal routing and
signal vias should be inside the perimeter ring of ground vias.
Power and Ground pins of each component shall be connected to the power and ground planes with one via for
each pin. Trace lengths for component power and ground pins should be minimized (ideally, less than 0.100”).
Unused or spare device pins that are connected to power or ground may be connected together with a single via
to power or ground. Ground plane slots are NOT allowed.
Route VOFFSET, VBIAS, and VRESET as a wide trace >20mils (wider if space allows) with 20 mils spacing.
10.2.1.2 LVDS Signals
The LVDS signals shall be first. Each pair of differential signals must be routed together at a constant separation
such that constant differential impedance (as in section Board Stack and Impedance Requirements ) is
maintained throughout the length. Avoid sharp turns and layer switching while keeping lengths to a minimum.
The distance from one pair of differential signals to another shall be at least 2 times the distance within the pair.
10.2.1.3 Critical Signals
The critical signals on the board must be hand routed in the order specified below. In case of length matching
requirements, the longer signals should be routed in a serpentine fashion, keeping the number of turns to a
minimum and the turn angles no sharper than 45 degrees. Avoid routing long trace all around the PCB.
Table 9. Timing Critical Signals
GROUP
SIGNAL
CONSTRAINTS
Refer to Table 6 and Table 7
ROUTING LAYERS
1
D_AP(0:15), D_AN(0:15), DCLK_AP,
DCLK_AN, SCTRL_AN, SCTRL_AP,
D_BP(0:15), D_BN (0:15), DCLK_BP,
DCLK_BN, SCTRL_BN, SCTRL_BP
2
RESET_ADDR_(0:3),
RESET_MODE_(0:1),
RESET_OEZ,
RESET_SEL_(0:1)
RESET_STROBE,
RESET_IRQZ.
Internal signal layers. Top and bottom as
required.
3
SCP_CLK, SCP_DO,
SCP_DI, SCP_DMD_CSZ.
Any
4
Others
No matching/length requirement
Internal signal layers. Avoid layer switching
when routing these signals.
Any
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10.2.1.4 Device Placement
Unless otherwise specified, all major components should be placed on top layer. Small components such as
ceramic, non-polarized capacitors, resistors and resistor networks can be placed on bottom layer. All high
frequency de-coupling capacitors for the ICs shall be placed near the parts. Distribute the capacitors evenly
around the IC and locate them as close to the device’s power pins as possible (preferably with no vias). In the
case where an IC has multiple de-coupling capacitors with different values, alternate the values of those that are
side by side as much as possible and place the smaller value capacitor closer to the device.
10.2.1.5 Device Orientation
It is desirable to have all polarized capacitors oriented with their positive terminals in the same direction. If
polarized capacitors are oriented both horizontally and vertically, then all horizontal capacitors should be oriented
with the “+” terminal the same direction and likewise for the vertically oriented ones.
10.2.1.6 Fiducials
Fiducials for automatic component insertion should be placed on the board according to the following guidelines
or on recommendation from manufacturer:
• Fiducials for optical auto insertion alignment shall be placed on three corners of both sides of the PWB.
• Fiducials shall also be placed in the center of the land patterns for fine pitch components (lead spacing
<0.05").
• Fiducials should be 0.050 inch copper with 0.100 inch cutout (antipad).
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11 Device Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 10. Package Specific Information
PACKAGE TYPE
PINS
CONNECTOR
FYE
350
PGA
DLP6500 FYE
Package Type
Device Descriptor
Figure 19. Part Number Description
11.1.2 Device Markings
The device marking will include both human-readable information and a 2-dimensional matrix code. The humanreadable information is described in Figure 20. The 2-dimensional matrix code is an alpha-numeric character
string that contains the DMD part number, Part 1 of Serial Number, and Part 2 of Serial Number. The first
character of the DMD Serial Number (part 1) is the manufacturing year. The second character of the DMD Serial
Number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias
voltage bin letter.
TI Internal Numbering
2-Dimension Matrix Code
(Part Number and
Serial Number)
DMD Part Number
DLP6500FYE
Part 1 of Serial Number
(7 characters)
Part 2 of Serial Number
(7 characters)
Figure 20. DMD Marking
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11.2 Documentation Support
11.2.1 Related Documentation
The following documents contain additional information related to the use of the DLP6500 device.
Table 11. Related Documents
DOCUMENT
DLPC900 Digital Controller Data Sheet
DLPS037
DLPC900 Software Programmer’s Guide
DLPU018
DMD101: Introduction to Digital Micromirror Device (DMD) Technology.
DLPA008
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
DLP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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26-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLP6500FYE
ACTIVE
Package Type Package Pins Package
Drawing
Qty
CPGA
FYE
350
1
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
PD NIPDAU
Level-1-NC-NC
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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26-May-2015
Addendum-Page 2
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